?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
- Add codec id for Realtek ALC268.
[dragonfly.git] / sys / dev / sound / pci / maestro3.c
blobfc3e3b722611a71851eb885d67a1294d58f2db00
1 /*-
2 * Copyright (c) 2001 Scott Long <scottl@freebsd.org>
3 * Copyright (c) 2001 Darrell Anderson <anderson@cs.duke.edu>
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $FreeBSD: src/sys/dev/sound/pci/maestro3.c,v 1.28.2.2 2007/03/12 02:03:25 ariff Exp $
28 * $DragonFly: src/sys/dev/sound/pci/maestro3.c,v 1.12 2007/06/16 20:07:19 dillon Exp $
29 */
30
31 /*
32 * Maestro-3/Allegro FreeBSD pcm sound driver
33 *
34 * executive status summary:
35 * (+) /dev/dsp multiple concurrent play channels.
36 * (+) /dev/dsp config (speed, mono/stereo, 8/16 bit).
37 * (+) /dev/mixer sets left/right volumes.
38 * (+) /dev/dsp recording works. Tested successfully with the cdrom channel
39 * (+) apm suspend/resume works, and works properly!.
40 * (-) hardware volme controls don't work =-(
41 * (-) setblocksize() does nothing.
42 *
43 * The real credit goes to:
44 *
45 * Zach Brown for his Linux driver core and helpful technical comments.
46 * <zab@zabbo.net>, http://www.zabbo.net/maestro3
47 *
48 * Cameron Grant created the pcm framework used here nearly verbatim.
49 * <cg@freebsd.org>, http://people.freebsd.org/~cg/template.c
50 *
51 * Taku YAMAMOTO for his Maestro-1/2 FreeBSD driver and sanity reference.
52 * <taku@cent.saitama-u.ac.jp>
53 *
54 * ESS docs explained a few magic registers and numbers.
55 * http://virgo.caltech.edu/~dmoore/maestro3.pdf.gz
56 */
57
58 #include <dev/sound/pcm/sound.h>
59 #include <dev/sound/pcm/ac97.h>
60
61 #include <bus/pci/pcireg.h>
62 #include <bus/pci/pcivar.h>
63
64 #include <dev/sound/pci/gnu/maestro3_reg.h>
65 #include <dev/sound/pci/gnu/maestro3_dsp.h>
66
67 SND_DECLARE_FILE("$DragonFly: src/sys/dev/sound/pci/maestro3.c,v 1.12 2007/06/16 20:07:19 dillon Exp $");
68
69 /* -------------------------------------------------------------------- */
70
71 enum {CHANGE=0, CALL=1, INTR=2, BORING=3, NONE=-1};
72 #ifndef M3_DEBUG_LEVEL
73 #define M3_DEBUG_LEVEL NONE
74 #endif
75 #define M3_DEBUG(level, _msg) {if ((level) <= M3_DEBUG_LEVEL) {kprintf _msg;}}
76
77 /* -------------------------------------------------------------------- */
78 enum {
79 ESS_ALLEGRO_1,
80 ESS_MAESTRO3
81 };
82
83 static struct m3_card_type {
84 u_int32_t pci_id; int which; int delay1; int delay2; char *name;
85 } m3_card_types[] = {
86 { 0x1988125d, ESS_ALLEGRO_1, 50, 800, "ESS Technology Allegro-1" },
87 { 0x1998125d, ESS_MAESTRO3, 20, 500, "ESS Technology Maestro3" },
88 { 0x199a125d, ESS_MAESTRO3, 20, 500, "ESS Technology Maestro3" },
89 { 0, 0, 0, 0, NULL }
90 };
91
92 #define M3_BUFSIZE_MIN 4096
93 #define M3_BUFSIZE_MAX 65536
94 #define M3_BUFSIZE_DEFAULT 4096
95 #define M3_PCHANS 4 /* create /dev/dsp0.[0-N] to use more than one */
96 #define M3_RCHANS 1
97 #define M3_MAXADDR ((1 << 27) - 1)
98
99 struct sc_info;
100
101 struct sc_pchinfo {
102 u_int32_t spd;
103 u_int32_t fmt;
104 struct snd_dbuf *buffer;
105 struct pcm_channel *channel;
106 struct sc_info *parent;
107 u_int32_t bufsize;
108 u_int32_t dac_data;
109 u_int32_t dac_idx;
110 u_int32_t active;
111 u_int32_t ptr;
112 u_int32_t prevptr;
113 };
114
115 struct sc_rchinfo {
116 u_int32_t spd;
117 u_int32_t fmt;
118 struct snd_dbuf *buffer;
119 struct pcm_channel *channel;
120 struct sc_info *parent;
121 u_int32_t bufsize;
122 u_int32_t adc_data;
123 u_int32_t adc_idx;
124 u_int32_t active;
125 u_int32_t ptr;
126 u_int32_t prevptr;
127 };
128
129 struct sc_info {
130 device_t dev;
131 u_int32_t type;
132 int which;
133 int delay1;
134 int delay2;
135
136 bus_space_tag_t st;
137 bus_space_handle_t sh;
138 bus_dma_tag_t parent_dmat;
139
140 struct resource *reg;
141 struct resource *irq;
142 int regtype;
143 int regid;
144 int irqid;
145 void *ih;
146
147 struct sc_pchinfo pch[M3_PCHANS];
148 struct sc_rchinfo rch[M3_RCHANS];
149 int pch_cnt;
150 int rch_cnt;
151 int pch_active_cnt;
152 unsigned int bufsz;
153 u_int16_t *savemem;
154
155 sndlock_t sc_lock;
156 };
157
158 #define M3_LOCK(_sc) snd_mtxlock((_sc)->sc_lock)
159 #define M3_UNLOCK(_sc) snd_mtxunlock((_sc)->sc_lock)
160 #define M3_LOCK_ASSERT(_sc) snd_mtxassert((_sc)->sc_lock)
161
162 /* -------------------------------------------------------------------- */
163
164 /* play channel interface */
165 static void *m3_pchan_init(kobj_t, void *, struct snd_dbuf *, struct pcm_channel *, int);
166 static int m3_pchan_free(kobj_t, void *);
167 static int m3_pchan_setformat(kobj_t, void *, u_int32_t);
168 static int m3_pchan_setspeed(kobj_t, void *, u_int32_t);
169 static int m3_pchan_setblocksize(kobj_t, void *, u_int32_t);
170 static int m3_pchan_trigger(kobj_t, void *, int);
171 static int m3_pchan_trigger_locked(kobj_t, void *, int);
172 static u_int32_t m3_pchan_getptr_internal(struct sc_pchinfo *);
173 static u_int32_t m3_pchan_getptr(kobj_t, void *);
174 static struct pcmchan_caps *m3_pchan_getcaps(kobj_t, void *);
175
176 /* record channel interface */
177 static void *m3_rchan_init(kobj_t, void *, struct snd_dbuf *, struct pcm_channel *, int);
178 static int m3_rchan_free(kobj_t, void *);
179 static int m3_rchan_setformat(kobj_t, void *, u_int32_t);
180 static int m3_rchan_setspeed(kobj_t, void *, u_int32_t);
181 static int m3_rchan_setblocksize(kobj_t, void *, u_int32_t);
182 static int m3_rchan_trigger(kobj_t, void *, int);
183 static int m3_rchan_trigger_locked(kobj_t, void *, int);
184 static u_int32_t m3_rchan_getptr_internal(struct sc_rchinfo *);
185 static u_int32_t m3_rchan_getptr(kobj_t, void *);
186 static struct pcmchan_caps *m3_rchan_getcaps(kobj_t, void *);
187
188 static int m3_chan_active(struct sc_info *);
189
190 /* talk to the codec - called from ac97.c */
191 static int m3_initcd(kobj_t, void *);
192 static int m3_rdcd(kobj_t, void *, int);
193 static int m3_wrcd(kobj_t, void *, int, u_int32_t);
194
195 /* stuff */
196 static void m3_intr(void *);
197 static int m3_power(struct sc_info *, int);
198 static int m3_init(struct sc_info *);
199 static int m3_uninit(struct sc_info *);
200 static u_int8_t m3_assp_halt(struct sc_info *);
201 static void m3_config(struct sc_info *);
202 static void m3_amp_enable(struct sc_info *);
203 static void m3_enable_ints(struct sc_info *);
204 static void m3_codec_reset(struct sc_info *);
205
206 /* -------------------------------------------------------------------- */
207 /* Codec descriptor */
208 static kobj_method_t m3_codec_methods[] = {
209 KOBJMETHOD(ac97_init, m3_initcd),
210 KOBJMETHOD(ac97_read, m3_rdcd),
211 KOBJMETHOD(ac97_write, m3_wrcd),
212 { 0, 0 }
213 };
214 AC97_DECLARE(m3_codec);
215
216 /* -------------------------------------------------------------------- */
217 /* channel descriptors */
218
219 static u_int32_t m3_playfmt[] = {
220 AFMT_U8,
221 AFMT_STEREO | AFMT_U8,
222 AFMT_S16_LE,
223 AFMT_STEREO | AFMT_S16_LE,
224 0
225 };
226 static struct pcmchan_caps m3_playcaps = {8000, 48000, m3_playfmt, 0};
227
228 static kobj_method_t m3_pch_methods[] = {
229 KOBJMETHOD(channel_init, m3_pchan_init),
230 KOBJMETHOD(channel_setformat, m3_pchan_setformat),
231 KOBJMETHOD(channel_setspeed, m3_pchan_setspeed),
232 KOBJMETHOD(channel_setblocksize, m3_pchan_setblocksize),
233 KOBJMETHOD(channel_trigger, m3_pchan_trigger),
234 KOBJMETHOD(channel_getptr, m3_pchan_getptr),
235 KOBJMETHOD(channel_getcaps, m3_pchan_getcaps),
236 KOBJMETHOD(channel_free, m3_pchan_free),
237 { 0, 0 }
238 };
239 CHANNEL_DECLARE(m3_pch);
240
241 static u_int32_t m3_recfmt[] = {
242 AFMT_U8,
243 AFMT_STEREO | AFMT_U8,
244 AFMT_S16_LE,
245 AFMT_STEREO | AFMT_S16_LE,
246 0
247 };
248 static struct pcmchan_caps m3_reccaps = {8000, 48000, m3_recfmt, 0};
249
250 static kobj_method_t m3_rch_methods[] = {
251 KOBJMETHOD(channel_init, m3_rchan_init),
252 KOBJMETHOD(channel_setformat, m3_rchan_setformat),
253 KOBJMETHOD(channel_setspeed, m3_rchan_setspeed),
254 KOBJMETHOD(channel_setblocksize, m3_rchan_setblocksize),
255 KOBJMETHOD(channel_trigger, m3_rchan_trigger),
256 KOBJMETHOD(channel_getptr, m3_rchan_getptr),
257 KOBJMETHOD(channel_getcaps, m3_rchan_getcaps),
258 KOBJMETHOD(channel_free, m3_rchan_free),
259 { 0, 0 }
260 };
261 CHANNEL_DECLARE(m3_rch);
262
263 /* -------------------------------------------------------------------- */
264 /* some i/o convenience functions */
265
266 #define m3_rd_1(sc, regno) bus_space_read_1(sc->st, sc->sh, regno)
267 #define m3_rd_2(sc, regno) bus_space_read_2(sc->st, sc->sh, regno)
268 #define m3_rd_4(sc, regno) bus_space_read_4(sc->st, sc->sh, regno)
269 #define m3_wr_1(sc, regno, data) bus_space_write_1(sc->st, sc->sh, regno, data)
270 #define m3_wr_2(sc, regno, data) bus_space_write_2(sc->st, sc->sh, regno, data)
271 #define m3_wr_4(sc, regno, data) bus_space_write_4(sc->st, sc->sh, regno, data)
272 #define m3_rd_assp_code(sc, index) \
273 m3_rd_assp(sc, MEMTYPE_INTERNAL_CODE, index)
274 #define m3_wr_assp_code(sc, index, data) \
275 m3_wr_assp(sc, MEMTYPE_INTERNAL_CODE, index, data)
276 #define m3_rd_assp_data(sc, index) \
277 m3_rd_assp(sc, MEMTYPE_INTERNAL_DATA, index)
278 #define m3_wr_assp_data(sc, index, data) \
279 m3_wr_assp(sc, MEMTYPE_INTERNAL_DATA, index, data)
280
281 static __inline u_int16_t
282 m3_rd_assp(struct sc_info *sc, u_int16_t region, u_int16_t index)
283 {
284 m3_wr_2(sc, DSP_PORT_MEMORY_TYPE, region & MEMTYPE_MASK);
285 m3_wr_2(sc, DSP_PORT_MEMORY_INDEX, index);
286 return m3_rd_2(sc, DSP_PORT_MEMORY_DATA);
287 }
288
289 static __inline void
290 m3_wr_assp(struct sc_info *sc, u_int16_t region, u_int16_t index,
291 u_int16_t data)
292 {
293 m3_wr_2(sc, DSP_PORT_MEMORY_TYPE, region & MEMTYPE_MASK);
294 m3_wr_2(sc, DSP_PORT_MEMORY_INDEX, index);
295 m3_wr_2(sc, DSP_PORT_MEMORY_DATA, data);
296 }
297
298 static __inline int
299 m3_wait(struct sc_info *sc)
300 {
301 int i;
302
303 for (i=0 ; i<20 ; i++) {
304 if ((m3_rd_1(sc, CODEC_STATUS) & 1) == 0) {
305 return 0;
306 }
307 DELAY(2);
308 }
309 return -1;
310 }
311
312 /* -------------------------------------------------------------------- */
313 /* ac97 codec */
314
315 static int
316 m3_initcd(kobj_t kobj, void *devinfo)
317 {
318 struct sc_info *sc = (struct sc_info *)devinfo;
319 u_int32_t data;
320
321 M3_DEBUG(CALL, ("m3_initcd\n"));
322
323 /* init ac-link */
324
325 data = m3_rd_1(sc, CODEC_COMMAND);
326 return ((data & 0x1) ? 0 : 1);
327 }
328
329 static int
330 m3_rdcd(kobj_t kobj, void *devinfo, int regno)
331 {
332 struct sc_info *sc = (struct sc_info *)devinfo;
333 u_int32_t data;
334
335 if (m3_wait(sc)) {
336 device_printf(sc->dev, "m3_rdcd timed out.\n");
337 return -1;
338 }
339 m3_wr_1(sc, CODEC_COMMAND, (regno & 0x7f) | 0x80);
340 DELAY(50); /* ac97 cycle = 20.8 usec */
341 if (m3_wait(sc)) {
342 device_printf(sc->dev, "m3_rdcd timed out.\n");
343 return -1;
344 }
345 data = m3_rd_2(sc, CODEC_DATA);
346 return data;
347 }
348
349 static int
350 m3_wrcd(kobj_t kobj, void *devinfo, int regno, u_int32_t data)
351 {
352 struct sc_info *sc = (struct sc_info *)devinfo;
353 if (m3_wait(sc)) {
354 device_printf(sc->dev, "m3_wrcd timed out.\n");
355 return -1;;
356 }
357 m3_wr_2(sc, CODEC_DATA, data);
358 m3_wr_1(sc, CODEC_COMMAND, regno & 0x7f);
359 DELAY(50); /* ac97 cycle = 20.8 usec */
360 return 0;
361 }
362
363 /* -------------------------------------------------------------------- */
364 /* play channel interface */
365
366 #define LO(x) (((x) & 0x0000ffff) )
367 #define HI(x) (((x) & 0xffff0000) >> 16)
368
369 static void *
370 m3_pchan_init(kobj_t kobj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir)
371 {
372 struct sc_info *sc = devinfo;
373 struct sc_pchinfo *ch;
374 u_int32_t bus_addr, i;
375 int idx, data_bytes, dac_data;
376 int dsp_in_size, dsp_out_size, dsp_in_buf, dsp_out_buf;
377
378 M3_LOCK(sc);
379 idx = sc->pch_cnt; /* dac instance number, no active reuse! */
380 M3_DEBUG(CHANGE, ("m3_pchan_init(dac=%d)\n", idx));
381
382 if (dir != PCMDIR_PLAY) {
383 M3_UNLOCK(sc);
384 device_printf(sc->dev, "m3_pchan_init not PCMDIR_PLAY\n");
385 return (NULL);
386 }
387
388 data_bytes = (((MINISRC_TMP_BUFFER_SIZE & ~1) +
389 (MINISRC_IN_BUFFER_SIZE & ~1) +
390 (MINISRC_OUT_BUFFER_SIZE & ~1) + 4) + 255) &~ 255;
391 dac_data = 0x1100 + (data_bytes * idx);
392
393 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x20 * 2);
394 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x20 * 2);
395 dsp_in_buf = dac_data + (MINISRC_TMP_BUFFER_SIZE/2);
396 dsp_out_buf = dsp_in_buf + (dsp_in_size/2) + 1;
397
398 ch = &sc->pch[idx];
399 ch->dac_idx = idx;
400 ch->dac_data = dac_data;
401 if (ch->dac_data + data_bytes/2 >= 0x1c00) {
402 M3_UNLOCK(sc);
403 device_printf(sc->dev, "m3_pchan_init: revb mem exhausted\n");
404 return (NULL);
405 }
406
407 ch->buffer = b;
408 ch->parent = sc;
409 ch->channel = c;
410 ch->fmt = AFMT_U8;
411 ch->spd = DSP_DEFAULT_SPEED;
412 M3_UNLOCK(sc); /* XXX */
413 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, sc->bufsz) != 0) {
414 device_printf(sc->dev, "m3_pchan_init chn_allocbuf failed\n");
415 return (NULL);
416 }
417 M3_LOCK(sc);
418 ch->bufsize = sndbuf_getsize(ch->buffer);
419
420 /* host dma buffer pointers */
421 bus_addr = sndbuf_getbufaddr(ch->buffer);
422 if (bus_addr & 3) {
423 device_printf(sc->dev, "m3_pchan_init unaligned bus_addr\n");
424 bus_addr = (bus_addr + 4) & ~3;
425 }
426 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_ADDRL, LO(bus_addr));
427 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_ADDRH, HI(bus_addr));
428 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_END_PLUS_1L,
429 LO(bus_addr + ch->bufsize));
430 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_END_PLUS_1H,
431 HI(bus_addr + ch->bufsize));
432 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_CURRENTL,
433 LO(bus_addr));
434 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_CURRENTH,
435 HI(bus_addr));
436
437 /* dsp buffers */
438 m3_wr_assp_data(sc, ch->dac_data + CDATA_IN_BUF_BEGIN, dsp_in_buf);
439 m3_wr_assp_data(sc, ch->dac_data + CDATA_IN_BUF_END_PLUS_1,
440 dsp_in_buf + dsp_in_size/2);
441 m3_wr_assp_data(sc, ch->dac_data + CDATA_IN_BUF_HEAD, dsp_in_buf);
442 m3_wr_assp_data(sc, ch->dac_data + CDATA_IN_BUF_TAIL, dsp_in_buf);
443 m3_wr_assp_data(sc, ch->dac_data + CDATA_OUT_BUF_BEGIN, dsp_out_buf);
444 m3_wr_assp_data(sc, ch->dac_data + CDATA_OUT_BUF_END_PLUS_1,
445 dsp_out_buf + dsp_out_size/2);
446 m3_wr_assp_data(sc, ch->dac_data + CDATA_OUT_BUF_HEAD, dsp_out_buf);
447 m3_wr_assp_data(sc, ch->dac_data + CDATA_OUT_BUF_TAIL, dsp_out_buf);
448
449 /* some per client initializers */
450 m3_wr_assp_data(sc, ch->dac_data + SRC3_DIRECTION_OFFSET + 12,
451 ch->dac_data + 40 + 8);
452 m3_wr_assp_data(sc, ch->dac_data + SRC3_DIRECTION_OFFSET + 19,
453 0x400 + MINISRC_COEF_LOC);
454 /* enable or disable low pass filter? (0xff if rate> 45000) */
455 m3_wr_assp_data(sc, ch->dac_data + SRC3_DIRECTION_OFFSET + 22, 0);
456 /* tell it which way dma is going? */
457 m3_wr_assp_data(sc, ch->dac_data + CDATA_DMA_CONTROL,
458 DMACONTROL_AUTOREPEAT + DMAC_PAGE3_SELECTOR +
459 DMAC_BLOCKF_SELECTOR);
460
461 /* set an armload of static initializers */
462 for(i = 0 ; i < (sizeof(pv) / sizeof(pv[0])) ; i++) {
463 m3_wr_assp_data(sc, ch->dac_data + pv[i].addr, pv[i].val);
464 }
465
466 /* put us in the packed task lists */
467 m3_wr_assp_data(sc, KDATA_INSTANCE0_MINISRC +
468 (sc->pch_cnt + sc->rch_cnt),
469 ch->dac_data >> DP_SHIFT_COUNT);
470 m3_wr_assp_data(sc, KDATA_DMA_XFER0 + (sc->pch_cnt + sc->rch_cnt),
471 ch->dac_data >> DP_SHIFT_COUNT);
472 m3_wr_assp_data(sc, KDATA_MIXER_XFER0 + sc->pch_cnt,
473 ch->dac_data >> DP_SHIFT_COUNT);
474
475 /* gotta start before stop */
476 m3_pchan_trigger_locked(NULL, ch, PCMTRIG_START);
477 /* silence noise on load */
478 m3_pchan_trigger_locked(NULL, ch, PCMTRIG_STOP);
479
480 sc->pch_cnt++;
481 M3_UNLOCK(sc);
482
483 return (ch);
484 }
485
486 static int
487 m3_pchan_free(kobj_t kobj, void *chdata)
488 {
489 struct sc_pchinfo *ch = chdata;
490 struct sc_info *sc = ch->parent;
491
492 M3_LOCK(sc);
493 M3_DEBUG(CHANGE, ("m3_pchan_free(dac=%d)\n", ch->dac_idx));
494
495 /*
496 * should remove this exact instance from the packed lists, but all
497 * are released at once (and in a stopped state) so this is ok.
498 */
499 m3_wr_assp_data(sc, KDATA_INSTANCE0_MINISRC +
500 (sc->pch_cnt - 1) + sc->rch_cnt, 0);
501 m3_wr_assp_data(sc, KDATA_DMA_XFER0 +
502 (sc->pch_cnt - 1) + sc->rch_cnt, 0);
503 m3_wr_assp_data(sc, KDATA_MIXER_XFER0 + (sc->pch_cnt-1), 0);
504 sc->pch_cnt--;
505 M3_UNLOCK(sc);
506
507 return (0);
508 }
509
510 static int
511 m3_pchan_setformat(kobj_t kobj, void *chdata, u_int32_t format)
512 {
513 struct sc_pchinfo *ch = chdata;
514 struct sc_info *sc = ch->parent;
515 u_int32_t data;
516
517 M3_LOCK(sc);
518 M3_DEBUG(CHANGE,
519 ("m3_pchan_setformat(dac=%d, format=0x%x{%s-%s})\n",
520 ch->dac_idx, format,
521 format & (AFMT_U8|AFMT_S8) ? "8bit":"16bit",
522 format & AFMT_STEREO ? "STEREO":"MONO"));
523
524 /* mono word */
525 data = (format & AFMT_STEREO) ? 0 : 1;
526 m3_wr_assp_data(sc, ch->dac_data + SRC3_MODE_OFFSET, data);
527
528 /* 8bit word */
529 data = ((format & AFMT_U8) || (format & AFMT_S8)) ? 1 : 0;
530 m3_wr_assp_data(sc, ch->dac_data + SRC3_WORD_LENGTH_OFFSET, data);
531
532 ch->fmt = format;
533 M3_UNLOCK(sc);
534
535 return (0);
536 }
537
538 static int
539 m3_pchan_setspeed(kobj_t kobj, void *chdata, u_int32_t speed)
540 {
541 struct sc_pchinfo *ch = chdata;
542 struct sc_info *sc = ch->parent;
543 u_int32_t freq;
544
545 M3_LOCK(sc);
546 M3_DEBUG(CHANGE, ("m3_pchan_setspeed(dac=%d, speed=%d)\n",
547 ch->dac_idx, speed));
548
549 if ((freq = ((speed << 15) + 24000) / 48000) != 0) {
550 freq--;
551 }
552
553 m3_wr_assp_data(sc, ch->dac_data + CDATA_FREQUENCY, freq);
554 ch->spd = speed;
555 M3_UNLOCK(sc);
556
557 /* return closest possible speed */
558 return (speed);
559 }
560
561 static int
562 m3_pchan_setblocksize(kobj_t kobj, void *chdata, u_int32_t blocksize)
563 {
564 struct sc_pchinfo *ch = chdata;
565
566 M3_DEBUG(CHANGE, ("m3_pchan_setblocksize(dac=%d, blocksize=%d)\n",
567 ch->dac_idx, blocksize));
568
569 return (sndbuf_getblksz(ch->buffer));
570 }
571
572 static int
573 m3_pchan_trigger(kobj_t kobj, void *chdata, int go)
574 {
575 struct sc_pchinfo *ch = chdata;
576 struct sc_info *sc = ch->parent;
577 int ret;
578
579 M3_LOCK(sc);
580 ret = m3_pchan_trigger_locked(kobj, chdata, go);
581 M3_UNLOCK(sc);
582
583 return (ret);
584 }
585
586 static int
587 m3_chan_active(struct sc_info *sc)
588 {
589 int i, ret;
590
591 ret = 0;
592
593 for (i = 0; i < sc->pch_cnt; i++)
594 ret += sc->pch[i].active;
595
596 for (i = 0; i < sc->rch_cnt; i++)
597 ret += sc->rch[i].active;
598
599 return (ret);
600 }
601
602 static int
603 m3_pchan_trigger_locked(kobj_t kobj, void *chdata, int go)
604 {
605 struct sc_pchinfo *ch = chdata;
606 struct sc_info *sc = ch->parent;
607 u_int32_t data;
608
609 M3_LOCK_ASSERT(sc);
610 M3_DEBUG(go == PCMTRIG_START ? CHANGE :
611 go == PCMTRIG_STOP ? CHANGE :
612 go == PCMTRIG_ABORT ? CHANGE :
613 CALL,
614 ("m3_pchan_trigger(dac=%d, go=0x%x{%s})\n", ch->dac_idx, go,
615 go == PCMTRIG_START ? "PCMTRIG_START" :
616 go == PCMTRIG_STOP ? "PCMTRIG_STOP" :
617 go == PCMTRIG_ABORT ? "PCMTRIG_ABORT" : "ignore"));
618
619 switch(go) {
620 case PCMTRIG_START:
621 if (ch->active) {
622 return 0;
623 }
624 ch->active = 1;
625 ch->ptr = 0;
626 ch->prevptr = 0;
627 sc->pch_active_cnt++;
628
629 /*[[inc_timer_users]]*/
630 if (m3_chan_active(sc) == 1) {
631 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_RELOAD, 240);
632 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_CURRENT, 240);
633 data = m3_rd_2(sc, HOST_INT_CTRL);
634 m3_wr_2(sc, HOST_INT_CTRL, data | CLKRUN_GEN_ENABLE);
635 }
636
637 m3_wr_assp_data(sc, ch->dac_data + CDATA_INSTANCE_READY, 1);
638 m3_wr_assp_data(sc, KDATA_MIXER_TASK_NUMBER,
639 sc->pch_active_cnt);
640 break;
641
642 case PCMTRIG_STOP:
643 case PCMTRIG_ABORT:
644 if (ch->active == 0) {
645 return 0;
646 }
647 ch->active = 0;
648 sc->pch_active_cnt--;
649
650 /* XXX should the channel be drained? */
651 /*[[dec_timer_users]]*/
652 if (m3_chan_active(sc) == 0) {
653 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_RELOAD, 0);
654 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_CURRENT, 0);
655 data = m3_rd_2(sc, HOST_INT_CTRL);
656 m3_wr_2(sc, HOST_INT_CTRL, data & ~CLKRUN_GEN_ENABLE);
657 }
658
659 m3_wr_assp_data(sc, ch->dac_data + CDATA_INSTANCE_READY, 0);
660 m3_wr_assp_data(sc, KDATA_MIXER_TASK_NUMBER,
661 sc->pch_active_cnt);
662 break;
663
664 case PCMTRIG_EMLDMAWR:
665 /* got play irq, transfer next buffer - ignore if using dma */
666 case PCMTRIG_EMLDMARD:
667 /* got rec irq, transfer next buffer - ignore if using dma */
668 default:
669 break;
670 }
671 return 0;
672 }
673
674 static u_int32_t
675 m3_pchan_getptr_internal(struct sc_pchinfo *ch)
676 {
677 struct sc_info *sc = ch->parent;
678 u_int32_t hi, lo, bus_base, bus_crnt;
679
680 bus_base = sndbuf_getbufaddr(ch->buffer);
681 hi = m3_rd_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_CURRENTH);
682 lo = m3_rd_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_CURRENTL);
683 bus_crnt = lo | (hi << 16);
684
685 M3_DEBUG(CALL, ("m3_pchan_getptr(dac=%d) result=%d\n",
686 ch->dac_idx, bus_crnt - bus_base));
687
688 return (bus_crnt - bus_base); /* current byte offset of channel */
689 }
690
691 static u_int32_t
692 m3_pchan_getptr(kobj_t kobj, void *chdata)
693 {
694 struct sc_pchinfo *ch = chdata;
695 struct sc_info *sc = ch->parent;
696 u_int32_t ptr;
697
698 M3_LOCK(sc);
699 ptr = ch->ptr;
700 M3_UNLOCK(sc);
701
702 return (ptr);
703 }
704
705 static struct pcmchan_caps *
706 m3_pchan_getcaps(kobj_t kobj, void *chdata)
707 {
708 struct sc_pchinfo *ch = chdata;
709
710 M3_DEBUG(CALL, ("m3_pchan_getcaps(dac=%d)\n", ch->dac_idx));
711
712 return &m3_playcaps;
713 }
714
715 /* -------------------------------------------------------------------- */
716 /* rec channel interface */
717
718 static void *
719 m3_rchan_init(kobj_t kobj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir)
720 {
721 struct sc_info *sc = devinfo;
722 struct sc_rchinfo *ch;
723 u_int32_t bus_addr, i;
724
725 int idx, data_bytes, adc_data;
726 int dsp_in_size, dsp_out_size, dsp_in_buf, dsp_out_buf;
727
728 M3_LOCK(sc);
729 idx = sc->rch_cnt; /* adc instance number, no active reuse! */
730 M3_DEBUG(CHANGE, ("m3_rchan_init(adc=%d)\n", idx));
731
732 if (dir != PCMDIR_REC) {
733 M3_UNLOCK(sc);
734 device_printf(sc->dev, "m3_pchan_init not PCMDIR_REC\n");
735 return (NULL);
736 }
737
738 data_bytes = (((MINISRC_TMP_BUFFER_SIZE & ~1) +
739 (MINISRC_IN_BUFFER_SIZE & ~1) +
740 (MINISRC_OUT_BUFFER_SIZE & ~1) + 4) + 255) &~ 255;
741 adc_data = 0x1100 + (data_bytes * idx) + data_bytes/2;
742 dsp_in_size = MINISRC_IN_BUFFER_SIZE + (0x10 * 2);
743 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x10 * 2);
744 dsp_in_buf = adc_data + (MINISRC_TMP_BUFFER_SIZE / 2);
745 dsp_out_buf = dsp_in_buf + (dsp_in_size / 2) + 1;
746
747 ch = &sc->rch[idx];
748 ch->adc_idx = idx;
749 ch->adc_data = adc_data;
750 if (ch->adc_data + data_bytes/2 >= 0x1c00) {
751 M3_UNLOCK(sc);
752 device_printf(sc->dev, "m3_rchan_init: revb mem exhausted\n");
753 return (NULL);
754 }
755
756 ch->buffer = b;
757 ch->parent = sc;
758 ch->channel = c;
759 ch->fmt = AFMT_U8;
760 ch->spd = DSP_DEFAULT_SPEED;
761 M3_UNLOCK(sc); /* XXX */
762 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, sc->bufsz) != 0) {
763 device_printf(sc->dev, "m3_rchan_init chn_allocbuf failed\n");
764 return (NULL);
765 }
766 M3_LOCK(sc);
767 ch->bufsize = sndbuf_getsize(ch->buffer);
768
769 /* host dma buffer pointers */
770 bus_addr = sndbuf_getbufaddr(ch->buffer);
771 if (bus_addr & 3) {
772 device_printf(sc->dev, "m3_rchan_init unaligned bus_addr\n");
773 bus_addr = (bus_addr + 4) & ~3;
774 }
775 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_ADDRL, LO(bus_addr));
776 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_ADDRH, HI(bus_addr));
777 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_END_PLUS_1L,
778 LO(bus_addr + ch->bufsize));
779 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_END_PLUS_1H,
780 HI(bus_addr + ch->bufsize));
781 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_CURRENTL,
782 LO(bus_addr));
783 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_CURRENTH,
784 HI(bus_addr));
785
786 /* dsp buffers */
787 m3_wr_assp_data(sc, ch->adc_data + CDATA_IN_BUF_BEGIN, dsp_in_buf);
788 m3_wr_assp_data(sc, ch->adc_data + CDATA_IN_BUF_END_PLUS_1,
789 dsp_in_buf + dsp_in_size/2);
790 m3_wr_assp_data(sc, ch->adc_data + CDATA_IN_BUF_HEAD, dsp_in_buf);
791 m3_wr_assp_data(sc, ch->adc_data + CDATA_IN_BUF_TAIL, dsp_in_buf);
792 m3_wr_assp_data(sc, ch->adc_data + CDATA_OUT_BUF_BEGIN, dsp_out_buf);
793 m3_wr_assp_data(sc, ch->adc_data + CDATA_OUT_BUF_END_PLUS_1,
794 dsp_out_buf + dsp_out_size/2);
795 m3_wr_assp_data(sc, ch->adc_data + CDATA_OUT_BUF_HEAD, dsp_out_buf);
796 m3_wr_assp_data(sc, ch->adc_data + CDATA_OUT_BUF_TAIL, dsp_out_buf);
797
798 /* some per client initializers */
799 m3_wr_assp_data(sc, ch->adc_data + SRC3_DIRECTION_OFFSET + 12,
800 ch->adc_data + 40 + 8);
801 m3_wr_assp_data(sc, ch->adc_data + CDATA_DMA_CONTROL,
802 DMACONTROL_DIRECTION + DMACONTROL_AUTOREPEAT +
803 DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
804
805 /* set an armload of static initializers */
806 for(i = 0 ; i < (sizeof(rv) / sizeof(rv[0])) ; i++) {
807 m3_wr_assp_data(sc, ch->adc_data + rv[i].addr, rv[i].val);
808 }
809
810 /* put us in the packed task lists */
811 m3_wr_assp_data(sc, KDATA_INSTANCE0_MINISRC +
812 (sc->pch_cnt + sc->rch_cnt),
813 ch->adc_data >> DP_SHIFT_COUNT);
814 m3_wr_assp_data(sc, KDATA_DMA_XFER0 + (sc->pch_cnt + sc->rch_cnt),
815 ch->adc_data >> DP_SHIFT_COUNT);
816 m3_wr_assp_data(sc, KDATA_ADC1_XFER0 + sc->rch_cnt,
817 ch->adc_data >> DP_SHIFT_COUNT);
818
819 /* gotta start before stop */
820 m3_rchan_trigger_locked(NULL, ch, PCMTRIG_START);
821 /* stop on init */
822 m3_rchan_trigger_locked(NULL, ch, PCMTRIG_STOP);
823
824 sc->rch_cnt++;
825 M3_UNLOCK(sc);
826
827 return (ch);
828 }
829
830 static int
831 m3_rchan_free(kobj_t kobj, void *chdata)
832 {
833 struct sc_rchinfo *ch = chdata;
834 struct sc_info *sc = ch->parent;
835
836 M3_LOCK(sc);
837 M3_DEBUG(CHANGE, ("m3_rchan_free(adc=%d)\n", ch->adc_idx));
838
839 /*
840 * should remove this exact instance from the packed lists, but all
841 * are released at once (and in a stopped state) so this is ok.
842 */
843 m3_wr_assp_data(sc, KDATA_INSTANCE0_MINISRC +
844 (sc->rch_cnt - 1) + sc->pch_cnt, 0);
845 m3_wr_assp_data(sc, KDATA_DMA_XFER0 +
846 (sc->rch_cnt - 1) + sc->pch_cnt, 0);
847 m3_wr_assp_data(sc, KDATA_ADC1_XFER0 + (sc->rch_cnt - 1), 0);
848 sc->rch_cnt--;
849 M3_UNLOCK(sc);
850
851 return (0);
852 }
853
854 static int
855 m3_rchan_setformat(kobj_t kobj, void *chdata, u_int32_t format)
856 {
857 struct sc_rchinfo *ch = chdata;
858 struct sc_info *sc = ch->parent;
859 u_int32_t data;
860
861 M3_LOCK(sc);
862 M3_DEBUG(CHANGE,
863 ("m3_rchan_setformat(dac=%d, format=0x%x{%s-%s})\n",
864 ch->adc_idx, format,
865 format & (AFMT_U8|AFMT_S8) ? "8bit":"16bit",
866 format & AFMT_STEREO ? "STEREO":"MONO"));
867
868 /* mono word */
869 data = (format & AFMT_STEREO) ? 0 : 1;
870 m3_wr_assp_data(sc, ch->adc_data + SRC3_MODE_OFFSET, data);
871
872 /* 8bit word */
873 data = ((format & AFMT_U8) || (format & AFMT_S8)) ? 1 : 0;
874 m3_wr_assp_data(sc, ch->adc_data + SRC3_WORD_LENGTH_OFFSET, data);
875 ch->fmt = format;
876 M3_UNLOCK(sc);
877
878 return (0);
879 }
880
881 static int
882 m3_rchan_setspeed(kobj_t kobj, void *chdata, u_int32_t speed)
883 {
884 struct sc_rchinfo *ch = chdata;
885 struct sc_info *sc = ch->parent;
886 u_int32_t freq;
887
888 M3_LOCK(sc);
889 M3_DEBUG(CHANGE, ("m3_rchan_setspeed(adc=%d, speed=%d)\n",
890 ch->adc_idx, speed));
891
892 if ((freq = ((speed << 15) + 24000) / 48000) != 0) {
893 freq--;
894 }
895
896 m3_wr_assp_data(sc, ch->adc_data + CDATA_FREQUENCY, freq);
897 ch->spd = speed;
898 M3_UNLOCK(sc);
899
900 /* return closest possible speed */
901 return (speed);
902 }
903
904 static int
905 m3_rchan_setblocksize(kobj_t kobj, void *chdata, u_int32_t blocksize)
906 {
907 struct sc_rchinfo *ch = chdata;
908
909 M3_DEBUG(CHANGE, ("m3_rchan_setblocksize(adc=%d, blocksize=%d)\n",
910 ch->adc_idx, blocksize));
911
912 return (sndbuf_getblksz(ch->buffer));
913 }
914
915 static int
916 m3_rchan_trigger(kobj_t kobj, void *chdata, int go)
917 {
918 struct sc_rchinfo *ch = chdata;
919 struct sc_info *sc = ch->parent;
920 int ret;
921
922 M3_LOCK(sc);
923 ret = m3_rchan_trigger_locked(kobj, chdata, go);
924 M3_UNLOCK(sc);
925
926 return (ret);
927 }
928
929 static int
930 m3_rchan_trigger_locked(kobj_t kobj, void *chdata, int go)
931 {
932 struct sc_rchinfo *ch = chdata;
933 struct sc_info *sc = ch->parent;
934 u_int32_t data;
935
936 M3_LOCK_ASSERT(sc);
937 M3_DEBUG(go == PCMTRIG_START ? CHANGE :
938 go == PCMTRIG_STOP ? CHANGE :
939 go == PCMTRIG_ABORT ? CHANGE :
940 CALL,
941 ("m3_rchan_trigger(adc=%d, go=0x%x{%s})\n", ch->adc_idx, go,
942 go == PCMTRIG_START ? "PCMTRIG_START" :
943 go == PCMTRIG_STOP ? "PCMTRIG_STOP" :
944 go == PCMTRIG_ABORT ? "PCMTRIG_ABORT" : "ignore"));
945
946 switch(go) {
947 case PCMTRIG_START:
948 if (ch->active) {
949 return 0;
950 }
951 ch->active = 1;
952 ch->ptr = 0;
953 ch->prevptr = 0;
954
955 /*[[inc_timer_users]]*/
956 if (m3_chan_active(sc) == 1) {
957 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_RELOAD, 240);
958 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_CURRENT, 240);
959 data = m3_rd_2(sc, HOST_INT_CTRL);
960 m3_wr_2(sc, HOST_INT_CTRL, data | CLKRUN_GEN_ENABLE);
961 }
962
963 m3_wr_assp_data(sc, KDATA_ADC1_REQUEST, 1);
964 m3_wr_assp_data(sc, ch->adc_data + CDATA_INSTANCE_READY, 1);
965 break;
966
967 case PCMTRIG_STOP:
968 case PCMTRIG_ABORT:
969 if (ch->active == 0) {
970 return 0;
971 }
972 ch->active = 0;
973
974 /*[[dec_timer_users]]*/
975 if (m3_chan_active(sc) == 0) {
976 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_RELOAD, 0);
977 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_CURRENT, 0);
978 data = m3_rd_2(sc, HOST_INT_CTRL);
979 m3_wr_2(sc, HOST_INT_CTRL, data & ~CLKRUN_GEN_ENABLE);
980 }
981
982 m3_wr_assp_data(sc, ch->adc_data + CDATA_INSTANCE_READY, 0);
983 m3_wr_assp_data(sc, KDATA_ADC1_REQUEST, 0);
984 break;
985
986 case PCMTRIG_EMLDMAWR:
987 /* got play irq, transfer next buffer - ignore if using dma */
988 case PCMTRIG_EMLDMARD:
989 /* got rec irq, transfer next buffer - ignore if using dma */
990 default:
991 break;
992 }
993 return 0;
994 }
995
996 static u_int32_t
997 m3_rchan_getptr_internal(struct sc_rchinfo *ch)
998 {
999 struct sc_info *sc = ch->parent;
1000 u_int32_t hi, lo, bus_base, bus_crnt;
1001
1002 bus_base = sndbuf_getbufaddr(ch->buffer);
1003 hi = m3_rd_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_CURRENTH);
1004 lo = m3_rd_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_CURRENTL);
1005 bus_crnt = lo | (hi << 16);
1006
1007 M3_DEBUG(CALL, ("m3_rchan_getptr(adc=%d) result=%d\n",
1008 ch->adc_idx, bus_crnt - bus_base));
1009
1010 return (bus_crnt - bus_base); /* current byte offset of channel */
1011 }
1012
1013 static u_int32_t
1014 m3_rchan_getptr(kobj_t kobj, void *chdata)
1015 {
1016 struct sc_rchinfo *ch = chdata;
1017 struct sc_info *sc = ch->parent;
1018 u_int32_t ptr;
1019
1020 M3_LOCK(sc);
1021 ptr = ch->ptr;
1022 M3_UNLOCK(sc);
1023
1024 return (ptr);
1025 }
1026
1027 static struct pcmchan_caps *
1028 m3_rchan_getcaps(kobj_t kobj, void *chdata)
1029 {
1030 struct sc_rchinfo *ch = chdata;
1031
1032 M3_DEBUG(CALL, ("m3_rchan_getcaps(adc=%d)\n", ch->adc_idx));
1033
1034 return &m3_reccaps;
1035 }
1036
1037 /* -------------------------------------------------------------------- */
1038 /* The interrupt handler */
1039
1040 static void
1041 m3_intr(void *p)
1042 {
1043 struct sc_info *sc = (struct sc_info *)p;
1044 struct sc_pchinfo *pch;
1045 struct sc_rchinfo *rch;
1046 u_int32_t status, ctl, i, delta;
1047
1048 M3_DEBUG(INTR, ("m3_intr\n"));
1049
1050 M3_LOCK(sc);
1051 status = m3_rd_1(sc, HOST_INT_STATUS);
1052 if (!status) {
1053 M3_UNLOCK(sc);
1054 return;
1055 }
1056
1057 m3_wr_1(sc, HOST_INT_STATUS, 0xff); /* ack the int? */
1058
1059 if (status & HV_INT_PENDING) {
1060 u_int8_t event;
1061
1062 event = m3_rd_1(sc, HW_VOL_COUNTER_MASTER);
1063 switch (event) {
1064 case 0x99:
1065 mixer_hwvol_mute(sc->dev);
1066 break;
1067 case 0xaa:
1068 mixer_hwvol_step(sc->dev, 1, 1);
1069 break;
1070 case 0x66:
1071 mixer_hwvol_step(sc->dev, -1, -1);
1072 break;
1073 case 0x88:
1074 break;
1075 default:
1076 device_printf(sc->dev, "Unknown HWVOL event\n");
1077 }
1078 m3_wr_1(sc, HW_VOL_COUNTER_MASTER, 0x88);
1079
1080 }
1081
1082 if (status & ASSP_INT_PENDING) {
1083 ctl = m3_rd_1(sc, ASSP_CONTROL_B);
1084 if (!(ctl & STOP_ASSP_CLOCK)) {
1085 ctl = m3_rd_1(sc, ASSP_HOST_INT_STATUS);
1086 if (ctl & DSP2HOST_REQ_TIMER) {
1087 m3_wr_1(sc, ASSP_HOST_INT_STATUS,
1088 DSP2HOST_REQ_TIMER);
1089 /*[[ess_update_ptr]]*/
1090 goto m3_handle_channel_intr;
1091 }
1092 }
1093 }
1094
1095 goto m3_handle_channel_intr_out;
1096
1097 m3_handle_channel_intr:
1098 for (i=0 ; i<sc->pch_cnt ; i++) {
1099 pch = &sc->pch[i];
1100 if (pch->active) {
1101 pch->ptr = m3_pchan_getptr_internal(pch);
1102 delta = pch->bufsize + pch->ptr - pch->prevptr;
1103 delta %= pch->bufsize;
1104 if (delta < sndbuf_getblksz(pch->buffer))
1105 continue;
1106 pch->prevptr = pch->ptr;
1107 M3_UNLOCK(sc);
1108 chn_intr(pch->channel);
1109 M3_LOCK(sc);
1110 }
1111 }
1112 for (i=0 ; i<sc->rch_cnt ; i++) {
1113 rch = &sc->rch[i];
1114 if (rch->active) {
1115 rch->ptr = m3_rchan_getptr_internal(rch);
1116 delta = rch->bufsize + rch->ptr - rch->prevptr;
1117 delta %= rch->bufsize;
1118 if (delta < sndbuf_getblksz(rch->buffer))
1119 continue;
1120 rch->prevptr = rch->ptr;
1121 M3_UNLOCK(sc);
1122 chn_intr(rch->channel);
1123 M3_LOCK(sc);
1124 }
1125 }
1126
1127 m3_handle_channel_intr_out:
1128 M3_UNLOCK(sc);
1129 }
1130
1131 /* -------------------------------------------------------------------- */
1132 /* stuff */
1133
1134 static int
1135 m3_power(struct sc_info *sc, int state)
1136 {
1137 u_int32_t data;
1138
1139 M3_DEBUG(CHANGE, ("m3_power(%d)\n", state));
1140 M3_LOCK_ASSERT(sc);
1141
1142 data = pci_read_config(sc->dev, 0x34, 1);
1143 if (pci_read_config(sc->dev, data, 1) == 1) {
1144 pci_write_config(sc->dev, data + 4, state, 1);
1145 }
1146
1147 return 0;
1148 }
1149
1150 static int
1151 m3_init(struct sc_info *sc)
1152 {
1153 u_int32_t data, i, size;
1154 u_int8_t reset_state;
1155
1156 M3_LOCK_ASSERT(sc);
1157 M3_DEBUG(CHANGE, ("m3_init\n"));
1158
1159 /* diable legacy emulations. */
1160 data = pci_read_config(sc->dev, PCI_LEGACY_AUDIO_CTRL, 2);
1161 data |= DISABLE_LEGACY;
1162 pci_write_config(sc->dev, PCI_LEGACY_AUDIO_CTRL, data, 2);
1163
1164 m3_config(sc);
1165
1166 reset_state = m3_assp_halt(sc);
1167
1168 m3_codec_reset(sc);
1169
1170 /* [m3_assp_init] */
1171 /* zero kernel data */
1172 size = REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA;
1173 for(i = 0 ; i < size / 2 ; i++) {
1174 m3_wr_assp_data(sc, KDATA_BASE_ADDR + i, 0);
1175 }
1176 /* zero mixer data? */
1177 size = REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA;
1178 for(i = 0 ; i < size / 2 ; i++) {
1179 m3_wr_assp_data(sc, KDATA_BASE_ADDR2 + i, 0);
1180 }
1181 /* init dma pointer */
1182 m3_wr_assp_data(sc, KDATA_CURRENT_DMA,
1183 KDATA_DMA_XFER0);
1184 /* write kernel into code memory */
1185 size = sizeof(assp_kernel_image);
1186 for(i = 0 ; i < size / 2; i++) {
1187 m3_wr_assp_code(sc, REV_B_CODE_MEMORY_BEGIN + i,
1188 assp_kernel_image[i]);
1189 }
1190 /*
1191 * We only have this one client and we know that 0x400 is kfree in
1192 * our kernel's mem map, so lets just drop it there. It seems that
1193 * the minisrc doesn't need vectors, so we won't bother with them..
1194 */
1195 size = sizeof(assp_minisrc_image);
1196 for(i = 0 ; i < size / 2; i++) {
1197 m3_wr_assp_code(sc, 0x400 + i, assp_minisrc_image[i]);
1198 }
1199 /* write the coefficients for the low pass filter? */
1200 size = sizeof(minisrc_lpf_image);
1201 for(i = 0; i < size / 2 ; i++) {
1202 m3_wr_assp_code(sc,0x400 + MINISRC_COEF_LOC + i,
1203 minisrc_lpf_image[i]);
1204 }
1205 m3_wr_assp_code(sc, 0x400 + MINISRC_COEF_LOC + size, 0x8000);
1206 /* the minisrc is the only thing on our task list */
1207 m3_wr_assp_data(sc, KDATA_TASK0, 0x400);
1208 /* init the mixer number */
1209 m3_wr_assp_data(sc, KDATA_MIXER_TASK_NUMBER, 0);
1210 /* extreme kernel master volume */
1211 m3_wr_assp_data(sc, KDATA_DAC_LEFT_VOLUME, ARB_VOLUME);
1212 m3_wr_assp_data(sc, KDATA_DAC_RIGHT_VOLUME, ARB_VOLUME);
1213
1214 m3_amp_enable(sc);
1215
1216 /* [m3_assp_client_init] (only one client at index 0) */
1217 for (i=0x1100 ; i<0x1c00 ; i++) {
1218 m3_wr_assp_data(sc, i, 0); /* zero entire dac/adc area */
1219 }
1220
1221 /* [m3_assp_continue] */
1222 m3_wr_1(sc, DSP_PORT_CONTROL_REG_B, reset_state | REGB_ENABLE_RESET);
1223
1224 return 0;
1225 }
1226
1227 static int
1228 m3_uninit(struct sc_info *sc)
1229 {
1230 M3_DEBUG(CHANGE, ("m3_uninit\n"));
1231 return 0;
1232 }
1233
1234 /* -------------------------------------------------------------------- */
1235 /* Probe and attach the card */
1236
1237 static int
1238 m3_pci_probe(device_t dev)
1239 {
1240 struct m3_card_type *card;
1241
1242 M3_DEBUG(CALL, ("m3_pci_probe(0x%x)\n", pci_get_devid(dev)));
1243
1244 for (card = m3_card_types ; card->pci_id ; card++) {
1245 if (pci_get_devid(dev) == card->pci_id) {
1246 device_set_desc(dev, card->name);
1247 return BUS_PROBE_DEFAULT;
1248 }
1249 }
1250 return ENXIO;
1251 }
1252
1253 static int
1254 m3_pci_attach(device_t dev)
1255 {
1256 struct sc_info *sc;
1257 struct ac97_info *codec = NULL;
1258 u_int32_t data;
1259 char status[SND_STATUSLEN];
1260 struct m3_card_type *card;
1261 int i, len, dacn, adcn;
1262
1263 M3_DEBUG(CALL, ("m3_pci_attach\n"));
1264
1265 if ((sc = kmalloc(sizeof(*sc), M_DEVBUF, M_NOWAIT | M_ZERO)) == NULL) {
1266 device_printf(dev, "cannot allocate softc\n");
1267 return ENXIO;
1268 }
1269
1270 sc->dev = dev;
1271 sc->type = pci_get_devid(dev);
1272 sc->sc_lock = snd_mtxcreate(device_get_nameunit(dev),
1273 "sound softc");
1274 if (sc->sc_lock == NULL) {
1275 device_printf(dev, "cannot create mutex\n");
1276 kfree(sc, M_DEVBUF);
1277 return (ENXIO);
1278 }
1279 for (card = m3_card_types ; card->pci_id ; card++) {
1280 if (sc->type == card->pci_id) {
1281 sc->which = card->which;
1282 sc->delay1 = card->delay1;
1283 sc->delay2 = card->delay2;
1284 break;
1285 }
1286 }
1287
1288 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
1289 "dac", &i) == 0) {
1290 if (i < 1)
1291 dacn = 1;
1292 else if (i > M3_PCHANS)
1293 dacn = M3_PCHANS;
1294 else
1295 dacn = i;
1296 } else
1297 dacn = M3_PCHANS;
1298
1299 adcn = M3_RCHANS;
1300
1301 data = pci_read_config(dev, PCIR_COMMAND, 2);
1302 data |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
1303 pci_write_config(dev, PCIR_COMMAND, data, 2);
1304
1305 sc->regid = PCIR_BAR(0);
1306 sc->regtype = SYS_RES_MEMORY;
1307 sc->reg = bus_alloc_resource_any(dev, sc->regtype, &sc->regid,
1308 RF_ACTIVE);
1309 if (!sc->reg) {
1310 sc->regtype = SYS_RES_IOPORT;
1311 sc->reg = bus_alloc_resource_any(dev, sc->regtype, &sc->regid,
1312 RF_ACTIVE);
1313 }
1314 if (!sc->reg) {
1315 device_printf(dev, "unable to allocate register space\n");
1316 goto bad;
1317 }
1318 sc->st = rman_get_bustag(sc->reg);
1319 sc->sh = rman_get_bushandle(sc->reg);
1320
1321 sc->irqid = 0;
1322 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irqid,
1323 RF_ACTIVE | RF_SHAREABLE);
1324 if (!sc->irq) {
1325 device_printf(dev, "unable to allocate interrupt\n");
1326 goto bad;
1327 }
1328
1329 if (snd_setup_intr(dev, sc->irq, INTR_MPSAFE, m3_intr, sc, &sc->ih)) {
1330 device_printf(dev, "unable to setup interrupt\n");
1331 goto bad;
1332 }
1333
1334 sc->bufsz = pcm_getbuffersize(dev, M3_BUFSIZE_MIN, M3_BUFSIZE_DEFAULT,
1335 M3_BUFSIZE_MAX);
1336
1337 if (bus_dma_tag_create(
1338 NULL, /* parent */
1339 2, 0, /* alignment, boundary */
1340 M3_MAXADDR, /* lowaddr */
1341 BUS_SPACE_MAXADDR, /* highaddr */
1342 NULL, NULL, /* filtfunc, filtfuncarg */
1343 sc->bufsz, /* maxsize */
1344 1, /* nsegments */
1345 0x3ffff, /* maxsegz */
1346 0, /* flags */
1347 &sc->parent_dmat) != 0) {
1348 device_printf(dev, "unable to create dma tag\n");
1349 goto bad;
1350 }
1351
1352 M3_LOCK(sc);
1353 m3_power(sc, 0); /* power up */
1354 /* init chip */
1355 i = m3_init(sc);
1356 M3_UNLOCK(sc);
1357 if (i == -1) {
1358 device_printf(dev, "unable to initialize the card\n");
1359 goto bad;
1360 }
1361
1362 /* create/init mixer */
1363 codec = AC97_CREATE(dev, sc, m3_codec);
1364 if (codec == NULL) {
1365 device_printf(dev, "ac97_create error\n");
1366 goto bad;
1367 }
1368 if (mixer_init(dev, ac97_getmixerclass(), codec)) {
1369 device_printf(dev, "mixer_init error\n");
1370 goto bad;
1371 }
1372
1373 m3_enable_ints(sc);
1374
1375 if (pcm_register(dev, sc, dacn, adcn)) {
1376 device_printf(dev, "pcm_register error\n");
1377 goto bad;
1378 }
1379 for (i=0 ; i<dacn ; i++) {
1380 if (pcm_addchan(dev, PCMDIR_PLAY, &m3_pch_class, sc)) {
1381 device_printf(dev, "pcm_addchan (play) error\n");
1382 goto bad;
1383 }
1384 }
1385 for (i=0 ; i<adcn ; i++) {
1386 if (pcm_addchan(dev, PCMDIR_REC, &m3_rch_class, sc)) {
1387 device_printf(dev, "pcm_addchan (rec) error\n");
1388 goto bad;
1389 }
1390 }
1391 ksnprintf(status, SND_STATUSLEN, "at %s 0x%lx irq %ld %s",
1392 (sc->regtype == SYS_RES_IOPORT)? "io" : "memory",
1393 rman_get_start(sc->reg), rman_get_start(sc->irq),
1394 PCM_KLDSTRING(snd_maestro3));
1395 if (pcm_setstatus(dev, status)) {
1396 device_printf(dev, "attach: pcm_setstatus error\n");
1397 goto bad;
1398 }
1399
1400 mixer_hwvol_init(dev);
1401
1402 /* Create the buffer for saving the card state during suspend */
1403 len = sizeof(u_int16_t) * (REV_B_CODE_MEMORY_LENGTH +
1404 REV_B_DATA_MEMORY_LENGTH);
1405 sc->savemem = (u_int16_t*)kmalloc(len, M_DEVBUF, M_NOWAIT | M_ZERO);
1406 if (sc->savemem == NULL) {
1407 device_printf(dev, "Failed to create suspend buffer\n");
1408 goto bad;
1409 }
1410
1411 return 0;
1412
1413 bad:
1414 if (codec)
1415 ac97_destroy(codec);
1416 if (sc->ih)
1417 bus_teardown_intr(dev, sc->irq, sc->ih);
1418 if (sc->irq)
1419 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
1420 if (sc->reg)
1421 bus_release_resource(dev, sc->regtype, sc->regid, sc->reg);
1422 if (sc->parent_dmat)
1423 bus_dma_tag_destroy(sc->parent_dmat);
1424 if (sc->sc_lock)
1425 snd_mtxfree(sc->sc_lock);
1426 kfree(sc, M_DEVBUF);
1427 return ENXIO;
1428 }
1429
1430 static int
1431 m3_pci_detach(device_t dev)
1432 {
1433 struct sc_info *sc = pcm_getdevinfo(dev);
1434 int r;
1435
1436 M3_DEBUG(CALL, ("m3_pci_detach\n"));
1437
1438 if ((r = pcm_unregister(dev)) != 0) {
1439 return r;
1440 }
1441
1442 M3_LOCK(sc);
1443 m3_uninit(sc); /* shutdown chip */
1444 m3_power(sc, 3); /* power off */
1445 M3_UNLOCK(sc);
1446
1447 bus_teardown_intr(dev, sc->irq, sc->ih);
1448 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
1449 bus_release_resource(dev, sc->regtype, sc->regid, sc->reg);
1450 bus_dma_tag_destroy(sc->parent_dmat);
1451
1452 kfree(sc->savemem, M_DEVBUF);
1453 snd_mtxfree(sc->sc_lock);
1454 kfree(sc, M_DEVBUF);
1455 return 0;
1456 }
1457
1458 static int
1459 m3_pci_suspend(device_t dev)
1460 {
1461 struct sc_info *sc = pcm_getdevinfo(dev);
1462 int i, index = 0;
1463
1464 M3_DEBUG(CHANGE, ("m3_pci_suspend\n"));
1465
1466 M3_LOCK(sc);
1467 for (i=0 ; i<sc->pch_cnt ; i++) {
1468 if (sc->pch[i].active) {
1469 m3_pchan_trigger_locked(NULL, &sc->pch[i],
1470 PCMTRIG_STOP);
1471 }
1472 }
1473 for (i=0 ; i<sc->rch_cnt ; i++) {
1474 if (sc->rch[i].active) {
1475 m3_rchan_trigger_locked(NULL, &sc->rch[i],
1476 PCMTRIG_STOP);
1477 }
1478 }
1479 DELAY(10 * 1000); /* give things a chance to stop */
1480
1481 /* Disable interrupts */
1482 m3_wr_2(sc, HOST_INT_CTRL, 0);
1483 m3_wr_1(sc, ASSP_CONTROL_C, 0);
1484
1485 m3_assp_halt(sc);
1486
1487 /* Save the state of the ASSP */
1488 for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
1489 sc->savemem[index++] = m3_rd_assp_code(sc, i);
1490 for (i = REV_B_DATA_MEMORY_BEGIN; i <= REV_B_DATA_MEMORY_END; i++)
1491 sc->savemem[index++] = m3_rd_assp_data(sc, i);
1492
1493 /* Power down the card to D3 state */
1494 m3_power(sc, 3);
1495 M3_UNLOCK(sc);
1496
1497 return 0;
1498 }
1499
1500 static int
1501 m3_pci_resume(device_t dev)
1502 {
1503 struct sc_info *sc = pcm_getdevinfo(dev);
1504 int i, index = 0;
1505 u_int8_t reset_state;
1506
1507 M3_DEBUG(CHANGE, ("m3_pci_resume\n"));
1508
1509 M3_LOCK(sc);
1510 /* Power the card back to D0 */
1511 m3_power(sc, 0);
1512
1513 m3_config(sc);
1514
1515 reset_state = m3_assp_halt(sc);
1516
1517 m3_codec_reset(sc);
1518
1519 /* Restore the ASSP state */
1520 for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
1521 m3_wr_assp_code(sc, i, sc->savemem[index++]);
1522 for (i = REV_B_DATA_MEMORY_BEGIN; i <= REV_B_DATA_MEMORY_END; i++)
1523 m3_wr_assp_data(sc, i, sc->savemem[index++]);
1524
1525 /* Restart the DMA engine */
1526 m3_wr_assp_data(sc, KDATA_DMA_ACTIVE, 0);
1527
1528 /* [m3_assp_continue] */
1529 m3_wr_1(sc, DSP_PORT_CONTROL_REG_B, reset_state | REGB_ENABLE_RESET);
1530
1531 m3_amp_enable(sc);
1532
1533 m3_enable_ints(sc);
1534
1535 M3_UNLOCK(sc); /* XXX */
1536 if (mixer_reinit(dev) == -1) {
1537 device_printf(dev, "unable to reinitialize the mixer\n");
1538 return (ENXIO);
1539 }
1540 M3_LOCK(sc);
1541
1542 /* Turn the channels back on */
1543 for (i=0 ; i<sc->pch_cnt ; i++) {
1544 if (sc->pch[i].active) {
1545 m3_pchan_trigger_locked(NULL, &sc->pch[i],
1546 PCMTRIG_START);
1547 }
1548 }
1549 for (i=0 ; i<sc->rch_cnt ; i++) {
1550 if (sc->rch[i].active) {
1551 m3_rchan_trigger_locked(NULL, &sc->rch[i],
1552 PCMTRIG_START);
1553 }
1554 }
1555
1556 M3_UNLOCK(sc);
1557 return 0;
1558 }
1559
1560 static int
1561 m3_pci_shutdown(device_t dev)
1562 {
1563 struct sc_info *sc = pcm_getdevinfo(dev);
1564
1565 M3_DEBUG(CALL, ("m3_pci_shutdown\n"));
1566
1567 M3_LOCK(sc);
1568 m3_power(sc, 3); /* power off */
1569 M3_UNLOCK(sc);
1570
1571 return 0;
1572 }
1573
1574 static u_int8_t
1575 m3_assp_halt(struct sc_info *sc)
1576 {
1577 u_int8_t data, reset_state;
1578
1579 M3_LOCK_ASSERT(sc);
1580
1581 data = m3_rd_1(sc, DSP_PORT_CONTROL_REG_B);
1582 reset_state = data & ~REGB_STOP_CLOCK; /* remember for continue */
1583 DELAY(10 * 1000);
1584 m3_wr_1(sc, DSP_PORT_CONTROL_REG_B, reset_state & ~REGB_ENABLE_RESET);
1585 DELAY(10 * 1000); /* necessary? */
1586
1587 return reset_state;
1588 }
1589
1590 static void
1591 m3_config(struct sc_info *sc)
1592 {
1593 u_int32_t data, hv_cfg;
1594 int hint;
1595
1596 M3_LOCK_ASSERT(sc);
1597
1598 M3_UNLOCK(sc);
1599 /*
1600 * The volume buttons can be wired up via two different sets of pins.
1601 * This presents a problem since we can't tell which way it's
1602 * configured. Allow the user to set a hint in order to twiddle
1603 * the proper bits.
1604 */
1605 if (resource_int_value(device_get_name(sc->dev),
1606 device_get_unit(sc->dev),
1607 "hwvol_config", &hint) == 0)
1608 hv_cfg = (hint > 0) ? HV_BUTTON_FROM_GD : 0;
1609 else
1610 hv_cfg = HV_BUTTON_FROM_GD;
1611 M3_LOCK(sc);
1612
1613 data = pci_read_config(sc->dev, PCI_ALLEGRO_CONFIG, 4);
1614 data &= ~HV_BUTTON_FROM_GD;
1615 data |= REDUCED_DEBOUNCE | HV_CTRL_ENABLE | hv_cfg;
1616 data |= PM_CTRL_ENABLE | CLK_DIV_BY_49 | USE_PCI_TIMING;
1617 pci_write_config(sc->dev, PCI_ALLEGRO_CONFIG, data, 4);
1618
1619 m3_wr_1(sc, ASSP_CONTROL_B, RESET_ASSP);
1620 data = pci_read_config(sc->dev, PCI_ALLEGRO_CONFIG, 4);
1621 data &= ~INT_CLK_SELECT;
1622 if (sc->which == ESS_MAESTRO3) {
1623 data &= ~INT_CLK_MULT_ENABLE;
1624 data |= INT_CLK_SRC_NOT_PCI;
1625 }
1626 data &= ~(CLK_MULT_MODE_SELECT | CLK_MULT_MODE_SELECT_2);
1627 pci_write_config(sc->dev, PCI_ALLEGRO_CONFIG, data, 4);
1628
1629 if (sc->which == ESS_ALLEGRO_1) {
1630 data = pci_read_config(sc->dev, PCI_USER_CONFIG, 4);
1631 data |= IN_CLK_12MHZ_SELECT;
1632 pci_write_config(sc->dev, PCI_USER_CONFIG, data, 4);
1633 }
1634
1635 data = m3_rd_1(sc, ASSP_CONTROL_A);
1636 data &= ~(DSP_CLK_36MHZ_SELECT | ASSP_CLK_49MHZ_SELECT);
1637 data |= ASSP_CLK_49MHZ_SELECT; /*XXX assumes 49MHZ dsp XXX*/
1638 data |= ASSP_0_WS_ENABLE;
1639 m3_wr_1(sc, ASSP_CONTROL_A, data);
1640
1641 m3_wr_1(sc, ASSP_CONTROL_B, RUN_ASSP);
1642 }
1643
1644 static void
1645 m3_enable_ints(struct sc_info *sc)
1646 {
1647 u_int8_t data;
1648
1649 m3_wr_2(sc, HOST_INT_CTRL, ASSP_INT_ENABLE | HV_INT_ENABLE);
1650 data = m3_rd_1(sc, ASSP_CONTROL_C);
1651 m3_wr_1(sc, ASSP_CONTROL_C, data | ASSP_HOST_INT_ENABLE);
1652 }
1653
1654 static void
1655 m3_amp_enable(struct sc_info *sc)
1656 {
1657 u_int32_t gpo, polarity_port, polarity;
1658 u_int16_t data;
1659
1660 M3_LOCK_ASSERT(sc);
1661
1662 switch (sc->which) {
1663 case ESS_ALLEGRO_1:
1664 polarity_port = 0x1800;
1665 break;
1666 case ESS_MAESTRO3:
1667 polarity_port = 0x1100;
1668 break;
1669 default:
1670 panic("bad sc->which");
1671 }
1672 gpo = (polarity_port >> 8) & 0x0f;
1673 polarity = polarity_port >> 12;
1674 polarity = !polarity; /* enable */
1675 polarity = polarity << gpo;
1676 gpo = 1 << gpo;
1677 m3_wr_2(sc, GPIO_MASK, ~gpo);
1678 data = m3_rd_2(sc, GPIO_DIRECTION);
1679 m3_wr_2(sc, GPIO_DIRECTION, data | gpo);
1680 data = GPO_SECONDARY_AC97 | GPO_PRIMARY_AC97 | polarity;
1681 m3_wr_2(sc, GPIO_DATA, data);
1682 m3_wr_2(sc, GPIO_MASK, ~0);
1683 }
1684
1685 static void
1686 m3_codec_reset(struct sc_info *sc)
1687 {
1688 u_int16_t data, dir;
1689 int retry = 0;
1690
1691 M3_LOCK_ASSERT(sc);
1692 do {
1693 data = m3_rd_2(sc, GPIO_DIRECTION);
1694 dir = data | 0x10; /* assuming pci bus master? */
1695
1696 /* [[remote_codec_config]] */
1697 data = m3_rd_2(sc, RING_BUS_CTRL_B);
1698 m3_wr_2(sc, RING_BUS_CTRL_B, data & ~SECOND_CODEC_ID_MASK);
1699 data = m3_rd_2(sc, SDO_OUT_DEST_CTRL);
1700 m3_wr_2(sc, SDO_OUT_DEST_CTRL, data & ~COMMAND_ADDR_OUT);
1701 data = m3_rd_2(sc, SDO_IN_DEST_CTRL);
1702 m3_wr_2(sc, SDO_IN_DEST_CTRL, data & ~STATUS_ADDR_IN);
1703
1704 m3_wr_2(sc, RING_BUS_CTRL_A, IO_SRAM_ENABLE);
1705 DELAY(20);
1706
1707 m3_wr_2(sc, GPIO_DIRECTION, dir & ~GPO_PRIMARY_AC97);
1708 m3_wr_2(sc, GPIO_MASK, ~GPO_PRIMARY_AC97);
1709 m3_wr_2(sc, GPIO_DATA, 0);
1710 m3_wr_2(sc, GPIO_DIRECTION, dir | GPO_PRIMARY_AC97);
1711 DELAY(sc->delay1 * 1000); /*delay1 (ALLEGRO:50, MAESTRO3:20)*/
1712 m3_wr_2(sc, GPIO_DATA, GPO_PRIMARY_AC97);
1713 DELAY(5);
1714 m3_wr_2(sc, RING_BUS_CTRL_A, IO_SRAM_ENABLE |
1715 SERIAL_AC_LINK_ENABLE);
1716 m3_wr_2(sc, GPIO_MASK, ~0);
1717 DELAY(sc->delay2 * 1000); /*delay2 (ALLEGRO:800, MAESTRO3:500)*/
1718
1719 /* [[try read vendor]] */
1720 data = m3_rdcd(NULL, sc, 0x7c);
1721 if ((data == 0) || (data == 0xffff)) {
1722 retry++;
1723 if (retry > 3) {
1724 device_printf(sc->dev, "Codec reset failed\n");
1725 break;
1726 }
1727 device_printf(sc->dev, "Codec reset retry\n");
1728 } else retry = 0;
1729 } while (retry);
1730 }
1731
1732 static device_method_t m3_methods[] = {
1733 DEVMETHOD(device_probe, m3_pci_probe),
1734 DEVMETHOD(device_attach, m3_pci_attach),
1735 DEVMETHOD(device_detach, m3_pci_detach),
1736 DEVMETHOD(device_suspend, m3_pci_suspend),
1737 DEVMETHOD(device_resume, m3_pci_resume),
1738 DEVMETHOD(device_shutdown, m3_pci_shutdown),
1739 { 0, 0 }
1740 };
1741
1742 static driver_t m3_driver = {
1743 "pcm",
1744 m3_methods,
1745 PCM_SOFTC_SIZE,
1746 };
1747
1748 DRIVER_MODULE(snd_maestro3, pci, m3_driver, pcm_devclass, 0, 0);
1749 MODULE_DEPEND(snd_maestro3, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
1750 MODULE_VERSION(snd_maestro3, 1);
DragonFly BSD