sys/dev/sound/pci/es137x.h

   1 /*-
   2  * This supports the ENSONIQ AudioPCI board based on the ES1370.
   3  *
   4  * Copyright (c) 1998 Joachim Kuebart <joki@kuebart.stuttgart.netsurf.de>
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice immediately at the beginning of the file, without modification,
  12  *    this list of conditions, and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  * 3. Absolutely no warranty of function or purpose is made by the author
  17  *    Joachim Kuebart.
  18  * 4. Modifications may be freely made to this file if the above conditions
  19  *    are met.
  20  *
  21  * $FreeBSD: src/sys/dev/sound/pci/es137x.h,v 1.5.2.1 2005/12/30 19:55:53 netchild Exp $
  22  * $DragonFly: src/sys/dev/sound/pci/es137x.h,v 1.3 2007/01/04 21:47:02 corecode Exp $
  23  */
  24
  25 #ifndef _ES1370_REG_H
  26 #define _ES1370_REG_H
  27
  28 #define ES1370_REG_CONTROL              0x00
  29 #define ES1370_REG_STATUS               0x04
  30 #define ES1370_REG_UART_DATA            0x08
  31 #define ES1370_REG_UART_STATUS          0x09
  32 #define ES1370_REG_UART_CONTROL         0x09
  33 #define ES1370_REG_UART_TEST            0x0a
  34 #define ES1370_REG_MEMPAGE              0x0c
  35 #define ES1370_REG_CODEC                0x10
  36 #define CODEC_INDEX_SHIFT               8
  37 #define ES1370_REG_SERIAL_CONTROL       0x20
  38 #define ES1370_REG_DAC1_SCOUNT          0x24
  39 #define ES1370_REG_DAC2_SCOUNT          0x28
  40 #define ES1370_REG_ADC_SCOUNT           0x2c
  41
  42 #define ES1370_REG_DAC1_FRAMEADR        0xc30
  43 #define ES1370_REG_DAC1_FRAMECNT        0xc34
  44 #define ES1370_REG_DAC2_FRAMEADR        0xc38
  45 #define ES1370_REG_DAC2_FRAMECNT        0xc3c
  46 #define ES1370_REG_ADC_FRAMEADR         0xd30
  47 #define ES1370_REG_ADC_FRAMECNT         0xd34
  48
  49 #define DAC2_SRTODIV(x) (((1411200 + (x) / 2) / (x) - 2) & 0x1fff)
  50 #define DAC2_DIVTOSR(x) (1411200 / ((x) + 2))
  51
  52 #define CTRL_ADC_STOP   0x80000000      /* 1 = ADC stopped */
  53 #define CTRL_XCTL1      0x40000000      /* SERR pin if enabled */
  54 #define CTRL_OPEN       0x20000000      /* no function, can be read and
  55                                          * written */
  56 #define CTRL_PCLKDIV    0x1fff0000      /* ADC/DAC2 clock divider */
  57 #define CTRL_SH_PCLKDIV 16
  58 #define CTRL_MSFMTSEL   0x00008000      /* MPEG serial data fmt: 0 = Sony, 1
  59                                          * = I2S */
  60 #define CTRL_M_SBB      0x00004000      /* DAC2 clock: 0 = PCLKDIV, 1 = MPEG */
  61 #define CTRL_WTSRSEL    0x00003000      /* DAC1 clock freq: 0=5512, 1=11025,
  62                                          * 2=22050, 3=44100 */
  63 #define CTRL_SH_WTSRSEL 12
  64 #define CTRL_DAC_SYNC   0x00000800      /* 1 = DAC2 runs off DAC1 clock */
  65 #define CTRL_CCB_INTRM  0x00000400      /* 1 = CCB "voice" ints enabled */
  66 #define CTRL_M_CB       0x00000200      /* recording source: 0 = ADC, 1 =
  67                                          * MPEG */
  68 #define CTRL_XCTL0      0x00000100      /* 0 = Line in, 1 = Line out */
  69 #define CTRL_BREQ       0x00000080      /* 1 = test mode (internal mem test) */
  70 #define CTRL_DAC1_EN    0x00000040      /* enable DAC1 */
  71 #define CTRL_DAC2_EN    0x00000020      /* enable DAC2 */
  72 #define CTRL_ADC_EN     0x00000010      /* enable ADC */
  73 #define CTRL_UART_EN    0x00000008      /* enable MIDI uart */
  74 #define CTRL_JYSTK_EN   0x00000004      /* enable Joystick port (presumably
  75                                          * at address 0x200) */
  76 #define CTRL_CDC_EN     0x00000002      /* enable serial (CODEC) interface */
  77 #define CTRL_SERR_DIS   0x00000001      /* 1 = disable PCI SERR signal */
  78
  79 #define SCTRL_P2ENDINC    0x00380000    /* */
  80 #define SCTRL_SH_P2ENDINC 19
  81 #define SCTRL_P2STINC     0x00070000    /* */
  82 #define SCTRL_SH_P2STINC  16
  83 #define SCTRL_R1LOOPSEL   0x00008000    /* 0 = loop mode */
  84 #define SCTRL_P2LOOPSEL   0x00004000    /* 0 = loop mode */
  85 #define SCTRL_P1LOOPSEL   0x00002000    /* 0 = loop mode */
  86 #define SCTRL_P2PAUSE     0x00001000    /* 1 = pause mode */
  87 #define SCTRL_P1PAUSE     0x00000800    /* 1 = pause mode */
  88 #define SCTRL_R1INTEN     0x00000400    /* enable interrupt */
  89 #define SCTRL_P2INTEN     0x00000200    /* enable interrupt */
  90 #define SCTRL_P1INTEN     0x00000100    /* enable interrupt */
  91 #define SCTRL_P1SCTRLD    0x00000080    /* reload sample count register for
  92                                          * DAC1 */
  93 #define SCTRL_P2DACSEN    0x00000040    /* 1 = DAC2 play back last sample
  94                                          * when disabled */
  95 #define SCTRL_R1SEB       0x00000020    /* 1 = 16bit */
  96 #define SCTRL_R1SMB       0x00000010    /* 1 = stereo */
  97 #define SCTRL_R1FMT       0x00000030    /* format mask */
  98 #define SCTRL_SH_R1FMT    4
  99 #define SCTRL_P2SEB       0x00000008    /* 1 = 16bit */
 100 #define SCTRL_P2SMB       0x00000004    /* 1 = stereo */
 101 #define SCTRL_P2FMT       0x0000000c    /* format mask */
 102 #define SCTRL_SH_P2FMT    2
 103 #define SCTRL_P1SEB       0x00000002    /* 1 = 16bit */
 104 #define SCTRL_P1SMB       0x00000001    /* 1 = stereo */
 105 #define SCTRL_P1FMT       0x00000003    /* format mask */
 106 #define SCTRL_SH_P1FMT    0
 107
 108 #define STAT_INTR       0x80000000      /* wired or of all interrupt bits */
 109 #define STAT_CSTAT      0x00000400      /* 1 = codec busy or codec write in
 110                                          * progress */
 111 #define STAT_CBUSY      0x00000200      /* 1 = codec busy */
 112 #define STAT_CWRIP      0x00000100      /* 1 = codec write in progress */
 113 #define STAT_VC         0x00000060      /* CCB int source, 0=DAC1, 1=DAC2,
 114                                          * 2=ADC, 3=undef */
 115 #define STAT_SH_VC      5
 116 #define STAT_MCCB       0x00000010      /* CCB int pending */
 117 #define STAT_UART       0x00000008      /* UART int pending */
 118 #define STAT_DAC1       0x00000004      /* DAC1 int pending */
 119 #define STAT_DAC2       0x00000002      /* DAC2 int pending */
 120 #define STAT_ADC        0x00000001      /* ADC int pending */
 121
 122 #define CODEC_OMIX1     0x10
 123 #define CODEC_OMIX2     0x11
 124 #define CODEC_LIMIX1    0x12
 125 #define CODEC_RIMIX1    0x13
 126 #define CODEC_LIMIX2    0x14
 127 #define CODEC_RIMIX2    0x15
 128 #define CODEC_RES_PD    0x16
 129 #define CODEC_CSEL      0x17
 130 #define CODEC_ADSEL     0x18
 131 #define CODEC_MGAIN     0x19
 132
 133 /* ES1371 specific */
 134
 135 #define CODEC_ID_SESHIFT        10
 136 #define CODEC_ID_SEMASK         0x1f
 137
 138 #define CODEC_PIRD              0x00800000  /* 0 = write AC97 register */
 139 #define CODEC_PIADD_MASK        0x007f0000
 140 #define CODEC_PIADD_SHIFT       16
 141 #define CODEC_PIDAT_MASK        0x0000ffff
 142 #define CODEC_PIDAT_SHIFT       0
 143
 144 #define CODEC_PORD              0x00800000  /* 0 = write AC97 register */
 145 #define CODEC_POADD_MASK        0x007f0000
 146 #define CODEC_POADD_SHIFT       16
 147 #define CODEC_PODAT_MASK        0x0000ffff
 148 #define CODEC_PODAT_SHIFT       0
 149
 150 #define CODEC_RDY               0x80000000  /* AC97 read data valid */
 151 #define CODEC_WIP               0x40000000  /* AC97 write in progress */
 152
 153 #define ES1370_REG_CONTROL      0x00
 154 #define ES1370_REG_SERIAL_CONTROL       0x20
 155 #define ES1371_REG_CODEC        0x14
 156 #define ES1371_REG_LEGACY       0x18         /* W/R: Legacy control/status register */
 157 #define ES1371_REG_SMPRATE      0x10         /* W/R: Codec rate converter interface register */
 158
 159 #define ES1371_SYNC_RES         (1<<14)  /* Warm AC97 reset */
 160 #define ES1371_DIS_R1           (1<<19)  /* record channel accumulator update disable */
 161 #define ES1371_DIS_P2           (1<<20)  /* playback channel 2 accumulator update disable */
 162 #define ES1371_DIS_P1           (1<<21)  /* playback channel 1 accumulator update disable */
 163 #define ES1371_DIS_SRC          (1<<22)  /* sample rate converter disable */
 164 #define ES1371_SRC_RAM_BUSY     (1<<23)  /* R/O: sample rate memory is busy */
 165 #define ES1371_SRC_RAM_WE       (1<<24)  /* R/W: read/write control for sample rate converter */
 166 #define ES1371_SRC_RAM_ADDRO(o) (((o)&0x7f)<<25)        /* address of the sample rate converter */
 167 #define ES1371_SRC_RAM_DATAO(o) (((o)&0xffff)<<0)       /* current value of the sample rate converter */
 168 #define ES1371_SRC_RAM_DATAI(i) (((i)>>0)&0xffff)       /* current value of the sample rate converter */
 169
 170 /*
 171  * S/PDIF specific
 172  */
 173
 174 /* Use ES1370_REG_CONTROL */
 175 #define RECEN_B                 0x08000000      /* Used to control mixing of analog with digital data */
 176 #define SPDIFEN_B               0x04000000      /* Reset to switch digital output mux to "THRU" mode */
 177 /* Use ES1370_REG_STATUS */
 178 #define ENABLE_SPDIF            0x00040000      /* Used to enable the S/PDIF circuitry */
 179 #define TEST_SPDIF              0x00020000      /* Used to put the S/PDIF module in "test mode" */
 180
 181 /*
 182  *  Sample rate converter addresses
 183  */
 184
 185 #define ES_SMPREG_DAC1          0x70
 186 #define ES_SMPREG_DAC2          0x74
 187 #define ES_SMPREG_ADC           0x78
 188 #define ES_SMPREG_TRUNC_N       0x00
 189 #define ES_SMPREG_INT_REGS      0x01
 190 #define ES_SMPREG_VFREQ_FRAC    0x03
 191 #define ES_SMPREG_VOL_ADC       0x6c
 192 #define ES_SMPREG_VOL_DAC1      0x7c
 193 #define ES_SMPREG_VOL_DAC2      0x7e
 194
 195 #endif