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1 /*-
2 * Copyright (c) 1999 Seigo Tanimura
3 * All rights reserved.
4 *
5 * Portions of this source are based on hwdefs.h in cwcealdr1.zip, the
6 * sample source by Crystal Semiconductor.
7 * Copyright (c) 1996-1998 Crystal Semiconductor Corp.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 * $FreeBSD: src/sys/dev/sound/pci/csareg.h,v 1.4 2005/06/27 07:43:57 glebius Exp $
31 * $DragonFly: src/sys/dev/sound/pci/csareg.h,v 1.3 2007/01/04 21:47:02 corecode Exp $
32 */
34 #ifndef _CSA_REG_H
35 #define _CSA_REG_H
37 /*
38 * The following constats are orginally in the sample by Crystal Semiconductor.
39 * Copyright (c) 1996-1998 Crystal Semiconductor Corp.
40 */
42 /*****************************************************************************
43 *
44 * The following define the offsets of the registers accessed via base address
45 * register zero on the CS461x part.
46 *
47 *****************************************************************************/
48 #define BA0_HISR 0x00000000L
49 #define BA0_HSR0 0x00000004L
50 #define BA0_HICR 0x00000008L
51 #define BA0_DMSR 0x00000100L
52 #define BA0_HSAR 0x00000110L
53 #define BA0_HDAR 0x00000114L
54 #define BA0_HDMR 0x00000118L
55 #define BA0_HDCR 0x0000011CL
56 #define BA0_PFMC 0x00000200L
57 #define BA0_PFCV1 0x00000204L
58 #define BA0_PFCV2 0x00000208L
59 #define BA0_PCICFG00 0x00000300L
60 #define BA0_PCICFG04 0x00000304L
61 #define BA0_PCICFG08 0x00000308L
62 #define BA0_PCICFG0C 0x0000030CL
63 #define BA0_PCICFG10 0x00000310L
64 #define BA0_PCICFG14 0x00000314L
65 #define BA0_PCICFG18 0x00000318L
66 #define BA0_PCICFG1C 0x0000031CL
67 #define BA0_PCICFG20 0x00000320L
68 #define BA0_PCICFG24 0x00000324L
69 #define BA0_PCICFG28 0x00000328L
70 #define BA0_PCICFG2C 0x0000032CL
71 #define BA0_PCICFG30 0x00000330L
72 #define BA0_PCICFG34 0x00000334L
73 #define BA0_PCICFG38 0x00000338L
74 #define BA0_PCICFG3C 0x0000033CL
75 #define BA0_CLKCR1 0x00000400L
76 #define BA0_CLKCR2 0x00000404L
77 #define BA0_PLLM 0x00000408L
78 #define BA0_PLLCC 0x0000040CL
79 #define BA0_FRR 0x00000410L
80 #define BA0_CFL1 0x00000414L
81 #define BA0_CFL2 0x00000418L
82 #define BA0_SERMC1 0x00000420L
83 #define BA0_SERMC2 0x00000424L
84 #define BA0_SERC1 0x00000428L
85 #define BA0_SERC2 0x0000042CL
86 #define BA0_SERC3 0x00000430L
87 #define BA0_SERC4 0x00000434L
88 #define BA0_SERC5 0x00000438L
89 #define BA0_SERBSP 0x0000043CL
90 #define BA0_SERBST 0x00000440L
91 #define BA0_SERBCM 0x00000444L
92 #define BA0_SERBAD 0x00000448L
93 #define BA0_SERBCF 0x0000044CL
94 #define BA0_SERBWP 0x00000450L
95 #define BA0_SERBRP 0x00000454L
96 #ifndef NO_CS4612
97 #define BA0_ASER_FADDR 0x00000458L
98 #endif
99 #define BA0_ACCTL 0x00000460L
100 #define BA0_ACSTS 0x00000464L
101 #define BA0_ACOSV 0x00000468L
102 #define BA0_ACCAD 0x0000046CL
103 #define BA0_ACCDA 0x00000470L
104 #define BA0_ACISV 0x00000474L
105 #define BA0_ACSAD 0x00000478L
106 #define BA0_ACSDA 0x0000047CL
107 #define BA0_JSPT 0x00000480L
108 #define BA0_JSCTL 0x00000484L
109 #define BA0_JSC1 0x00000488L
110 #define BA0_JSC2 0x0000048CL
111 #define BA0_MIDCR 0x00000490L
112 #define BA0_MIDSR 0x00000494L
113 #define BA0_MIDWP 0x00000498L
114 #define BA0_MIDRP 0x0000049CL
115 #define BA0_JSIO 0x000004A0L
116 #ifndef NO_CS4612
117 #define BA0_ASER_MASTER 0x000004A4L
118 #endif
119 #define BA0_CFGI 0x000004B0L
120 #define BA0_SSVID 0x000004B4L
121 #define BA0_GPIOR 0x000004B8L
122 #ifndef NO_CS4612
123 #define BA0_EGPIODR 0x000004BCL
124 #define BA0_EGPIOPTR 0x000004C0L
125 #define BA0_EGPIOTR 0x000004C4L
126 #define BA0_EGPIOWR 0x000004C8L
127 #define BA0_EGPIOSR 0x000004CCL
128 #define BA0_SERC6 0x000004D0L
129 #define BA0_SERC7 0x000004D4L
130 #define BA0_SERACC 0x000004D8L
131 #define BA0_ACCTL2 0x000004E0L
132 #define BA0_ACSTS2 0x000004E4L
133 #define BA0_ACOSV2 0x000004E8L
134 #define BA0_ACCAD2 0x000004ECL
135 #define BA0_ACCDA2 0x000004F0L
136 #define BA0_ACISV2 0x000004F4L
137 #define BA0_ACSAD2 0x000004F8L
138 #define BA0_ACSDA2 0x000004FCL
139 #define BA0_IOTAC0 0x00000500L
140 #define BA0_IOTAC1 0x00000504L
141 #define BA0_IOTAC2 0x00000508L
142 #define BA0_IOTAC3 0x0000050CL
143 #define BA0_IOTAC4 0x00000510L
144 #define BA0_IOTAC5 0x00000514L
145 #define BA0_IOTAC6 0x00000518L
146 #define BA0_IOTAC7 0x0000051CL
147 #define BA0_IOTAC8 0x00000520L
148 #define BA0_IOTAC9 0x00000524L
149 #define BA0_IOTAC10 0x00000528L
150 #define BA0_IOTAC11 0x0000052CL
151 #define BA0_IOTFR0 0x00000540L
152 #define BA0_IOTFR1 0x00000544L
153 #define BA0_IOTFR2 0x00000548L
154 #define BA0_IOTFR3 0x0000054CL
155 #define BA0_IOTFR4 0x00000550L
156 #define BA0_IOTFR5 0x00000554L
157 #define BA0_IOTFR6 0x00000558L
158 #define BA0_IOTFR7 0x0000055CL
159 #define BA0_IOTFIFO 0x00000580L
160 #define BA0_IOTRRD 0x00000584L
161 #define BA0_IOTFP 0x00000588L
162 #define BA0_IOTCR 0x0000058CL
163 #define BA0_DPCID 0x00000590L
164 #define BA0_DPCIA 0x00000594L
165 #define BA0_DPCIC 0x00000598L
166 #define BA0_PCPCIR 0x00000600L
167 #define BA0_PCPCIG 0x00000604L
168 #define BA0_PCPCIEN 0x00000608L
169 #define BA0_EPCIPMC 0x00000610L
170 #endif
172 /*****************************************************************************
173 *
174 * The following define the offsets of the AC97 shadow registers, which appear
175 * as a virtual extension to the base address register zero memory range.
176 *
177 *****************************************************************************/
178 #define BA0_AC97_RESET 0x00001000L
179 #define BA0_AC97_MASTER_VOLUME 0x00001002L
180 #define BA0_AC97_HEADPHONE_VOLUME 0x00001004L
181 #define BA0_AC97_MASTER_VOLUME_MONO 0x00001006L
182 #define BA0_AC97_MASTER_TONE 0x00001008L
183 #define BA0_AC97_PC_BEEP_VOLUME 0x0000100AL
184 #define BA0_AC97_PHONE_VOLUME 0x0000100CL
185 #define BA0_AC97_MIC_VOLUME 0x0000100EL
186 #define BA0_AC97_LINE_IN_VOLUME 0x00001010L
187 #define BA0_AC97_CD_VOLUME 0x00001012L
188 #define BA0_AC97_VIDEO_VOLUME 0x00001014L
189 #define BA0_AC97_AUX_VOLUME 0x00001016L
190 #define BA0_AC97_PCM_OUT_VOLUME 0x00001018L
191 #define BA0_AC97_RECORD_SELECT 0x0000101AL
192 #define BA0_AC97_RECORD_GAIN 0x0000101CL
193 #define BA0_AC97_RECORD_GAIN_MIC 0x0000101EL
194 #define BA0_AC97_GENERAL_PURPOSE 0x00001020L
195 #define BA0_AC97_3D_CONTROL 0x00001022L
196 #define BA0_AC97_MODEM_RATE 0x00001024L
197 #define BA0_AC97_POWERDOWN 0x00001026L
198 #define BA0_AC97_RESERVED_28 0x00001028L
199 #define BA0_AC97_RESERVED_2A 0x0000102AL
200 #define BA0_AC97_RESERVED_2C 0x0000102CL
201 #define BA0_AC97_RESERVED_2E 0x0000102EL
202 #define BA0_AC97_RESERVED_30 0x00001030L
203 #define BA0_AC97_RESERVED_32 0x00001032L
204 #define BA0_AC97_RESERVED_34 0x00001034L
205 #define BA0_AC97_RESERVED_36 0x00001036L
206 #define BA0_AC97_RESERVED_38 0x00001038L
207 #define BA0_AC97_RESERVED_3A 0x0000103AL
208 #define BA0_AC97_RESERVED_3C 0x0000103CL
209 #define BA0_AC97_RESERVED_3E 0x0000103EL
210 #define BA0_AC97_RESERVED_40 0x00001040L
211 #define BA0_AC97_RESERVED_42 0x00001042L
212 #define BA0_AC97_RESERVED_44 0x00001044L
213 #define BA0_AC97_RESERVED_46 0x00001046L
214 #define BA0_AC97_RESERVED_48 0x00001048L
215 #define BA0_AC97_RESERVED_4A 0x0000104AL
216 #define BA0_AC97_RESERVED_4C 0x0000104CL
217 #define BA0_AC97_RESERVED_4E 0x0000104EL
218 #define BA0_AC97_RESERVED_50 0x00001050L
219 #define BA0_AC97_RESERVED_52 0x00001052L
220 #define BA0_AC97_RESERVED_54 0x00001054L
221 #define BA0_AC97_RESERVED_56 0x00001056L
222 #define BA0_AC97_RESERVED_58 0x00001058L
223 #define BA0_AC97_VENDOR_RESERVED_5A 0x0000105AL
224 #define BA0_AC97_VENDOR_RESERVED_5C 0x0000105CL
225 #define BA0_AC97_VENDOR_RESERVED_5E 0x0000105EL
226 #define BA0_AC97_VENDOR_RESERVED_60 0x00001060L
227 #define BA0_AC97_VENDOR_RESERVED_62 0x00001062L
228 #define BA0_AC97_VENDOR_RESERVED_64 0x00001064L
229 #define BA0_AC97_VENDOR_RESERVED_66 0x00001066L
230 #define BA0_AC97_VENDOR_RESERVED_68 0x00001068L
231 #define BA0_AC97_VENDOR_RESERVED_6A 0x0000106AL
232 #define BA0_AC97_VENDOR_RESERVED_6C 0x0000106CL
233 #define BA0_AC97_VENDOR_RESERVED_6E 0x0000106EL
234 #define BA0_AC97_VENDOR_RESERVED_70 0x00001070L
235 #define BA0_AC97_VENDOR_RESERVED_72 0x00001072L
236 #define BA0_AC97_VENDOR_RESERVED_74 0x00001074L
237 #define BA0_AC97_VENDOR_RESERVED_76 0x00001076L
238 #define BA0_AC97_VENDOR_RESERVED_78 0x00001078L
239 #define BA0_AC97_VENDOR_RESERVED_7A 0x0000107AL
240 #define BA0_AC97_VENDOR_ID1 0x0000107CL
241 #define BA0_AC97_VENDOR_ID2 0x0000107EL
243 /*****************************************************************************
244 *
245 * The following define the offsets of the registers and memories accessed via
246 * base address register one on the CS461x part.
247 *
248 *****************************************************************************/
249 #define BA1_SP_DMEM0 0x00000000L
250 #define BA1_SP_DMEM1 0x00010000L
251 #define BA1_SP_PMEM 0x00020000L
252 #define BA1_SPCR 0x00030000L
253 #define BA1_DREG 0x00030004L
254 #define BA1_DSRWP 0x00030008L
255 #define BA1_TWPR 0x0003000CL
256 #define BA1_SPWR 0x00030010L
257 #define BA1_SPIR 0x00030014L
258 #define BA1_FGR1 0x00030020L
259 #define BA1_SPCS 0x00030028L
260 #define BA1_SDSR 0x0003002CL
261 #define BA1_FRMT 0x00030030L
262 #define BA1_FRCC 0x00030034L
263 #define BA1_FRSC 0x00030038L
264 #define BA1_OMNI_MEM 0x000E0000L
266 /*****************************************************************************
267 *
268 * The following defines are for the flags in the PCI interrupt register.
269 *
270 *****************************************************************************/
271 #define PI_LINE_MASK 0x000000FFL
272 #define PI_PIN_MASK 0x0000FF00L
273 #define PI_MIN_GRANT_MASK 0x00FF0000L
274 #define PI_MAX_LATENCY_MASK 0xFF000000L
275 #define PI_LINE_SHIFT 0L
276 #define PI_PIN_SHIFT 8L
277 #define PI_MIN_GRANT_SHIFT 16L
278 #define PI_MAX_LATENCY_SHIFT 24L
280 /*****************************************************************************
281 *
282 * The following defines are for the flags in the host interrupt status
283 * register.
284 *
285 *****************************************************************************/
286 #define HISR_VC_MASK 0x0000FFFFL
287 #define HISR_VC0 0x00000001L
288 #define HISR_VC1 0x00000002L
289 #define HISR_VC2 0x00000004L
290 #define HISR_VC3 0x00000008L
291 #define HISR_VC4 0x00000010L
292 #define HISR_VC5 0x00000020L
293 #define HISR_VC6 0x00000040L
294 #define HISR_VC7 0x00000080L
295 #define HISR_VC8 0x00000100L
296 #define HISR_VC9 0x00000200L
297 #define HISR_VC10 0x00000400L
298 #define HISR_VC11 0x00000800L
299 #define HISR_VC12 0x00001000L
300 #define HISR_VC13 0x00002000L
301 #define HISR_VC14 0x00004000L
302 #define HISR_VC15 0x00008000L
303 #define HISR_INT0 0x00010000L
304 #define HISR_INT1 0x00020000L
305 #define HISR_DMAI 0x00040000L
306 #define HISR_FROVR 0x00080000L
307 #define HISR_MIDI 0x00100000L
308 #ifdef NO_CS4612
309 #define HISR_RESERVED 0x0FE00000L
310 #else
311 #define HISR_SBINT 0x00200000L
312 #define HISR_RESERVED 0x0FC00000L
313 #endif
314 #define HISR_H0P 0x40000000L
315 #define HISR_INTENA 0x80000000L
317 /*****************************************************************************
318 *
319 * The following defines are for the flags in the host signal register 0.
320 *
321 *****************************************************************************/
322 #define HSR0_VC_MASK 0xFFFFFFFFL
323 #define HSR0_VC16 0x00000001L
324 #define HSR0_VC17 0x00000002L
325 #define HSR0_VC18 0x00000004L
326 #define HSR0_VC19 0x00000008L
327 #define HSR0_VC20 0x00000010L
328 #define HSR0_VC21 0x00000020L
329 #define HSR0_VC22 0x00000040L
330 #define HSR0_VC23 0x00000080L
331 #define HSR0_VC24 0x00000100L
332 #define HSR0_VC25 0x00000200L
333 #define HSR0_VC26 0x00000400L
334 #define HSR0_VC27 0x00000800L
335 #define HSR0_VC28 0x00001000L
336 #define HSR0_VC29 0x00002000L
337 #define HSR0_VC30 0x00004000L
338 #define HSR0_VC31 0x00008000L
339 #define HSR0_VC32 0x00010000L
340 #define HSR0_VC33 0x00020000L
341 #define HSR0_VC34 0x00040000L
342 #define HSR0_VC35 0x00080000L
343 #define HSR0_VC36 0x00100000L
344 #define HSR0_VC37 0x00200000L
345 #define HSR0_VC38 0x00400000L
346 #define HSR0_VC39 0x00800000L
347 #define HSR0_VC40 0x01000000L
348 #define HSR0_VC41 0x02000000L
349 #define HSR0_VC42 0x04000000L
350 #define HSR0_VC43 0x08000000L
351 #define HSR0_VC44 0x10000000L
352 #define HSR0_VC45 0x20000000L
353 #define HSR0_VC46 0x40000000L
354 #define HSR0_VC47 0x80000000L
356 /*****************************************************************************
357 *
358 * The following defines are for the flags in the host interrupt control
359 * register.
360 *
361 *****************************************************************************/
362 #define HICR_IEV 0x00000001L
363 #define HICR_CHGM 0x00000002L
365 /*****************************************************************************
366 *
367 * The following defines are for the flags in the DMA status register.
368 *
369 *****************************************************************************/
370 #define DMSR_HP 0x00000001L
371 #define DMSR_HR 0x00000002L
372 #define DMSR_SP 0x00000004L
373 #define DMSR_SR 0x00000008L
375 /*****************************************************************************
376 *
377 * The following defines are for the flags in the host DMA source address
378 * register.
379 *
380 *****************************************************************************/
381 #define HSAR_HOST_ADDR_MASK 0xFFFFFFFFL
382 #define HSAR_DSP_ADDR_MASK 0x0000FFFFL
383 #define HSAR_MEMID_MASK 0x000F0000L
384 #define HSAR_MEMID_SP_DMEM0 0x00000000L
385 #define HSAR_MEMID_SP_DMEM1 0x00010000L
386 #define HSAR_MEMID_SP_PMEM 0x00020000L
387 #define HSAR_MEMID_SP_DEBUG 0x00030000L
388 #define HSAR_MEMID_OMNI_MEM 0x000E0000L
389 #define HSAR_END 0x40000000L
390 #define HSAR_ERR 0x80000000L
392 /*****************************************************************************
393 *
394 * The following defines are for the flags in the host DMA destination address
395 * register.
396 *
397 *****************************************************************************/
398 #define HDAR_HOST_ADDR_MASK 0xFFFFFFFFL
399 #define HDAR_DSP_ADDR_MASK 0x0000FFFFL
400 #define HDAR_MEMID_MASK 0x000F0000L
401 #define HDAR_MEMID_SP_DMEM0 0x00000000L
402 #define HDAR_MEMID_SP_DMEM1 0x00010000L
403 #define HDAR_MEMID_SP_PMEM 0x00020000L
404 #define HDAR_MEMID_SP_DEBUG 0x00030000L
405 #define HDAR_MEMID_OMNI_MEM 0x000E0000L
406 #define HDAR_END 0x40000000L
407 #define HDAR_ERR 0x80000000L
409 /*****************************************************************************
410 *
411 * The following defines are for the flags in the host DMA control register.
412 *
413 *****************************************************************************/
414 #define HDMR_AC_MASK 0x0000F000L
415 #define HDMR_AC_8_16 0x00001000L
416 #define HDMR_AC_M_S 0x00002000L
417 #define HDMR_AC_B_L 0x00004000L
418 #define HDMR_AC_S_U 0x00008000L
420 /*****************************************************************************
421 *
422 * The following defines are for the flags in the host DMA control register.
423 *
424 *****************************************************************************/
425 #define HDCR_COUNT_MASK 0x000003FFL
426 #define HDCR_DONE 0x00004000L
427 #define HDCR_OPT 0x00008000L
428 #define HDCR_WBD 0x00400000L
429 #define HDCR_WBS 0x00800000L
430 #define HDCR_DMS_MASK 0x07000000L
431 #define HDCR_DMS_LINEAR 0x00000000L
432 #define HDCR_DMS_16_DWORDS 0x01000000L
433 #define HDCR_DMS_32_DWORDS 0x02000000L
434 #define HDCR_DMS_64_DWORDS 0x03000000L
435 #define HDCR_DMS_128_DWORDS 0x04000000L
436 #define HDCR_DMS_256_DWORDS 0x05000000L
437 #define HDCR_DMS_512_DWORDS 0x06000000L
438 #define HDCR_DMS_1024_DWORDS 0x07000000L
439 #define HDCR_DH 0x08000000L
440 #define HDCR_SMS_MASK 0x70000000L
441 #define HDCR_SMS_LINEAR 0x00000000L
442 #define HDCR_SMS_16_DWORDS 0x10000000L
443 #define HDCR_SMS_32_DWORDS 0x20000000L
444 #define HDCR_SMS_64_DWORDS 0x30000000L
445 #define HDCR_SMS_128_DWORDS 0x40000000L
446 #define HDCR_SMS_256_DWORDS 0x50000000L
447 #define HDCR_SMS_512_DWORDS 0x60000000L
448 #define HDCR_SMS_1024_DWORDS 0x70000000L
449 #define HDCR_SH 0x80000000L
450 #define HDCR_COUNT_SHIFT 0L
452 /*****************************************************************************
453 *
454 * The following defines are for the flags in the performance monitor control
455 * register.
456 *
457 *****************************************************************************/
458 #define PFMC_C1SS_MASK 0x0000001FL
459 #define PFMC_C1EV 0x00000020L
460 #define PFMC_C1RS 0x00008000L
461 #define PFMC_C2SS_MASK 0x001F0000L
462 #define PFMC_C2EV 0x00200000L
463 #define PFMC_C2RS 0x80000000L
464 #define PFMC_C1SS_SHIFT 0L
465 #define PFMC_C2SS_SHIFT 16L
466 #define PFMC_BUS_GRANT 0L
467 #define PFMC_GRANT_AFTER_REQ 1L
468 #define PFMC_TRANSACTION 2L
469 #define PFMC_DWORD_TRANSFER 3L
470 #define PFMC_SLAVE_READ 4L
471 #define PFMC_SLAVE_WRITE 5L
472 #define PFMC_PREEMPTION 6L
473 #define PFMC_DISCONNECT_RETRY 7L
474 #define PFMC_INTERRUPT 8L
475 #define PFMC_BUS_OWNERSHIP 9L
476 #define PFMC_TRANSACTION_LAG 10L
477 #define PFMC_PCI_CLOCK 11L
478 #define PFMC_SERIAL_CLOCK 12L
479 #define PFMC_SP_CLOCK 13L
481 /*****************************************************************************
482 *
483 * The following defines are for the flags in the performance counter value 1
484 * register.
485 *
486 *****************************************************************************/
487 #define PFCV1_PC1V_MASK 0xFFFFFFFFL
488 #define PFCV1_PC1V_SHIFT 0L
490 /*****************************************************************************
491 *
492 * The following defines are for the flags in the performance counter value 2
493 * register.
494 *
495 *****************************************************************************/
496 #define PFCV2_PC2V_MASK 0xFFFFFFFFL
497 #define PFCV2_PC2V_SHIFT 0L
499 /*****************************************************************************
500 *
501 * The following defines are for the flags in the clock control register 1.
502 *
503 *****************************************************************************/
504 #define CLKCR1_OSCS 0x00000001L
505 #define CLKCR1_OSCP 0x00000002L
506 #define CLKCR1_PLLSS_MASK 0x0000000CL
507 #define CLKCR1_PLLSS_SERIAL 0x00000000L
508 #define CLKCR1_PLLSS_CRYSTAL 0x00000004L
509 #define CLKCR1_PLLSS_PCI 0x00000008L
510 #define CLKCR1_PLLSS_RESERVED 0x0000000CL
511 #define CLKCR1_PLLP 0x00000010L
512 #define CLKCR1_SWCE 0x00000020L
513 #define CLKCR1_PLLOS 0x00000040L
515 /*****************************************************************************
516 *
517 * The following defines are for the flags in the clock control register 2.
518 *
519 *****************************************************************************/
520 #define CLKCR2_PDIVS_MASK 0x0000000FL
521 #define CLKCR2_PDIVS_1 0x00000001L
522 #define CLKCR2_PDIVS_2 0x00000002L
523 #define CLKCR2_PDIVS_4 0x00000004L
524 #define CLKCR2_PDIVS_7 0x00000007L
525 #define CLKCR2_PDIVS_8 0x00000008L
526 #define CLKCR2_PDIVS_16 0x00000000L
528 /*****************************************************************************
529 *
530 * The following defines are for the flags in the PLL multiplier register.
531 *
532 *****************************************************************************/
533 #define PLLM_MASK 0x000000FFL
534 #define PLLM_SHIFT 0L
536 /*****************************************************************************
537 *
538 * The following defines are for the flags in the PLL capacitor coefficient
539 * register.
540 *
541 *****************************************************************************/
542 #define PLLCC_CDR_MASK 0x00000007L
543 #ifndef NO_CS4610
544 #define PLLCC_CDR_240_350_MHZ 0x00000000L
545 #define PLLCC_CDR_184_265_MHZ 0x00000001L
546 #define PLLCC_CDR_144_205_MHZ 0x00000002L
547 #define PLLCC_CDR_111_160_MHZ 0x00000003L
548 #define PLLCC_CDR_87_123_MHZ 0x00000004L
549 #define PLLCC_CDR_67_96_MHZ 0x00000005L
550 #define PLLCC_CDR_52_74_MHZ 0x00000006L
551 #define PLLCC_CDR_45_58_MHZ 0x00000007L
552 #endif
553 #ifndef NO_CS4612
554 #define PLLCC_CDR_271_398_MHZ 0x00000000L
555 #define PLLCC_CDR_227_330_MHZ 0x00000001L
556 #define PLLCC_CDR_167_239_MHZ 0x00000002L
557 #define PLLCC_CDR_150_215_MHZ 0x00000003L
558 #define PLLCC_CDR_107_154_MHZ 0x00000004L
559 #define PLLCC_CDR_98_140_MHZ 0x00000005L
560 #define PLLCC_CDR_73_104_MHZ 0x00000006L
561 #define PLLCC_CDR_63_90_MHZ 0x00000007L
562 #endif
563 #define PLLCC_LPF_MASK 0x000000F8L
564 #ifndef NO_CS4610
565 #define PLLCC_LPF_23850_60000_KHZ 0x00000000L
566 #define PLLCC_LPF_7960_26290_KHZ 0x00000008L
567 #define PLLCC_LPF_4160_10980_KHZ 0x00000018L
568 #define PLLCC_LPF_1740_4580_KHZ 0x00000038L
569 #define PLLCC_LPF_724_1910_KHZ 0x00000078L
570 #define PLLCC_LPF_317_798_KHZ 0x000000F8L
571 #endif
572 #ifndef NO_CS4612
573 #define PLLCC_LPF_25580_64530_KHZ 0x00000000L
574 #define PLLCC_LPF_14360_37270_KHZ 0x00000008L
575 #define PLLCC_LPF_6100_16020_KHZ 0x00000018L
576 #define PLLCC_LPF_2540_6690_KHZ 0x00000038L
577 #define PLLCC_LPF_1050_2780_KHZ 0x00000078L
578 #define PLLCC_LPF_450_1160_KHZ 0x000000F8L
579 #endif
581 /*****************************************************************************
582 *
583 * The following defines are for the flags in the feature reporting register.
584 *
585 *****************************************************************************/
586 #define FRR_FAB_MASK 0x00000003L
587 #define FRR_MASK_MASK 0x0000001CL
588 #ifdef NO_CS4612
589 #define FRR_CFOP_MASK 0x000000E0L
590 #else
591 #define FRR_CFOP_MASK 0x00000FE0L
592 #endif
593 #define FRR_CFOP_NOT_DVD 0x00000020L
594 #define FRR_CFOP_A3D 0x00000040L
595 #define FRR_CFOP_128_PIN 0x00000080L
596 #ifndef NO_CS4612
597 #define FRR_CFOP_CS4280 0x00000800L
598 #endif
599 #define FRR_FAB_SHIFT 0L
600 #define FRR_MASK_SHIFT 2L
601 #define FRR_CFOP_SHIFT 5L
603 /*****************************************************************************
604 *
605 * The following defines are for the flags in the configuration load 1
606 * register.
607 *
608 *****************************************************************************/
609 #define CFL1_CLOCK_SOURCE_MASK 0x00000003L
610 #define CFL1_CLOCK_SOURCE_CS423X 0x00000000L
611 #define CFL1_CLOCK_SOURCE_AC97 0x00000001L
612 #define CFL1_CLOCK_SOURCE_CRYSTAL 0x00000002L
613 #define CFL1_CLOCK_SOURCE_DUAL_AC97 0x00000003L
614 #define CFL1_VALID_DATA_MASK 0x000000FFL
616 /*****************************************************************************
617 *
618 * The following defines are for the flags in the configuration load 2
619 * register.
620 *
621 *****************************************************************************/
622 #define CFL2_VALID_DATA_MASK 0x000000FFL
624 /*****************************************************************************
625 *
626 * The following defines are for the flags in the serial port master control
627 * register 1.
628 *
629 *****************************************************************************/
630 #define SERMC1_MSPE 0x00000001L
631 #define SERMC1_PTC_MASK 0x0000000EL
632 #define SERMC1_PTC_CS423X 0x00000000L
633 #define SERMC1_PTC_AC97 0x00000002L
634 #define SERMC1_PTC_DAC 0x00000004L
635 #define SERMC1_PLB 0x00000010L
636 #define SERMC1_XLB 0x00000020L
638 /*****************************************************************************
639 *
640 * The following defines are for the flags in the serial port master control
641 * register 2.
642 *
643 *****************************************************************************/
644 #define SERMC2_LROE 0x00000001L
645 #define SERMC2_MCOE 0x00000002L
646 #define SERMC2_MCDIV 0x00000004L
648 /*****************************************************************************
649 *
650 * The following defines are for the flags in the serial port 1 configuration
651 * register.
652 *
653 *****************************************************************************/
654 #define SERC1_SO1EN 0x00000001L
655 #define SERC1_SO1F_MASK 0x0000000EL
656 #define SERC1_SO1F_CS423X 0x00000000L
657 #define SERC1_SO1F_AC97 0x00000002L
658 #define SERC1_SO1F_DAC 0x00000004L
659 #define SERC1_SO1F_SPDIF 0x00000006L
661 /*****************************************************************************
662 *
663 * The following defines are for the flags in the serial port 2 configuration
664 * register.
665 *
666 *****************************************************************************/
667 #define SERC2_SI1EN 0x00000001L
668 #define SERC2_SI1F_MASK 0x0000000EL
669 #define SERC2_SI1F_CS423X 0x00000000L
670 #define SERC2_SI1F_AC97 0x00000002L
671 #define SERC2_SI1F_ADC 0x00000004L
672 #define SERC2_SI1F_SPDIF 0x00000006L
674 /*****************************************************************************
675 *
676 * The following defines are for the flags in the serial port 3 configuration
677 * register.
678 *
679 *****************************************************************************/
680 #define SERC3_SO2EN 0x00000001L
681 #define SERC3_SO2F_MASK 0x00000006L
682 #define SERC3_SO2F_DAC 0x00000000L
683 #define SERC3_SO2F_SPDIF 0x00000002L
685 /*****************************************************************************
686 *
687 * The following defines are for the flags in the serial port 4 configuration
688 * register.
689 *
690 *****************************************************************************/
691 #define SERC4_SO3EN 0x00000001L
692 #define SERC4_SO3F_MASK 0x00000006L
693 #define SERC4_SO3F_DAC 0x00000000L
694 #define SERC4_SO3F_SPDIF 0x00000002L
696 /*****************************************************************************
697 *
698 * The following defines are for the flags in the serial port 5 configuration
699 * register.
700 *
701 *****************************************************************************/
702 #define SERC5_SI2EN 0x00000001L
703 #define SERC5_SI2F_MASK 0x00000006L
704 #define SERC5_SI2F_ADC 0x00000000L
705 #define SERC5_SI2F_SPDIF 0x00000002L
707 /*****************************************************************************
708 *
709 * The following defines are for the flags in the serial port backdoor sample
710 * pointer register.
711 *
712 *****************************************************************************/
713 #define SERBSP_FSP_MASK 0x0000000FL
714 #define SERBSP_FSP_SHIFT 0L
716 /*****************************************************************************
717 *
718 * The following defines are for the flags in the serial port backdoor status
719 * register.
720 *
721 *****************************************************************************/
722 #define SERBST_RRDY 0x00000001L
723 #define SERBST_WBSY 0x00000002L
725 /*****************************************************************************
726 *
727 * The following defines are for the flags in the serial port backdoor command
728 * register.
729 *
730 *****************************************************************************/
731 #define SERBCM_RDC 0x00000001L
732 #define SERBCM_WRC 0x00000002L
734 /*****************************************************************************
735 *
736 * The following defines are for the flags in the serial port backdoor address
737 * register.
738 *
739 *****************************************************************************/
740 #ifdef NO_CS4612
741 #define SERBAD_FAD_MASK 0x000000FFL
742 #else
743 #define SERBAD_FAD_MASK 0x000001FFL
744 #endif
745 #define SERBAD_FAD_SHIFT 0L
747 /*****************************************************************************
748 *
749 * The following defines are for the flags in the serial port backdoor
750 * configuration register.
751 *
752 *****************************************************************************/
753 #define SERBCF_HBP 0x00000001L
755 /*****************************************************************************
756 *
757 * The following defines are for the flags in the serial port backdoor write
758 * port register.
759 *
760 *****************************************************************************/
761 #define SERBWP_FWD_MASK 0x000FFFFFL
762 #define SERBWP_FWD_SHIFT 0L
764 /*****************************************************************************
765 *
766 * The following defines are for the flags in the serial port backdoor read
767 * port register.
768 *
769 *****************************************************************************/
770 #define SERBRP_FRD_MASK 0x000FFFFFL
771 #define SERBRP_FRD_SHIFT 0L
773 /*****************************************************************************
774 *
775 * The following defines are for the flags in the async FIFO address register.
776 *
777 *****************************************************************************/
778 #ifndef NO_CS4612
779 #define ASER_FADDR_A1_MASK 0x000001FFL
780 #define ASER_FADDR_EN1 0x00008000L
781 #define ASER_FADDR_A2_MASK 0x01FF0000L
782 #define ASER_FADDR_EN2 0x80000000L
783 #define ASER_FADDR_A1_SHIFT 0L
784 #define ASER_FADDR_A2_SHIFT 16L
785 #endif
787 /*****************************************************************************
788 *
789 * The following defines are for the flags in the AC97 control register.
790 *
791 *****************************************************************************/
792 #define ACCTL_RSTN 0x00000001L
793 #define ACCTL_ESYN 0x00000002L
794 #define ACCTL_VFRM 0x00000004L
795 #define ACCTL_DCV 0x00000008L
796 #define ACCTL_CRW 0x00000010L
797 #define ACCTL_ASYN 0x00000020L
798 #ifndef NO_CS4612
799 #define ACCTL_TC 0x00000040L
800 #endif
802 /*****************************************************************************
803 *
804 * The following defines are for the flags in the AC97 status register.
805 *
806 *****************************************************************************/
807 #define ACSTS_CRDY 0x00000001L
808 #define ACSTS_VSTS 0x00000002L
809 #ifndef NO_CS4612
810 #define ACSTS_WKUP 0x00000004L
811 #endif
813 /*****************************************************************************
814 *
815 * The following defines are for the flags in the AC97 output slot valid
816 * register.
817 *
818 *****************************************************************************/
819 #define ACOSV_SLV3 0x00000001L
820 #define ACOSV_SLV4 0x00000002L
821 #define ACOSV_SLV5 0x00000004L
822 #define ACOSV_SLV6 0x00000008L
823 #define ACOSV_SLV7 0x00000010L
824 #define ACOSV_SLV8 0x00000020L
825 #define ACOSV_SLV9 0x00000040L
826 #define ACOSV_SLV10 0x00000080L
827 #define ACOSV_SLV11 0x00000100L
828 #define ACOSV_SLV12 0x00000200L
830 /*****************************************************************************
831 *
832 * The following defines are for the flags in the AC97 command address
833 * register.
834 *
835 *****************************************************************************/
836 #define ACCAD_CI_MASK 0x0000007FL
837 #define ACCAD_CI_SHIFT 0L
839 /*****************************************************************************
840 *
841 * The following defines are for the flags in the AC97 command data register.
842 *
843 *****************************************************************************/
844 #define ACCDA_CD_MASK 0x0000FFFFL
845 #define ACCDA_CD_SHIFT 0L
847 /*****************************************************************************
848 *
849 * The following defines are for the flags in the AC97 input slot valid
850 * register.
851 *
852 *****************************************************************************/
853 #define ACISV_ISV3 0x00000001L
854 #define ACISV_ISV4 0x00000002L
855 #define ACISV_ISV5 0x00000004L
856 #define ACISV_ISV6 0x00000008L
857 #define ACISV_ISV7 0x00000010L
858 #define ACISV_ISV8 0x00000020L
859 #define ACISV_ISV9 0x00000040L
860 #define ACISV_ISV10 0x00000080L
861 #define ACISV_ISV11 0x00000100L
862 #define ACISV_ISV12 0x00000200L
864 /*****************************************************************************
865 *
866 * The following defines are for the flags in the AC97 status address
867 * register.
868 *
869 *****************************************************************************/
870 #define ACSAD_SI_MASK 0x0000007FL
871 #define ACSAD_SI_SHIFT 0L
873 /*****************************************************************************
874 *
875 * The following defines are for the flags in the AC97 status data register.
876 *
877 *****************************************************************************/
878 #define ACSDA_SD_MASK 0x0000FFFFL
879 #define ACSDA_SD_SHIFT 0L
881 /*****************************************************************************
882 *
883 * The following defines are for the flags in the joystick poll/trigger
884 * register.
885 *
886 *****************************************************************************/
887 #define JSPT_CAX 0x00000001L
888 #define JSPT_CAY 0x00000002L
889 #define JSPT_CBX 0x00000004L
890 #define JSPT_CBY 0x00000008L
891 #define JSPT_BA1 0x00000010L
892 #define JSPT_BA2 0x00000020L
893 #define JSPT_BB1 0x00000040L
894 #define JSPT_BB2 0x00000080L
896 /*****************************************************************************
897 *
898 * The following defines are for the flags in the joystick control register.
899 *
900 *****************************************************************************/
901 #define JSCTL_SP_MASK 0x00000003L
902 #define JSCTL_SP_SLOW 0x00000000L
903 #define JSCTL_SP_MEDIUM_SLOW 0x00000001L
904 #define JSCTL_SP_MEDIUM_FAST 0x00000002L
905 #define JSCTL_SP_FAST 0x00000003L
906 #define JSCTL_ARE 0x00000004L
908 /*****************************************************************************
909 *
910 * The following defines are for the flags in the joystick coordinate pair 1
911 * readback register.
912 *
913 *****************************************************************************/
914 #define JSC1_Y1V_MASK 0x0000FFFFL
915 #define JSC1_X1V_MASK 0xFFFF0000L
916 #define JSC1_Y1V_SHIFT 0L
917 #define JSC1_X1V_SHIFT 16L
919 /*****************************************************************************
920 *
921 * The following defines are for the flags in the joystick coordinate pair 2
922 * readback register.
923 *
924 *****************************************************************************/
925 #define JSC2_Y2V_MASK 0x0000FFFFL
926 #define JSC2_X2V_MASK 0xFFFF0000L
927 #define JSC2_Y2V_SHIFT 0L
928 #define JSC2_X2V_SHIFT 16L
930 /*****************************************************************************
931 *
932 * The following defines are for the flags in the MIDI control register.
933 *
934 *****************************************************************************/
935 #define MIDCR_TXE 0x00000001L
936 #define MIDCR_RXE 0x00000002L
937 #define MIDCR_RIE 0x00000004L
938 #define MIDCR_TIE 0x00000008L
939 #define MIDCR_MLB 0x00000010L
940 #define MIDCR_MRST 0x00000020L
942 /*****************************************************************************
943 *
944 * The following defines are for the flags in the MIDI status register.
945 *
946 *****************************************************************************/
947 #define MIDSR_TBF 0x00000001L
948 #define MIDSR_RBE 0x00000002L
950 /*****************************************************************************
951 *
952 * The following defines are for the flags in the MIDI write port register.
953 *
954 *****************************************************************************/
955 #define MIDWP_MWD_MASK 0x000000FFL
956 #define MIDWP_MWD_SHIFT 0L
958 /*****************************************************************************
959 *
960 * The following defines are for the flags in the MIDI read port register.
961 *
962 *****************************************************************************/
963 #define MIDRP_MRD_MASK 0x000000FFL
964 #define MIDRP_MRD_SHIFT 0L
966 /*****************************************************************************
967 *
968 * The following defines are for the flags in the joystick GPIO register.
969 *
970 *****************************************************************************/
971 #define JSIO_DAX 0x00000001L
972 #define JSIO_DAY 0x00000002L
973 #define JSIO_DBX 0x00000004L
974 #define JSIO_DBY 0x00000008L
975 #define JSIO_AXOE 0x00000010L
976 #define JSIO_AYOE 0x00000020L
977 #define JSIO_BXOE 0x00000040L
978 #define JSIO_BYOE 0x00000080L
980 /*****************************************************************************
981 *
982 * The following defines are for the flags in the master async/sync serial
983 * port enable register.
984 *
985 *****************************************************************************/
986 #ifndef NO_CS4612
987 #define ASER_MASTER_ME 0x00000001L
988 #endif
990 /*****************************************************************************
991 *
992 * The following defines are for the flags in the configuration interface
993 * register.
994 *
995 *****************************************************************************/
996 #define CFGI_CLK 0x00000001L
997 #define CFGI_DOUT 0x00000002L
998 #define CFGI_DIN_EEN 0x00000004L
999 #define CFGI_EELD 0x00000008L
1001 /*****************************************************************************
1002 *
1003 * The following defines are for the flags in the subsystem ID and vendor ID
1004 * register.
1005 *
1006 *****************************************************************************/
1007 #define SSVID_VID_MASK 0x0000FFFFL
1008 #define SSVID_SID_MASK 0xFFFF0000L
1009 #define SSVID_VID_SHIFT 0L
1010 #define SSVID_SID_SHIFT 16L
1012 /*****************************************************************************
1013 *
1014 * The following defines are for the flags in the GPIO pin interface register.
1015 *
1016 *****************************************************************************/
1017 #define GPIOR_VOLDN 0x00000001L
1018 #define GPIOR_VOLUP 0x00000002L
1019 #define GPIOR_SI2D 0x00000004L
1020 #define GPIOR_SI2OE 0x00000008L
1022 /*****************************************************************************
1023 *
1024 * The following defines are for the flags in the extended GPIO pin direction
1025 * register.
1026 *
1027 *****************************************************************************/
1028 #ifndef NO_CS4612
1029 #define EGPIODR_GPOE0 0x00000001L
1030 #define EGPIODR_GPOE1 0x00000002L
1031 #define EGPIODR_GPOE2 0x00000004L
1032 #define EGPIODR_GPOE3 0x00000008L
1033 #define EGPIODR_GPOE4 0x00000010L
1034 #define EGPIODR_GPOE5 0x00000020L
1035 #define EGPIODR_GPOE6 0x00000040L
1036 #define EGPIODR_GPOE7 0x00000080L
1037 #define EGPIODR_GPOE8 0x00000100L
1038 #endif
1040 /*****************************************************************************
1041 *
1042 * The following defines are for the flags in the extended GPIO pin polarity/
1043 * type register.
1044 *
1045 *****************************************************************************/
1046 #ifndef NO_CS4612
1047 #define EGPIOPTR_GPPT0 0x00000001L
1048 #define EGPIOPTR_GPPT1 0x00000002L
1049 #define EGPIOPTR_GPPT2 0x00000004L
1050 #define EGPIOPTR_GPPT3 0x00000008L
1051 #define EGPIOPTR_GPPT4 0x00000010L
1052 #define EGPIOPTR_GPPT5 0x00000020L
1053 #define EGPIOPTR_GPPT6 0x00000040L
1054 #define EGPIOPTR_GPPT7 0x00000080L
1055 #define EGPIOPTR_GPPT8 0x00000100L
1056 #endif
1058 /*****************************************************************************
1059 *
1060 * The following defines are for the flags in the extended GPIO pin sticky
1061 * register.
1062 *
1063 *****************************************************************************/
1064 #ifndef NO_CS4612
1065 #define EGPIOTR_GPS0 0x00000001L
1066 #define EGPIOTR_GPS1 0x00000002L
1067 #define EGPIOTR_GPS2 0x00000004L
1068 #define EGPIOTR_GPS3 0x00000008L
1069 #define EGPIOTR_GPS4 0x00000010L
1070 #define EGPIOTR_GPS5 0x00000020L
1071 #define EGPIOTR_GPS6 0x00000040L
1072 #define EGPIOTR_GPS7 0x00000080L
1073 #define EGPIOTR_GPS8 0x00000100L
1074 #endif
1076 /*****************************************************************************
1077 *
1078 * The following defines are for the flags in the extended GPIO ping wakeup
1079 * register.
1080 *
1081 *****************************************************************************/
1082 #ifndef NO_CS4612
1083 #define EGPIOWR_GPW0 0x00000001L
1084 #define EGPIOWR_GPW1 0x00000002L
1085 #define EGPIOWR_GPW2 0x00000004L
1086 #define EGPIOWR_GPW3 0x00000008L
1087 #define EGPIOWR_GPW4 0x00000010L
1088 #define EGPIOWR_GPW5 0x00000020L
1089 #define EGPIOWR_GPW6 0x00000040L
1090 #define EGPIOWR_GPW7 0x00000080L
1091 #define EGPIOWR_GPW8 0x00000100L
1092 #endif
1094 /*****************************************************************************
1095 *
1096 * The following defines are for the flags in the extended GPIO pin status
1097 * register.
1098 *
1099 *****************************************************************************/
1100 #ifndef NO_CS4612
1101 #define EGPIOSR_GPS0 0x00000001L
1102 #define EGPIOSR_GPS1 0x00000002L
1103 #define EGPIOSR_GPS2 0x00000004L
1104 #define EGPIOSR_GPS3 0x00000008L
1105 #define EGPIOSR_GPS4 0x00000010L
1106 #define EGPIOSR_GPS5 0x00000020L
1107 #define EGPIOSR_GPS6 0x00000040L
1108 #define EGPIOSR_GPS7 0x00000080L
1109 #define EGPIOSR_GPS8 0x00000100L
1110 #endif
1112 /*****************************************************************************
1113 *
1114 * The following defines are for the flags in the serial port 6 configuration
1115 * register.
1116 *
1117 *****************************************************************************/
1118 #ifndef NO_CS4612
1119 #define SERC6_ASDO2EN 0x00000001L
1120 #endif
1122 /*****************************************************************************
1123 *
1124 * The following defines are for the flags in the serial port 7 configuration
1125 * register.
1126 *
1127 *****************************************************************************/
1128 #ifndef NO_CS4612
1129 #define SERC7_ASDI2EN 0x00000001L
1130 #define SERC7_POSILB 0x00000002L
1131 #define SERC7_SIPOLB 0x00000004L
1132 #define SERC7_SOSILB 0x00000008L
1133 #define SERC7_SISOLB 0x00000010L
1134 #endif
1136 /*****************************************************************************
1137 *
1138 * The following defines are for the flags in the serial port AC link
1139 * configuration register.
1140 *
1141 *****************************************************************************/
1142 #ifndef NO_CS4612
1143 #define SERACC_CODEC_TYPE_MASK 0x00000001L
1144 #define SERACC_CODEC_TYPE_1_03 0x00000000L
1145 #define SERACC_CODEC_TYPE_2_0 0x00000001L
1146 #define SERACC_TWO_CODECS 0x00000002L
1147 #define SERACC_MDM 0x00000004L
1148 #define SERACC_HSP 0x00000008L
1149 #endif
1151 /*****************************************************************************
1152 *
1153 * The following defines are for the flags in the AC97 control register 2.
1154 *
1155 *****************************************************************************/
1156 #ifndef NO_CS4612
1157 #define ACCTL2_RSTN 0x00000001L
1158 #define ACCTL2_ESYN 0x00000002L
1159 #define ACCTL2_VFRM 0x00000004L
1160 #define ACCTL2_DCV 0x00000008L
1161 #define ACCTL2_CRW 0x00000010L
1162 #define ACCTL2_ASYN 0x00000020L
1163 #endif
1165 /*****************************************************************************
1166 *
1167 * The following defines are for the flags in the AC97 status register 2.
1168 *
1169 *****************************************************************************/
1170 #ifndef NO_CS4612
1171 #define ACSTS2_CRDY 0x00000001L
1172 #define ACSTS2_VSTS 0x00000002L
1173 #endif
1175 /*****************************************************************************
1176 *
1177 * The following defines are for the flags in the AC97 output slot valid
1178 * register 2.
1179 *
1180 *****************************************************************************/
1181 #ifndef NO_CS4612
1182 #define ACOSV2_SLV3 0x00000001L
1183 #define ACOSV2_SLV4 0x00000002L
1184 #define ACOSV2_SLV5 0x00000004L
1185 #define ACOSV2_SLV6 0x00000008L
1186 #define ACOSV2_SLV7 0x00000010L
1187 #define ACOSV2_SLV8 0x00000020L
1188 #define ACOSV2_SLV9 0x00000040L
1189 #define ACOSV2_SLV10 0x00000080L
1190 #define ACOSV2_SLV11 0x00000100L
1191 #define ACOSV2_SLV12 0x00000200L
1192 #endif
1194 /*****************************************************************************
1195 *
1196 * The following defines are for the flags in the AC97 command address
1197 * register 2.
1198 *
1199 *****************************************************************************/
1200 #ifndef NO_CS4612
1201 #define ACCAD2_CI_MASK 0x0000007FL
1202 #define ACCAD2_CI_SHIFT 0L
1203 #endif
1205 /*****************************************************************************
1206 *
1207 * The following defines are for the flags in the AC97 command data register
1208 * 2.
1209 *
1210 *****************************************************************************/
1211 #ifndef NO_CS4612
1212 #define ACCDA2_CD_MASK 0x0000FFFFL
1213 #define ACCDA2_CD_SHIFT 0L
1214 #endif
1216 /*****************************************************************************
1217 *
1218 * The following defines are for the flags in the AC97 input slot valid
1219 * register 2.
1220 *
1221 *****************************************************************************/
1222 #ifndef NO_CS4612
1223 #define ACISV2_ISV3 0x00000001L
1224 #define ACISV2_ISV4 0x00000002L
1225 #define ACISV2_ISV5 0x00000004L
1226 #define ACISV2_ISV6 0x00000008L
1227 #define ACISV2_ISV7 0x00000010L
1228 #define ACISV2_ISV8 0x00000020L
1229 #define ACISV2_ISV9 0x00000040L
1230 #define ACISV2_ISV10 0x00000080L
1231 #define ACISV2_ISV11 0x00000100L
1232 #define ACISV2_ISV12 0x00000200L
1233 #endif
1235 /*****************************************************************************
1236 *
1237 * The following defines are for the flags in the AC97 status address
1238 * register 2.
1239 *
1240 *****************************************************************************/
1241 #ifndef NO_CS4612
1242 #define ACSAD2_SI_MASK 0x0000007FL
1243 #define ACSAD2_SI_SHIFT 0L
1244 #endif
1246 /*****************************************************************************
1247 *
1248 * The following defines are for the flags in the AC97 status data register 2.
1249 *
1250 *****************************************************************************/
1251 #ifndef NO_CS4612
1252 #define ACSDA2_SD_MASK 0x0000FFFFL
1253 #define ACSDA2_SD_SHIFT 0L
1254 #endif
1256 /*****************************************************************************
1257 *
1258 * The following defines are for the flags in the I/O trap address and control
1259 * registers (all 12).
1260 *
1261 *****************************************************************************/
1262 #ifndef NO_CS4612
1263 #define IOTAC_SA_MASK 0x0000FFFFL
1264 #define IOTAC_MSK_MASK 0x000F0000L
1265 #define IOTAC_IODC_MASK 0x06000000L
1266 #define IOTAC_IODC_16_BIT 0x00000000L
1267 #define IOTAC_IODC_10_BIT 0x02000000L
1268 #define IOTAC_IODC_12_BIT 0x04000000L
1269 #define IOTAC_WSPI 0x08000000L
1270 #define IOTAC_RSPI 0x10000000L
1271 #define IOTAC_WSE 0x20000000L
1272 #define IOTAC_WE 0x40000000L
1273 #define IOTAC_RE 0x80000000L
1274 #define IOTAC_SA_SHIFT 0L
1275 #define IOTAC_MSK_SHIFT 16L
1276 #endif
1278 /*****************************************************************************
1279 *
1280 * The following defines are for the flags in the I/O trap fast read registers
1281 * (all 8).
1282 *
1283 *****************************************************************************/
1284 #ifndef NO_CS4612
1285 #define IOTFR_D_MASK 0x0000FFFFL
1286 #define IOTFR_A_MASK 0x000F0000L
1287 #define IOTFR_R_MASK 0x0F000000L
1288 #define IOTFR_ALL 0x40000000L
1289 #define IOTFR_VL 0x80000000L
1290 #define IOTFR_D_SHIFT 0L
1291 #define IOTFR_A_SHIFT 16L
1292 #define IOTFR_R_SHIFT 24L
1293 #endif
1295 /*****************************************************************************
1296 *
1297 * The following defines are for the flags in the I/O trap FIFO register.
1298 *
1299 *****************************************************************************/
1300 #ifndef NO_CS4612
1301 #define IOTFIFO_BA_MASK 0x00003FFFL
1302 #define IOTFIFO_S_MASK 0x00FF0000L
1303 #define IOTFIFO_OF 0x40000000L
1304 #define IOTFIFO_SPIOF 0x80000000L
1305 #define IOTFIFO_BA_SHIFT 0L
1306 #define IOTFIFO_S_SHIFT 16L
1307 #endif
1309 /*****************************************************************************
1310 *
1311 * The following defines are for the flags in the I/O trap retry read data
1312 * register.
1313 *
1314 *****************************************************************************/
1315 #ifndef NO_CS4612
1316 #define IOTRRD_D_MASK 0x0000FFFFL
1317 #define IOTRRD_RDV 0x80000000L
1318 #define IOTRRD_D_SHIFT 0L
1319 #endif
1321 /*****************************************************************************
1322 *
1323 * The following defines are for the flags in the I/O trap FIFO pointer
1324 * register.
1325 *
1326 *****************************************************************************/
1327 #ifndef NO_CS4612
1328 #define IOTFP_CA_MASK 0x00003FFFL
1329 #define IOTFP_PA_MASK 0x3FFF0000L
1330 #define IOTFP_CA_SHIFT 0L
1331 #define IOTFP_PA_SHIFT 16L
1332 #endif
1334 /*****************************************************************************
1335 *
1336 * The following defines are for the flags in the I/O trap control register.
1337 *
1338 *****************************************************************************/
1339 #ifndef NO_CS4612
1340 #define IOTCR_ITD 0x00000001L
1341 #define IOTCR_HRV 0x00000002L
1342 #define IOTCR_SRV 0x00000004L
1343 #define IOTCR_DTI 0x00000008L
1344 #define IOTCR_DFI 0x00000010L
1345 #define IOTCR_DDP 0x00000020L
1346 #define IOTCR_JTE 0x00000040L
1347 #define IOTCR_PPE 0x00000080L
1348 #endif
1350 /*****************************************************************************
1351 *
1352 * The following defines are for the flags in the direct PCI data register.
1353 *
1354 *****************************************************************************/
1355 #ifndef NO_CS4612
1356 #define DPCID_D_MASK 0xFFFFFFFFL
1357 #define DPCID_D_SHIFT 0L
1358 #endif
1360 /*****************************************************************************
1361 *
1362 * The following defines are for the flags in the direct PCI address register.
1363 *
1364 *****************************************************************************/
1365 #ifndef NO_CS4612
1366 #define DPCIA_A_MASK 0xFFFFFFFFL
1367 #define DPCIA_A_SHIFT 0L
1368 #endif
1370 /*****************************************************************************
1371 *
1372 * The following defines are for the flags in the direct PCI command register.
1373 *
1374 *****************************************************************************/
1375 #ifndef NO_CS4612
1376 #define DPCIC_C_MASK 0x0000000FL
1377 #define DPCIC_C_IOREAD 0x00000002L
1378 #define DPCIC_C_IOWRITE 0x00000003L
1379 #define DPCIC_BE_MASK 0x000000F0L
1380 #endif
1382 /*****************************************************************************
1383 *
1384 * The following defines are for the flags in the PC/PCI request register.
1385 *
1386 *****************************************************************************/
1387 #ifndef NO_CS4612
1388 #define PCPCIR_RDC_MASK 0x00000007L
1389 #define PCPCIR_C_MASK 0x00007000L
1390 #define PCPCIR_REQ 0x00008000L
1391 #define PCPCIR_RDC_SHIFT 0L
1392 #define PCPCIR_C_SHIFT 12L
1393 #endif
1395 /*****************************************************************************
1396 *
1397 * The following defines are for the flags in the PC/PCI grant register.
1398 *
1399 *****************************************************************************/
1400 #ifndef NO_CS4612
1401 #define PCPCIG_GDC_MASK 0x00000007L
1402 #define PCPCIG_VL 0x00008000L
1403 #define PCPCIG_GDC_SHIFT 0L
1404 #endif
1406 /*****************************************************************************
1407 *
1408 * The following defines are for the flags in the PC/PCI master enable
1409 * register.
1410 *
1411 *****************************************************************************/
1412 #ifndef NO_CS4612
1413 #define PCPCIEN_EN 0x00000001L
1414 #endif
1416 /*****************************************************************************
1417 *
1418 * The following defines are for the flags in the extended PCI power
1419 * management control register.
1420 *
1421 *****************************************************************************/
1422 #ifndef NO_CS4612
1423 #define EPCIPMC_GWU 0x00000001L
1424 #define EPCIPMC_FSPC 0x00000002L
1425 #endif
1427 /*****************************************************************************
1428 *
1429 * The following defines are for the flags in the SP control register.
1430 *
1431 *****************************************************************************/
1432 #define SPCR_RUN 0x00000001L
1433 #define SPCR_STPFR 0x00000002L
1434 #define SPCR_RUNFR 0x00000004L
1435 #define SPCR_TICK 0x00000008L
1436 #define SPCR_DRQEN 0x00000020L
1437 #define SPCR_RSTSP 0x00000040L
1438 #define SPCR_OREN 0x00000080L
1439 #ifndef NO_CS4612
1440 #define SPCR_PCIINT 0x00000100L
1441 #define SPCR_OINTD 0x00000200L
1442 #define SPCR_CRE 0x00008000L
1443 #endif
1445 /*****************************************************************************
1446 *
1447 * The following defines are for the flags in the debug index register.
1448 *
1449 *****************************************************************************/
1450 #define DREG_REGID_MASK 0x0000007FL
1451 #define DREG_DEBUG 0x00000080L
1452 #define DREG_RGBK_MASK 0x00000700L
1453 #define DREG_TRAP 0x00000800L
1454 #if !defined(NO_CS4612)
1455 #if !defined(NO_CS4615)
1456 #define DREG_TRAPX 0x00001000L
1457 #endif
1458 #endif
1459 #define DREG_REGID_SHIFT 0L
1460 #define DREG_RGBK_SHIFT 8L
1461 #define DREG_RGBK_REGID_MASK 0x0000077FL
1462 #define DREG_REGID_R0 0x00000010L
1463 #define DREG_REGID_R1 0x00000011L
1464 #define DREG_REGID_R2 0x00000012L
1465 #define DREG_REGID_R3 0x00000013L
1466 #define DREG_REGID_R4 0x00000014L
1467 #define DREG_REGID_R5 0x00000015L
1468 #define DREG_REGID_R6 0x00000016L
1469 #define DREG_REGID_R7 0x00000017L
1470 #define DREG_REGID_R8 0x00000018L
1471 #define DREG_REGID_R9 0x00000019L
1472 #define DREG_REGID_RA 0x0000001AL
1473 #define DREG_REGID_RB 0x0000001BL
1474 #define DREG_REGID_RC 0x0000001CL
1475 #define DREG_REGID_RD 0x0000001DL
1476 #define DREG_REGID_RE 0x0000001EL
1477 #define DREG_REGID_RF 0x0000001FL
1478 #define DREG_REGID_RA_BUS_LOW 0x00000020L
1479 #define DREG_REGID_RA_BUS_HIGH 0x00000038L
1480 #define DREG_REGID_YBUS_LOW 0x00000050L
1481 #define DREG_REGID_YBUS_HIGH 0x00000058L
1482 #define DREG_REGID_TRAP_0 0x00000100L
1483 #define DREG_REGID_TRAP_1 0x00000101L
1484 #define DREG_REGID_TRAP_2 0x00000102L
1485 #define DREG_REGID_TRAP_3 0x00000103L
1486 #define DREG_REGID_TRAP_4 0x00000104L
1487 #define DREG_REGID_TRAP_5 0x00000105L
1488 #define DREG_REGID_TRAP_6 0x00000106L
1489 #define DREG_REGID_TRAP_7 0x00000107L
1490 #define DREG_REGID_INDIRECT_ADDRESS 0x0000010EL
1491 #define DREG_REGID_TOP_OF_STACK 0x0000010FL
1492 #if !defined(NO_CS4612)
1493 #if !defined(NO_CS4615)
1494 #define DREG_REGID_TRAP_8 0x00000110L
1495 #define DREG_REGID_TRAP_9 0x00000111L
1496 #define DREG_REGID_TRAP_10 0x00000112L
1497 #define DREG_REGID_TRAP_11 0x00000113L
1498 #define DREG_REGID_TRAP_12 0x00000114L
1499 #define DREG_REGID_TRAP_13 0x00000115L
1500 #define DREG_REGID_TRAP_14 0x00000116L
1501 #define DREG_REGID_TRAP_15 0x00000117L
1502 #define DREG_REGID_TRAP_16 0x00000118L
1503 #define DREG_REGID_TRAP_17 0x00000119L
1504 #define DREG_REGID_TRAP_18 0x0000011AL
1505 #define DREG_REGID_TRAP_19 0x0000011BL
1506 #define DREG_REGID_TRAP_20 0x0000011CL
1507 #define DREG_REGID_TRAP_21 0x0000011DL
1508 #define DREG_REGID_TRAP_22 0x0000011EL
1509 #define DREG_REGID_TRAP_23 0x0000011FL
1510 #endif
1511 #endif
1512 #define DREG_REGID_RSA0_LOW 0x00000200L
1513 #define DREG_REGID_RSA0_HIGH 0x00000201L
1514 #define DREG_REGID_RSA1_LOW 0x00000202L
1515 #define DREG_REGID_RSA1_HIGH 0x00000203L
1516 #define DREG_REGID_RSA2 0x00000204L
1517 #define DREG_REGID_RSA3 0x00000205L
1518 #define DREG_REGID_RSI0_LOW 0x00000206L
1519 #define DREG_REGID_RSI0_HIGH 0x00000207L
1520 #define DREG_REGID_RSI1 0x00000208L
1521 #define DREG_REGID_RSI2 0x00000209L
1522 #define DREG_REGID_SAGUSTATUS 0x0000020AL
1523 #define DREG_REGID_RSCONFIG01_LOW 0x0000020BL
1524 #define DREG_REGID_RSCONFIG01_HIGH 0x0000020CL
1525 #define DREG_REGID_RSCONFIG23_LOW 0x0000020DL
1526 #define DREG_REGID_RSCONFIG23_HIGH 0x0000020EL
1527 #define DREG_REGID_RSDMA01E 0x0000020FL
1528 #define DREG_REGID_RSDMA23E 0x00000210L
1529 #define DREG_REGID_RSD0_LOW 0x00000211L
1530 #define DREG_REGID_RSD0_HIGH 0x00000212L
1531 #define DREG_REGID_RSD1_LOW 0x00000213L
1532 #define DREG_REGID_RSD1_HIGH 0x00000214L
1533 #define DREG_REGID_RSD2_LOW 0x00000215L
1534 #define DREG_REGID_RSD2_HIGH 0x00000216L
1535 #define DREG_REGID_RSD3_LOW 0x00000217L
1536 #define DREG_REGID_RSD3_HIGH 0x00000218L
1537 #define DREG_REGID_SRAR_HIGH 0x0000021AL
1538 #define DREG_REGID_SRAR_LOW 0x0000021BL
1539 #define DREG_REGID_DMA_STATE 0x0000021CL
1540 #define DREG_REGID_CURRENT_DMA_STREAM 0x0000021DL
1541 #define DREG_REGID_NEXT_DMA_STREAM 0x0000021EL
1542 #define DREG_REGID_CPU_STATUS 0x00000300L
1543 #define DREG_REGID_MAC_MODE 0x00000301L
1544 #define DREG_REGID_STACK_AND_REPEAT 0x00000302L
1545 #define DREG_REGID_INDEX0 0x00000304L
1546 #define DREG_REGID_INDEX1 0x00000305L
1547 #define DREG_REGID_DMA_STATE_0_3 0x00000400L
1548 #define DREG_REGID_DMA_STATE_4_7 0x00000404L
1549 #define DREG_REGID_DMA_STATE_8_11 0x00000408L
1550 #define DREG_REGID_DMA_STATE_12_15 0x0000040CL
1551 #define DREG_REGID_DMA_STATE_16_19 0x00000410L
1552 #define DREG_REGID_DMA_STATE_20_23 0x00000414L
1553 #define DREG_REGID_DMA_STATE_24_27 0x00000418L
1554 #define DREG_REGID_DMA_STATE_28_31 0x0000041CL
1555 #define DREG_REGID_DMA_STATE_32_35 0x00000420L
1556 #define DREG_REGID_DMA_STATE_36_39 0x00000424L
1557 #define DREG_REGID_DMA_STATE_40_43 0x00000428L
1558 #define DREG_REGID_DMA_STATE_44_47 0x0000042CL
1559 #define DREG_REGID_DMA_STATE_48_51 0x00000430L
1560 #define DREG_REGID_DMA_STATE_52_55 0x00000434L
1561 #define DREG_REGID_DMA_STATE_56_59 0x00000438L
1562 #define DREG_REGID_DMA_STATE_60_63 0x0000043CL
1563 #define DREG_REGID_DMA_STATE_64_67 0x00000440L
1564 #define DREG_REGID_DMA_STATE_68_71 0x00000444L
1565 #define DREG_REGID_DMA_STATE_72_75 0x00000448L
1566 #define DREG_REGID_DMA_STATE_76_79 0x0000044CL
1567 #define DREG_REGID_DMA_STATE_80_83 0x00000450L
1568 #define DREG_REGID_DMA_STATE_84_87 0x00000454L
1569 #define DREG_REGID_DMA_STATE_88_91 0x00000458L
1570 #define DREG_REGID_DMA_STATE_92_95 0x0000045CL
1571 #define DREG_REGID_TRAP_SELECT 0x00000500L
1572 #define DREG_REGID_TRAP_WRITE_0 0x00000500L
1573 #define DREG_REGID_TRAP_WRITE_1 0x00000501L
1574 #define DREG_REGID_TRAP_WRITE_2 0x00000502L
1575 #define DREG_REGID_TRAP_WRITE_3 0x00000503L
1576 #define DREG_REGID_TRAP_WRITE_4 0x00000504L
1577 #define DREG_REGID_TRAP_WRITE_5 0x00000505L
1578 #define DREG_REGID_TRAP_WRITE_6 0x00000506L
1579 #define DREG_REGID_TRAP_WRITE_7 0x00000507L
1580 #if !defined(NO_CS4612)
1581 #if !defined(NO_CS4615)
1582 #define DREG_REGID_TRAP_WRITE_8 0x00000510L
1583 #define DREG_REGID_TRAP_WRITE_9 0x00000511L
1584 #define DREG_REGID_TRAP_WRITE_10 0x00000512L
1585 #define DREG_REGID_TRAP_WRITE_11 0x00000513L
1586 #define DREG_REGID_TRAP_WRITE_12 0x00000514L
1587 #define DREG_REGID_TRAP_WRITE_13 0x00000515L
1588 #define DREG_REGID_TRAP_WRITE_14 0x00000516L
1589 #define DREG_REGID_TRAP_WRITE_15 0x00000517L
1590 #define DREG_REGID_TRAP_WRITE_16 0x00000518L
1591 #define DREG_REGID_TRAP_WRITE_17 0x00000519L
1592 #define DREG_REGID_TRAP_WRITE_18 0x0000051AL
1593 #define DREG_REGID_TRAP_WRITE_19 0x0000051BL
1594 #define DREG_REGID_TRAP_WRITE_20 0x0000051CL
1595 #define DREG_REGID_TRAP_WRITE_21 0x0000051DL
1596 #define DREG_REGID_TRAP_WRITE_22 0x0000051EL
1597 #define DREG_REGID_TRAP_WRITE_23 0x0000051FL
1598 #endif
1599 #endif
1600 #define DREG_REGID_MAC0_ACC0_LOW 0x00000600L
1601 #define DREG_REGID_MAC0_ACC1_LOW 0x00000601L
1602 #define DREG_REGID_MAC0_ACC2_LOW 0x00000602L
1603 #define DREG_REGID_MAC0_ACC3_LOW 0x00000603L
1604 #define DREG_REGID_MAC1_ACC0_LOW 0x00000604L
1605 #define DREG_REGID_MAC1_ACC1_LOW 0x00000605L
1606 #define DREG_REGID_MAC1_ACC2_LOW 0x00000606L
1607 #define DREG_REGID_MAC1_ACC3_LOW 0x00000607L
1608 #define DREG_REGID_MAC0_ACC0_MID 0x00000608L
1609 #define DREG_REGID_MAC0_ACC1_MID 0x00000609L
1610 #define DREG_REGID_MAC0_ACC2_MID 0x0000060AL
1611 #define DREG_REGID_MAC0_ACC3_MID 0x0000060BL
1612 #define DREG_REGID_MAC1_ACC0_MID 0x0000060CL
1613 #define DREG_REGID_MAC1_ACC1_MID 0x0000060DL
1614 #define DREG_REGID_MAC1_ACC2_MID 0x0000060EL
1615 #define DREG_REGID_MAC1_ACC3_MID 0x0000060FL
1616 #define DREG_REGID_MAC0_ACC0_HIGH 0x00000610L
1617 #define DREG_REGID_MAC0_ACC1_HIGH 0x00000611L
1618 #define DREG_REGID_MAC0_ACC2_HIGH 0x00000612L
1619 #define DREG_REGID_MAC0_ACC3_HIGH 0x00000613L
1620 #define DREG_REGID_MAC1_ACC0_HIGH 0x00000614L
1621 #define DREG_REGID_MAC1_ACC1_HIGH 0x00000615L
1622 #define DREG_REGID_MAC1_ACC2_HIGH 0x00000616L
1623 #define DREG_REGID_MAC1_ACC3_HIGH 0x00000617L
1624 #define DREG_REGID_RSHOUT_LOW 0x00000620L
1625 #define DREG_REGID_RSHOUT_MID 0x00000628L
1626 #define DREG_REGID_RSHOUT_HIGH 0x00000630L
1628 /*****************************************************************************
1629 *
1630 * The following defines are for the flags in the DMA stream requestor write
1631 * port register.
1632 *
1633 *****************************************************************************/
1634 #define DSRWP_DSR_MASK 0x0000000FL
1635 #define DSRWP_DSR_BG_RQ 0x00000001L
1636 #define DSRWP_DSR_PRIORITY_MASK 0x00000006L
1637 #define DSRWP_DSR_PRIORITY_0 0x00000000L
1638 #define DSRWP_DSR_PRIORITY_1 0x00000002L
1639 #define DSRWP_DSR_PRIORITY_2 0x00000004L
1640 #define DSRWP_DSR_PRIORITY_3 0x00000006L
1641 #define DSRWP_DSR_RQ_PENDING 0x00000008L
1643 /*****************************************************************************
1644 *
1645 * The following defines are for the flags in the trap write port register.
1646 *
1647 *****************************************************************************/
1648 #define TWPR_TW_MASK 0x0000FFFFL
1649 #define TWPR_TW_SHIFT 0L
1651 /*****************************************************************************
1652 *
1653 * The following defines are for the flags in the stack pointer write
1654 * register.
1655 *
1656 *****************************************************************************/
1657 #define SPWR_STKP_MASK 0x0000000FL
1658 #define SPWR_STKP_SHIFT 0L
1660 /*****************************************************************************
1661 *
1662 * The following defines are for the flags in the SP interrupt register.
1663 *
1664 *****************************************************************************/
1665 #define SPIR_FRI 0x00000001L
1666 #define SPIR_DOI 0x00000002L
1667 #define SPIR_GPI2 0x00000004L
1668 #define SPIR_GPI3 0x00000008L
1669 #define SPIR_IP0 0x00000010L
1670 #define SPIR_IP1 0x00000020L
1671 #define SPIR_IP2 0x00000040L
1672 #define SPIR_IP3 0x00000080L
1674 /*****************************************************************************
1675 *
1676 * The following defines are for the flags in the functional group 1 register.
1677 *
1678 *****************************************************************************/
1679 #define FGR1_F1S_MASK 0x0000FFFFL
1680 #define FGR1_F1S_SHIFT 0L
1682 /*****************************************************************************
1683 *
1684 * The following defines are for the flags in the SP clock status register.
1685 *
1686 *****************************************************************************/
1687 #define SPCS_FRI 0x00000001L
1688 #define SPCS_DOI 0x00000002L
1689 #define SPCS_GPI2 0x00000004L
1690 #define SPCS_GPI3 0x00000008L
1691 #define SPCS_IP0 0x00000010L
1692 #define SPCS_IP1 0x00000020L
1693 #define SPCS_IP2 0x00000040L
1694 #define SPCS_IP3 0x00000080L
1695 #define SPCS_SPRUN 0x00000100L
1696 #define SPCS_SLEEP 0x00000200L
1697 #define SPCS_FG 0x00000400L
1698 #define SPCS_ORUN 0x00000800L
1699 #define SPCS_IRQ 0x00001000L
1700 #define SPCS_FGN_MASK 0x0000E000L
1701 #define SPCS_FGN_SHIFT 13L
1703 /*****************************************************************************
1704 *
1705 * The following defines are for the flags in the SP DMA requestor status
1706 * register.
1707 *
1708 *****************************************************************************/
1709 #define SDSR_DCS_MASK 0x000000FFL
1710 #define SDSR_DCS_SHIFT 0L
1711 #define SDSR_DCS_NONE 0x00000007L
1713 /*****************************************************************************
1714 *
1715 * The following defines are for the flags in the frame timer register.
1716 *
1717 *****************************************************************************/
1718 #define FRMT_FTV_MASK 0x0000FFFFL
1719 #define FRMT_FTV_SHIFT 0L
1721 /*****************************************************************************
1722 *
1723 * The following defines are for the flags in the frame timer current count
1724 * register.
1725 *
1726 *****************************************************************************/
1727 #define FRCC_FCC_MASK 0x0000FFFFL
1728 #define FRCC_FCC_SHIFT 0L
1730 /*****************************************************************************
1731 *
1732 * The following defines are for the flags in the frame timer save count
1733 * register.
1734 *
1735 *****************************************************************************/
1736 #define FRSC_FCS_MASK 0x0000FFFFL
1737 #define FRSC_FCS_SHIFT 0L
1739 /*****************************************************************************
1740 *
1741 * The following define the various flags stored in the scatter/gather
1742 * descriptors.
1743 *
1744 *****************************************************************************/
1745 #define DMA_SG_NEXT_ENTRY_MASK 0x00000FF8L
1746 #define DMA_SG_SAMPLE_END_MASK 0x0FFF0000L
1747 #define DMA_SG_SAMPLE_END_FLAG 0x10000000L
1748 #define DMA_SG_LOOP_END_FLAG 0x20000000L
1749 #define DMA_SG_SIGNAL_END_FLAG 0x40000000L
1750 #define DMA_SG_SIGNAL_PAGE_FLAG 0x80000000L
1751 #define DMA_SG_NEXT_ENTRY_SHIFT 3L
1752 #define DMA_SG_SAMPLE_END_SHIFT 16L
1754 /*****************************************************************************
1755 *
1756 * The following define the offsets of the fields within the on-chip generic
1757 * DMA requestor.
1758 *
1759 *****************************************************************************/
1760 #define DMA_RQ_CONTROL1 0x00000000L
1761 #define DMA_RQ_CONTROL2 0x00000004L
1762 #define DMA_RQ_SOURCE_ADDR 0x00000008L
1763 #define DMA_RQ_DESTINATION_ADDR 0x0000000CL
1764 #define DMA_RQ_NEXT_PAGE_ADDR 0x00000010L
1765 #define DMA_RQ_NEXT_PAGE_SGDESC 0x00000014L
1766 #define DMA_RQ_LOOP_START_ADDR 0x00000018L
1767 #define DMA_RQ_POST_LOOP_ADDR 0x0000001CL
1768 #define DMA_RQ_PAGE_MAP_ADDR 0x00000020L
1770 /*****************************************************************************
1771 *
1772 * The following defines are for the flags in the first control word of the
1773 * on-chip generic DMA requestor.
1774 *
1775 *****************************************************************************/
1776 #define DMA_RQ_C1_COUNT_MASK 0x000003FFL
1777 #define DMA_RQ_C1_DESTINATION_SCATTER 0x00001000L
1778 #define DMA_RQ_C1_SOURCE_GATHER 0x00002000L
1779 #define DMA_RQ_C1_DONE_FLAG 0x00004000L
1780 #define DMA_RQ_C1_OPTIMIZE_STATE 0x00008000L
1781 #define DMA_RQ_C1_SAMPLE_END_STATE_MASK 0x00030000L
1782 #define DMA_RQ_C1_FULL_PAGE 0x00000000L
1783 #define DMA_RQ_C1_BEFORE_SAMPLE_END 0x00010000L
1784 #define DMA_RQ_C1_PAGE_MAP_ERROR 0x00020000L
1785 #define DMA_RQ_C1_AT_SAMPLE_END 0x00030000L
1786 #define DMA_RQ_C1_LOOP_END_STATE_MASK 0x000C0000L
1787 #define DMA_RQ_C1_NOT_LOOP_END 0x00000000L
1788 #define DMA_RQ_C1_BEFORE_LOOP_END 0x00040000L
1789 #define DMA_RQ_C1_2PAGE_LOOP_BEGIN 0x00080000L
1790 #define DMA_RQ_C1_LOOP_BEGIN 0x000C0000L
1791 #define DMA_RQ_C1_PAGE_MAP_MASK 0x00300000L
1792 #define DMA_RQ_C1_PM_NONE_PENDING 0x00000000L
1793 #define DMA_RQ_C1_PM_NEXT_PENDING 0x00100000L
1794 #define DMA_RQ_C1_PM_RESERVED 0x00200000L
1795 #define DMA_RQ_C1_PM_LOOP_NEXT_PENDING 0x00300000L
1796 #define DMA_RQ_C1_WRITEBACK_DEST_FLAG 0x00400000L
1797 #define DMA_RQ_C1_WRITEBACK_SRC_FLAG 0x00800000L
1798 #define DMA_RQ_C1_DEST_SIZE_MASK 0x07000000L
1799 #define DMA_RQ_C1_DEST_LINEAR 0x00000000L
1800 #define DMA_RQ_C1_DEST_MOD16 0x01000000L
1801 #define DMA_RQ_C1_DEST_MOD32 0x02000000L
1802 #define DMA_RQ_C1_DEST_MOD64 0x03000000L
1803 #define DMA_RQ_C1_DEST_MOD128 0x04000000L
1804 #define DMA_RQ_C1_DEST_MOD256 0x05000000L
1805 #define DMA_RQ_C1_DEST_MOD512 0x06000000L
1806 #define DMA_RQ_C1_DEST_MOD1024 0x07000000L
1807 #define DMA_RQ_C1_DEST_ON_HOST 0x08000000L
1808 #define DMA_RQ_C1_SOURCE_SIZE_MASK 0x70000000L
1809 #define DMA_RQ_C1_SOURCE_LINEAR 0x00000000L
1810 #define DMA_RQ_C1_SOURCE_MOD16 0x10000000L
1811 #define DMA_RQ_C1_SOURCE_MOD32 0x20000000L
1812 #define DMA_RQ_C1_SOURCE_MOD64 0x30000000L
1813 #define DMA_RQ_C1_SOURCE_MOD128 0x40000000L
1814 #define DMA_RQ_C1_SOURCE_MOD256 0x50000000L
1815 #define DMA_RQ_C1_SOURCE_MOD512 0x60000000L
1816 #define DMA_RQ_C1_SOURCE_MOD1024 0x70000000L
1817 #define DMA_RQ_C1_SOURCE_ON_HOST 0x80000000L
1818 #define DMA_RQ_C1_COUNT_SHIFT 0L
1820 /*****************************************************************************
1821 *
1822 * The following defines are for the flags in the second control word of the
1823 * on-chip generic DMA requestor.
1824 *
1825 *****************************************************************************/
1826 #define DMA_RQ_C2_VIRTUAL_CHANNEL_MASK 0x0000003FL
1827 #define DMA_RQ_C2_VIRTUAL_SIGNAL_MASK 0x00000300L
1828 #define DMA_RQ_C2_NO_VIRTUAL_SIGNAL 0x00000000L
1829 #define DMA_RQ_C2_SIGNAL_EVERY_DMA 0x00000100L
1830 #define DMA_RQ_C2_SIGNAL_SOURCE_PINGPONG 0x00000200L
1831 #define DMA_RQ_C2_SIGNAL_DEST_PINGPONG 0x00000300L
1832 #define DMA_RQ_C2_AUDIO_CONVERT_MASK 0x0000F000L
1833 #define DMA_RQ_C2_AC_NONE 0x00000000L
1834 #define DMA_RQ_C2_AC_8_TO_16_BIT 0x00001000L
1835 #define DMA_RQ_C2_AC_MONO_TO_STEREO 0x00002000L
1836 #define DMA_RQ_C2_AC_ENDIAN_CONVERT 0x00004000L
1837 #define DMA_RQ_C2_AC_SIGNED_CONVERT 0x00008000L
1838 #define DMA_RQ_C2_LOOP_END_MASK 0x0FFF0000L
1839 #define DMA_RQ_C2_LOOP_MASK 0x30000000L
1840 #define DMA_RQ_C2_NO_LOOP 0x00000000L
1841 #define DMA_RQ_C2_ONE_PAGE_LOOP 0x10000000L
1842 #define DMA_RQ_C2_TWO_PAGE_LOOP 0x20000000L
1843 #define DMA_RQ_C2_MULTI_PAGE_LOOP 0x30000000L
1844 #define DMA_RQ_C2_SIGNAL_LOOP_BACK 0x40000000L
1845 #define DMA_RQ_C2_SIGNAL_POST_BEGIN_PAGE 0x80000000L
1846 #define DMA_RQ_C2_VIRTUAL_CHANNEL_SHIFT 0L
1847 #define DMA_RQ_C2_LOOP_END_SHIFT 16L
1849 /*****************************************************************************
1850 *
1851 * The following defines are for the flags in the source and destination words
1852 * of the on-chip generic DMA requestor.
1853 *
1854 *****************************************************************************/
1855 #define DMA_RQ_SD_ADDRESS_MASK 0x0000FFFFL
1856 #define DMA_RQ_SD_MEMORY_ID_MASK 0x000F0000L
1857 #define DMA_RQ_SD_SP_PARAM_ADDR 0x00000000L
1858 #define DMA_RQ_SD_SP_SAMPLE_ADDR 0x00010000L
1859 #define DMA_RQ_SD_SP_PROGRAM_ADDR 0x00020000L
1860 #define DMA_RQ_SD_SP_DEBUG_ADDR 0x00030000L
1861 #define DMA_RQ_SD_OMNIMEM_ADDR 0x000E0000L
1862 #define DMA_RQ_SD_END_FLAG 0x40000000L
1863 #define DMA_RQ_SD_ERROR_FLAG 0x80000000L
1864 #define DMA_RQ_SD_ADDRESS_SHIFT 0L
1866 /*****************************************************************************
1867 *
1868 * The following defines are for the flags in the page map address word of the
1869 * on-chip generic DMA requestor.
1870 *
1871 *****************************************************************************/
1872 #define DMA_RQ_PMA_LOOP_THIRD_PAGE_ENTRY_MASK 0x00000FF8L
1873 #define DMA_RQ_PMA_PAGE_TABLE_MASK 0xFFFFF000L
1874 #define DMA_RQ_PMA_LOOP_THIRD_PAGE_ENTRY_SHIFT 3L
1875 #define DMA_RQ_PMA_PAGE_TABLE_SHIFT 12L
1877 /*****************************************************************************
1878 *
1879 * The following defines are for the flags in the rsConfig01/23 registers of
1880 * the SP.
1881 *
1882 *****************************************************************************/
1883 #define RSCONFIG_MODULO_SIZE_MASK 0x0000000FL
1884 #define RSCONFIG_MODULO_16 0x00000001L
1885 #define RSCONFIG_MODULO_32 0x00000002L
1886 #define RSCONFIG_MODULO_64 0x00000003L
1887 #define RSCONFIG_MODULO_128 0x00000004L
1888 #define RSCONFIG_MODULO_256 0x00000005L
1889 #define RSCONFIG_MODULO_512 0x00000006L
1890 #define RSCONFIG_MODULO_1024 0x00000007L
1891 #define RSCONFIG_MODULO_4 0x00000008L
1892 #define RSCONFIG_MODULO_8 0x00000009L
1893 #define RSCONFIG_SAMPLE_SIZE_MASK 0x000000C0L
1894 #define RSCONFIG_SAMPLE_8MONO 0x00000000L
1895 #define RSCONFIG_SAMPLE_8STEREO 0x00000040L
1896 #define RSCONFIG_SAMPLE_16MONO 0x00000080L
1897 #define RSCONFIG_SAMPLE_16STEREO 0x000000C0L
1898 #define RSCONFIG_UNDERRUN_ZERO 0x00004000L
1899 #define RSCONFIG_DMA_TO_HOST 0x00008000L
1900 #define RSCONFIG_STREAM_NUM_MASK 0x00FF0000L
1901 #define RSCONFIG_MAX_DMA_SIZE_MASK 0x1F000000L
1902 #define RSCONFIG_DMA_ENABLE 0x20000000L
1903 #define RSCONFIG_PRIORITY_MASK 0xC0000000L
1904 #define RSCONFIG_PRIORITY_HIGH 0x00000000L
1905 #define RSCONFIG_PRIORITY_MEDIUM_HIGH 0x40000000L
1906 #define RSCONFIG_PRIORITY_MEDIUM_LOW 0x80000000L
1907 #define RSCONFIG_PRIORITY_LOW 0xC0000000L
1908 #define RSCONFIG_STREAM_NUM_SHIFT 16L
1909 #define RSCONFIG_MAX_DMA_SIZE_SHIFT 24L
1911 #define BA1_VARIDEC_BUF_1 0x000
1935 /* PM state definitions */
1936 #define CS461x_AC97_HIGHESTREGTORESTORE 0x26
1937 #define CS461x_AC97_NUMBER_RESTORE_REGS (CS461x_AC97_HIGHESTREGTORESTORE/2-1)
1939 #define CS_POWER_DAC 0x0001
1940 #define CS_POWER_ADC 0x0002
1941 #define CS_POWER_MIXVON 0x0004
1942 #define CS_POWER_MIXVOFF 0x0008
1944 #define CS_AC97_POWER_CONTROL_ADC 0x0100
1945 #define CS_AC97_POWER_CONTROL_DAC 0x0200
1946 #define CS_AC97_POWER_CONTROL_MIXVON 0x0400
1947 #define CS_AC97_POWER_CONTROL_MIXVOFF 0x0800
1948 #define CS_AC97_POWER_CONTROL_ADC_ON 0x0001
1949 #define CS_AC97_POWER_CONTROL_DAC_ON 0x0002
1950 #define CS_AC97_POWER_CONTROL_MIXVON_ON 0x0004
1951 #define CS_AC97_POWER_CONTROL_MIXVOFF_ON 0x0008
1953 /* The following struct holds the initialization array. */
1955 /*
1956 * this is 3*1024 for parameter, 3.5*1024 for sample and 2*3.5*1024 for code since
1957 * each instruction is 40 bits and takes two dwords
1958 */
1959 #define INKY_BA1_DWORD_SIZE (13 * 1024 + 512)
1960 #define INKY_MEMORY_COUNT 3
1962 struct BA1struct
1963 {
1964 struct
1965 {
1966 u_long ulDestByteOffset,
1967 ulSourceByteSize;
1971 };