sys/dev/sound/pci/csa.c

   1 /*-
   2  * Copyright (c) 1999 Seigo Tanimura
   3  * All rights reserved.
   4  *
   5  * Portions of this source are based on cwcealdr.cpp and dhwiface.cpp in
   6  * cwcealdr1.zip, the sample sources by Crystal Semiconductor.
   7  * Copyright (c) 1996-1998 Crystal Semiconductor Corp.
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  19  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  22  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  23  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  24  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  26  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  28  * SUCH DAMAGE.
  29  *
  30  * $FreeBSD: src/sys/dev/sound/pci/csa.c,v 1.33.2.1 2005/12/30 19:55:53 netchild Exp $
  31  * $DragonFly: src/sys/dev/sound/pci/csa.c,v 1.8 2007/01/04 21:47:02 corecode Exp $
  32  */
  33
  34 #include <sys/param.h>
  35 #include <sys/systm.h>
  36 #include <sys/kernel.h>
  37 #include <sys/bus.h>
  38 #include <sys/malloc.h>
  39 #include <sys/module.h>
  40 #include <sys/rman.h>
  41 #include <sys/soundcard.h>
  42
  43 #include <dev/sound/pcm/sound.h>
  44 #include <dev/sound/chip.h>
  45 #include <dev/sound/pci/csareg.h>
  46 #include <dev/sound/pci/csavar.h>
  47
  48 #include <bus/pci/pcireg.h>
  49 #include <bus/pci/pcivar.h>
  50
  51 #include <dev/sound/pci/gnu/csaimg.h>
  52
  53 SND_DECLARE_FILE("$DragonFly: src/sys/dev/sound/pci/csa.c,v 1.8 2007/01/04 21:47:02 corecode Exp $");
  54
  55 /* This is the pci device id. */
  56 #define CS4610_PCI_ID 0x60011013
  57 #define CS4614_PCI_ID 0x60031013
  58 #define CS4615_PCI_ID 0x60041013
  59
  60 /* Here is the parameter structure per a device. */
  61 struct csa_softc {
  62         device_t dev; /* device */
  63         csa_res res; /* resources */
  64
  65         device_t pcm; /* pcm device */
  66         driver_intr_t* pcmintr; /* pcm intr */
  67         void *pcmintr_arg; /* pcm intr arg */
  68         device_t midi; /* midi device */
  69         driver_intr_t* midiintr; /* midi intr */
  70         void *midiintr_arg; /* midi intr arg */
  71         void *ih; /* cookie */
  72
  73         struct csa_card *card;
  74         struct csa_bridgeinfo binfo; /* The state of this bridge. */
  75 };
  76
  77 typedef struct csa_softc *sc_p;
  78
  79 static int csa_probe(device_t dev);
  80 static int csa_attach(device_t dev);
  81 static struct resource *csa_alloc_resource(device_t bus, device_t child, int type, int *rid,
  82                                               u_long start, u_long end, u_long count, u_int flags);
  83 static int csa_release_resource(device_t bus, device_t child, int type, int rid,
  84                                    struct resource *r);
  85 static int csa_setup_intr(device_t bus, device_t child,
  86                           struct resource *irq, int flags,
  87                           driver_intr_t *intr, void *arg, void **cookiep);
  88 static int csa_teardown_intr(device_t bus, device_t child,
  89                              struct resource *irq, void *cookie);
  90 static driver_intr_t csa_intr;
  91 static int csa_initialize(sc_p scp);
  92 static int csa_downloadimage(csa_res *resp);
  93
  94 static devclass_t csa_devclass;
  95
  96 static void
  97 amp_none(void)
  98 {
  99 }
 100
 101 static void
 102 amp_voyetra(void)
 103 {
 104 }
 105
 106 static int
 107 clkrun_hack(int run)
 108 {
 109 #ifdef __i386__
 110         devclass_t              pci_devclass;
 111         device_t                *pci_devices, *pci_children, *busp, *childp;
 112         int                     pci_count = 0, pci_childcount = 0;
 113         int                     i, j, port;
 114         u_int16_t               control;
 115         bus_space_tag_t         btag;
 116
 117         if ((pci_devclass = devclass_find("pci")) == NULL) {
 118                 return ENXIO;
 119         }
 120
 121         devclass_get_devices(pci_devclass, &pci_devices, &pci_count);
 122
 123         for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) {
 124                 pci_childcount = 0;
 125                 device_get_children(*busp, &pci_children, &pci_childcount);
 126                 for (j = 0, childp = pci_children; j < pci_childcount; j++, childp++) {
 127                         if (pci_get_vendor(*childp) == 0x8086 && pci_get_device(*childp) == 0x7113) {
 128                                 port = (pci_read_config(*childp, 0x41, 1) << 8) + 0x10;
 129                                 /* XXX */
 130                                 btag = I386_BUS_SPACE_IO;
 131
 132                                 control = bus_space_read_2(btag, 0x0, port);
 133                                 control &= ~0x2000;
 134                                 control |= run? 0 : 0x2000;
 135                                 bus_space_write_2(btag, 0x0, port, control);
 136                                 kfree(pci_devices, M_TEMP);
 137                                 kfree(pci_children, M_TEMP);
 138                                 return 0;
 139                         }
 140                 }
 141                 kfree(pci_children, M_TEMP);
 142         }
 143
 144         kfree(pci_devices, M_TEMP);
 145         return ENXIO;
 146 #else
 147         return 0;
 148 #endif
 149 }
 150
 151 static struct csa_card cards_4610[] = {
 152         {0, 0, "Unknown/invalid SSID (CS4610)", NULL, NULL, NULL, 0},
 153 };
 154
 155 static struct csa_card cards_4614[] = {
 156         {0x1489, 0x7001, "Genius Soundmaker 128 value", amp_none, NULL, NULL, 0},
 157         {0x5053, 0x3357, "Turtle Beach Santa Cruz", amp_voyetra, NULL, NULL, 1},
 158         {0x1071, 0x6003, "Mitac MI6020/21", amp_voyetra, NULL, NULL, 0},
 159         {0x14AF, 0x0050, "Hercules Game Theatre XP", NULL, NULL, NULL, 0},
 160         {0x1681, 0x0050, "Hercules Game Theatre XP", NULL, NULL, NULL, 0},
 161         {0x1014, 0x0132, "Thinkpad 570", amp_none, NULL, NULL, 0},
 162         {0x1014, 0x0153, "Thinkpad 600X/A20/T20", amp_none, NULL, clkrun_hack, 0},
 163         {0x1014, 0x1010, "Thinkpad 600E (unsupported)", NULL, NULL, NULL, 0},
 164         {0, 0, "Unknown/invalid SSID (CS4614)", NULL, NULL, NULL, 0},
 165 };
 166
 167 static struct csa_card cards_4615[] = {
 168         {0, 0, "Unknown/invalid SSID (CS4615)", NULL, NULL, NULL, 0},
 169 };
 170
 171 static struct csa_card nocard = {0, 0, "unknown", NULL, NULL, NULL, 0};
 172
 173 struct card_type {
 174         u_int32_t devid;
 175         char *name;
 176         struct csa_card *cards;
 177 };
 178
 179 static struct card_type cards[] = {
 180         {CS4610_PCI_ID, "CS4610/CS4611", cards_4610},
 181         {CS4614_PCI_ID, "CS4280/CS4614/CS4622/CS4624/CS4630", cards_4614},
 182         {CS4615_PCI_ID, "CS4615", cards_4615},
 183         {0, NULL, NULL},
 184 };
 185
 186 static struct card_type *
 187 csa_findcard(device_t dev)
 188 {
 189         int i;
 190
 191         i = 0;
 192         while (cards[i].devid != 0) {
 193                 if (pci_get_devid(dev) == cards[i].devid)
 194                         return &cards[i];
 195                 i++;
 196         }
 197         return NULL;
 198 }
 199
 200 struct csa_card *
 201 csa_findsubcard(device_t dev)
 202 {
 203         int i;
 204         struct card_type *card;
 205         struct csa_card *subcard;
 206
 207         card = csa_findcard(dev);
 208         if (card == NULL)
 209                 return &nocard;
 210         subcard = card->cards;
 211         i = 0;
 212         while (subcard[i].subvendor != 0) {
 213                 if (pci_get_subvendor(dev) == subcard[i].subvendor
 214                     && pci_get_subdevice(dev) == subcard[i].subdevice) {
 215                         return &subcard[i];
 216                 }
 217                 i++;
 218         }
 219         return &subcard[i];
 220 }
 221
 222 static int
 223 csa_probe(device_t dev)
 224 {
 225         struct card_type *card;
 226
 227         card = csa_findcard(dev);
 228         if (card) {
 229                 device_set_desc(dev, card->name);
 230                 return BUS_PROBE_DEFAULT;
 231         }
 232         return ENXIO;
 233 }
 234
 235 static int
 236 csa_attach(device_t dev)
 237 {
 238         u_int32_t stcmd;
 239         sc_p scp;
 240         csa_res *resp;
 241         struct sndcard_func *func;
 242         int error = ENXIO;
 243
 244         scp = device_get_softc(dev);
 245
 246         /* Fill in the softc. */
 247         bzero(scp, sizeof(*scp));
 248         scp->dev = dev;
 249
 250         /* Wake up the device. */
 251         stcmd = pci_read_config(dev, PCIR_COMMAND, 2);
 252         if ((stcmd & PCIM_CMD_MEMEN) == 0 || (stcmd & PCIM_CMD_BUSMASTEREN) == 0) {
 253                 stcmd |= (PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
 254                 pci_write_config(dev, PCIR_COMMAND, stcmd, 2);
 255         }
 256
 257         /* Allocate the resources. */
 258         resp = &scp->res;
 259         scp->card = csa_findsubcard(dev);
 260         scp->binfo.card = scp->card;
 261         kprintf("csa: card is %s\n", scp->card->name);
 262         resp->io_rid = PCIR_BAR(0);
 263         resp->io = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
 264                 &resp->io_rid, RF_ACTIVE);
 265         if (resp->io == NULL)
 266                 return (ENXIO);
 267         resp->mem_rid = PCIR_BAR(1);
 268         resp->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
 269                 &resp->mem_rid, RF_ACTIVE);
 270         if (resp->mem == NULL)
 271                 goto err_io;
 272         resp->irq_rid = 0;
 273         resp->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
 274                 &resp->irq_rid, RF_ACTIVE | RF_SHAREABLE);
 275         if (resp->irq == NULL)
 276                 goto err_mem;
 277
 278         /* Enable interrupt. */
 279         if (snd_setup_intr(dev, resp->irq, 0, csa_intr, scp, &scp->ih))
 280                 goto err_intr;
 281 #if 0
 282         if ((csa_readio(resp, BA0_HISR) & HISR_INTENA) == 0)
 283                 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
 284 #endif
 285
 286         /* Initialize the chip. */
 287         if (csa_initialize(scp))
 288                 goto err_teardown;
 289
 290         /* Reset the Processor. */
 291         csa_resetdsp(resp);
 292
 293         /* Download the Processor Image to the processor. */
 294         if (csa_downloadimage(resp))
 295                 goto err_teardown;
 296
 297         /* Attach the children. */
 298
 299         /* PCM Audio */
 300         func = kmalloc(sizeof(struct sndcard_func), M_DEVBUF, M_NOWAIT | M_ZERO);
 301         if (func == NULL) {
 302                 error = ENOMEM;
 303                 goto err_teardown;
 304         }
 305         func->varinfo = &scp->binfo;
 306         func->func = SCF_PCM;
 307         scp->pcm = device_add_child(dev, "pcm", -1);
 308         device_set_ivars(scp->pcm, func);
 309
 310         /* Midi Interface */
 311         func = kmalloc(sizeof(struct sndcard_func), M_DEVBUF, M_NOWAIT | M_ZERO);
 312         if (func == NULL) {
 313                 error = ENOMEM;
 314                 goto err_teardown;
 315         }
 316         func->varinfo = &scp->binfo;
 317         func->func = SCF_MIDI;
 318         scp->midi = device_add_child(dev, "midi", -1);
 319         device_set_ivars(scp->midi, func);
 320
 321         bus_generic_attach(dev);
 322
 323         return (0);
 324
 325 err_teardown:
 326         bus_teardown_intr(dev, resp->irq, scp->ih);
 327 err_intr:
 328         bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq);
 329 err_mem:
 330         bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem);
 331 err_io:
 332         bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io);
 333         return (error);
 334 }
 335
 336 static int
 337 csa_detach(device_t dev)
 338 {
 339         csa_res *resp;
 340         sc_p scp;
 341         int err;
 342
 343         scp = device_get_softc(dev);
 344         resp = &scp->res;
 345
 346         err = 0;
 347         if (scp->midi != NULL)
 348                 err = device_delete_child(dev, scp->midi);
 349         if (err)
 350                 return err;
 351         scp->midi = NULL;
 352
 353         if (scp->pcm != NULL)
 354                 err = device_delete_child(dev, scp->pcm);
 355         if (err)
 356                 return err;
 357         scp->pcm = NULL;
 358
 359         bus_teardown_intr(dev, resp->irq, scp->ih);
 360         bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq);
 361         bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem);
 362         bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io);
 363
 364         return bus_generic_detach(dev);
 365 }
 366
 367 static int
 368 csa_resume(device_t dev)
 369 {
 370         csa_res *resp;
 371         sc_p scp;
 372
 373         scp = device_get_softc(dev);
 374         resp = &scp->res;
 375
 376         /* Initialize the chip. */
 377         if (csa_initialize(scp))
 378                 return (ENXIO);
 379
 380         /* Reset the Processor. */
 381         csa_resetdsp(resp);
 382
 383         /* Download the Processor Image to the processor. */
 384         if (csa_downloadimage(resp))
 385                 return (ENXIO);
 386
 387         return (bus_generic_resume(dev));
 388 }
 389
 390 static struct resource *
 391 csa_alloc_resource(device_t bus, device_t child, int type, int *rid,
 392                       u_long start, u_long end, u_long count, u_int flags)
 393 {
 394         sc_p scp;
 395         csa_res *resp;
 396         struct resource *res;
 397
 398         scp = device_get_softc(bus);
 399         resp = &scp->res;
 400         switch (type) {
 401         case SYS_RES_IRQ:
 402                 if (*rid != 0)
 403                         return (NULL);
 404                 res = resp->irq;
 405                 break;
 406         case SYS_RES_MEMORY:
 407                 switch (*rid) {
 408                 case PCIR_BAR(0):
 409                         res = resp->io;
 410                         break;
 411                 case PCIR_BAR(1):
 412                         res = resp->mem;
 413                         break;
 414                 default:
 415                         return (NULL);
 416                 }
 417                 break;
 418         default:
 419                 return (NULL);
 420         }
 421
 422         return res;
 423 }
 424
 425 static int
 426 csa_release_resource(device_t bus, device_t child, int type, int rid,
 427                         struct resource *r)
 428 {
 429         return (0);
 430 }
 431
 432 /*
 433  * The following three functions deal with interrupt handling.
 434  * An interrupt is primarily handled by the bridge driver.
 435  * The bridge driver then determines the child devices to pass
 436  * the interrupt. Certain information of the device can be read
 437  * only once(eg the value of HISR). The bridge driver is responsible
 438  * to pass such the information to the children.
 439  */
 440
 441 static int
 442 csa_setup_intr(device_t bus, device_t child,
 443                struct resource *irq, int flags,
 444                driver_intr_t *intr, void *arg, void **cookiep)
 445 {
 446         sc_p scp;
 447         csa_res *resp;
 448         struct sndcard_func *func;
 449
 450         scp = device_get_softc(bus);
 451         resp = &scp->res;
 452
 453         /*
 454          * Look at the function code of the child to determine
 455          * the appropriate hander for it.
 456          */
 457         func = device_get_ivars(child);
 458         if (func == NULL || irq != resp->irq)
 459                 return (EINVAL);
 460
 461         switch (func->func) {
 462         case SCF_PCM:
 463                 scp->pcmintr = intr;
 464                 scp->pcmintr_arg = arg;
 465                 break;
 466
 467         case SCF_MIDI:
 468                 scp->midiintr = intr;
 469                 scp->midiintr_arg = arg;
 470                 break;
 471
 472         default:
 473                 return (EINVAL);
 474         }
 475         *cookiep = scp;
 476         if ((csa_readio(resp, BA0_HISR) & HISR_INTENA) == 0)
 477                 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
 478
 479         return (0);
 480 }
 481
 482 static int
 483 csa_teardown_intr(device_t bus, device_t child,
 484                   struct resource *irq, void *cookie)
 485 {
 486         sc_p scp;
 487         csa_res *resp;
 488         struct sndcard_func *func;
 489
 490         scp = device_get_softc(bus);
 491         resp = &scp->res;
 492
 493         /*
 494          * Look at the function code of the child to determine
 495          * the appropriate hander for it.
 496          */
 497         func = device_get_ivars(child);
 498         if (func == NULL || irq != resp->irq || cookie != scp)
 499                 return (EINVAL);
 500
 501         switch (func->func) {
 502         case SCF_PCM:
 503                 scp->pcmintr = NULL;
 504                 scp->pcmintr_arg = NULL;
 505                 break;
 506
 507         case SCF_MIDI:
 508                 scp->midiintr = NULL;
 509                 scp->midiintr_arg = NULL;
 510                 break;
 511
 512         default:
 513                 return (EINVAL);
 514         }
 515
 516         return (0);
 517 }
 518
 519 /* The interrupt handler */
 520 static void
 521 csa_intr(void *arg)
 522 {
 523         sc_p scp = arg;
 524         csa_res *resp;
 525         u_int32_t hisr;
 526
 527         resp = &scp->res;
 528
 529         /* Is this interrupt for us? */
 530         hisr = csa_readio(resp, BA0_HISR);
 531         if ((hisr & 0x7fffffff) == 0) {
 532                 /* Throw an eoi. */
 533                 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
 534                 return;
 535         }
 536
 537         /*
 538          * Pass the value of HISR via struct csa_bridgeinfo.
 539          * The children get access through their ivars.
 540          */
 541         scp->binfo.hisr = hisr;
 542
 543         /* Invoke the handlers of the children. */
 544         if ((hisr & (HISR_VC0 | HISR_VC1)) != 0 && scp->pcmintr != NULL) {
 545                 scp->pcmintr(scp->pcmintr_arg);
 546                 hisr &= ~(HISR_VC0 | HISR_VC1);
 547         }
 548         if ((hisr & HISR_MIDI) != 0 && scp->midiintr != NULL) {
 549                 scp->midiintr(scp->midiintr_arg);
 550                 hisr &= ~HISR_MIDI;
 551         }
 552
 553         /* Throw an eoi. */
 554         csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
 555 }
 556
 557 static int
 558 csa_initialize(sc_p scp)
 559 {
 560         int i;
 561         u_int32_t acsts, acisv;
 562         csa_res *resp;
 563
 564         resp = &scp->res;
 565
 566         /*
 567          * First, blast the clock control register to zero so that the PLL starts
 568          * out in a known state, and blast the master serial port control register
 569          * to zero so that the serial ports also start out in a known state.
 570          */
 571         csa_writeio(resp, BA0_CLKCR1, 0);
 572         csa_writeio(resp, BA0_SERMC1, 0);
 573
 574         /*
 575          * If we are in AC97 mode, then we must set the part to a host controlled
 576          * AC-link.  Otherwise, we won't be able to bring up the link.
 577          */
 578 #if 1
 579         csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_1_03); /* 1.03 codec */
 580 #else
 581         csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_2_0); /* 2.0 codec */
 582 #endif /* 1 */
 583
 584         /*
 585          * Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97
 586          * spec) and then drive it high.  This is done for non AC97 modes since
 587          * there might be logic external to the CS461x that uses the ARST# line
 588          * for a reset.
 589          */
 590         csa_writeio(resp, BA0_ACCTL, 1);
 591         DELAY(50);
 592         csa_writeio(resp, BA0_ACCTL, 0);
 593         DELAY(50);
 594         csa_writeio(resp, BA0_ACCTL, ACCTL_RSTN);
 595
 596         /*
 597          * The first thing we do here is to enable sync generation.  As soon
 598          * as we start receiving bit clock, we'll start producing the SYNC
 599          * signal.
 600          */
 601         csa_writeio(resp, BA0_ACCTL, ACCTL_ESYN | ACCTL_RSTN);
 602
 603         /*
 604          * Now wait for a short while to allow the AC97 part to start
 605          * generating bit clock (so we don't try to start the PLL without an
 606          * input clock).
 607          */
 608         DELAY(50000);
 609
 610         /*
 611          * Set the serial port timing configuration, so that
 612          * the clock control circuit gets its clock from the correct place.
 613          */
 614         csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97);
 615         DELAY(700000);
 616
 617         /*
 618          * Write the selected clock control setup to the hardware.  Do not turn on
 619          * SWCE yet (if requested), so that the devices clocked by the output of
 620          * PLL are not clocked until the PLL is stable.
 621          */
 622         csa_writeio(resp, BA0_PLLCC, PLLCC_LPF_1050_2780_KHZ | PLLCC_CDR_73_104_MHZ);
 623         csa_writeio(resp, BA0_PLLM, 0x3a);
 624         csa_writeio(resp, BA0_CLKCR2, CLKCR2_PDIVS_8);
 625
 626         /*
 627          * Power up the PLL.
 628          */
 629         csa_writeio(resp, BA0_CLKCR1, CLKCR1_PLLP);
 630
 631         /*
 632          * Wait until the PLL has stabilized.
 633          */
 634         DELAY(5000);
 635
 636         /*
 637          * Turn on clocking of the core so that we can setup the serial ports.
 638          */
 639         csa_writeio(resp, BA0_CLKCR1, csa_readio(resp, BA0_CLKCR1) | CLKCR1_SWCE);
 640
 641         /*
 642          * Fill the serial port FIFOs with silence.
 643          */
 644         csa_clearserialfifos(resp);
 645
 646         /*
 647          * Set the serial port FIFO pointer to the first sample in the FIFO.
 648          */
 649 #ifdef notdef
 650         csa_writeio(resp, BA0_SERBSP, 0);
 651 #endif /* notdef */
 652
 653         /*
 654          *  Write the serial port configuration to the part.  The master
 655          *  enable bit is not set until all other values have been written.
 656          */
 657         csa_writeio(resp, BA0_SERC1, SERC1_SO1F_AC97 | SERC1_SO1EN);
 658         csa_writeio(resp, BA0_SERC2, SERC2_SI1F_AC97 | SERC1_SO1EN);
 659         csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97 | SERMC1_MSPE);
 660
 661         /*
 662          * Wait for the codec ready signal from the AC97 codec.
 663          */
 664         acsts = 0;
 665         for (i = 0 ; i < 1000 ; i++) {
 666                 /*
 667                  * First, lets wait a short while to let things settle out a bit,
 668                  * and to prevent retrying the read too quickly.
 669                  */
 670                 DELAY(125);
 671
 672                 /*
 673                  * Read the AC97 status register to see if we've seen a CODEC READY
 674                  * signal from the AC97 codec.
 675                  */
 676                 acsts = csa_readio(resp, BA0_ACSTS);
 677                 if ((acsts & ACSTS_CRDY) != 0)
 678                         break;
 679         }
 680
 681         /*
 682          * Make sure we sampled CODEC READY.
 683          */
 684         if ((acsts & ACSTS_CRDY) == 0)
 685                 return (ENXIO);
 686
 687         /*
 688          * Assert the vaid frame signal so that we can start sending commands
 689          * to the AC97 codec.
 690          */
 691         csa_writeio(resp, BA0_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
 692
 693         /*
 694          * Wait until we've sampled input slots 3 and 4 as valid, meaning that
 695          * the codec is pumping ADC data across the AC-link.
 696          */
 697         acisv = 0;
 698         for (i = 0 ; i < 1000 ; i++) {
 699                 /*
 700                  * First, lets wait a short while to let things settle out a bit,
 701                  * and to prevent retrying the read too quickly.
 702                  */
 703 #ifdef notdef
 704                 DELAY(10000000L); /* clw */
 705 #else
 706                 DELAY(1000);
 707 #endif /* notdef */
 708                 /*
 709                  * Read the input slot valid register and see if input slots 3 and
 710                  * 4 are valid yet.
 711                  */
 712                 acisv = csa_readio(resp, BA0_ACISV);
 713                 if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4))
 714                         break;
 715         }
 716         /*
 717          * Make sure we sampled valid input slots 3 and 4.  If not, then return
 718          * an error.
 719          */
 720         if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) != (ACISV_ISV3 | ACISV_ISV4))
 721                 return (ENXIO);
 722
 723         /*
 724          * Now, assert valid frame and the slot 3 and 4 valid bits.  This will
 725          * commense the transfer of digital audio data to the AC97 codec.
 726          */
 727         csa_writeio(resp, BA0_ACOSV, ACOSV_SLV3 | ACOSV_SLV4);
 728
 729         /*
 730          * Power down the DAC and ADC.  We will power them up (if) when we need
 731          * them.
 732          */
 733 #ifdef notdef
 734         csa_writeio(resp, BA0_AC97_POWERDOWN, 0x300);
 735 #endif /* notdef */
 736
 737         /*
 738          * Turn off the Processor by turning off the software clock enable flag in
 739          * the clock control register.
 740          */
 741 #ifdef notdef
 742         clkcr1 = csa_readio(resp, BA0_CLKCR1) & ~CLKCR1_SWCE;
 743         csa_writeio(resp, BA0_CLKCR1, clkcr1);
 744 #endif /* notdef */
 745
 746         /*
 747          * Enable interrupts on the part.
 748          */
 749 #if 0
 750         csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
 751 #endif /* notdef */
 752
 753         return (0);
 754 }
 755
 756 void
 757 csa_clearserialfifos(csa_res *resp)
 758 {
 759         int i, j, pwr;
 760         u_int8_t clkcr1, serbst;
 761
 762         /*
 763          * See if the devices are powered down.  If so, we must power them up first
 764          * or they will not respond.
 765          */
 766         pwr = 1;
 767         clkcr1 = csa_readio(resp, BA0_CLKCR1);
 768         if ((clkcr1 & CLKCR1_SWCE) == 0) {
 769                 csa_writeio(resp, BA0_CLKCR1, clkcr1 | CLKCR1_SWCE);
 770                 pwr = 0;
 771         }
 772
 773         /*
 774          * We want to clear out the serial port FIFOs so we don't end up playing
 775          * whatever random garbage happens to be in them.  We fill the sample FIFOs
 776          * with zero (silence).
 777          */
 778         csa_writeio(resp, BA0_SERBWP, 0);
 779
 780         /* Fill all 256 sample FIFO locations. */
 781         serbst = 0;
 782         for (i = 0 ; i < 256 ; i++) {
 783                 /* Make sure the previous FIFO write operation has completed. */
 784                 for (j = 0 ; j < 5 ; j++) {
 785                         DELAY(100);
 786                         serbst = csa_readio(resp, BA0_SERBST);
 787                         if ((serbst & SERBST_WBSY) == 0)
 788                                 break;
 789                 }
 790                 if ((serbst & SERBST_WBSY) != 0) {
 791                         if (!pwr)
 792                                 csa_writeio(resp, BA0_CLKCR1, clkcr1);
 793                 }
 794                 /* Write the serial port FIFO index. */
 795                 csa_writeio(resp, BA0_SERBAD, i);
 796                 /* Tell the serial port to load the new value into the FIFO location. */
 797                 csa_writeio(resp, BA0_SERBCM, SERBCM_WRC);
 798         }
 799         /*
 800          *  Now, if we powered up the devices, then power them back down again.
 801          *  This is kinda ugly, but should never happen.
 802          */
 803         if (!pwr)
 804                 csa_writeio(resp, BA0_CLKCR1, clkcr1);
 805 }
 806
 807 void
 808 csa_resetdsp(csa_res *resp)
 809 {
 810         int i;
 811
 812         /*
 813          * Write the reset bit of the SP control register.
 814          */
 815         csa_writemem(resp, BA1_SPCR, SPCR_RSTSP);
 816
 817         /*
 818          * Write the control register.
 819          */
 820         csa_writemem(resp, BA1_SPCR, SPCR_DRQEN);
 821
 822         /*
 823          * Clear the trap registers.
 824          */
 825         for (i = 0 ; i < 8 ; i++) {
 826                 csa_writemem(resp, BA1_DREG, DREG_REGID_TRAP_SELECT + i);
 827                 csa_writemem(resp, BA1_TWPR, 0xffff);
 828         }
 829         csa_writemem(resp, BA1_DREG, 0);
 830
 831         /*
 832          * Set the frame timer to reflect the number of cycles per frame.
 833          */
 834         csa_writemem(resp, BA1_FRMT, 0xadf);
 835 }
 836
 837 static int
 838 csa_downloadimage(csa_res *resp)
 839 {
 840         int i;
 841         u_int32_t tmp, src, dst, count, data;
 842
 843         for (i = 0; i < CLEAR__COUNT; i++) {
 844                 dst = ClrStat[i].BA1__DestByteOffset;
 845                 count = ClrStat[i].BA1__SourceSize;
 846                 for (tmp = 0; tmp < count; tmp += 4)
 847                         csa_writemem(resp, dst + tmp, 0x00000000);
 848         }
 849
 850         for (i = 0; i < FILL__COUNT; i++) {
 851                 src = 0;
 852                 dst = FillStat[i].Offset;
 853                 count = FillStat[i].Size;
 854                 for (tmp = 0; tmp < count; tmp += 4) {
 855                         data = FillStat[i].pFill[src];
 856                         csa_writemem(resp, dst + tmp, data);
 857                         src++;
 858                 }
 859         }
 860
 861         return (0);
 862 }
 863
 864 int
 865 csa_readcodec(csa_res *resp, u_long offset, u_int32_t *data)
 866 {
 867         int i;
 868         u_int32_t acsda, acctl, acsts;
 869
 870         /*
 871          * Make sure that there is not data sitting around from a previous
 872          * uncompleted access. ACSDA = Status Data Register = 47Ch
 873          */
 874         acsda = csa_readio(resp, BA0_ACSDA);
 875
 876         /*
 877          * Setup the AC97 control registers on the CS461x to send the
 878          * appropriate command to the AC97 to perform the read.
 879          * ACCAD = Command Address Register = 46Ch
 880          * ACCDA = Command Data Register = 470h
 881          * ACCTL = Control Register = 460h
 882          * set DCV - will clear when process completed
 883          * set CRW - Read command
 884          * set VFRM - valid frame enabled
 885          * set ESYN - ASYNC generation enabled
 886          * set RSTN - ARST# inactive, AC97 codec not reset
 887          */
 888
 889         /*
 890          * Get the actual AC97 register from the offset
 891          */
 892         csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET);
 893         csa_writeio(resp, BA0_ACCDA, 0);
 894         csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
 895
 896         /*
 897          * Wait for the read to occur.
 898          */
 899         acctl = 0;
 900         for (i = 0 ; i < 10 ; i++) {
 901                 /*
 902                  * First, we want to wait for a short time.
 903                  */
 904                 DELAY(25);
 905
 906                 /*
 907                  * Now, check to see if the read has completed.
 908                  * ACCTL = 460h, DCV should be reset by now and 460h = 17h
 909                  */
 910                 acctl = csa_readio(resp, BA0_ACCTL);
 911                 if ((acctl & ACCTL_DCV) == 0)
 912                         break;
 913         }
 914
 915         /*
 916          * Make sure the read completed.
 917          */
 918         if ((acctl & ACCTL_DCV) != 0)
 919                 return (EAGAIN);
 920
 921         /*
 922          * Wait for the valid status bit to go active.
 923          */
 924         acsts = 0;
 925         for (i = 0 ; i < 10 ; i++) {
 926                 /*
 927                  * Read the AC97 status register.
 928                  * ACSTS = Status Register = 464h
 929                  */
 930                 acsts = csa_readio(resp, BA0_ACSTS);
 931                 /*
 932                  * See if we have valid status.
 933                  * VSTS - Valid Status
 934                  */
 935                 if ((acsts & ACSTS_VSTS) != 0)
 936                         break;
 937                 /*
 938                  * Wait for a short while.
 939                  */
 940                  DELAY(25);
 941         }
 942
 943         /*
 944          * Make sure we got valid status.
 945          */
 946         if ((acsts & ACSTS_VSTS) == 0)
 947                 return (EAGAIN);
 948
 949         /*
 950          * Read the data returned from the AC97 register.
 951          * ACSDA = Status Data Register = 474h
 952          */
 953         *data = csa_readio(resp, BA0_ACSDA);
 954
 955         return (0);
 956 }
 957
 958 int
 959 csa_writecodec(csa_res *resp, u_long offset, u_int32_t data)
 960 {
 961         int i;
 962         u_int32_t acctl;
 963
 964         /*
 965          * Setup the AC97 control registers on the CS461x to send the
 966          * appropriate command to the AC97 to perform the write.
 967          * ACCAD = Command Address Register = 46Ch
 968          * ACCDA = Command Data Register = 470h
 969          * ACCTL = Control Register = 460h
 970          * set DCV - will clear when process completed
 971          * set VFRM - valid frame enabled
 972          * set ESYN - ASYNC generation enabled
 973          * set RSTN - ARST# inactive, AC97 codec not reset
 974          */
 975
 976         /*
 977          * Get the actual AC97 register from the offset
 978          */
 979         csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET);
 980         csa_writeio(resp, BA0_ACCDA, data);
 981         csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
 982
 983         /*
 984          * Wait for the write to occur.
 985          */
 986         acctl = 0;
 987         for (i = 0 ; i < 10 ; i++) {
 988                 /*
 989                  * First, we want to wait for a short time.
 990                  */
 991                 DELAY(25);
 992
 993                 /*
 994                  * Now, check to see if the read has completed.
 995                  * ACCTL = 460h, DCV should be reset by now and 460h = 17h
 996                  */
 997                 acctl = csa_readio(resp, BA0_ACCTL);
 998                 if ((acctl & ACCTL_DCV) == 0)
 999                         break;
1000         }
1001
1002         /*
1003          * Make sure the write completed.
1004          */
1005         if ((acctl & ACCTL_DCV) != 0)
1006                 return (EAGAIN);
1007
1008         return (0);
1009 }
1010
1011 u_int32_t
1012 csa_readio(csa_res *resp, u_long offset)
1013 {
1014         u_int32_t ul;
1015
1016         if (offset < BA0_AC97_RESET)
1017                 return bus_space_read_4(rman_get_bustag(resp->io), rman_get_bushandle(resp->io), offset) & 0xffffffff;
1018         else {
1019                 if (csa_readcodec(resp, offset, &ul))
1020                         ul = 0;
1021                 return (ul);
1022         }
1023 }
1024
1025 void
1026 csa_writeio(csa_res *resp, u_long offset, u_int32_t data)
1027 {
1028         if (offset < BA0_AC97_RESET)
1029                 bus_space_write_4(rman_get_bustag(resp->io), rman_get_bushandle(resp->io), offset, data);
1030         else
1031                 csa_writecodec(resp, offset, data);
1032 }
1033
1034 u_int32_t
1035 csa_readmem(csa_res *resp, u_long offset)
1036 {
1037         return bus_space_read_4(rman_get_bustag(resp->mem), rman_get_bushandle(resp->mem), offset);
1038 }
1039
1040 void
1041 csa_writemem(csa_res *resp, u_long offset, u_int32_t data)
1042 {
1043         bus_space_write_4(rman_get_bustag(resp->mem), rman_get_bushandle(resp->mem), offset, data);
1044 }
1045
1046 static device_method_t csa_methods[] = {
1047         /* Device interface */
1048         DEVMETHOD(device_probe,         csa_probe),
1049         DEVMETHOD(device_attach,        csa_attach),
1050         DEVMETHOD(device_detach,        csa_detach),
1051         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
1052         DEVMETHOD(device_suspend,       bus_generic_suspend),
1053         DEVMETHOD(device_resume,        csa_resume),
1054
1055         /* Bus interface */
1056         DEVMETHOD(bus_print_child,      bus_generic_print_child),
1057         DEVMETHOD(bus_alloc_resource,   csa_alloc_resource),
1058         DEVMETHOD(bus_release_resource, csa_release_resource),
1059         DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
1060         DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
1061         DEVMETHOD(bus_setup_intr,       csa_setup_intr),
1062         DEVMETHOD(bus_teardown_intr,    csa_teardown_intr),
1063
1064         { 0, 0 }
1065 };
1066
1067 static driver_t csa_driver = {
1068         "csa",
1069         csa_methods,
1070         sizeof(struct csa_softc),
1071 };
1072
1073 /*
1074  * csa can be attached to a pci bus.
1075  */
1076 DRIVER_MODULE(snd_csa, pci, csa_driver, csa_devclass, 0, 0);
1077 MODULE_DEPEND(snd_csa, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
1078 MODULE_VERSION(snd_csa, 1);