sys/dev/sound/pci/atiixp.h

   1 /*-
   2  * Copyright (c) 2005 Ariff Abdullah <ariff@FreeBSD.org>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  *
  26  * $FreeBSD: src/sys/dev/sound/pci/atiixp.h,v 1.1.2.2 2006/03/02 00:09:30 ariff Exp $
  27  * $DragonFly: src/sys/dev/sound/pci/atiixp.h,v 1.1 2007/01/04 21:47:02 corecode Exp $
  28  */
  29
  30 #ifndef _ATIIXP_H_
  31 #define _ATIIXP_H_
  32
  33 /*
  34  * Constants, pretty much FreeBSD specific.
  35  */
  36
  37 /* Number of playback / recording channel */
  38 #define ATI_IXP_NPCHAN          1
  39 #define ATI_IXP_NRCHAN          1
  40 #define ATI_IXP_NCHANS          (ATI_IXP_NPCHAN + ATI_IXP_NRCHAN)
  41
  42 /*
  43  * Maximum segments/descriptors is 256, but 2 for
  44  * each channel should be more than enough for us.
  45  */
  46 #define ATI_IXP_DMA_CHSEGS      2
  47 #define ATI_IXP_DMA_CHSEGS_MIN  2
  48 #define ATI_IXP_DMA_CHSEGS_MAX  256
  49
  50 #define ATI_IXP_DEFAULT_BUFSZ   (1 << 13)       /* 8192 */
  51
  52 #define ATI_VENDOR_ID           0x1002  /* ATI Technologies */
  53 #define ATI_IXP_200_ID          0x4341
  54 #define ATI_IXP_300_ID          0x4361
  55 #define ATI_IXP_400_ID          0x4370
  56
  57 #define ATI_IXP_BASE_RATE       48000
  58
  59 /*
  60  * Register definitions for ATI IXP
  61  *
  62  * References: ALSA snd-atiixp.c , OpenBSD/NetBSD auixp-*.h
  63  */
  64
  65 #define ATI_IXP_CODECS 3
  66
  67 #define ATI_REG_ISR                     0x00            /* interrupt source */
  68 #define  ATI_REG_ISR_IN_XRUN            (1U<<0)
  69 #define  ATI_REG_ISR_IN_STATUS          (1U<<1)
  70 #define  ATI_REG_ISR_OUT_XRUN           (1U<<2)
  71 #define  ATI_REG_ISR_OUT_STATUS         (1U<<3)
  72 #define  ATI_REG_ISR_SPDF_XRUN          (1U<<4)
  73 #define  ATI_REG_ISR_SPDF_STATUS        (1U<<5)
  74 #define  ATI_REG_ISR_PHYS_INTR          (1U<<8)
  75 #define  ATI_REG_ISR_PHYS_MISMATCH      (1U<<9)
  76 #define  ATI_REG_ISR_CODEC0_NOT_READY   (1U<<10)
  77 #define  ATI_REG_ISR_CODEC1_NOT_READY   (1U<<11)
  78 #define  ATI_REG_ISR_CODEC2_NOT_READY   (1U<<12)
  79 #define  ATI_REG_ISR_NEW_FRAME          (1U<<13)
  80
  81 #define ATI_REG_IER                     0x04            /* interrupt enable */
  82 #define  ATI_REG_IER_IN_XRUN_EN         (1U<<0)
  83 #define  ATI_REG_IER_IO_STATUS_EN       (1U<<1)
  84 #define  ATI_REG_IER_OUT_XRUN_EN        (1U<<2)
  85 #define  ATI_REG_IER_OUT_XRUN_COND      (1U<<3)
  86 #define  ATI_REG_IER_SPDF_XRUN_EN       (1U<<4)
  87 #define  ATI_REG_IER_SPDF_STATUS_EN     (1U<<5)
  88 #define  ATI_REG_IER_PHYS_INTR_EN       (1U<<8)
  89 #define  ATI_REG_IER_PHYS_MISMATCH_EN   (1U<<9)
  90 #define  ATI_REG_IER_CODEC0_INTR_EN     (1U<<10)
  91 #define  ATI_REG_IER_CODEC1_INTR_EN     (1U<<11)
  92 #define  ATI_REG_IER_CODEC2_INTR_EN     (1U<<12)
  93 #define  ATI_REG_IER_NEW_FRAME_EN       (1U<<13)        /* (RO) */
  94 #define  ATI_REG_IER_SET_BUS_BUSY       (1U<<14)        /* (WO) audio is running */
  95
  96 #define ATI_REG_CMD                     0x08            /* command */
  97 #define  ATI_REG_CMD_POWERDOWN          (1U<<0)
  98 #define  ATI_REG_CMD_RECEIVE_EN         (1U<<1)
  99 #define  ATI_REG_CMD_SEND_EN            (1U<<2)
 100 #define  ATI_REG_CMD_STATUS_MEM         (1U<<3)
 101 #define  ATI_REG_CMD_SPDF_OUT_EN        (1U<<4)
 102 #define  ATI_REG_CMD_SPDF_STATUS_MEM    (1U<<5)
 103 #define  ATI_REG_CMD_SPDF_THRESHOLD     (3U<<6)
 104 #define  ATI_REG_CMD_SPDF_THRESHOLD_SHIFT       6
 105 #define  ATI_REG_CMD_IN_DMA_EN          (1U<<8)
 106 #define  ATI_REG_CMD_OUT_DMA_EN         (1U<<9)
 107 #define  ATI_REG_CMD_SPDF_DMA_EN        (1U<<10)
 108 #define  ATI_REG_CMD_SPDF_OUT_STOPPED   (1U<<11)
 109 #define  ATI_REG_CMD_SPDF_CONFIG_MASK   (7U<<12)
 110 #define   ATI_REG_CMD_SPDF_CONFIG_34    (1U<<12)
 111 #define   ATI_REG_CMD_SPDF_CONFIG_78    (2U<<12)
 112 #define   ATI_REG_CMD_SPDF_CONFIG_69    (3U<<12)
 113 #define   ATI_REG_CMD_SPDF_CONFIG_01    (4U<<12)
 114 #define  ATI_REG_CMD_INTERLEAVE_SPDF    (1U<<16)
 115 #define  ATI_REG_CMD_AUDIO_PRESENT      (1U<<20)
 116 #define  ATI_REG_CMD_INTERLEAVE_IN      (1U<<21)
 117 #define  ATI_REG_CMD_INTERLEAVE_OUT     (1U<<22)
 118 #define  ATI_REG_CMD_LOOPBACK_EN        (1U<<23)
 119 #define  ATI_REG_CMD_PACKED_DIS         (1U<<24)
 120 #define  ATI_REG_CMD_BURST_EN           (1U<<25)
 121 #define  ATI_REG_CMD_PANIC_EN           (1U<<26)
 122 #define  ATI_REG_CMD_MODEM_PRESENT      (1U<<27)
 123 #define  ATI_REG_CMD_ACLINK_ACTIVE      (1U<<28)
 124 #define  ATI_REG_CMD_AC_SOFT_RESET      (1U<<29)
 125 #define  ATI_REG_CMD_AC_SYNC            (1U<<30)
 126 #define  ATI_REG_CMD_AC_RESET           (1U<<31)
 127
 128 #define ATI_REG_PHYS_OUT_ADDR           0x0c
 129 #define  ATI_REG_PHYS_OUT_CODEC_MASK    (3U<<0)
 130 #define  ATI_REG_PHYS_OUT_RW            (1U<<2)
 131 #define  ATI_REG_PHYS_OUT_ADDR_EN       (1U<<8)
 132 #define  ATI_REG_PHYS_OUT_ADDR_SHIFT    9
 133 #define  ATI_REG_PHYS_OUT_DATA_SHIFT    16
 134
 135 #define ATI_REG_PHYS_IN_ADDR            0x10
 136 #define  ATI_REG_PHYS_IN_READ_FLAG      (1U<<8)
 137 #define  ATI_REG_PHYS_IN_ADDR_SHIFT     9
 138 #define  ATI_REG_PHYS_IN_DATA_SHIFT     16
 139
 140 #define ATI_REG_SLOTREQ                 0x14
 141
 142 #define ATI_REG_COUNTER                 0x18
 143 #define  ATI_REG_COUNTER_SLOT           (3U<<0)         /* slot # */
 144 #define  ATI_REG_COUNTER_BITCLOCK       (31U<<8)
 145
 146 #define ATI_REG_IN_FIFO_THRESHOLD       0x1c
 147
 148 #define ATI_REG_IN_DMA_LINKPTR          0x20
 149 #define ATI_REG_IN_DMA_DT_START         0x24            /* RO */
 150 #define ATI_REG_IN_DMA_DT_NEXT          0x28            /* RO */
 151 #define ATI_REG_IN_DMA_DT_CUR           0x2c            /* RO */
 152 #define ATI_REG_IN_DMA_DT_SIZE          0x30
 153
 154 #define ATI_REG_OUT_DMA_SLOT            0x34
 155 #define  ATI_REG_OUT_DMA_SLOT_BIT(x)    (1U << ((x) - 3))
 156 #define  ATI_REG_OUT_DMA_SLOT_MASK      0x1ff
 157 #define  ATI_REG_OUT_DMA_THRESHOLD_MASK 0xf800
 158 #define  ATI_REG_OUT_DMA_THRESHOLD_SHIFT        11
 159
 160 #define ATI_REG_OUT_DMA_LINKPTR         0x38
 161 #define ATI_REG_OUT_DMA_DT_START        0x3c            /* RO */
 162 #define ATI_REG_OUT_DMA_DT_NEXT         0x40            /* RO */
 163 #define ATI_REG_OUT_DMA_DT_CUR          0x44            /* RO */
 164 #define ATI_REG_OUT_DMA_DT_SIZE         0x48
 165
 166 #define ATI_REG_SPDF_CMD                0x4c
 167 #define  ATI_REG_SPDF_CMD_LFSR          (1U<<4)
 168 #define  ATI_REG_SPDF_CMD_SINGLE_CH     (1U<<5)
 169 #define  ATI_REG_SPDF_CMD_LFSR_ACC      (0xff<<8)       /* RO */
 170
 171 #define ATI_REG_SPDF_DMA_LINKPTR        0x50
 172 #define ATI_REG_SPDF_DMA_DT_START       0x54            /* RO */
 173 #define ATI_REG_SPDF_DMA_DT_NEXT        0x58            /* RO */
 174 #define ATI_REG_SPDF_DMA_DT_CUR         0x5c            /* RO */
 175 #define ATI_REG_SPDF_DMA_DT_SIZE        0x60
 176
 177 #define ATI_REG_MODEM_MIRROR            0x7c
 178 #define ATI_REG_AUDIO_MIRROR            0x80
 179
 180 #define ATI_REG_6CH_REORDER             0x84            /* reorder slots for 6ch */
 181 #define  ATI_REG_6CH_REORDER_EN         (1U<<0)         /* 3,4,7,8,6,9 -> 3,4,6,9,7,8 */
 182
 183 #define ATI_REG_FIFO_FLUSH              0x88
 184 #define  ATI_REG_FIFO_OUT_FLUSH         (1U<<0)
 185 #define  ATI_REG_FIFO_IN_FLUSH          (1U<<1)
 186
 187 /* LINKPTR */
 188 #define  ATI_REG_LINKPTR_EN             (1U<<0)
 189
 190 /* [INT|OUT|SPDIF]_DMA_DT_SIZE */
 191 #define  ATI_REG_DMA_DT_SIZE            (0xffffU<<0)
 192 #define  ATI_REG_DMA_FIFO_USED          (0x1fU<<16)
 193 #define  ATI_REG_DMA_FIFO_FREE          (0x1fU<<21)
 194 #define  ATI_REG_DMA_STATE              (7U<<26)
 195
 196 #define ATI_MAX_DESCRIPTORS     256     /* max number of descriptor packets */
 197
 198 /* codec detection constant indicating the interrupt flags */
 199 #define ALL_CODECS_NOT_READY \
 200     (ATI_REG_ISR_CODEC0_NOT_READY | ATI_REG_ISR_CODEC1_NOT_READY |\
 201      ATI_REG_ISR_CODEC2_NOT_READY)
 202 #define CODEC_CHECK_BITS (ALL_CODECS_NOT_READY|ATI_REG_ISR_NEW_FRAME)
 203
 204 #endif