sys/dev/disk/nata/ata-lowlevel.c

   1 /*-
   2  * Copyright (c) 1998 - 2006 Søren Schmidt <sos@FreeBSD.org>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer,
  10  *    without modification, immediately at the beginning of the file.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  18  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  20  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  21  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  22  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  23  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  24  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  25  *
  26  * $FreeBSD: src/sys/dev/ata/ata-lowlevel.c,v 1.77 2006/07/04 20:36:03 sos Exp $
  27  */
  28
  29 #include "opt_ata.h"
  30
  31 #include <sys/param.h>
  32 #include <sys/bus.h>
  33 #include <sys/callout.h>
  34 #include <sys/libkern.h>
  35 #include <sys/nata.h>
  36 #include <sys/systm.h>
  37
  38 #include "ata-all.h"
  39 #include "ata_if.h"
  40
  41 /* prototypes */
  42 static int ata_generic_status(device_t dev);
  43 static int ata_wait(struct ata_channel *ch, struct ata_device *, u_int8_t);
  44 static void ata_pio_read(struct ata_request *, int);
  45 static void ata_pio_write(struct ata_request *, int);
  46
  47 /*
  48  * low level ATA functions
  49  */
  50 void
  51 ata_generic_hw(device_t dev)
  52 {
  53     struct ata_channel *ch = device_get_softc(dev);
  54
  55     ch->hw.begin_transaction = ata_begin_transaction;
  56     ch->hw.end_transaction = ata_end_transaction;
  57     ch->hw.status = ata_generic_status;
  58     ch->hw.command = ata_generic_command;
  59 }
  60
  61 /* must be called with ATA channel locked and state_mtx held */
  62 int
  63 ata_begin_transaction(struct ata_request *request)
  64 {
  65     struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
  66     struct ata_device *atadev = device_get_softc(request->dev);
  67     int dummy, error;
  68
  69     ATA_DEBUG_RQ(request, "begin transaction");
  70
  71     /* disable ATAPI DMA writes if HW doesn't support it */
  72     if ((ch->flags & ATA_ATAPI_DMA_RO) &&
  73         ((request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE)) ==
  74          (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE)))
  75         request->flags &= ~ATA_R_DMA;
  76
  77     /* check for 48 bit access and convert if needed */
  78     ata_modify_if_48bit(request);
  79
  80     switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA)) {
  81
  82     /* ATA PIO data transfer and control commands */
  83     default:
  84         {
  85         /* record command direction here as our request might be gone later */
  86         int write = (request->flags & ATA_R_WRITE);
  87
  88             /* issue command */
  89             if (ch->hw.command(request)) {
  90                 device_printf(request->dev, "error issuing %s command\n",
  91                            ata_cmd2str(request));
  92                 request->result = EIO;
  93                 goto begin_finished;
  94             }
  95
  96             /* device reset doesn't interrupt */
  97             if (request->u.ata.command == ATA_DEVICE_RESET) {
  98                 int timeout = 1000000;
  99                 do {
 100                     DELAY(10);
 101                     request->status = ATA_IDX_INB(ch, ATA_STATUS);
 102                 } while (request->status & ATA_S_BUSY && timeout--);
 103                 if (request->status & ATA_S_ERROR)
 104                     request->error = ATA_IDX_INB(ch, ATA_ERROR);
 105                 goto begin_finished;
 106             }
 107
 108             /* if write command output the data */
 109             if (write) {
 110                 if (ata_wait(ch, atadev, (ATA_S_READY | ATA_S_DRQ)) < 0) {
 111                     device_printf(request->dev,
 112                                   "timeout waiting for write DRQ\n");
 113                     request->result = EIO;
 114                     goto begin_finished;
 115                 }
 116                 ata_pio_write(request, request->transfersize);
 117             }
 118         }
 119         goto begin_continue;
 120
 121     /* ATA DMA data transfer commands */
 122     case ATA_R_DMA:
 123         /* check sanity, setup SG list and DMA engine */
 124         if ((error = ch->dma->load(ch->dev, request->data, request->bytecount,
 125                                    request->flags & ATA_R_READ, ch->dma->sg,
 126                                    &dummy))) {
 127             device_printf(request->dev, "setting up DMA failed\n");
 128             request->result = error;
 129             goto begin_finished;
 130         }
 131
 132         /* issue command */
 133         if (ch->hw.command(request)) {
 134             device_printf(request->dev, "error issuing %s command\n",
 135                        ata_cmd2str(request));
 136             request->result = EIO;
 137             goto begin_finished;
 138         }
 139
 140         /* start DMA engine */
 141         if (ch->dma->start && ch->dma->start(request->dev)) {
 142             device_printf(request->dev, "error starting DMA\n");
 143             request->result = EIO;
 144             goto begin_finished;
 145         }
 146         goto begin_continue;
 147
 148     /* ATAPI PIO commands */
 149     case ATA_R_ATAPI:
 150         /* is this just a POLL DSC command ? */
 151         if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) {
 152             ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | atadev->unit);
 153             DELAY(10);
 154             if (!(ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_DSC))
 155                 request->result = EBUSY;
 156             goto begin_finished;
 157         }
 158
 159         /* start ATAPI operation */
 160         if (ch->hw.command(request)) {
 161             device_printf(request->dev, "error issuing ATA PACKET command\n");
 162             request->result = EIO;
 163             goto begin_finished;
 164         }
 165         goto begin_continue;
 166
 167    /* ATAPI DMA commands */
 168     case ATA_R_ATAPI|ATA_R_DMA:
 169         /* is this just a POLL DSC command ? */
 170         if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) {
 171             ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | atadev->unit);
 172             DELAY(10);
 173             if (!(ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_DSC))
 174                 request->result = EBUSY;
 175             goto begin_finished;
 176         }
 177
 178         /* check sanity, setup SG list and DMA engine */
 179         if ((error = ch->dma->load(ch->dev, request->data, request->bytecount,
 180                                    request->flags & ATA_R_READ, ch->dma->sg,
 181                                    &dummy))) {
 182             device_printf(request->dev, "setting up DMA failed\n");
 183             request->result = error;
 184             goto begin_finished;
 185         }
 186
 187         /* start ATAPI operation */
 188         if (ch->hw.command(request)) {
 189             device_printf(request->dev, "error issuing ATA PACKET command\n");
 190             request->result = EIO;
 191             goto begin_finished;
 192         }
 193
 194         /* start DMA engine */
 195         if (ch->dma->start && ch->dma->start(request->dev)) {
 196             request->result = EIO;
 197             goto begin_finished;
 198         }
 199         goto begin_continue;
 200     }
 201     /* NOT REACHED */
 202     kprintf("ata_begin_transaction OOPS!!!\n");
 203
 204 begin_finished:
 205     if (ch->dma && ch->dma->flags & ATA_DMA_LOADED)
 206         ch->dma->unload(ch->dev);
 207     return ATA_OP_FINISHED;
 208
 209 begin_continue:
 210     /* caller holds ch->state_mtx */
 211     callout_reset(&request->callout, request->timeout * hz,
 212                   (timeout_t*)ata_timeout, request);
 213     return ATA_OP_CONTINUES;
 214 }
 215
 216 /* must be called with ATA channel locked and state_mtx held */
 217 int
 218 ata_end_transaction(struct ata_request *request)
 219 {
 220     struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
 221     struct ata_device *atadev = device_get_softc(request->dev);
 222     int length;
 223
 224     ATA_DEBUG_RQ(request, "end transaction");
 225
 226     /* clear interrupt and get status */
 227     request->status = ATA_IDX_INB(ch, ATA_STATUS);
 228
 229     switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_CONTROL)) {
 230
 231     /* ATA PIO data transfer and control commands */
 232     default:
 233
 234         /* on timeouts we have no data or anything so just return */
 235         if (request->flags & ATA_R_TIMEOUT)
 236             goto end_finished;
 237
 238         /* on control commands read back registers to the request struct */
 239         if (request->flags & ATA_R_CONTROL) {
 240             if (atadev->flags & ATA_D_48BIT_ACTIVE) {
 241                 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT | ATA_A_HOB);
 242                 request->u.ata.count = (ATA_IDX_INB(ch, ATA_COUNT) << 8);
 243                 request->u.ata.lba =
 244                     ((u_int64_t)(ATA_IDX_INB(ch, ATA_SECTOR)) << 24) |
 245                     ((u_int64_t)(ATA_IDX_INB(ch, ATA_CYL_LSB)) << 32) |
 246                     ((u_int64_t)(ATA_IDX_INB(ch, ATA_CYL_MSB)) << 40);
 247
 248                 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT);
 249                 request->u.ata.count |= ATA_IDX_INB(ch, ATA_COUNT);
 250                 request->u.ata.lba |=
 251                     (ATA_IDX_INB(ch, ATA_SECTOR) |
 252                      (ATA_IDX_INB(ch, ATA_CYL_LSB) << 8) |
 253                      (ATA_IDX_INB(ch, ATA_CYL_MSB) << 16));
 254             }
 255             else {
 256                 request->u.ata.count = ATA_IDX_INB(ch, ATA_COUNT);
 257                 request->u.ata.lba = ATA_IDX_INB(ch, ATA_SECTOR) |
 258                                      (ATA_IDX_INB(ch, ATA_CYL_LSB) << 8) |
 259                                      (ATA_IDX_INB(ch, ATA_CYL_MSB) << 16) |
 260                                      ((ATA_IDX_INB(ch, ATA_DRIVE) & 0xf) << 24);
 261             }
 262         }
 263
 264         /* if we got an error we are done with the HW */
 265         if (request->status & ATA_S_ERROR) {
 266             request->error = ATA_IDX_INB(ch, ATA_ERROR);
 267             goto end_finished;
 268         }
 269
 270         /* are we moving data ? */
 271         if (request->flags & (ATA_R_READ | ATA_R_WRITE)) {
 272
 273             /* if read data get it */
 274             if (request->flags & ATA_R_READ) {
 275                 int flags = ATA_S_DRQ;
 276
 277                 if (request->u.ata.command != ATA_ATAPI_IDENTIFY)
 278                     flags |= ATA_S_READY;
 279                 if (ata_wait(ch, atadev, flags) < 0) {
 280                     device_printf(request->dev,
 281                                   "timeout waiting for read DRQ\n");
 282                     request->result = EIO;
 283                     goto end_finished;
 284                 }
 285                 ata_pio_read(request, request->transfersize);
 286             }
 287
 288             /* update how far we've gotten */
 289             request->donecount += request->transfersize;
 290
 291             /* do we need a scoop more ? */
 292             if (request->bytecount > request->donecount) {
 293
 294                 /* set this transfer size according to HW capabilities */
 295                 request->transfersize =
 296                     min((request->bytecount - request->donecount),
 297                         request->transfersize);
 298
 299                 /* if data write command, output the data */
 300                 if (request->flags & ATA_R_WRITE) {
 301
 302                     /* if we get an error here we are done with the HW */
 303                     if (ata_wait(ch, atadev, (ATA_S_READY | ATA_S_DRQ)) < 0) {
 304                         device_printf(request->dev,
 305                                       "timeout waiting for write DRQ\n");
 306                         request->status = ATA_IDX_INB(ch, ATA_STATUS);
 307                         goto end_finished;
 308                     }
 309
 310                     /* output data and return waiting for new interrupt */
 311                     ata_pio_write(request, request->transfersize);
 312                     goto end_continue;
 313                 }
 314
 315                 /* if data read command, return & wait for interrupt */
 316                 if (request->flags & ATA_R_READ)
 317                     goto end_continue;
 318             }
 319         }
 320         /* done with HW */
 321         goto end_finished;
 322
 323     /* ATA DMA data transfer commands */
 324     case ATA_R_DMA:
 325
 326         /* stop DMA engine and get status */
 327         if (ch->dma->stop)
 328             request->dmastat = ch->dma->stop(request->dev);
 329
 330         /* did we get error or data */
 331         if (request->status & ATA_S_ERROR)
 332             request->error = ATA_IDX_INB(ch, ATA_ERROR);
 333         else if (request->dmastat & ATA_BMSTAT_ERROR)
 334             request->status |= ATA_S_ERROR;
 335         else if (!(request->flags & ATA_R_TIMEOUT))
 336             request->donecount = request->bytecount;
 337
 338         /* release SG list etc */
 339         ch->dma->unload(ch->dev);
 340
 341         /* done with HW */
 342         goto end_finished;
 343
 344     /* ATAPI PIO commands */
 345     case ATA_R_ATAPI:
 346         length = ATA_IDX_INB(ch, ATA_CYL_LSB)|(ATA_IDX_INB(ch, ATA_CYL_MSB)<<8);
 347
 348         /* on timeouts we have no data or anything so just return */
 349         if (request->flags & ATA_R_TIMEOUT)
 350             goto end_finished;
 351
 352         switch ((ATA_IDX_INB(ch, ATA_IREASON) & (ATA_I_CMD | ATA_I_IN)) |
 353                 (request->status & ATA_S_DRQ)) {
 354
 355         case ATAPI_P_CMDOUT:
 356             /* this seems to be needed for some (slow) devices */
 357             DELAY(10);
 358
 359             if (!(request->status & ATA_S_DRQ)) {
 360                 device_printf(request->dev, "command interrupt without DRQ\n");
 361                 request->status = ATA_S_ERROR;
 362                 goto end_finished;
 363             }
 364             ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (int16_t *)request->u.atapi.ccb,
 365                                (atadev->param.config &
 366                                 ATA_PROTO_MASK)== ATA_PROTO_ATAPI_12 ? 6 : 8);
 367             /* return wait for interrupt */
 368             goto end_continue;
 369
 370         case ATAPI_P_WRITE:
 371             if (request->flags & ATA_R_READ) {
 372                 request->status = ATA_S_ERROR;
 373                 device_printf(request->dev,
 374                               "%s trying to write on read buffer\n",
 375                            ata_cmd2str(request));
 376                 goto end_finished;
 377             }
 378             ata_pio_write(request, length);
 379             request->donecount += length;
 380
 381             /* set next transfer size according to HW capabilities */
 382             request->transfersize = min((request->bytecount-request->donecount),
 383                                         request->transfersize);
 384             /* return wait for interrupt */
 385             goto end_continue;
 386
 387         case ATAPI_P_READ:
 388             if (request->flags & ATA_R_WRITE) {
 389                 request->status = ATA_S_ERROR;
 390                 device_printf(request->dev,
 391                               "%s trying to read on write buffer\n",
 392                            ata_cmd2str(request));
 393                 goto end_finished;
 394             }
 395             ata_pio_read(request, length);
 396             request->donecount += length;
 397
 398             /* set next transfer size according to HW capabilities */
 399             request->transfersize = min((request->bytecount-request->donecount),
 400                                         request->transfersize);
 401             /* return wait for interrupt */
 402             goto end_continue;
 403
 404         case ATAPI_P_DONEDRQ:
 405             device_printf(request->dev,
 406                           "WARNING - %s DONEDRQ non conformant device\n",
 407                           ata_cmd2str(request));
 408             if (request->flags & ATA_R_READ) {
 409                 ata_pio_read(request, length);
 410                 request->donecount += length;
 411             }
 412             else if (request->flags & ATA_R_WRITE) {
 413                 ata_pio_write(request, length);
 414                 request->donecount += length;
 415             }
 416             else
 417                 request->status = ATA_S_ERROR;
 418             /* FALLTHROUGH */
 419
 420         case ATAPI_P_ABORT:
 421         case ATAPI_P_DONE:
 422             if (request->status & (ATA_S_ERROR | ATA_S_DWF))
 423                 request->error = ATA_IDX_INB(ch, ATA_ERROR);
 424             goto end_finished;
 425
 426         default:
 427             device_printf(request->dev, "unknown transfer phase\n");
 428             request->status = ATA_S_ERROR;
 429         }
 430
 431         /* done with HW */
 432         goto end_finished;
 433
 434     /* ATAPI DMA commands */
 435     case ATA_R_ATAPI|ATA_R_DMA:
 436
 437         /* stop DMA engine and get status */
 438         if (ch->dma->stop)
 439             request->dmastat = ch->dma->stop(request->dev);
 440
 441         /* did we get error or data */
 442         if (request->status & (ATA_S_ERROR | ATA_S_DWF))
 443             request->error = ATA_IDX_INB(ch, ATA_ERROR);
 444         else if (request->dmastat & ATA_BMSTAT_ERROR)
 445             request->status |= ATA_S_ERROR;
 446         else if (!(request->flags & ATA_R_TIMEOUT))
 447             request->donecount = request->bytecount;
 448
 449         /* release SG list etc */
 450         ch->dma->unload(ch->dev);
 451
 452         /* done with HW */
 453         goto end_finished;
 454     }
 455     /* NOT REACHED */
 456     kprintf("ata_end_transaction OOPS!!\n");
 457
 458 end_finished:
 459     callout_stop_sync(&request->callout);
 460     return ATA_OP_FINISHED;
 461
 462 end_continue:
 463     return ATA_OP_CONTINUES;
 464 }
 465
 466 /* must be called with ATA channel locked and state_mtx held */
 467 void
 468 ata_generic_reset(device_t dev)
 469 {
 470     struct ata_channel *ch = device_get_softc(dev);
 471
 472     u_int8_t ostat0 = 0, stat0 = 0, ostat1 = 0, stat1 = 0;
 473     u_int8_t err = 0, lsb = 0, msb = 0;
 474     int mask = 0, timeout;
 475
 476     /* do we have any signs of ATA/ATAPI HW being present ? */
 477     ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_MASTER);
 478     DELAY(10);
 479     ostat0 = ATA_IDX_INB(ch, ATA_STATUS);
 480     if ((ostat0 & 0xf8) != 0xf8 && ostat0 != 0xa5) {
 481         stat0 = ATA_S_BUSY;
 482         mask |= 0x01;
 483     }
 484
 485     /* in some setups we dont want to test for a slave */
 486     if (!(ch->flags & ATA_NO_SLAVE)) {
 487         ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_SLAVE);
 488         DELAY(10);
 489         ostat1 = ATA_IDX_INB(ch, ATA_STATUS);
 490         if ((ostat1 & 0xf8) != 0xf8 && ostat1 != 0xa5) {
 491             stat1 = ATA_S_BUSY;
 492             mask |= 0x02;
 493         }
 494     }
 495
 496     if (bootverbose)
 497         device_printf(dev, "reset tp1 mask=%02x ostat0=%02x ostat1=%02x\n",
 498                       mask, ostat0, ostat1);
 499
 500     /* if nothing showed up there is no need to get any further */
 501     /* XXX SOS is that too strong?, we just might loose devices here */
 502     ch->devices = 0;
 503     if (!mask)
 504         return;
 505
 506     /* reset (both) devices on this channel */
 507     ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_MASTER);
 508     DELAY(10);
 509     ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS | ATA_A_RESET);
 510     ata_udelay(10000);
 511     ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS);
 512     ata_udelay(100000);
 513     ATA_IDX_INB(ch, ATA_ERROR);
 514
 515     /* wait for BUSY to go inactive */
 516     for (timeout = 0; timeout < 310; timeout++) {
 517         if ((mask & 0x01) && (stat0 & ATA_S_BUSY)) {
 518             ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_MASTER);
 519             DELAY(10);
 520             err = ATA_IDX_INB(ch, ATA_ERROR);
 521             lsb = ATA_IDX_INB(ch, ATA_CYL_LSB);
 522             msb = ATA_IDX_INB(ch, ATA_CYL_MSB);
 523             stat0 = ATA_IDX_INB(ch, ATA_STATUS);
 524             if (bootverbose)
 525                 device_printf(dev,
 526                               "stat0=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n",
 527                               stat0, err, lsb, msb);
 528             if (stat0 == err && lsb == err && msb == err &&
 529                 timeout > (stat0 & ATA_S_BUSY ? 100 : 10))
 530                 mask &= ~0x01;
 531             if (!(stat0 & ATA_S_BUSY)) {
 532                 if ((err & 0x7f) == ATA_E_ILI) {
 533                     if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) {
 534                         ch->devices |= ATA_ATAPI_MASTER;
 535                     }
 536                     else if (stat0 & ATA_S_READY) {
 537                         ch->devices |= ATA_ATA_MASTER;
 538                     }
 539                 }
 540                 else if ((stat0 & 0x0f) && err == lsb && err == msb) {
 541                     stat0 |= ATA_S_BUSY;
 542                 }
 543             }
 544         }
 545
 546         if ((mask & 0x02) && (stat1 & ATA_S_BUSY) &&
 547             !((mask & 0x01) && (stat0 & ATA_S_BUSY))) {
 548             ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_SLAVE);
 549             DELAY(10);
 550             err = ATA_IDX_INB(ch, ATA_ERROR);
 551             lsb = ATA_IDX_INB(ch, ATA_CYL_LSB);
 552             msb = ATA_IDX_INB(ch, ATA_CYL_MSB);
 553             stat1 = ATA_IDX_INB(ch, ATA_STATUS);
 554             if (bootverbose)
 555                 device_printf(dev,
 556                               "stat1=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n",
 557                               stat1, err, lsb, msb);
 558             if (stat1 == err && lsb == err && msb == err &&
 559                 timeout > (stat1 & ATA_S_BUSY ? 100 : 10))
 560                 mask &= ~0x02;
 561             if (!(stat1 & ATA_S_BUSY)) {
 562                 if ((err & 0x7f) == ATA_E_ILI) {
 563                     if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) {
 564                         ch->devices |= ATA_ATAPI_SLAVE;
 565                     }
 566                     else if (stat1 & ATA_S_READY) {
 567                         ch->devices |= ATA_ATA_SLAVE;
 568                     }
 569                 }
 570                 else if ((stat1 & 0x0f) && err == lsb && err == msb) {
 571                     stat1 |= ATA_S_BUSY;
 572                 }
 573             }
 574         }
 575
 576         if (mask == 0x00)       /* nothing to wait for */
 577             break;
 578         if (mask == 0x01)       /* wait for master only */
 579             if (!(stat0 & ATA_S_BUSY) || (stat0 == 0xff && timeout > 10))
 580                 break;
 581         if (mask == 0x02)       /* wait for slave only */
 582             if (!(stat1 & ATA_S_BUSY) || (stat1 == 0xff && timeout > 10))
 583                 break;
 584         if (mask == 0x03) {     /* wait for both master & slave */
 585             if (!(stat0 & ATA_S_BUSY) && !(stat1 & ATA_S_BUSY))
 586                 break;
 587             if ((stat0 == 0xff) && (timeout > 20))
 588                 mask &= ~0x01;
 589             if ((stat1 == 0xff) && (timeout > 20))
 590                 mask &= ~0x02;
 591         }
 592         ata_udelay(100000);
 593     }
 594
 595     if (bootverbose)
 596         device_printf(dev, "reset tp2 stat0=%02x stat1=%02x devices=0x%b\n",
 597                       stat0, stat1, ch->devices,
 598                       "\20\4ATAPI_SLAVE\3ATAPI_MASTER\2ATA_SLAVE\1ATA_MASTER");
 599 }
 600
 601 /* must be called with ATA channel locked and state_mtx held */
 602 int
 603 ata_generic_status(device_t dev)
 604 {
 605     struct ata_channel *ch = device_get_softc(dev);
 606
 607     if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) {
 608         DELAY(100);
 609         if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY)
 610             return 0;
 611     }
 612     return 1;
 613 }
 614
 615 static int
 616 ata_wait(struct ata_channel *ch, struct ata_device *atadev, u_int8_t mask)
 617 {
 618     u_int8_t status;
 619     int timeout = 0;
 620
 621     DELAY(1);
 622
 623     /* wait at max 1 second for device to get !BUSY */
 624     while (timeout < 1000000) {
 625         status = ATA_IDX_INB(ch, ATA_ALTSTAT);
 626
 627         /* if drive fails status, reselect the drive and try again */
 628         if (status == 0xff) {
 629             ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | atadev->unit);
 630             timeout += 1000;
 631             DELAY(1000);
 632             continue;
 633         }
 634
 635         /* are we done ? */
 636         if (!(status & ATA_S_BUSY))
 637             break;
 638
 639         if (timeout > 1000) {
 640             timeout += 1000;
 641             DELAY(1000);
 642         }
 643         else {
 644             timeout += 10;
 645             DELAY(10);
 646         }
 647     }
 648     if (timeout >= 1000000)
 649         return -2;
 650     if (!mask)
 651         return (status & ATA_S_ERROR);
 652
 653     DELAY(1);
 654
 655     /* wait 50 msec for bits wanted */
 656     timeout = 5000;
 657     while (timeout--) {
 658         status = ATA_IDX_INB(ch, ATA_ALTSTAT);
 659         if ((status & mask) == mask)
 660             return (status & ATA_S_ERROR);
 661         DELAY(10);
 662     }
 663     return -3;
 664 }
 665
 666 int
 667 ata_generic_command(struct ata_request *request)
 668 {
 669     struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
 670     struct ata_device *atadev = device_get_softc(request->dev);
 671
 672     /* select device */
 673     ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | atadev->unit);
 674
 675     /* ready to issue command ? */
 676     if (ata_wait(ch, atadev, 0) < 0) {
 677         device_printf(request->dev, "timeout waiting to issue command\n");
 678         return -1;
 679     }
 680
 681     /* enable interrupt */
 682     ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT);
 683
 684     if (request->flags & ATA_R_ATAPI) {
 685         int timeout = 5000;
 686
 687         /* issue packet command to controller */
 688         if (request->flags & ATA_R_DMA) {
 689             ATA_IDX_OUTB(ch, ATA_FEATURE, ATA_F_DMA);
 690             ATA_IDX_OUTB(ch, ATA_CYL_LSB, 0);
 691             ATA_IDX_OUTB(ch, ATA_CYL_MSB, 0);
 692         }
 693         else {
 694             ATA_IDX_OUTB(ch, ATA_FEATURE, 0);
 695             ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->transfersize);
 696             ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->transfersize >> 8);
 697         }
 698         ATA_IDX_OUTB(ch, ATA_COMMAND, ATA_PACKET_CMD);
 699
 700         /* command interrupt device ? just return and wait for interrupt */
 701         if ((atadev->param.config & ATA_DRQ_MASK) == ATA_DRQ_INTR)
 702             return 0;
 703
 704         /* wait for ready to write ATAPI command block */
 705         while (timeout--) {
 706             int reason = ATA_IDX_INB(ch, ATA_IREASON);
 707             int status = ATA_IDX_INB(ch, ATA_STATUS);
 708
 709             if (((reason & (ATA_I_CMD | ATA_I_IN)) |
 710                  (status & (ATA_S_DRQ | ATA_S_BUSY))) == ATAPI_P_CMDOUT)
 711                 break;
 712             DELAY(20);
 713         }
 714         if (timeout <= 0) {
 715             device_printf(request->dev, "timeout waiting for ATAPI ready\n");
 716             request->result = EIO;
 717             return -1;
 718         }
 719
 720         /* this seems to be needed for some (slow) devices */
 721         DELAY(10);
 722
 723         /* output command block */
 724         ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (int16_t *)request->u.atapi.ccb,
 725                            (atadev->param.config & ATA_PROTO_MASK) ==
 726                            ATA_PROTO_ATAPI_12 ? 6 : 8);
 727     }
 728     else {
 729         if (atadev->flags & ATA_D_48BIT_ACTIVE) {
 730             ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature >> 8);
 731             ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature);
 732             ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count >> 8);
 733             ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count);
 734             ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba >> 24);
 735             ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba);
 736             ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 32);
 737             ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8);
 738             ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 40);
 739             ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16);
 740             ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_LBA | atadev->unit);
 741         }
 742         else {
 743             ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature);
 744             ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count);
 745             if (atadev->flags & ATA_D_USE_CHS) {
 746                 int heads, sectors;
 747
 748                 if (atadev->param.atavalid & ATA_FLAG_54_58) {
 749                     heads = atadev->param.current_heads;
 750                     sectors = atadev->param.current_sectors;
 751                 }
 752                 else {
 753                     heads = atadev->param.heads;
 754                     sectors = atadev->param.sectors;
 755                 }
 756                 ATA_IDX_OUTB(ch, ATA_SECTOR, (request->u.ata.lba % sectors)+1);
 757                 ATA_IDX_OUTB(ch, ATA_CYL_LSB,
 758                              (request->u.ata.lba / (sectors * heads)));
 759                 ATA_IDX_OUTB(ch, ATA_CYL_MSB,
 760                              (request->u.ata.lba / (sectors * heads)) >> 8);
 761                 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | atadev->unit |
 762                              (((request->u.ata.lba% (sectors * heads)) /
 763                                sectors) & 0xf));
 764             }
 765             else {
 766                 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba);
 767                 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8);
 768                 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16);
 769                 ATA_IDX_OUTB(ch, ATA_DRIVE,
 770                              ATA_D_IBM | ATA_D_LBA | atadev->unit |
 771                              ((request->u.ata.lba >> 24) & 0x0f));
 772             }
 773         }
 774
 775         /* issue command to controller */
 776         ATA_IDX_OUTB(ch, ATA_COMMAND, request->u.ata.command);
 777     }
 778
 779     return 0;
 780 }
 781
 782 static void
 783 ata_pio_read(struct ata_request *request, int length)
 784 {
 785     struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
 786     int size = min(request->transfersize, length);
 787     int resid;
 788
 789     if (ch->flags & ATA_USE_16BIT || (size % sizeof(int32_t)))
 790         ATA_IDX_INSW_STRM(ch, ATA_DATA,
 791                           (void*)((uintptr_t)request->data+request->donecount),
 792                           size / sizeof(int16_t));
 793     else
 794         ATA_IDX_INSL_STRM(ch, ATA_DATA,
 795                           (void*)((uintptr_t)request->data+request->donecount),
 796                           size / sizeof(int32_t));
 797
 798     if (request->transfersize < length) {
 799         device_printf(request->dev, "WARNING - %s read data overrun %d>%d\n",
 800                    ata_cmd2str(request), length, request->transfersize);
 801         for (resid = request->transfersize; resid < length;
 802              resid += sizeof(int16_t))
 803             ATA_IDX_INW(ch, ATA_DATA);
 804     }
 805 }
 806
 807 static void
 808 ata_pio_write(struct ata_request *request, int length)
 809 {
 810     struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
 811     int size = min(request->transfersize, length);
 812     int resid;
 813
 814     if (ch->flags & ATA_USE_16BIT || (size % sizeof(int32_t)))
 815         ATA_IDX_OUTSW_STRM(ch, ATA_DATA,
 816                            (void*)((uintptr_t)request->data+request->donecount),
 817                            size / sizeof(int16_t));
 818     else
 819         ATA_IDX_OUTSL_STRM(ch, ATA_DATA,
 820                            (void*)((uintptr_t)request->data+request->donecount),
 821                            size / sizeof(int32_t));
 822
 823     if (request->transfersize < length) {
 824         device_printf(request->dev, "WARNING - %s write data underrun %d>%d\n",
 825                    ata_cmd2str(request), length, request->transfersize);
 826         for (resid = request->transfersize; resid < length;
 827              resid += sizeof(int16_t))
 828             ATA_IDX_OUTW(ch, ATA_DATA, 0);
 829     }
 830 }