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sdhci - Handle ADMA error interrupt, similar to ACMD12 error interrupt.
[dragonfly.git] / sys / dev / disk / nata / ata-all.h
blob4008f052f90f6fe0bdf7562281992fa359477279
1 /*-
2 * Copyright (c) 1998 - 2006 Søren Schmidt <sos@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * $FreeBSD: src/sys/dev/ata/ata-all.h,v 1.123 2007/04/08 19:18:51 sos Exp $
27 */
28
29 #include <sys/param.h>
30 #include <sys/bio.h>
31 #include <sys/bus.h>
32 #include <sys/callout.h>
33 #include <sys/kernel.h>
34 #include <sys/malloc.h>
35 #include <sys/nata.h>
36 #include <sys/objcache.h>
37 #include <sys/queue.h>
38 #include <sys/rman.h>
39 #include <sys/systm.h>
40 #include <sys/taskqueue.h>
41
42 #include <machine/bus_dma.h>
43
44 /* ATA register defines */
45 #define ATA_DATA 0 /* (RW) data */
46
47 #define ATA_FEATURE 1 /* (W) feature */
48 #define ATA_F_DMA 0x01 /* enable DMA */
49 #define ATA_F_OVL 0x02 /* enable overlap */
50
51 #define ATA_COUNT 2 /* (W) sector count */
52
53 #define ATA_SECTOR 3 /* (RW) sector # */
54 #define ATA_CYL_LSB 4 /* (RW) cylinder# LSB */
55 #define ATA_CYL_MSB 5 /* (RW) cylinder# MSB */
56 #define ATA_DRIVE 6 /* (W) Sector/Drive/Head */
57 #define ATA_D_LBA 0x40 /* use LBA addressing */
58 #define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */
59
60 #define ATA_COMMAND 7 /* (W) command */
61
62 #define ATA_ERROR 8 /* (R) error */
63 #define ATA_E_ILI 0x01 /* illegal length */
64 #define ATA_E_NM 0x02 /* no media */
65 #define ATA_E_ABORT 0x04 /* command aborted */
66 #define ATA_E_MCR 0x08 /* media change request */
67 #define ATA_E_IDNF 0x10 /* ID not found */
68 #define ATA_E_MC 0x20 /* media changed */
69 #define ATA_E_UNC 0x40 /* uncorrectable data */
70 #define ATA_E_ICRC 0x80 /* UDMA crc error */
71 #define ATA_E_ATAPI_SENSE_MASK 0xf0 /* ATAPI sense key mask */
72
73 #define ATA_IREASON 9 /* (R) interrupt reason */
74 #define ATA_I_CMD 0x01 /* cmd (1) | data (0) */
75 #define ATA_I_IN 0x02 /* read (1) | write (0) */
76 #define ATA_I_RELEASE 0x04 /* released bus (1) */
77 #define ATA_I_TAGMASK 0xf8 /* tag mask */
78
79 #define ATA_STATUS 10 /* (R) status */
80 #define ATA_ALTSTAT 11 /* (R) alternate status */
81 #define ATA_S_ERROR 0x01 /* error */
82 #define ATA_S_INDEX 0x02 /* index */
83 #define ATA_S_CORR 0x04 /* data corrected */
84 #define ATA_S_DRQ 0x08 /* data request */
85 #define ATA_S_DSC 0x10 /* drive seek completed */
86 #define ATA_S_SERVICE 0x10 /* drive needs service */
87 #define ATA_S_DWF 0x20 /* drive write fault */
88 #define ATA_S_DMA 0x20 /* DMA ready */
89 #define ATA_S_READY 0x40 /* drive ready */
90 #define ATA_S_BUSY 0x80 /* busy */
91
92 #define ATA_CONTROL 12 /* (W) control */
93
94 #define ATA_CTLOFFSET 0x206 /* control register offset */
95 #define ATA_PCCARD_CTLOFFSET 0x0e /* do for PCCARD devices */
96 #define ATA_PC98_CTLOFFSET 0x10c /* do for PC98 devices */
97 #define ATA_A_IDS 0x02 /* disable interrupts */
98 #define ATA_A_RESET 0x04 /* RESET controller */
99 #define ATA_A_4BIT 0x08 /* 4 head bits */
100 #define ATA_A_HOB 0x80 /* High Order Byte enable */
101
102 /* SATA register defines */
103 #define ATA_SSTATUS 13
104 #define ATA_SS_DET_MASK 0x0000000f
105 #define ATA_SS_DET_NO_DEVICE 0x00000000
106 #define ATA_SS_DET_DEV_PRESENT 0x00000001
107 #define ATA_SS_DET_PHY_ONLINE 0x00000003
108 #define ATA_SS_DET_PHY_OFFLINE 0x00000004
109
110 #define ATA_SS_SPD_MASK 0x000000f0
111 #define ATA_SS_SPD_NO_SPEED 0x00000000
112 #define ATA_SS_SPD_GEN1 0x00000010
113 #define ATA_SS_SPD_GEN2 0x00000020
114
115 #define ATA_SS_IPM_MASK 0x00000f00
116 #define ATA_SS_IPM_NO_DEVICE 0x00000000
117 #define ATA_SS_IPM_ACTIVE 0x00000100
118 #define ATA_SS_IPM_PARTIAL 0x00000200
119 #define ATA_SS_IPM_SLUMBER 0x00000600
120
121 #define ATA_SS_CONWELL_MASK \
122 (ATA_SS_DET_MASK|ATA_SS_SPD_MASK|ATA_SS_IPM_MASK)
123 #define ATA_SS_CONWELL_GEN1 \
124 (ATA_SS_DET_PHY_ONLINE|ATA_SS_SPD_GEN1|ATA_SS_IPM_ACTIVE)
125 #define ATA_SS_CONWELL_GEN2 \
126 (ATA_SS_DET_PHY_ONLINE|ATA_SS_SPD_GEN2|ATA_SS_IPM_ACTIVE)
127
128 #define ATA_SERROR 14
129 #define ATA_SE_DATA_CORRECTED 0x00000001
130 #define ATA_SE_COMM_CORRECTED 0x00000002
131 #define ATA_SE_DATA_ERR 0x00000100
132 #define ATA_SE_COMM_ERR 0x00000200
133 #define ATA_SE_PROT_ERR 0x00000400
134 #define ATA_SE_HOST_ERR 0x00000800
135 #define ATA_SE_PHY_CHANGED 0x00010000
136 #define ATA_SE_PHY_IERROR 0x00020000
137 #define ATA_SE_COMM_WAKE 0x00040000
138 #define ATA_SE_DECODE_ERR 0x00080000
139 #define ATA_SE_PARITY_ERR 0x00100000
140 #define ATA_SE_CRC_ERR 0x00200000
141 #define ATA_SE_HANDSHAKE_ERR 0x00400000
142 #define ATA_SE_LINKSEQ_ERR 0x00800000
143 #define ATA_SE_TRANSPORT_ERR 0x01000000
144 #define ATA_SE_UNKNOWN_FIS 0x02000000
145
146 #define ATA_SCONTROL 15
147 #define ATA_SC_DET_MASK 0x0000000f
148 #define ATA_SC_DET_IDLE 0x00000000
149 #define ATA_SC_DET_RESET 0x00000001
150 #define ATA_SC_DET_DISABLE 0x00000004
151
152 #define ATA_SC_SPD_MASK 0x000000f0
153 #define ATA_SC_SPD_NO_SPEED 0x00000000
154 #define ATA_SC_SPD_SPEED_GEN1 0x00000010
155 #define ATA_SC_SPD_SPEED_GEN2 0x00000020
156
157 #define ATA_SC_IPM_MASK 0x00000f00
158 #define ATA_SC_IPM_NONE 0x00000000
159 #define ATA_SC_IPM_DIS_PARTIAL 0x00000100
160 #define ATA_SC_IPM_DIS_SLUMBER 0x00000200
161
162 #define ATA_SACTIVE 16
163
164 /* SATA AHCI v1.0 register defines */
165 #define ATA_AHCI_CAP 0x00
166 #define ATA_AHCI_NPMASK 0x1f
167 #define ATA_AHCI_CAP_CLO 0x01000000
168 #define ATA_AHCI_CAP_64BIT 0x80000000
169
170 #define ATA_AHCI_GHC 0x04
171 #define ATA_AHCI_GHC_AE 0x80000000
172 #define ATA_AHCI_GHC_IE 0x00000002
173 #define ATA_AHCI_GHC_HR 0x80000001
174
175 #define ATA_AHCI_IS 0x08
176 #define ATA_AHCI_PI 0x0c
177 #define ATA_AHCI_VS 0x10
178
179 #define ATA_AHCI_OFFSET 0x80
180
181 #define ATA_AHCI_P_CLB 0x100
182 #define ATA_AHCI_P_CLBU 0x104
183 #define ATA_AHCI_P_FB 0x108
184 #define ATA_AHCI_P_FBU 0x10c
185 #define ATA_AHCI_P_IS 0x110
186 #define ATA_AHCI_P_IE 0x114
187 #define ATA_AHCI_P_IX_DHR 0x00000001
188 #define ATA_AHCI_P_IX_PS 0x00000002
189 #define ATA_AHCI_P_IX_DS 0x00000004
190 #define ATA_AHCI_P_IX_SDB 0x00000008
191 #define ATA_AHCI_P_IX_UF 0x00000010
192 #define ATA_AHCI_P_IX_DP 0x00000020
193 #define ATA_AHCI_P_IX_PC 0x00000040
194 #define ATA_AHCI_P_IX_DI 0x00000080
195
196 #define ATA_AHCI_P_IX_PRC 0x00400000
197 #define ATA_AHCI_P_IX_IPM 0x00800000
198 #define ATA_AHCI_P_IX_OF 0x01000000
199 #define ATA_AHCI_P_IX_INF 0x04000000
200 #define ATA_AHCI_P_IX_IF 0x08000000
201 #define ATA_AHCI_P_IX_HBD 0x10000000
202 #define ATA_AHCI_P_IX_HBF 0x20000000
203 #define ATA_AHCI_P_IX_TFE 0x40000000
204 #define ATA_AHCI_P_IX_CPD 0x80000000
205
206 #define ATA_AHCI_P_CMD 0x118
207 #define ATA_AHCI_P_CMD_ST 0x00000001
208 #define ATA_AHCI_P_CMD_SUD 0x00000002
209 #define ATA_AHCI_P_CMD_POD 0x00000004
210 #define ATA_AHCI_P_CMD_CLO 0x00000008
211 #define ATA_AHCI_P_CMD_FRE 0x00000010
212 #define ATA_AHCI_P_CMD_CCS_MASK 0x00001f00
213 #define ATA_AHCI_P_CMD_ISS 0x00002000
214 #define ATA_AHCI_P_CMD_FR 0x00004000
215 #define ATA_AHCI_P_CMD_CR 0x00008000
216 #define ATA_AHCI_P_CMD_CPS 0x00010000
217 #define ATA_AHCI_P_CMD_PMA 0x00020000
218 #define ATA_AHCI_P_CMD_HPCP 0x00040000
219 #define ATA_AHCI_P_CMD_ISP 0x00080000
220 #define ATA_AHCI_P_CMD_CPD 0x00100000
221 #define ATA_AHCI_P_CMD_ATAPI 0x01000000
222 #define ATA_AHCI_P_CMD_DLAE 0x02000000
223 #define ATA_AHCI_P_CMD_ALPE 0x04000000
224 #define ATA_AHCI_P_CMD_ASP 0x08000000
225 #define ATA_AHCI_P_CMD_ICC_MASK 0xf0000000
226 #define ATA_AHCI_P_CMD_NOOP 0x00000000
227 #define ATA_AHCI_P_CMD_ACTIVE 0x10000000
228 #define ATA_AHCI_P_CMD_PARTIAL 0x20000000
229 #define ATA_AHCI_P_CMD_SLUMPER 0x60000000
230
231 #define ATA_AHCI_P_TFD 0x120
232 #define ATA_AHCI_P_SIG 0x124
233 #define ATA_AHCI_P_SSTS 0x128
234 #define ATA_AHCI_P_SCTL 0x12c
235 #define ATA_AHCI_P_SERR 0x130
236 #define ATA_AHCI_P_SACT 0x134
237 #define ATA_AHCI_P_CI 0x138
238
239 #define ATA_AHCI_CL_SIZE 32
240 #define ATA_AHCI_CL_OFFSET 0
241 #define ATA_AHCI_FB_OFFSET 1024
242 #define ATA_AHCI_CT_OFFSET 1024+256
243 #define ATA_AHCI_CT_SG_OFFSET 128
244 #define ATA_AHCI_CT_SIZE 256
245
246 struct ata_ahci_dma_prd {
247 u_int64_t dba;
248 u_int32_t reserved;
249 u_int32_t dbc; /* 0 based */
250 #define ATA_AHCI_PRD_MASK 0x003fffff /* max 4MB */
251 #define ATA_AHCI_PRD_IPC (1<<31)
252 } __packed;
253
254 struct ata_ahci_cmd_tab {
255 u_int8_t cfis[64];
256 u_int8_t acmd[32];
257 u_int8_t reserved[32];
258 struct ata_ahci_dma_prd prd_tab[16];
259 } __packed;
260
261 struct ata_ahci_cmd_list {
262 u_int16_t cmd_flags;
263 u_int16_t prd_length; /* PRD entries */
264 u_int32_t bytecount;
265 u_int64_t cmd_table_phys; /* 128byte aligned */
266 } __packed;
267
268 /* DMA register defines */
269 #define ATA_DMA_ENTRIES 256
270 #define ATA_DMA_EOT 0x80000000
271
272 #define ATA_BMCMD_PORT 17
273 #define ATA_BMCMD_START_STOP 0x01
274 #define ATA_BMCMD_WRITE_READ 0x08
275
276 #define ATA_BMDEVSPEC_0 18
277 #define ATA_BMSTAT_PORT 19
278 #define ATA_BMSTAT_ACTIVE 0x01
279 #define ATA_BMSTAT_ERROR 0x02
280 #define ATA_BMSTAT_INTERRUPT 0x04
281 #define ATA_BMSTAT_MASK 0x07
282 #define ATA_BMSTAT_DMA_MASTER 0x20
283 #define ATA_BMSTAT_DMA_SLAVE 0x40
284 #define ATA_BMSTAT_DMA_SIMPLEX 0x80
285
286 #define ATA_BMDEVSPEC_1 20
287 #define ATA_BMDTP_PORT 21
288
289 #define ATA_IDX_ADDR 22
290 #define ATA_IDX_DATA 23
291 #define ATA_MAX_RES 24
292
293 /* misc defines */
294 #define ATA_PRIMARY 0x1f0
295 #define ATA_SECONDARY 0x170
296 #define ATA_PC98_BANK 0x432
297 #define ATA_IOSIZE 0x08
298 #define ATA_PC98_IOSIZE 0x10
299 #define ATA_CTLIOSIZE 0x01
300 #define ATA_BMIOSIZE 0x08
301 #define ATA_PC98_BANKIOSIZE 0x01
302 #define ATA_IOADDR_RID 0
303 #define ATA_CTLADDR_RID 1
304 #define ATA_BMADDR_RID 0x20
305 #define ATA_PC98_CTLADDR_RID 8
306 #define ATA_PC98_BANKADDR_RID 9
307 #define ATA_IRQ_RID 0
308 #define ATA_DEV(device) ((device == ATA_MASTER) ? 0 : 1)
309 #define ATA_CFA_MAGIC1 0x844A
310 #define ATA_CFA_MAGIC2 0x848A
311 #define ATA_CFA_MAGIC3 0x8400
312 #define ATAPI_MAGIC_LSB 0x14
313 #define ATAPI_MAGIC_MSB 0xeb
314 #define ATAPI_P_READ (ATA_S_DRQ | ATA_I_IN)
315 #define ATAPI_P_WRITE (ATA_S_DRQ)
316 #define ATAPI_P_CMDOUT (ATA_S_DRQ | ATA_I_CMD)
317 #define ATAPI_P_DONEDRQ (ATA_S_DRQ | ATA_I_CMD | ATA_I_IN)
318 #define ATAPI_P_DONE (ATA_I_CMD | ATA_I_IN)
319 #define ATAPI_P_ABORT 0
320 #define ATA_INTR_FLAGS (INTR_NOPOLL)
321 #define ATA_OP_CONTINUES 0
322 #define ATA_OP_FINISHED 1
323 #define ATA_MAX_28BIT_LBA 268435455UL
324
325 /* structure used for composite atomic operations */
326 #define MAX_COMPOSITES 32 /* u_int32_t bits */
327 struct ata_composite {
328 struct lock lock; /* control lock */
329 u_int32_t rd_needed; /* needed read subdisks */
330 u_int32_t rd_done; /* done read subdisks */
331 u_int32_t wr_needed; /* needed write subdisks */
332 u_int32_t wr_depend; /* write depends on subdisks */
333 u_int32_t wr_done; /* done write subdisks */
334 struct ata_request *request[MAX_COMPOSITES];
335 u_int32_t residual; /* bytes still to transfer */
336 caddr_t data_1;
337 caddr_t data_2;
338 };
339
340 /* structure used to queue an ATA/ATAPI request */
341 struct ata_request {
342 device_t dev; /* device handle */
343 device_t parent; /* channel handle */
344 union {
345 struct {
346 u_int8_t command; /* command reg */
347 u_int16_t feature; /* feature reg */
348 u_int16_t count; /* count reg */
349 u_int64_t lba; /* lba reg */
350 } ata;
351 struct {
352 u_int8_t ccb[16]; /* ATAPI command block */
353 struct atapi_sense sense; /* ATAPI request sense data */
354 u_int8_t saved_cmd; /* ATAPI saved command */
355 } atapi;
356 } u;
357 u_int32_t bytecount; /* bytes to transfer */
358 u_int32_t transfersize; /* bytes pr transfer */
359 caddr_t data; /* pointer to data buf */
360 int flags;
361 #define ATA_R_CONTROL 0x00000001
362 #define ATA_R_READ 0x00000002
363 #define ATA_R_WRITE 0x00000004
364 #define ATA_R_ATAPI 0x00000008
365 #define ATA_R_DMA 0x00000010
366 #define ATA_R_QUIET 0x00000020
367 #define ATA_R_TIMEOUT 0x00000040
368 #define ATA_R_COMPLETED 0x00000080
369
370 #define ATA_R_ORDERED 0x00000100
371 #define ATA_R_AT_HEAD 0x00000200
372 #define ATA_R_REQUEUE 0x00000400
373 #define ATA_R_THREAD 0x00000800
374 #define ATA_R_DIRECT 0x00001000
375
376 #define ATA_R_HWCMDQUEUED 0x00010000
377
378 #define ATA_R_DEBUG 0x10000000
379 #define ATA_R_DANGER1 0x20000000
380 #define ATA_R_DANGER2 0x40000000
381
382 u_int8_t status; /* ATA status */
383 u_int8_t error; /* ATA error */
384 u_int8_t dmastat; /* DMA status */
385 u_int32_t donecount; /* bytes transferred */
386 int result; /* result error code */
387 void (*callback)(struct ata_request *request);
388 struct lock done; /* request done sema */
389 int retries; /* retry count */
390 int timeout; /* timeout for this cmd */
391 int unused01;
392 struct callout callout; /* callout management */
393 struct task task; /* task management */
394 struct bio *bio; /* bio for this request */
395 int this; /* this request ID */
396 struct ata_composite *composite; /* for composite atomic ops */
397 void *driver; /* driver specific */
398 TAILQ_ENTRY(ata_request) chain; /* list management */
399 };
400
401 /* define this for debugging request processing */
402 #if 0
403 #define ATA_DEBUG_RQ(request, string) \
404 { \
405 if (request->flags & ATA_R_DEBUG) \
406 device_printf(request->dev, "req=%p %s " string "\n", \
407 request, ata_cmd2str(request)); \
408 }
409 #else
410 #define ATA_DEBUG_RQ(request, string)
411 #endif
412
413
414 /* structure describing an ATA/ATAPI device */
415 struct ata_device {
416 device_t dev; /* device handle */
417 int unit; /* physical unit */
418 #define ATA_MASTER 0x00
419 #define ATA_SLAVE 0x10
420
421 struct ata_params param; /* ata param structure */
422 int mode; /* current transfermode */
423 u_int32_t max_iosize; /* max IO size */
424 int flags;
425 #define ATA_D_USE_CHS 0x0001
426 #define ATA_D_MEDIA_CHANGED 0x0002
427 #define ATA_D_ENC_PRESENT 0x0004
428 #define ATA_D_48BIT_ACTIVE 0x0008
429 int opencount; /* when tracking needed */
430 };
431
432 /* structure for holding DMA Physical Region Descriptors (PRD) entries */
433 struct ata_dma_prdentry {
434 u_int32_t addr;
435 u_int32_t count;
436 };
437
438 /* structure used by the setprd function */
439 struct ata_dmasetprd_args {
440 void *dmatab;
441 int nsegs;
442 int error;
443 };
444
445 /* structure holding DMA related information */
446 struct ata_dma {
447 bus_dma_tag_t dmatag; /* parent DMA tag */
448 bus_dma_tag_t sg_tag; /* SG list DMA tag */
449 bus_dmamap_t sg_map; /* SG list DMA map */
450 void *sg; /* DMA transfer table */
451 bus_addr_t sg_bus; /* bus address of dmatab */
452 bus_dma_tag_t data_tag; /* data DMA tag */
453 bus_dmamap_t data_map; /* data DMA map */
454 bus_dma_tag_t work_tag; /* workspace DMA tag */
455 bus_dmamap_t work_map; /* workspace DMA map */
456 u_int8_t *work; /* workspace */
457 bus_addr_t work_bus; /* bus address of dmatab */
458
459 u_int32_t alignment; /* DMA SG list alignment */
460 u_int32_t boundary; /* DMA SG list boundary */
461 u_int32_t segsize; /* DMA SG list segment size */
462 u_int32_t max_iosize; /* DMA data max IO size */
463 u_int32_t cur_iosize; /* DMA data current IO size */
464 u_int64_t max_address; /* highest DMA'able address */
465 int flags;
466 #define ATA_DMA_READ 0x01 /* transaction is a read */
467 #define ATA_DMA_LOADED 0x02 /* DMA tables etc loaded */
468 #define ATA_DMA_ACTIVE 0x04 /* DMA transfer in progress */
469
470 void (*alloc)(device_t dev);
471 void (*free)(device_t dev);
472 void (*setprd)(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
473 int (*load)(device_t dev, caddr_t data, int32_t count, int dir, void *addr, int *nsegs);
474 int (*unload)(device_t dev);
475 int (*start)(device_t dev);
476 int (*stop)(device_t dev);
477 void (*reset)(device_t dev);
478 };
479
480 /* structure holding lowlevel functions */
481 struct ata_lowlevel {
482 int (*status)(device_t dev);
483 int (*begin_transaction)(struct ata_request *request);
484 int (*end_transaction)(struct ata_request *request);
485 int (*command)(struct ata_request *request);
486 };
487
488 /* structure holding resources for an ATA channel */
489 struct ata_resource {
490 struct resource *res;
491 int offset;
492 };
493
494 /* structure describing an ATA channel */
495 struct ata_channel {
496 device_t dev; /* device handle */
497 int unit; /* physical channel */
498 struct ata_resource r_io[ATA_MAX_RES];/* I/O resources */
499 struct resource *r_irq; /* interrupt of this channel */
500 void *ih; /* interrupt handle */
501 struct ata_lowlevel hw; /* lowlevel HW functions */
502 struct ata_dma *dma; /* DMA data / functions */
503 int flags; /* channel flags */
504 #define ATA_NO_SLAVE 0x01
505 #define ATA_USE_16BIT 0x02
506 #define ATA_ATAPI_DMA_RO 0x04
507 #define ATA_NO_48BIT_DMA 0x08
508 #define ATA_ALWAYS_DMASTAT 0x10
509
510 int devices; /* what is present */
511 #define ATA_ATA_MASTER 0x01
512 #define ATA_ATA_SLAVE 0x02
513 #define ATA_ATAPI_MASTER 0x04
514 #define ATA_ATAPI_SLAVE 0x08
515 #define ATA_PORTMULTIPLIER 0x10
516
517 struct lock state_mtx; /* state lock */
518 int state; /* ATA channel state */
519 #define ATA_IDLE 0x0000
520 #define ATA_ACTIVE 0x0001
521 #define ATA_STALL_QUEUE 0x0002
522
523 struct lock queue_mtx; /* queue lock */
524 TAILQ_HEAD(, ata_request) ata_queue; /* head of ATA queue */
525 int reorder; /* limit sort reordering */
526 struct ata_request *transition;
527 struct ata_request *running; /* currently running request */
528 };
529
530 /* disk bay/enclosure related */
531 #define ATA_LED_OFF 0x00
532 #define ATA_LED_RED 0x01
533 #define ATA_LED_GREEN 0x02
534 #define ATA_LED_ORANGE 0x03
535 #define ATA_LED_MASK 0x03
536
537 /* externs */
538 extern int (*ata_raid_ioctl_func)(u_long cmd, caddr_t data);
539 extern devclass_t ata_devclass;
540 extern int ata_wc;
541
542 /* public prototypes */
543 /* ata-all.c: */
544 int ata_probe(device_t dev);
545 int ata_attach(device_t dev);
546 int ata_detach(device_t dev);
547 int ata_reinit(device_t dev);
548 int ata_suspend(device_t dev);
549 int ata_resume(device_t dev);
550 int ata_interrupt(void *data);
551 int ata_device_ioctl(device_t dev, u_long cmd, caddr_t data);
552 int ata_identify(device_t dev);
553 void ata_default_registers(device_t dev);
554 void ata_modify_if_48bit(struct ata_request *request);
555 void ata_udelay(int interval);
556 char *ata_mode2str(int mode);
557 int ata_pmode(struct ata_params *ap);
558 int ata_wmode(struct ata_params *ap);
559 int ata_umode(struct ata_params *ap);
560 int ata_limit_mode(device_t dev, int mode, int maxmode);
561
562 /* ata-queue.c: */
563 int ata_controlcmd(device_t dev, u_int8_t command, u_int16_t feature, u_int64_t lba, u_int16_t count);
564 int ata_atapicmd(device_t dev, u_int8_t *ccb, caddr_t data, int count, int flags, int timeout);
565 void ata_drop_requests(device_t dev);
566 void ata_queue_init(struct ata_channel *ch);
567 void ata_queue_request(struct ata_request *request);
568 void ata_start(device_t dev);
569 void ata_finish(struct ata_request *request);
570 void ata_timeout(struct ata_request *);
571 void ata_catch_inflight(device_t dev);
572 void ata_fail_requests(device_t dev);
573 char *ata_cmd2str(struct ata_request *request);
574
575 /* ata-lowlevel.c: */
576 void ata_generic_hw(device_t dev);
577 int ata_begin_transaction(struct ata_request *);
578 int ata_end_transaction(struct ata_request *);
579 void ata_generic_reset(device_t dev);
580 int ata_generic_command(struct ata_request *request);
581
582 /* macros for alloc/free of struct ata_request */
583 extern struct objcache *ata_request_cache;
584 #define ata_alloc_request() objcache_get(ata_request_cache, M_WAITOK)
585 /* zero the object so objects in the cache are guaranteed to be zero'ed */
586 #define ata_free_request(request) { \
587 if (!(request->flags & ATA_R_DANGER2)) { \
588 bzero(request, sizeof(struct ata_request)); \
589 objcache_put(ata_request_cache, request); \
590 } \
591 }
592 /* macros for alloc/free of struct ata_composite */
593 extern struct objcache *ata_composite_cache;
594 #define ata_alloc_composite() objcache_get(ata_composite_cache, M_WAITOK)
595 /* zero the object so objects in the cache are guaranteed to be zero'ed */
596 #define ata_free_composite(composite) { \
597 bzero(composite, sizeof(struct ata_composite)); \
598 objcache_put(ata_composite_cache, composite); \
599 }
600
601 MALLOC_DECLARE(M_ATA);
602
603 /* misc newbus defines */
604 #define GRANDPARENT(dev) device_get_parent(device_get_parent(dev))
605
606 /* macros to hide busspace uglyness */
607 #define ATA_INB(res, offset) \
608 bus_space_read_1(rman_get_bustag((res)), \
609 rman_get_bushandle((res)), (offset))
610
611 #define ATA_INW(res, offset) \
612 bus_space_read_2(rman_get_bustag((res)), \
613 rman_get_bushandle((res)), (offset))
614 #define ATA_INL(res, offset) \
615 bus_space_read_4(rman_get_bustag((res)), \
616 rman_get_bushandle((res)), (offset))
617 #define ATA_INSW(res, offset, addr, count) \
618 bus_space_read_multi_2(rman_get_bustag((res)), \
619 rman_get_bushandle((res)), \
620 (offset), (addr), (count))
621 #define ATA_INSW_STRM(res, offset, addr, count) \
622 bus_space_read_multi_stream_2(rman_get_bustag((res)), \
623 rman_get_bushandle((res)), \
624 (offset), (addr), (count))
625 #define ATA_INSL(res, offset, addr, count) \
626 bus_space_read_multi_4(rman_get_bustag((res)), \
627 rman_get_bushandle((res)), \
628 (offset), (addr), (count))
629 #define ATA_INSL_STRM(res, offset, addr, count) \
630 bus_space_read_multi_stream_4(rman_get_bustag((res)), \
631 rman_get_bushandle((res)), \
632 (offset), (addr), (count))
633 #define ATA_OUTB(res, offset, value) \
634 bus_space_write_1(rman_get_bustag((res)), \
635 rman_get_bushandle((res)), (offset), (value))
636 #define ATA_OUTW(res, offset, value) \
637 bus_space_write_2(rman_get_bustag((res)), \
638 rman_get_bushandle((res)), (offset), (value))
639 #define ATA_OUTL(res, offset, value) \
640 bus_space_write_4(rman_get_bustag((res)), \
641 rman_get_bushandle((res)), (offset), (value))
642 #define ATA_OUTSW(res, offset, addr, count) \
643 bus_space_write_multi_2(rman_get_bustag((res)), \
644 rman_get_bushandle((res)), \
645 (offset), (addr), (count))
646 #define ATA_OUTSW_STRM(res, offset, addr, count) \
647 bus_space_write_multi_stream_2(rman_get_bustag((res)), \
648 rman_get_bushandle((res)), \
649 (offset), (addr), (count))
650 #define ATA_OUTSL(res, offset, addr, count) \
651 bus_space_write_multi_4(rman_get_bustag((res)), \
652 rman_get_bushandle((res)), \
653 (offset), (addr), (count))
654 #define ATA_OUTSL_STRM(res, offset, addr, count) \
655 bus_space_write_multi_stream_4(rman_get_bustag((res)), \
656 rman_get_bushandle((res)), \
657 (offset), (addr), (count))
658
659 #define ATA_IDX_INB(ch, idx) \
660 ATA_INB(ch->r_io[idx].res, ch->r_io[idx].offset)
661
662 #define ATA_IDX_INW(ch, idx) \
663 ATA_INW(ch->r_io[idx].res, ch->r_io[idx].offset)
664
665 #define ATA_IDX_INL(ch, idx) \
666 ATA_INL(ch->r_io[idx].res, ch->r_io[idx].offset)
667
668 #define ATA_IDX_INSW(ch, idx, addr, count) \
669 ATA_INSW(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
670
671 #define ATA_IDX_INSW_STRM(ch, idx, addr, count) \
672 ATA_INSW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
673
674 #define ATA_IDX_INSL(ch, idx, addr, count) \
675 ATA_INSL(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
676
677 #define ATA_IDX_INSL_STRM(ch, idx, addr, count) \
678 ATA_INSL_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
679
680 #define ATA_IDX_OUTB(ch, idx, value) \
681 ATA_OUTB(ch->r_io[idx].res, ch->r_io[idx].offset, value)
682
683 #define ATA_IDX_OUTW(ch, idx, value) \
684 ATA_OUTW(ch->r_io[idx].res, ch->r_io[idx].offset, value)
685
686 #define ATA_IDX_OUTL(ch, idx, value) \
687 ATA_OUTL(ch->r_io[idx].res, ch->r_io[idx].offset, value)
688
689 #define ATA_IDX_OUTSW(ch, idx, addr, count) \
690 ATA_OUTSW(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
691
692 #define ATA_IDX_OUTSW_STRM(ch, idx, addr, count) \
693 ATA_OUTSW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
694
695 #define ATA_IDX_OUTSL(ch, idx, addr, count) \
696 ATA_OUTSL(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
697
698 #define ATA_IDX_OUTSL_STRM(ch, idx, addr, count) \
699 ATA_OUTSL_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
700
701 /* Dragonfly: Default request timeout increased from 5 to 10 */
702 #define ATA_DEFAULT_TIMEOUT 10
703
DragonFly BSD