2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_rl.c,v 1.38.2.16 2003/03/05 18:42:33 njl Exp $
36 * RealTek 8129/8139 PCI NIC driver
38 * Supports several extremely cheap PCI 10/100 adapters based on
39 * the RealTek chipset. Datasheets can be obtained from
42 * Written by Bill Paul <wpaul@ctr.columbia.edu>
43 * Electrical Engineering Department
44 * Columbia University, New York City
48 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is
49 * probably the worst PCI ethernet controller ever made, with the possible
50 * exception of the FEAST chip made by SMC. The 8139 supports bus-master
51 * DMA, but it has a terrible interface that nullifies any performance
52 * gains that bus-master DMA usually offers.
54 * For transmission, the chip offers a series of four TX descriptor
55 * registers. Each transmit frame must be in a contiguous buffer, aligned
56 * on a longword (32-bit) boundary. This means we almost always have to
57 * do mbuf copies in order to transmit a frame, except in the unlikely
58 * case where a) the packet fits into a single mbuf, and b) the packet
59 * is 32-bit aligned within the mbuf's data area. The presence of only
60 * four descriptor registers means that we can never have more than four
61 * packets queued for transmission at any one time.
63 * Reception is not much better. The driver has to allocate a single large
64 * buffer area (up to 64K in size) into which the chip will DMA received
65 * frames. Because we don't know where within this region received packets
66 * will begin or end, we have no choice but to copy data from the buffer
67 * area into mbufs in order to pass the packets up to the higher protocol
70 * It's impossible given this rotten design to really achieve decent
71 * performance at 100Mbps, unless you happen to have a 400Mhz PII or
72 * some equally overmuscled CPU to drive it.
74 * On the bright side, the 8139 does have a built-in PHY, although
75 * rather than using an MDIO serial interface like most other NICs, the
76 * PHY registers are directly accessible through the 8139's register
77 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast
80 * The 8129 chip is an older version of the 8139 that uses an external PHY
81 * chip. The 8129 has a serial MDIO interface for accessing the MII where
82 * the 8139 lets you directly access the on-board PHY registers. We need
83 * to select which interface to use depending on the chip type.
86 #include "opt_ifpoll.h"
88 #include <sys/param.h>
89 #include <sys/endian.h>
90 #include <sys/systm.h>
91 #include <sys/sockio.h>
93 #include <sys/malloc.h>
94 #include <sys/kernel.h>
95 #include <sys/module.h>
96 #include <sys/socket.h>
97 #include <sys/serialize.h>
100 #include <sys/thread2.h>
101 #include <sys/interrupt.h>
104 #include <net/ifq_var.h>
105 #include <net/if_arp.h>
106 #include <net/ethernet.h>
107 #include <net/if_dl.h>
108 #include <net/if_media.h>
109 #include <net/if_poll.h>
113 #include <dev/netif/mii_layer/mii.h>
114 #include <dev/netif/mii_layer/miivar.h>
117 #include <bus/pci/pcireg.h>
118 #include <bus/pci/pcivar.h>
120 /* "controller miibus0" required. See GENERIC if you get errors here. */
121 #include "miibus_if.h"
124 * Default to using PIO access for this driver. On SMP systems,
125 * there appear to be problems with memory mapped mode: it looks like
126 * doing too many memory mapped access back to back in rapid succession
127 * can hang the bus. I'm inclined to blame this on crummy design/construction
128 * on the part of RealTek. Memory mapped mode does appear to work on
129 * uniprocessor systems though.
131 #define RL_USEIOSPACE
133 #include <dev/netif/rl/if_rlreg.h>
136 * Various supported device vendors/types and their names.
138 static struct rl_type
{
143 { PCI_VENDOR_REALTEK
, PCI_PRODUCT_REALTEK_RT8129
,
144 "RealTek 8129 10/100BaseTX" },
145 { PCI_VENDOR_REALTEK
, PCI_PRODUCT_REALTEK_RT8139
,
146 "RealTek 8139 10/100BaseTX" },
147 { PCI_VENDOR_REALTEK
, PCI_PRODUCT_REALTEK_RT8139B
,
148 "RealTek 8139 10/100BaseTX CardBus" },
149 { PCI_VENDOR_ACCTON
, PCI_PRODUCT_ACCTON_MPX5030
,
150 "Accton MPX 5030/5038 10/100BaseTX" },
151 { PCI_VENDOR_DELTA
, PCI_PRODUCT_DELTA_8139
,
152 "Delta Electronics 8139 10/100BaseTX" },
153 { PCI_VENDOR_ADDTRON
, PCI_PRODUCT_ADDTRON_8139
,
154 "Addtron Technology 8139 10/100BaseTX" },
155 { PCI_VENDOR_DLINK
, PCI_PRODUCT_DLINK_DFE520TX_C1
,
156 "D-Link DFE-520TX C1 10/100BaseTX" },
157 { PCI_VENDOR_DLINK
, PCI_PRODUCT_DLINK_DFE530TXPLUS
,
158 "D-Link DFE-530TX+ 10/100BaseTX" },
159 { PCI_VENDOR_DLINK
, PCI_PRODUCT_DLINK_DFE690TXD
,
160 "D-Link DFE-690TX 10/100BaseTX" },
161 { PCI_VENDOR_NORTEL
, PCI_PRODUCT_NORTEL_BAYSTACK_21
,
162 "Nortel Networks 10/100BaseTX" },
163 { PCI_VENDOR_PEPPERCON
, PCI_PRODUCT_PEPPERCON_ROLF
,
164 "Peppercon AG ROL/F" },
165 { PCI_VENDOR_COREGA
, PCI_PRODUCT_COREGA_CB_TXD
,
166 "Corega FEther CB-TXD" },
167 { PCI_VENDOR_COREGA
, PCI_PRODUCT_COREGA_2CB_TXD
,
168 "Corega FEtherII CB-TXD" },
169 { PCI_VENDOR_PLANEX
, PCI_PRODUCT_PLANEX_FNW_3800_TX
,
170 "Planex FNW-3800-TX" },
174 static int rl_probe(device_t
);
175 static int rl_attach(device_t
);
176 static int rl_detach(device_t
);
178 static int rl_encap(struct rl_softc
*, struct mbuf
* );
180 static void rl_rxeof(struct rl_softc
*);
181 static void rl_txeof(struct rl_softc
*);
182 static void rl_intr(void *);
183 static void rl_tick(void *);
184 static void rl_start(struct ifnet
*, struct ifaltq_subque
*);
185 static int rl_ioctl(struct ifnet
*, u_long
, caddr_t
, struct ucred
*);
186 static void rl_init(void *);
187 static void rl_stop (struct rl_softc
*);
188 static void rl_watchdog(struct ifnet
*);
189 static int rl_suspend(device_t
);
190 static int rl_resume(device_t
);
191 static void rl_shutdown(device_t
);
192 static int rl_ifmedia_upd(struct ifnet
*);
193 static void rl_ifmedia_sts(struct ifnet
*, struct ifmediareq
*);
195 static void rl_eeprom_putbyte(struct rl_softc
*, int);
196 static void rl_eeprom_getword(struct rl_softc
*, int, uint16_t *);
197 static void rl_read_eeprom(struct rl_softc
*, caddr_t
, int, int, int);
198 static void rl_mii_sync(struct rl_softc
*);
199 static void rl_mii_send(struct rl_softc
*, uint32_t, int);
200 static int rl_mii_readreg(struct rl_softc
*, struct rl_mii_frame
*);
201 static int rl_mii_writereg(struct rl_softc
*, struct rl_mii_frame
*);
203 static int rl_miibus_readreg(device_t
, int, int);
204 static int rl_miibus_writereg(device_t
, int, int, int);
205 static void rl_miibus_statchg(device_t
);
207 static void rl_setmulti(struct rl_softc
*);
208 static void rl_reset(struct rl_softc
*);
209 static void rl_list_tx_init(struct rl_softc
*);
212 static void rl_npoll(struct ifnet
*, struct ifpoll_info
*);
213 static void rl_npoll_compat(struct ifnet
*, void *, int);
216 static int rl_dma_alloc(struct rl_softc
*);
217 static void rl_dma_free(struct rl_softc
*);
220 #define RL_RES SYS_RES_IOPORT
221 #define RL_RID RL_PCI_LOIO
223 #define RL_RES SYS_RES_MEMORY
224 #define RL_RID RL_PCI_LOMEM
227 static device_method_t rl_methods
[] = {
228 /* Device interface */
229 DEVMETHOD(device_probe
, rl_probe
),
230 DEVMETHOD(device_attach
, rl_attach
),
231 DEVMETHOD(device_detach
, rl_detach
),
232 DEVMETHOD(device_suspend
, rl_suspend
),
233 DEVMETHOD(device_resume
, rl_resume
),
234 DEVMETHOD(device_shutdown
, rl_shutdown
),
237 DEVMETHOD(bus_print_child
, bus_generic_print_child
),
238 DEVMETHOD(bus_driver_added
, bus_generic_driver_added
),
241 DEVMETHOD(miibus_readreg
, rl_miibus_readreg
),
242 DEVMETHOD(miibus_writereg
, rl_miibus_writereg
),
243 DEVMETHOD(miibus_statchg
, rl_miibus_statchg
),
248 static DEFINE_CLASS_0(rl
, rl_driver
, rl_methods
, sizeof(struct rl_softc
));
249 static devclass_t rl_devclass
;
251 DECLARE_DUMMY_MODULE(if_rl
);
252 DRIVER_MODULE(if_rl
, pci
, rl_driver
, rl_devclass
, NULL
, NULL
);
253 DRIVER_MODULE(if_rl
, cardbus
, rl_driver
, rl_devclass
, NULL
, NULL
);
254 DRIVER_MODULE(miibus
, rl
, miibus_driver
, miibus_devclass
, NULL
, NULL
);
255 MODULE_DEPEND(if_rl
, miibus
, 1, 1, 1);
258 CSR_WRITE_1(sc, RL_EECMD, CSR_READ_1(sc, RL_EECMD) | (x))
261 CSR_WRITE_1(sc, RL_EECMD, CSR_READ_1(sc, RL_EECMD) & ~(x))
264 * Send a read command and address to the EEPROM, check for ACK.
267 rl_eeprom_putbyte(struct rl_softc
*sc
, int addr
)
271 d
= addr
| sc
->rl_eecmd_read
;
274 * Feed in each bit and strobe the clock.
276 for (i
= 0x400; i
; i
>>= 1) {
278 EE_SET(RL_EE_DATAIN
);
280 EE_CLR(RL_EE_DATAIN
);
290 * Read a word of data stored in the EEPROM at address 'addr.'
293 rl_eeprom_getword(struct rl_softc
*sc
, int addr
, uint16_t *dest
)
298 /* Enter EEPROM access mode. */
299 CSR_WRITE_1(sc
, RL_EECMD
, RL_EEMODE_PROGRAM
|RL_EE_SEL
);
302 * Send address of word we want to read.
304 rl_eeprom_putbyte(sc
, addr
);
306 CSR_WRITE_1(sc
, RL_EECMD
, RL_EEMODE_PROGRAM
|RL_EE_SEL
);
309 * Start reading bits from EEPROM.
311 for (i
= 0x8000; i
; i
>>= 1) {
314 if (CSR_READ_1(sc
, RL_EECMD
) & RL_EE_DATAOUT
)
320 /* Turn off EEPROM access mode. */
321 CSR_WRITE_1(sc
, RL_EECMD
, RL_EEMODE_OFF
);
327 * Read a sequence of words from the EEPROM.
330 rl_read_eeprom(struct rl_softc
*sc
, caddr_t dest
, int off
, int cnt
, int swap
)
333 u_int16_t word
= 0, *ptr
;
335 for (i
= 0; i
< cnt
; i
++) {
336 rl_eeprom_getword(sc
, off
+ i
, &word
);
337 ptr
= (u_int16_t
*)(dest
+ (i
* 2));
347 * MII access routines are provided for the 8129, which
348 * doesn't have a built-in PHY. For the 8139, we fake things
349 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the
350 * direct access PHY registers.
353 CSR_WRITE_1(sc, RL_MII, CSR_READ_1(sc, RL_MII) | x)
356 CSR_WRITE_1(sc, RL_MII, CSR_READ_1(sc, RL_MII) & ~x)
359 * Sync the PHYs by setting data bit and strobing the clock 32 times.
362 rl_mii_sync(struct rl_softc
*sc
)
366 MII_SET(RL_MII_DIR
|RL_MII_DATAOUT
);
368 for (i
= 0; i
< 32; i
++) {
377 * Clock a series of bits through the MII.
380 rl_mii_send(struct rl_softc
*sc
, uint32_t bits
, int cnt
)
386 for (i
= (0x1 << (cnt
- 1)); i
; i
>>= 1) {
388 MII_SET(RL_MII_DATAOUT
);
390 MII_CLR(RL_MII_DATAOUT
);
399 * Read an PHY register through the MII.
402 rl_mii_readreg(struct rl_softc
*sc
, struct rl_mii_frame
*frame
)
407 * Set up frame for RX.
409 frame
->mii_stdelim
= RL_MII_STARTDELIM
;
410 frame
->mii_opcode
= RL_MII_READOP
;
411 frame
->mii_turnaround
= 0;
414 CSR_WRITE_2(sc
, RL_MII
, 0);
424 * Send command/address info.
426 rl_mii_send(sc
, frame
->mii_stdelim
, 2);
427 rl_mii_send(sc
, frame
->mii_opcode
, 2);
428 rl_mii_send(sc
, frame
->mii_phyaddr
, 5);
429 rl_mii_send(sc
, frame
->mii_regaddr
, 5);
432 MII_CLR((RL_MII_CLK
|RL_MII_DATAOUT
));
443 ack
= CSR_READ_2(sc
, RL_MII
) & RL_MII_DATAIN
;
448 * Now try reading data bits. If the ack failed, we still
449 * need to clock through 16 cycles to keep the PHY(s) in sync.
452 for(i
= 0; i
< 16; i
++) {
459 for (i
= 0x8000; i
; i
>>= 1) {
463 if (CSR_READ_2(sc
, RL_MII
) & RL_MII_DATAIN
)
464 frame
->mii_data
|= i
;
481 * Write to a PHY register through the MII.
484 rl_mii_writereg(struct rl_softc
*sc
, struct rl_mii_frame
*frame
)
487 * Set up frame for TX.
489 frame
->mii_stdelim
= RL_MII_STARTDELIM
;
490 frame
->mii_opcode
= RL_MII_WRITEOP
;
491 frame
->mii_turnaround
= RL_MII_TURNAROUND
;
494 * Turn on data output.
500 rl_mii_send(sc
, frame
->mii_stdelim
, 2);
501 rl_mii_send(sc
, frame
->mii_opcode
, 2);
502 rl_mii_send(sc
, frame
->mii_phyaddr
, 5);
503 rl_mii_send(sc
, frame
->mii_regaddr
, 5);
504 rl_mii_send(sc
, frame
->mii_turnaround
, 2);
505 rl_mii_send(sc
, frame
->mii_data
, 16);
522 rl_miibus_readreg(device_t dev
, int phy
, int reg
)
525 struct rl_mii_frame frame
;
527 uint16_t rl8139_reg
= 0;
529 sc
= device_get_softc(dev
);
531 if (sc
->rl_type
== RL_8139
) {
532 /* Pretend the internal PHY is only at address 0 */
537 rl8139_reg
= RL_BMCR
;
540 rl8139_reg
= RL_BMSR
;
543 rl8139_reg
= RL_ANAR
;
546 rl8139_reg
= RL_ANER
;
549 rl8139_reg
= RL_LPAR
;
556 * Allow the rlphy driver to read the media status
557 * register. If we have a link partner which does not
558 * support NWAY, this is the register which will tell
559 * us the results of parallel detection.
562 rval
= CSR_READ_1(sc
, RL_MEDIASTAT
);
565 device_printf(dev
, "bad phy register\n");
568 rval
= CSR_READ_2(sc
, rl8139_reg
);
572 bzero(&frame
, sizeof(frame
));
574 frame
.mii_phyaddr
= phy
;
575 frame
.mii_regaddr
= reg
;
576 rl_mii_readreg(sc
, &frame
);
578 return(frame
.mii_data
);
582 rl_miibus_writereg(device_t dev
, int phy
, int reg
, int data
)
585 struct rl_mii_frame frame
;
586 u_int16_t rl8139_reg
= 0;
588 sc
= device_get_softc(dev
);
590 if (sc
->rl_type
== RL_8139
) {
591 /* Pretend the internal PHY is only at address 0 */
596 rl8139_reg
= RL_BMCR
;
599 rl8139_reg
= RL_BMSR
;
602 rl8139_reg
= RL_ANAR
;
605 rl8139_reg
= RL_ANER
;
608 rl8139_reg
= RL_LPAR
;
614 device_printf(dev
, "bad phy register\n");
617 CSR_WRITE_2(sc
, rl8139_reg
, data
);
621 bzero(&frame
, sizeof(frame
));
623 frame
.mii_phyaddr
= phy
;
624 frame
.mii_regaddr
= reg
;
625 frame
.mii_data
= data
;
627 rl_mii_writereg(sc
, &frame
);
633 rl_miibus_statchg(device_t dev
)
638 * Program the 64-bit multicast hash filter.
641 rl_setmulti(struct rl_softc
*sc
)
645 uint32_t hashes
[2] = { 0, 0 };
646 struct ifmultiaddr
*ifma
;
650 ifp
= &sc
->arpcom
.ac_if
;
652 rxfilt
= CSR_READ_4(sc
, RL_RXCFG
);
654 if (ifp
->if_flags
& IFF_ALLMULTI
|| ifp
->if_flags
& IFF_PROMISC
) {
655 rxfilt
|= RL_RXCFG_RX_MULTI
;
656 CSR_WRITE_4(sc
, RL_RXCFG
, rxfilt
);
657 CSR_WRITE_4(sc
, RL_MAR0
, 0xFFFFFFFF);
658 CSR_WRITE_4(sc
, RL_MAR4
, 0xFFFFFFFF);
662 /* first, zot all the existing hash bits */
663 CSR_WRITE_4(sc
, RL_MAR0
, 0);
664 CSR_WRITE_4(sc
, RL_MAR4
, 0);
666 /* now program new ones */
667 TAILQ_FOREACH(ifma
, &ifp
->if_multiaddrs
, ifma_link
) {
668 if (ifma
->ifma_addr
->sa_family
!= AF_LINK
)
671 LLADDR((struct sockaddr_dl
*)ifma
->ifma_addr
),
672 ETHER_ADDR_LEN
) >> 26;
674 hashes
[0] |= (1 << h
);
676 hashes
[1] |= (1 << (h
- 32));
681 rxfilt
|= RL_RXCFG_RX_MULTI
;
683 rxfilt
&= ~RL_RXCFG_RX_MULTI
;
685 CSR_WRITE_4(sc
, RL_RXCFG
, rxfilt
);
686 CSR_WRITE_4(sc
, RL_MAR0
, hashes
[0]);
687 CSR_WRITE_4(sc
, RL_MAR4
, hashes
[1]);
691 rl_reset(struct rl_softc
*sc
)
695 CSR_WRITE_1(sc
, RL_COMMAND
, RL_CMD_RESET
);
697 for (i
= 0; i
< RL_TIMEOUT
; i
++) {
699 if (!(CSR_READ_1(sc
, RL_COMMAND
) & RL_CMD_RESET
))
703 device_printf(sc
->rl_dev
, "reset never completed!\n");
707 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device
708 * IDs against our list and return a device name if we find a match.
710 * Return with a value < 0 to give re(4) a change to attach.
713 rl_probe(device_t dev
)
716 uint16_t product
= pci_get_device(dev
);
717 uint16_t vendor
= pci_get_vendor(dev
);
719 for (t
= rl_devs
; t
->rl_name
!= NULL
; t
++) {
720 if (vendor
== t
->rl_vid
&& product
== t
->rl_did
) {
721 device_set_desc(dev
, t
->rl_name
);
730 * Attach the interface. Allocate softc structures, do ifmedia
731 * setup and ethernet/BPF attach.
734 rl_attach(device_t dev
)
736 uint8_t eaddr
[ETHER_ADDR_LEN
];
741 int error
= 0, rid
, i
;
743 sc
= device_get_softc(dev
);
747 * Handle power management nonsense.
750 if (pci_get_powerstate(dev
) != PCI_POWERSTATE_D0
) {
751 uint32_t iobase
, membase
, irq
;
753 /* Save important PCI config data. */
754 iobase
= pci_read_config(dev
, RL_PCI_LOIO
, 4);
755 membase
= pci_read_config(dev
, RL_PCI_LOMEM
, 4);
756 irq
= pci_read_config(dev
, RL_PCI_INTLINE
, 4);
758 /* Reset the power state. */
759 device_printf(dev
, "chip is in D%d power mode "
760 "-- setting to D0\n", pci_get_powerstate(dev
));
761 pci_set_powerstate(dev
, PCI_POWERSTATE_D0
);
763 /* Restore PCI config data. */
764 pci_write_config(dev
, RL_PCI_LOIO
, iobase
, 4);
765 pci_write_config(dev
, RL_PCI_LOMEM
, membase
, 4);
766 pci_write_config(dev
, RL_PCI_INTLINE
, irq
, 4);
769 pci_enable_busmaster(dev
);
772 sc
->rl_res
= bus_alloc_resource_any(dev
, RL_RES
, &rid
, RF_ACTIVE
);
774 if (sc
->rl_res
== NULL
) {
775 device_printf(dev
, "couldn't map ports/memory\n");
780 sc
->rl_btag
= rman_get_bustag(sc
->rl_res
);
781 sc
->rl_bhandle
= rman_get_bushandle(sc
->rl_res
);
784 sc
->rl_irq
= bus_alloc_resource_any(dev
, SYS_RES_IRQ
, &rid
,
785 RF_SHAREABLE
| RF_ACTIVE
);
787 if (sc
->rl_irq
== NULL
) {
788 device_printf(dev
, "couldn't map interrupt\n");
793 callout_init(&sc
->rl_stat_timer
);
795 /* Reset the adapter. */
798 sc
->rl_eecmd_read
= RL_EECMD_READ_6BIT
;
799 rl_read_eeprom(sc
, (uint8_t *)&rl_did
, 0, 1, 0);
800 if (rl_did
!= 0x8129)
801 sc
->rl_eecmd_read
= RL_EECMD_READ_8BIT
;
804 * Get station address from the EEPROM.
806 rl_read_eeprom(sc
, (caddr_t
)as
, RL_EE_EADDR
, 3, 0);
807 for (i
= 0; i
< 3; i
++) {
808 eaddr
[(i
* 2) + 0] = as
[i
] & 0xff;
809 eaddr
[(i
* 2) + 1] = as
[i
] >> 8;
813 * Now read the exact device type from the EEPROM to find
814 * out if it's an 8129 or 8139.
816 rl_read_eeprom(sc
, (caddr_t
)&rl_did
, RL_EE_PCI_DID
, 1, 0);
818 if (rl_did
== PCI_PRODUCT_REALTEK_RT8139
||
819 rl_did
== PCI_PRODUCT_ACCTON_MPX5030
||
820 rl_did
== PCI_PRODUCT_DELTA_8139
||
821 rl_did
== PCI_PRODUCT_ADDTRON_8139
||
822 rl_did
== PCI_PRODUCT_DLINK_DFE530TXPLUS
||
823 rl_did
== PCI_PRODUCT_REALTEK_RT8139B
||
824 rl_did
== PCI_PRODUCT_DLINK_DFE690TXD
||
825 rl_did
== PCI_PRODUCT_COREGA_CB_TXD
||
826 rl_did
== PCI_PRODUCT_COREGA_2CB_TXD
||
827 rl_did
== PCI_PRODUCT_PLANEX_FNW_3800_TX
) {
828 sc
->rl_type
= RL_8139
;
829 } else if (rl_did
== PCI_PRODUCT_REALTEK_RT8129
) {
830 sc
->rl_type
= RL_8129
;
832 device_printf(dev
, "unknown device ID: %x\n", rl_did
);
833 sc
->rl_type
= RL_8139
;
835 * Read RL_IDR register to get ethernet address as accessing
836 * EEPROM may not extract correct address.
838 for (i
= 0; i
< ETHER_ADDR_LEN
; i
++)
839 eaddr
[i
] = CSR_READ_1(sc
, RL_IDR0
+ i
);
842 error
= rl_dma_alloc(sc
);
847 if (mii_phy_probe(dev
, &sc
->rl_miibus
, rl_ifmedia_upd
,
849 device_printf(dev
, "MII without any phy!\n");
854 ifp
= &sc
->arpcom
.ac_if
;
856 if_initname(ifp
, device_get_name(dev
), device_get_unit(dev
));
857 ifp
->if_mtu
= ETHERMTU
;
858 ifp
->if_flags
= IFF_BROADCAST
| IFF_SIMPLEX
| IFF_MULTICAST
;
859 ifp
->if_ioctl
= rl_ioctl
;
860 ifp
->if_start
= rl_start
;
861 ifp
->if_watchdog
= rl_watchdog
;
862 ifp
->if_init
= rl_init
;
863 ifp
->if_baudrate
= 10000000;
864 ifp
->if_capabilities
= IFCAP_VLAN_MTU
;
866 ifp
->if_npoll
= rl_npoll
;
868 ifq_set_maxlen(&ifp
->if_snd
, IFQ_MAXLEN
);
869 ifq_set_ready(&ifp
->if_snd
);
872 * Call MI attach routine.
874 ether_ifattach(ifp
, eaddr
, NULL
);
876 ifq_set_cpuid(&ifp
->if_snd
, rman_get_cpuid(sc
->rl_irq
));
879 ifpoll_compat_setup(&sc
->rl_npoll
, NULL
, NULL
, device_get_unit(dev
),
883 error
= bus_setup_intr(dev
, sc
->rl_irq
, INTR_MPSAFE
, rl_intr
,
884 sc
, &sc
->rl_intrhand
, ifp
->if_serializer
);
887 device_printf(dev
, "couldn't set up irq\n");
900 rl_detach(device_t dev
)
905 sc
= device_get_softc(dev
);
906 ifp
= &sc
->arpcom
.ac_if
;
908 if (device_is_attached(dev
)) {
909 lwkt_serialize_enter(ifp
->if_serializer
);
911 bus_teardown_intr(dev
, sc
->rl_irq
, sc
->rl_intrhand
);
912 lwkt_serialize_exit(ifp
->if_serializer
);
918 device_delete_child(dev
, sc
->rl_miibus
);
919 bus_generic_detach(dev
);
922 bus_release_resource(dev
, SYS_RES_IRQ
, 0, sc
->rl_irq
);
924 bus_release_resource(dev
, RL_RES
, RL_RID
, sc
->rl_res
);
932 * Initialize the transmit descriptors.
935 rl_list_tx_init(struct rl_softc
*sc
)
937 struct rl_chain_data
*cd
;
941 for (i
= 0; i
< RL_TX_LIST_CNT
; i
++) {
942 cd
->rl_tx_chain
[i
] = NULL
;
943 CSR_WRITE_4(sc
, RL_TXADDR0
+ (i
* sizeof(uint32_t)),
947 sc
->rl_cdata
.cur_tx
= 0;
948 sc
->rl_cdata
.last_tx
= 0;
952 * A frame has been uploaded: pass the resulting mbuf chain up to
953 * the higher level protocols.
955 * You know there's something wrong with a PCI bus-master chip design
956 * when you have to use m_devget().
958 * The receive operation is badly documented in the datasheet, so I'll
959 * attempt to document it here. The driver provides a buffer area and
960 * places its base address in the RX buffer start address register.
961 * The chip then begins copying frames into the RX buffer. Each frame
962 * is preceded by a 32-bit RX status word which specifies the length
963 * of the frame and certain other status bits. Each frame (starting with
964 * the status word) is also 32-bit aligned. The frame length is in the
965 * first 16 bits of the status word; the lower 15 bits correspond with
966 * the 'rx status register' mentioned in the datasheet.
968 * Note: to make the Alpha happy, the frame payload needs to be aligned
969 * on a 32-bit boundary. To achieve this, we cheat a bit by copying from
970 * the ring buffer starting at an address two bytes before the actual
971 * data location. We can then shave off the first two bytes using m_adj().
972 * The reason we do this is because m_devget() doesn't let us specify an
973 * offset into the mbuf storage space, so we have to artificially create
974 * one. The ring is allocated in such a way that there are a few unused
975 * bytes of space preceecing it so that it will be safe for us to do the
976 * 2-byte backstep even if reading from the ring at offset 0.
979 rl_rxeof(struct rl_softc
*sc
)
986 int wrap
= 0, done
= 0;
987 uint16_t cur_rx
= 0, max_bytes
= 0, rx_bytes
= 0;
989 ifp
= &sc
->arpcom
.ac_if
;
991 while((CSR_READ_1(sc
, RL_COMMAND
) & RL_CMD_EMPTY_RXBUF
) == 0) {
997 cur_rx
= (CSR_READ_2(sc
, RL_CURRXADDR
) + 16) %
1000 /* Do not try to read past this point. */
1001 limit
= CSR_READ_2(sc
, RL_CURRXBUF
) % RL_RXBUFLEN
;
1003 max_bytes
= (RL_RXBUFLEN
- cur_rx
) + limit
;
1005 max_bytes
= limit
- cur_rx
;
1007 #ifdef IFPOLL_ENABLE
1008 if (ifp
->if_flags
& IFF_NPOLLING
) {
1009 if (sc
->rxcycles
<= 0)
1013 #endif /* IFPOLL_ENABLE */
1014 rxbufpos
= sc
->rl_cdata
.rl_rx_buf
+ cur_rx
;
1015 rxstat
= le32toh(*(uint32_t *)rxbufpos
);
1018 * Here's a totally undocumented fact for you. When the
1019 * RealTek chip is in the process of copying a packet into
1020 * RAM for you, the length will be 0xfff0. If you spot a
1021 * packet header with this value, you need to stop. The
1022 * datasheet makes absolutely no mention of this and
1023 * RealTek should be shot for this.
1025 if ((uint16_t)(rxstat
>> 16) == RL_RXSTAT_UNFINISHED
)
1028 if ((rxstat
& RL_RXSTAT_RXOK
) == 0) {
1029 IFNET_STAT_INC(ifp
, ierrors
, 1);
1034 /* No errors; receive the packet. */
1035 total_len
= rxstat
>> 16;
1036 rx_bytes
+= total_len
+ 4;
1039 * XXX The RealTek chip includes the CRC with every
1040 * received frame, and there's no way to turn this
1041 * behavior off (at least, I can't find anything in
1042 * the manual that explains how to do it) so we have
1043 * to trim off the CRC manually.
1045 total_len
-= ETHER_CRC_LEN
;
1048 * Avoid trying to read more bytes than we know
1049 * the chip has prepared for us.
1051 if (rx_bytes
> max_bytes
)
1054 rxbufpos
= sc
->rl_cdata
.rl_rx_buf
+
1055 ((cur_rx
+ sizeof(uint32_t)) % RL_RXBUFLEN
);
1057 if (rxbufpos
== (sc
->rl_cdata
.rl_rx_buf
+ RL_RXBUFLEN
))
1058 rxbufpos
= sc
->rl_cdata
.rl_rx_buf
;
1060 wrap
= (sc
->rl_cdata
.rl_rx_buf
+ RL_RXBUFLEN
) - rxbufpos
;
1062 if (total_len
> wrap
) {
1064 * Fool m_devget() into thinking we want to copy
1065 * the whole buffer so we don't end up fragmenting
1068 m
= m_devget(rxbufpos
- RL_ETHER_ALIGN
,
1069 wrap
+ RL_ETHER_ALIGN
, 0, ifp
);
1071 IFNET_STAT_INC(ifp
, ierrors
, 1);
1073 m_adj(m
, RL_ETHER_ALIGN
);
1074 m_copyback(m
, wrap
, total_len
- wrap
,
1075 sc
->rl_cdata
.rl_rx_buf
);
1077 cur_rx
= (total_len
- wrap
+ ETHER_CRC_LEN
);
1079 m
= m_devget(rxbufpos
- RL_ETHER_ALIGN
,
1080 total_len
+ RL_ETHER_ALIGN
, 0, ifp
);
1082 IFNET_STAT_INC(ifp
, ierrors
, 1);
1084 m_adj(m
, RL_ETHER_ALIGN
);
1085 cur_rx
+= total_len
+ 4 + ETHER_CRC_LEN
;
1089 * Round up to 32-bit boundary.
1091 cur_rx
= (cur_rx
+ 3) & ~3;
1092 CSR_WRITE_2(sc
, RL_CURRXADDR
, cur_rx
- 16);
1097 IFNET_STAT_INC(ifp
, ipackets
, 1);
1099 ifp
->if_input(ifp
, m
, NULL
, -1);
1104 * A frame was downloaded to the chip. It's safe for us to clean up
1108 rl_txeof(struct rl_softc
*sc
)
1113 ifp
= &sc
->arpcom
.ac_if
;
1116 * Go through our tx list and free mbufs for those
1117 * frames that have been uploaded.
1120 if (RL_LAST_TXMBUF(sc
) == NULL
)
1122 txstat
= CSR_READ_4(sc
, RL_LAST_TXSTAT(sc
));
1123 if ((txstat
& (RL_TXSTAT_TX_OK
| RL_TXSTAT_TX_UNDERRUN
|
1124 RL_TXSTAT_TXABRT
)) == 0)
1127 IFNET_STAT_INC(ifp
, collisions
,
1128 (txstat
& RL_TXSTAT_COLLCNT
) >> 24);
1130 bus_dmamap_unload(sc
->rl_cdata
.rl_tx_tag
, RL_LAST_DMAMAP(sc
));
1131 m_freem(RL_LAST_TXMBUF(sc
));
1132 RL_LAST_TXMBUF(sc
) = NULL
;
1133 RL_INC(sc
->rl_cdata
.last_tx
);
1135 if (txstat
& RL_TXSTAT_TX_UNDERRUN
) {
1136 sc
->rl_txthresh
+= 32;
1137 if (sc
->rl_txthresh
> RL_TX_THRESH_MAX
)
1138 sc
->rl_txthresh
= RL_TX_THRESH_MAX
;
1141 if (txstat
& RL_TXSTAT_TX_OK
) {
1142 IFNET_STAT_INC(ifp
, opackets
, 1);
1144 IFNET_STAT_INC(ifp
, oerrors
, 1);
1145 if (txstat
& (RL_TXSTAT_TXABRT
| RL_TXSTAT_OUTOFWIN
))
1146 CSR_WRITE_4(sc
, RL_TXCFG
, RL_TXCFG_CONFIG
);
1148 ifq_clr_oactive(&ifp
->if_snd
);
1149 } while (sc
->rl_cdata
.last_tx
!= sc
->rl_cdata
.cur_tx
);
1151 if (RL_LAST_TXMBUF(sc
) == NULL
)
1153 else if (ifp
->if_timer
== 0)
1160 struct rl_softc
*sc
= xsc
;
1161 struct mii_data
*mii
;
1163 lwkt_serialize_enter(sc
->arpcom
.ac_if
.if_serializer
);
1165 mii
= device_get_softc(sc
->rl_miibus
);
1168 callout_reset(&sc
->rl_stat_timer
, hz
, rl_tick
, sc
);
1170 lwkt_serialize_exit(sc
->arpcom
.ac_if
.if_serializer
);
1173 #ifdef IFPOLL_ENABLE
1176 rl_npoll_compat(struct ifnet
*ifp
, void *arg __unused
, int count
)
1178 struct rl_softc
*sc
= ifp
->if_softc
;
1180 ASSERT_SERIALIZED(ifp
->if_serializer
);
1182 sc
->rxcycles
= count
;
1185 if (!ifq_is_empty(&ifp
->if_snd
))
1188 if (sc
->rl_npoll
.ifpc_stcount
-- == 0) {
1191 sc
->rl_npoll
.ifpc_stcount
= sc
->rl_npoll
.ifpc_stfrac
;
1193 status
= CSR_READ_2(sc
, RL_ISR
);
1194 if (status
== 0xffff)
1197 CSR_WRITE_2(sc
, RL_ISR
, status
);
1200 * XXX check behaviour on receiver stalls.
1203 if (status
& RL_ISR_SYSTEM_ERR
) {
1211 rl_npoll(struct ifnet
*ifp
, struct ifpoll_info
*info
)
1213 struct rl_softc
*sc
= ifp
->if_softc
;
1215 ASSERT_SERIALIZED(ifp
->if_serializer
);
1218 int cpuid
= sc
->rl_npoll
.ifpc_cpuid
;
1220 info
->ifpi_rx
[cpuid
].poll_func
= rl_npoll_compat
;
1221 info
->ifpi_rx
[cpuid
].arg
= NULL
;
1222 info
->ifpi_rx
[cpuid
].serializer
= ifp
->if_serializer
;
1224 if (ifp
->if_flags
& IFF_RUNNING
) {
1225 /* disable interrupts */
1226 CSR_WRITE_2(sc
, RL_IMR
, 0x0000);
1227 sc
->rl_npoll
.ifpc_stcount
= 0;
1229 ifq_set_cpuid(&ifp
->if_snd
, cpuid
);
1231 if (ifp
->if_flags
& IFF_RUNNING
) {
1232 /* enable interrupts */
1233 CSR_WRITE_2(sc
, RL_IMR
, RL_INTRS
);
1235 ifq_set_cpuid(&ifp
->if_snd
, rman_get_cpuid(sc
->rl_irq
));
1239 #endif /* IFPOLL_ENABLE */
1244 struct rl_softc
*sc
;
1253 ifp
= &sc
->arpcom
.ac_if
;
1256 status
= CSR_READ_2(sc
, RL_ISR
);
1257 /* If the card has gone away, the read returns 0xffff. */
1258 if (status
== 0xffff)
1262 CSR_WRITE_2(sc
, RL_ISR
, status
);
1264 if ((status
& RL_INTRS
) == 0)
1267 if (status
& RL_ISR_RX_OK
)
1270 if (status
& RL_ISR_RX_ERR
)
1273 if ((status
& RL_ISR_TX_OK
) || (status
& RL_ISR_TX_ERR
))
1276 if (status
& RL_ISR_SYSTEM_ERR
) {
1283 if (!ifq_is_empty(&ifp
->if_snd
))
1288 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1289 * pointers to the fragment pointers.
1292 rl_encap(struct rl_softc
*sc
, struct mbuf
*m_head
)
1294 struct mbuf
*m_new
= NULL
;
1295 bus_dma_segment_t seg
;
1299 * The RealTek is brain damaged and wants longword-aligned
1300 * TX buffers, plus we can only have one fragment buffer
1301 * per packet. We have to copy pretty much all the time.
1303 m_new
= m_defrag(m_head
, M_NOWAIT
);
1304 if (m_new
== NULL
) {
1310 /* Pad frames to at least 60 bytes. */
1311 if (m_head
->m_pkthdr
.len
< RL_MIN_FRAMELEN
) {
1312 error
= m_devpad(m_head
, RL_MIN_FRAMELEN
);
1319 /* Extract physical address. */
1320 error
= bus_dmamap_load_mbuf_segment(sc
->rl_cdata
.rl_tx_tag
,
1321 RL_CUR_DMAMAP(sc
), m_head
,
1322 &seg
, 1, &nseg
, BUS_DMA_NOWAIT
);
1328 /* Sync the loaded TX buffer. */
1329 bus_dmamap_sync(sc
->rl_cdata
.rl_tx_tag
, RL_CUR_DMAMAP(sc
),
1330 BUS_DMASYNC_PREWRITE
);
1333 CSR_WRITE_4(sc
, RL_CUR_TXADDR(sc
), seg
.ds_addr
);
1334 CSR_WRITE_4(sc
, RL_CUR_TXSTAT(sc
),
1335 RL_TXTHRESH(sc
->rl_txthresh
) | seg
.ds_len
);
1337 RL_CUR_TXMBUF(sc
) = m_head
;
1342 * Main transmit routine.
1346 rl_start(struct ifnet
*ifp
, struct ifaltq_subque
*ifsq
)
1348 struct rl_softc
*sc
= ifp
->if_softc
;
1349 struct mbuf
*m_head
= NULL
;
1351 ASSERT_ALTQ_SQ_DEFAULT(ifp
, ifsq
);
1353 if ((ifp
->if_flags
& IFF_RUNNING
) == 0 || ifq_is_oactive(&ifp
->if_snd
))
1356 while (RL_CUR_TXMBUF(sc
) == NULL
) {
1357 m_head
= ifq_dequeue(&ifp
->if_snd
);
1361 if (rl_encap(sc
, m_head
))
1365 * If there's a BPF listener, bounce a copy of this frame
1368 BPF_MTAP(ifp
, RL_CUR_TXMBUF(sc
));
1370 RL_INC(sc
->rl_cdata
.cur_tx
);
1373 * Set a timeout in case the chip goes out to lunch.
1379 * We broke out of the loop because all our TX slots are
1380 * full. Mark the NIC as busy until it drains some of the
1381 * packets from the queue.
1383 if (RL_CUR_TXMBUF(sc
) != NULL
)
1384 ifq_set_oactive(&ifp
->if_snd
);
1390 struct rl_softc
*sc
= xsc
;
1391 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
1392 struct mii_data
*mii
;
1395 mii
= device_get_softc(sc
->rl_miibus
);
1398 * Cancel pending I/O and free all RX/TX buffers.
1403 * Init our MAC address. Even though the chipset documentation
1404 * doesn't mention it, we need to enter "Config register write enable"
1405 * mode to modify the ID registers.
1407 CSR_WRITE_1(sc
, RL_EECMD
, RL_EEMODE_WRITECFG
);
1408 CSR_WRITE_STREAM_4(sc
, RL_IDR0
,
1409 *(uint32_t *)(&sc
->arpcom
.ac_enaddr
[0]));
1410 CSR_WRITE_STREAM_4(sc
, RL_IDR4
,
1411 *(uint32_t *)(&sc
->arpcom
.ac_enaddr
[4]));
1412 CSR_WRITE_1(sc
, RL_EECMD
, RL_EEMODE_OFF
);
1414 /* Init the RX buffer pointer register. */
1415 CSR_WRITE_4(sc
, RL_RXADDR
, sc
->rl_cdata
.rl_rx_buf_paddr
);
1417 /* Init TX descriptors. */
1418 rl_list_tx_init(sc
);
1421 * Enable transmit and receive.
1423 CSR_WRITE_1(sc
, RL_COMMAND
, RL_CMD_TX_ENB
|RL_CMD_RX_ENB
);
1426 * Set the initial TX and RX configuration.
1428 CSR_WRITE_4(sc
, RL_TXCFG
, RL_TXCFG_CONFIG
);
1429 CSR_WRITE_4(sc
, RL_RXCFG
, RL_RXCFG_CONFIG
);
1431 /* Set the individual bit to receive frames for this host only. */
1432 rxcfg
= CSR_READ_4(sc
, RL_RXCFG
);
1433 rxcfg
|= RL_RXCFG_RX_INDIV
;
1435 /* If we want promiscuous mode, set the allframes bit. */
1436 if (ifp
->if_flags
& IFF_PROMISC
) {
1437 rxcfg
|= RL_RXCFG_RX_ALLPHYS
;
1438 CSR_WRITE_4(sc
, RL_RXCFG
, rxcfg
);
1440 rxcfg
&= ~RL_RXCFG_RX_ALLPHYS
;
1441 CSR_WRITE_4(sc
, RL_RXCFG
, rxcfg
);
1445 * Set capture broadcast bit to capture broadcast frames.
1447 if (ifp
->if_flags
& IFF_BROADCAST
) {
1448 rxcfg
|= RL_RXCFG_RX_BROAD
;
1449 CSR_WRITE_4(sc
, RL_RXCFG
, rxcfg
);
1451 rxcfg
&= ~RL_RXCFG_RX_BROAD
;
1452 CSR_WRITE_4(sc
, RL_RXCFG
, rxcfg
);
1456 * Program the multicast filter, if necessary.
1460 #ifdef IFPOLL_ENABLE
1462 * Only enable interrupts if we are polling, keep them off otherwise.
1464 if (ifp
->if_flags
& IFF_NPOLLING
) {
1465 CSR_WRITE_2(sc
, RL_IMR
, 0);
1466 sc
->rl_npoll
.ifpc_stcount
= 0;
1468 #endif /* IFPOLL_ENABLE */
1470 * Enable interrupts.
1472 CSR_WRITE_2(sc
, RL_IMR
, RL_INTRS
);
1474 /* Set initial TX threshold */
1475 sc
->rl_txthresh
= RL_TX_THRESH_INIT
;
1477 /* Start RX/TX process. */
1478 CSR_WRITE_4(sc
, RL_MISSEDPKT
, 0);
1480 /* Enable receiver and transmitter. */
1481 CSR_WRITE_1(sc
, RL_COMMAND
, RL_CMD_TX_ENB
|RL_CMD_RX_ENB
);
1485 CSR_WRITE_1(sc
, RL_CFG1
, RL_CFG1_DRVLOAD
|RL_CFG1_FULLDUPLEX
);
1487 ifp
->if_flags
|= IFF_RUNNING
;
1488 ifq_clr_oactive(&ifp
->if_snd
);
1490 callout_reset(&sc
->rl_stat_timer
, hz
, rl_tick
, sc
);
1494 * Set media options.
1497 rl_ifmedia_upd(struct ifnet
*ifp
)
1499 struct rl_softc
*sc
;
1500 struct mii_data
*mii
;
1503 mii
= device_get_softc(sc
->rl_miibus
);
1510 * Report current media status.
1513 rl_ifmedia_sts(struct ifnet
*ifp
, struct ifmediareq
*ifmr
)
1515 struct rl_softc
*sc
= ifp
->if_softc
;
1516 struct mii_data
*mii
= device_get_softc(sc
->rl_miibus
);
1519 ifmr
->ifm_active
= mii
->mii_media_active
;
1520 ifmr
->ifm_status
= mii
->mii_media_status
;
1524 rl_ioctl(struct ifnet
*ifp
, u_long command
, caddr_t data
, struct ucred
*cr
)
1526 struct rl_softc
*sc
= ifp
->if_softc
;
1527 struct ifreq
*ifr
= (struct ifreq
*) data
;
1528 struct mii_data
*mii
;
1533 if (ifp
->if_flags
& IFF_UP
) {
1536 if (ifp
->if_flags
& IFF_RUNNING
)
1548 mii
= device_get_softc(sc
->rl_miibus
);
1549 error
= ifmedia_ioctl(ifp
, ifr
, &mii
->mii_media
, command
);
1554 error
= ether_ioctl(ifp
, command
, data
);
1562 rl_watchdog(struct ifnet
*ifp
)
1564 struct rl_softc
*sc
= ifp
->if_softc
;
1566 device_printf(sc
->rl_dev
, "watchdog timeout\n");
1568 IFNET_STAT_INC(ifp
, oerrors
, 1);
1576 * Stop the adapter and free any mbufs allocated to the
1580 rl_stop(struct rl_softc
*sc
)
1582 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
1587 callout_stop(&sc
->rl_stat_timer
);
1588 ifp
->if_flags
&= ~IFF_RUNNING
;
1589 ifq_clr_oactive(&ifp
->if_snd
);
1591 CSR_WRITE_1(sc
, RL_COMMAND
, 0x00);
1592 CSR_WRITE_2(sc
, RL_IMR
, 0x0000);
1595 * Free the TX list buffers.
1597 for (i
= 0; i
< RL_TX_LIST_CNT
; i
++) {
1598 if (sc
->rl_cdata
.rl_tx_chain
[i
] != NULL
) {
1599 bus_dmamap_unload(sc
->rl_cdata
.rl_tx_tag
,
1600 sc
->rl_cdata
.rl_tx_dmamap
[i
]);
1601 m_freem(sc
->rl_cdata
.rl_tx_chain
[i
]);
1602 sc
->rl_cdata
.rl_tx_chain
[i
] = NULL
;
1603 CSR_WRITE_4(sc
, RL_TXADDR0
+ (i
* sizeof(uint32_t)),
1610 * Stop all chip I/O so that the kernel's probe routines don't
1611 * get confused by errant DMAs when rebooting.
1614 rl_shutdown(device_t dev
)
1616 struct rl_softc
*sc
;
1618 sc
= device_get_softc(dev
);
1619 lwkt_serialize_enter(sc
->arpcom
.ac_if
.if_serializer
);
1621 lwkt_serialize_exit(sc
->arpcom
.ac_if
.if_serializer
);
1625 * Device suspend routine. Stop the interface and save some PCI
1626 * settings in case the BIOS doesn't restore them properly on
1630 rl_suspend(device_t dev
)
1632 struct rl_softc
*sc
= device_get_softc(dev
);
1635 lwkt_serialize_enter(sc
->arpcom
.ac_if
.if_serializer
);
1638 for (i
= 0; i
< 5; i
++)
1639 sc
->saved_maps
[i
] = pci_read_config(dev
, PCIR_BAR(i
), 4);
1640 sc
->saved_biosaddr
= pci_read_config(dev
, PCIR_BIOS
, 4);
1641 sc
->saved_intline
= pci_read_config(dev
, PCIR_INTLINE
, 1);
1642 sc
->saved_cachelnsz
= pci_read_config(dev
, PCIR_CACHELNSZ
, 1);
1643 sc
->saved_lattimer
= pci_read_config(dev
, PCIR_LATTIMER
, 1);
1647 lwkt_serialize_exit(sc
->arpcom
.ac_if
.if_serializer
);
1652 * Device resume routine. Restore some PCI settings in case the BIOS
1653 * doesn't, re-enable busmastering, and restart the interface if
1657 rl_resume(device_t dev
)
1659 struct rl_softc
*sc
= device_get_softc(dev
);
1660 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
1663 lwkt_serialize_enter(ifp
->if_serializer
);
1665 /* better way to do this? */
1666 for (i
= 0; i
< 5; i
++)
1667 pci_write_config(dev
, PCIR_BAR(i
), sc
->saved_maps
[i
], 4);
1668 pci_write_config(dev
, PCIR_BIOS
, sc
->saved_biosaddr
, 4);
1669 pci_write_config(dev
, PCIR_INTLINE
, sc
->saved_intline
, 1);
1670 pci_write_config(dev
, PCIR_CACHELNSZ
, sc
->saved_cachelnsz
, 1);
1671 pci_write_config(dev
, PCIR_LATTIMER
, sc
->saved_lattimer
, 1);
1673 /* reenable busmastering */
1674 pci_enable_busmaster(dev
);
1675 pci_enable_io(dev
, RL_RES
);
1677 /* reinitialize interface if necessary */
1678 if (ifp
->if_flags
& IFF_UP
)
1682 lwkt_serialize_exit(ifp
->if_serializer
);
1687 rl_dma_alloc(struct rl_softc
*sc
)
1692 error
= bus_dma_tag_create(NULL
, /* parent */
1693 1, 0, /* alignment, boundary */
1694 BUS_SPACE_MAXADDR_32BIT
,/* lowaddr */
1695 BUS_SPACE_MAXADDR
, /* highaddr */
1696 NULL
, NULL
, /* filter, filterarg */
1697 BUS_SPACE_MAXSIZE_32BIT
,/* maxsize */
1699 BUS_SPACE_MAXSIZE_32BIT
,/* maxsegsize */
1701 &sc
->rl_parent_tag
);
1703 device_printf(sc
->rl_dev
, "can't create parent tag\n");
1707 /* Allocate a chunk of coherent memory for RX */
1708 error
= bus_dmamem_coherent(sc
->rl_parent_tag
, 1, 0,
1709 BUS_SPACE_MAXADDR
, BUS_SPACE_MAXADDR
,
1710 RL_RXBUFLEN
+ 1518, BUS_DMA_WAITOK
, &dmem
);
1714 sc
->rl_cdata
.rl_rx_tag
= dmem
.dmem_tag
;
1715 sc
->rl_cdata
.rl_rx_dmamap
= dmem
.dmem_map
;
1716 sc
->rl_cdata
.rl_rx_buf_ptr
= dmem
.dmem_addr
;
1718 /* NOTE: Apply same adjustment to vaddr and paddr */
1719 sc
->rl_cdata
.rl_rx_buf
= sc
->rl_cdata
.rl_rx_buf_ptr
+ sizeof(uint64_t);
1720 sc
->rl_cdata
.rl_rx_buf_paddr
= dmem
.dmem_busaddr
+ sizeof(uint64_t);
1723 * Allocate TX mbuf's DMA tag and maps
1725 error
= bus_dma_tag_create(sc
->rl_parent_tag
,/* parent */
1726 RL_TXBUF_ALIGN
, 0, /* alignment, boundary */
1727 BUS_SPACE_MAXADDR
, /* lowaddr */
1728 BUS_SPACE_MAXADDR
, /* highaddr */
1729 NULL
, NULL
, /* filter, filterarg */
1730 MCLBYTES
, /* maxsize */
1732 MCLBYTES
, /* maxsegsize */
1733 BUS_DMA_ALLOCNOW
| BUS_DMA_WAITOK
|
1734 BUS_DMA_ALIGNED
, /* flags */
1735 &sc
->rl_cdata
.rl_tx_tag
);
1737 device_printf(sc
->rl_dev
, "can't create TX mbuf tag\n");
1741 for (i
= 0; i
< RL_TX_LIST_CNT
; ++i
) {
1742 error
= bus_dmamap_create(sc
->rl_cdata
.rl_tx_tag
,
1743 BUS_DMA_WAITOK
, &sc
->rl_cdata
.rl_tx_dmamap
[i
]);
1747 for (j
= 0; j
< i
; ++j
) {
1748 bus_dmamap_destroy(sc
->rl_cdata
.rl_tx_tag
,
1749 sc
->rl_cdata
.rl_tx_dmamap
[j
]);
1751 bus_dma_tag_destroy(sc
->rl_cdata
.rl_tx_tag
);
1752 sc
->rl_cdata
.rl_tx_tag
= NULL
;
1754 device_printf(sc
->rl_dev
, "can't create TX mbuf map\n");
1762 rl_dma_free(struct rl_softc
*sc
)
1764 if (sc
->rl_cdata
.rl_tx_tag
!= NULL
) {
1767 for (i
= 0; i
< RL_TX_LIST_CNT
; ++i
) {
1768 bus_dmamap_destroy(sc
->rl_cdata
.rl_tx_tag
,
1769 sc
->rl_cdata
.rl_tx_dmamap
[i
]);
1771 bus_dma_tag_destroy(sc
->rl_cdata
.rl_tx_tag
);
1774 if (sc
->rl_cdata
.rl_rx_tag
!= NULL
) {
1775 bus_dmamap_unload(sc
->rl_cdata
.rl_rx_tag
,
1776 sc
->rl_cdata
.rl_rx_dmamap
);
1777 /* NOTE: Use rl_rx_buf_ptr here */
1778 bus_dmamem_free(sc
->rl_cdata
.rl_rx_tag
,
1779 sc
->rl_cdata
.rl_rx_buf_ptr
,
1780 sc
->rl_cdata
.rl_rx_dmamap
);
1781 bus_dma_tag_destroy(sc
->rl_cdata
.rl_rx_tag
);
1784 if (sc
->rl_parent_tag
)
1785 bus_dma_tag_destroy(sc
->rl_parent_tag
);