1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
57 removed because there is no way to know which register it was
60 To simplify substitution, we combine only when the earlier insn(s)
61 consist of only a single assignment. To simplify updating afterward,
62 we never combine when a subroutine call appears in the middle.
64 Since we do not represent assignments to CC0 explicitly except when that
65 is all an insn does, there is no LOG_LINKS entry in an insn that uses
66 the condition code for the insn that set the condition code.
67 Fortunately, these two insns must be consecutive.
68 Therefore, every JUMP_INSN is taken to have an implicit logical link
69 to the preceding insn. This is not quite right, since non-jumps can
70 also use the condition code; but in practice such insns would not
75 #include "coretypes.h"
82 #include "hard-reg-set.h"
83 #include "basic-block.h"
84 #include "insn-config.h"
86 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
88 #include "insn-attr.h"
94 #include "insn-codes.h"
95 #include "rtlhooks-def.h"
96 /* Include output.h for dump_file. */
100 /* Number of attempts to combine instructions in this function. */
102 static int combine_attempts
;
104 /* Number of attempts that got as far as substitution in this function. */
106 static int combine_merges
;
108 /* Number of instructions combined with added SETs in this function. */
110 static int combine_extras
;
112 /* Number of instructions combined in this function. */
114 static int combine_successes
;
116 /* Totals over entire compilation. */
118 static int total_attempts
, total_merges
, total_extras
, total_successes
;
121 /* Vector mapping INSN_UIDs to cuids.
122 The cuids are like uids but increase monotonically always.
123 Combine always uses cuids so that it can compare them.
124 But actually renumbering the uids, which we used to do,
125 proves to be a bad idea because it makes it hard to compare
126 the dumps produced by earlier passes with those from later passes. */
128 static int *uid_cuid
;
129 static int max_uid_cuid
;
131 /* Get the cuid of an insn. */
133 #define INSN_CUID(INSN) \
134 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
136 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
137 BITS_PER_WORD would invoke undefined behavior. Work around it. */
139 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
140 (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1)
142 /* Maximum register number, which is the size of the tables below. */
144 static unsigned int combine_max_regno
;
147 /* Record last point of death of (hard or pseudo) register n. */
150 /* Record last point of modification of (hard or pseudo) register n. */
153 /* The next group of fields allows the recording of the last value assigned
154 to (hard or pseudo) register n. We use this information to see if an
155 operation being processed is redundant given a prior operation performed
156 on the register. For example, an `and' with a constant is redundant if
157 all the zero bits are already known to be turned off.
159 We use an approach similar to that used by cse, but change it in the
162 (1) We do not want to reinitialize at each label.
163 (2) It is useful, but not critical, to know the actual value assigned
164 to a register. Often just its form is helpful.
166 Therefore, we maintain the following fields:
168 last_set_value the last value assigned
169 last_set_label records the value of label_tick when the
170 register was assigned
171 last_set_table_tick records the value of label_tick when a
172 value using the register is assigned
173 last_set_invalid set to nonzero when it is not valid
174 to use the value of this register in some
177 To understand the usage of these tables, it is important to understand
178 the distinction between the value in last_set_value being valid and
179 the register being validly contained in some other expression in the
182 (The next two parameters are out of date).
184 reg_stat[i].last_set_value is valid if it is nonzero, and either
185 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
187 Register I may validly appear in any expression returned for the value
188 of another register if reg_n_sets[i] is 1. It may also appear in the
189 value for register J if reg_stat[j].last_set_invalid is zero, or
190 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
192 If an expression is found in the table containing a register which may
193 not validly appear in an expression, the register is replaced by
194 something that won't match, (clobber (const_int 0)). */
196 /* Record last value assigned to (hard or pseudo) register n. */
200 /* Record the value of label_tick when an expression involving register n
201 is placed in last_set_value. */
203 int last_set_table_tick
;
205 /* Record the value of label_tick when the value for register n is placed in
210 /* These fields are maintained in parallel with last_set_value and are
211 used to store the mode in which the register was last set, the bits
212 that were known to be zero when it was last set, and the number of
213 sign bits copies it was known to have when it was last set. */
215 unsigned HOST_WIDE_INT last_set_nonzero_bits
;
216 char last_set_sign_bit_copies
;
217 ENUM_BITFIELD(machine_mode
) last_set_mode
: 8;
219 /* Set nonzero if references to register n in expressions should not be
220 used. last_set_invalid is set nonzero when this register is being
221 assigned to and last_set_table_tick == label_tick. */
223 char last_set_invalid
;
225 /* Some registers that are set more than once and used in more than one
226 basic block are nevertheless always set in similar ways. For example,
227 a QImode register may be loaded from memory in two places on a machine
228 where byte loads zero extend.
230 We record in the following fields if a register has some leading bits
231 that are always equal to the sign bit, and what we know about the
232 nonzero bits of a register, specifically which bits are known to be
235 If an entry is zero, it means that we don't know anything special. */
237 unsigned char sign_bit_copies
;
239 unsigned HOST_WIDE_INT nonzero_bits
;
242 static struct reg_stat
*reg_stat
;
244 /* Record the cuid of the last insn that invalidated memory
245 (anything that writes memory, and subroutine calls, but not pushes). */
247 static int mem_last_set
;
249 /* Record the cuid of the last CALL_INSN
250 so we can tell whether a potential combination crosses any calls. */
252 static int last_call_cuid
;
254 /* When `subst' is called, this is the insn that is being modified
255 (by combining in a previous insn). The PATTERN of this insn
256 is still the old pattern partially modified and it should not be
257 looked at, but this may be used to examine the successors of the insn
258 to judge whether a simplification is valid. */
260 static rtx subst_insn
;
262 /* This is the lowest CUID that `subst' is currently dealing with.
263 get_last_value will not return a value if the register was set at or
264 after this CUID. If not for this mechanism, we could get confused if
265 I2 or I1 in try_combine were an insn that used the old value of a register
266 to obtain a new value. In that case, we might erroneously get the
267 new value of the register when we wanted the old one. */
269 static int subst_low_cuid
;
271 /* This contains any hard registers that are used in newpat; reg_dead_at_p
272 must consider all these registers to be always live. */
274 static HARD_REG_SET newpat_used_regs
;
276 /* This is an insn to which a LOG_LINKS entry has been added. If this
277 insn is the earlier than I2 or I3, combine should rescan starting at
280 static rtx added_links_insn
;
282 /* Basic block in which we are performing combines. */
283 static basic_block this_basic_block
;
285 /* A bitmap indicating which blocks had registers go dead at entry.
286 After combine, we'll need to re-do global life analysis with
287 those blocks as starting points. */
288 static sbitmap refresh_blocks
;
290 /* The following array records the insn_rtx_cost for every insn
291 in the instruction stream. */
293 static int *uid_insn_cost
;
295 /* Length of the currently allocated uid_insn_cost array. */
297 static int last_insn_cost
;
299 /* Incremented for each label. */
301 static int label_tick
;
303 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
304 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
306 static enum machine_mode nonzero_bits_mode
;
308 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
309 be safely used. It is zero while computing them and after combine has
310 completed. This former test prevents propagating values based on
311 previously set values, which can be incorrect if a variable is modified
314 static int nonzero_sign_valid
;
317 /* Record one modification to rtl structure
318 to be undone by storing old_contents into *where.
319 is_int is 1 if the contents are an int. */
325 union {rtx r
; int i
;} old_contents
;
326 union {rtx
*r
; int *i
;} where
;
329 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
330 num_undo says how many are currently recorded.
332 other_insn is nonzero if we have modified some other insn in the process
333 of working on subst_insn. It must be verified too. */
342 static struct undobuf undobuf
;
344 /* Number of times the pseudo being substituted for
345 was found and replaced. */
347 static int n_occurrences
;
349 static rtx
reg_nonzero_bits_for_combine (rtx
, enum machine_mode
, rtx
,
351 unsigned HOST_WIDE_INT
,
352 unsigned HOST_WIDE_INT
*);
353 static rtx
reg_num_sign_bit_copies_for_combine (rtx
, enum machine_mode
, rtx
,
355 unsigned int, unsigned int *);
356 static void do_SUBST (rtx
*, rtx
);
357 static void do_SUBST_INT (int *, int);
358 static void init_reg_last (void);
359 static void setup_incoming_promotions (void);
360 static void set_nonzero_bits_and_sign_copies (rtx
, rtx
, void *);
361 static int cant_combine_insn_p (rtx
);
362 static int can_combine_p (rtx
, rtx
, rtx
, rtx
, rtx
*, rtx
*);
363 static int combinable_i3pat (rtx
, rtx
*, rtx
, rtx
, int, rtx
*);
364 static int contains_muldiv (rtx
);
365 static rtx
try_combine (rtx
, rtx
, rtx
, int *);
366 static void undo_all (void);
367 static void undo_commit (void);
368 static rtx
*find_split_point (rtx
*, rtx
);
369 static rtx
subst (rtx
, rtx
, rtx
, int, int);
370 static rtx
combine_simplify_rtx (rtx
, enum machine_mode
, int);
371 static rtx
simplify_if_then_else (rtx
);
372 static rtx
simplify_set (rtx
);
373 static rtx
simplify_logical (rtx
);
374 static rtx
expand_compound_operation (rtx
);
375 static rtx
expand_field_assignment (rtx
);
376 static rtx
make_extraction (enum machine_mode
, rtx
, HOST_WIDE_INT
,
377 rtx
, unsigned HOST_WIDE_INT
, int, int, int);
378 static rtx
extract_left_shift (rtx
, int);
379 static rtx
make_compound_operation (rtx
, enum rtx_code
);
380 static int get_pos_from_mask (unsigned HOST_WIDE_INT
,
381 unsigned HOST_WIDE_INT
*);
382 static rtx
force_to_mode (rtx
, enum machine_mode
,
383 unsigned HOST_WIDE_INT
, rtx
, int);
384 static rtx
if_then_else_cond (rtx
, rtx
*, rtx
*);
385 static rtx
known_cond (rtx
, enum rtx_code
, rtx
, rtx
);
386 static int rtx_equal_for_field_assignment_p (rtx
, rtx
);
387 static rtx
make_field_assignment (rtx
);
388 static rtx
apply_distributive_law (rtx
);
389 static rtx
distribute_and_simplify_rtx (rtx
, int);
390 static rtx
simplify_and_const_int (rtx
, enum machine_mode
, rtx
,
391 unsigned HOST_WIDE_INT
);
392 static int merge_outer_ops (enum rtx_code
*, HOST_WIDE_INT
*, enum rtx_code
,
393 HOST_WIDE_INT
, enum machine_mode
, int *);
394 static rtx
simplify_shift_const (rtx
, enum rtx_code
, enum machine_mode
, rtx
,
396 static int recog_for_combine (rtx
*, rtx
, rtx
*);
397 static rtx
gen_lowpart_for_combine (enum machine_mode
, rtx
);
398 static enum rtx_code
simplify_comparison (enum rtx_code
, rtx
*, rtx
*);
399 static void update_table_tick (rtx
);
400 static void record_value_for_reg (rtx
, rtx
, rtx
);
401 static void check_promoted_subreg (rtx
, rtx
);
402 static void record_dead_and_set_regs_1 (rtx
, rtx
, void *);
403 static void record_dead_and_set_regs (rtx
);
404 static int get_last_value_validate (rtx
*, rtx
, int, int);
405 static rtx
get_last_value (rtx
);
406 static int use_crosses_set_p (rtx
, int);
407 static void reg_dead_at_p_1 (rtx
, rtx
, void *);
408 static int reg_dead_at_p (rtx
, rtx
);
409 static void move_deaths (rtx
, rtx
, int, rtx
, rtx
*);
410 static int reg_bitfield_target_p (rtx
, rtx
);
411 static void distribute_notes (rtx
, rtx
, rtx
, rtx
);
412 static void distribute_links (rtx
);
413 static void mark_used_regs_combine (rtx
);
414 static int insn_cuid (rtx
);
415 static void record_promoted_value (rtx
, rtx
);
416 static rtx
reversed_comparison (rtx
, enum machine_mode
, rtx
, rtx
);
417 static enum rtx_code
combine_reversed_comparison_code (rtx
);
418 static int unmentioned_reg_p_1 (rtx
*, void *);
419 static bool unmentioned_reg_p (rtx
, rtx
);
422 /* It is not safe to use ordinary gen_lowpart in combine.
423 See comments in gen_lowpart_for_combine. */
424 #undef RTL_HOOKS_GEN_LOWPART
425 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
427 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
428 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
430 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
431 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
433 static const struct rtl_hooks combine_rtl_hooks
= RTL_HOOKS_INITIALIZER
;
436 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
437 insn. The substitution can be undone by undo_all. If INTO is already
438 set to NEWVAL, do not record this change. Because computing NEWVAL might
439 also call SUBST, we have to compute it before we put anything into
443 do_SUBST (rtx
*into
, rtx newval
)
448 if (oldval
== newval
)
451 /* We'd like to catch as many invalid transformations here as
452 possible. Unfortunately, there are way too many mode changes
453 that are perfectly valid, so we'd waste too much effort for
454 little gain doing the checks here. Focus on catching invalid
455 transformations involving integer constants. */
456 if (GET_MODE_CLASS (GET_MODE (oldval
)) == MODE_INT
457 && GET_CODE (newval
) == CONST_INT
)
459 /* Sanity check that we're replacing oldval with a CONST_INT
460 that is a valid sign-extension for the original mode. */
461 gcc_assert (INTVAL (newval
)
462 == trunc_int_for_mode (INTVAL (newval
), GET_MODE (oldval
)));
464 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
465 CONST_INT is not valid, because after the replacement, the
466 original mode would be gone. Unfortunately, we can't tell
467 when do_SUBST is called to replace the operand thereof, so we
468 perform this test on oldval instead, checking whether an
469 invalid replacement took place before we got here. */
470 gcc_assert (!(GET_CODE (oldval
) == SUBREG
471 && GET_CODE (SUBREG_REG (oldval
)) == CONST_INT
));
472 gcc_assert (!(GET_CODE (oldval
) == ZERO_EXTEND
473 && GET_CODE (XEXP (oldval
, 0)) == CONST_INT
));
477 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
479 buf
= xmalloc (sizeof (struct undo
));
483 buf
->old_contents
.r
= oldval
;
486 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
489 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
491 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
492 for the value of a HOST_WIDE_INT value (including CONST_INT) is
496 do_SUBST_INT (int *into
, int newval
)
501 if (oldval
== newval
)
505 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
507 buf
= xmalloc (sizeof (struct undo
));
511 buf
->old_contents
.i
= oldval
;
514 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
517 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
519 /* Subroutine of try_combine. Determine whether the combine replacement
520 patterns NEWPAT and NEWI2PAT are cheaper according to insn_rtx_cost
521 that the original instruction sequence I1, I2 and I3. Note that I1
522 and/or NEWI2PAT may be NULL_RTX. This function returns false, if the
523 costs of all instructions can be estimated, and the replacements are
524 more expensive than the original sequence. */
527 combine_validate_cost (rtx i1
, rtx i2
, rtx i3
, rtx newpat
, rtx newi2pat
)
529 int i1_cost
, i2_cost
, i3_cost
;
530 int new_i2_cost
, new_i3_cost
;
531 int old_cost
, new_cost
;
533 /* Lookup the original insn_rtx_costs. */
534 i2_cost
= INSN_UID (i2
) <= last_insn_cost
535 ? uid_insn_cost
[INSN_UID (i2
)] : 0;
536 i3_cost
= INSN_UID (i3
) <= last_insn_cost
537 ? uid_insn_cost
[INSN_UID (i3
)] : 0;
541 i1_cost
= INSN_UID (i1
) <= last_insn_cost
542 ? uid_insn_cost
[INSN_UID (i1
)] : 0;
543 old_cost
= (i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0)
544 ? i1_cost
+ i2_cost
+ i3_cost
: 0;
548 old_cost
= (i2_cost
> 0 && i3_cost
> 0) ? i2_cost
+ i3_cost
: 0;
552 /* Calculate the replacement insn_rtx_costs. */
553 new_i3_cost
= insn_rtx_cost (newpat
);
556 new_i2_cost
= insn_rtx_cost (newi2pat
);
557 new_cost
= (new_i2_cost
> 0 && new_i3_cost
> 0)
558 ? new_i2_cost
+ new_i3_cost
: 0;
562 new_cost
= new_i3_cost
;
566 if (undobuf
.other_insn
)
568 int old_other_cost
, new_other_cost
;
570 old_other_cost
= (INSN_UID (undobuf
.other_insn
) <= last_insn_cost
571 ? uid_insn_cost
[INSN_UID (undobuf
.other_insn
)] : 0);
572 new_other_cost
= insn_rtx_cost (PATTERN (undobuf
.other_insn
));
573 if (old_other_cost
> 0 && new_other_cost
> 0)
575 old_cost
+= old_other_cost
;
576 new_cost
+= new_other_cost
;
582 /* Disallow this recombination if both new_cost and old_cost are
583 greater than zero, and new_cost is greater than old cost. */
585 && new_cost
> old_cost
)
592 "rejecting combination of insns %d, %d and %d\n",
593 INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
594 fprintf (dump_file
, "original costs %d + %d + %d = %d\n",
595 i1_cost
, i2_cost
, i3_cost
, old_cost
);
600 "rejecting combination of insns %d and %d\n",
601 INSN_UID (i2
), INSN_UID (i3
));
602 fprintf (dump_file
, "original costs %d + %d = %d\n",
603 i2_cost
, i3_cost
, old_cost
);
608 fprintf (dump_file
, "replacement costs %d + %d = %d\n",
609 new_i2_cost
, new_i3_cost
, new_cost
);
612 fprintf (dump_file
, "replacement cost %d\n", new_cost
);
618 /* Update the uid_insn_cost array with the replacement costs. */
619 uid_insn_cost
[INSN_UID (i2
)] = new_i2_cost
;
620 uid_insn_cost
[INSN_UID (i3
)] = new_i3_cost
;
622 uid_insn_cost
[INSN_UID (i1
)] = 0;
627 /* Main entry point for combiner. F is the first insn of the function.
628 NREGS is the first unused pseudo-reg number.
630 Return nonzero if the combiner has turned an indirect jump
631 instruction into a direct jump. */
633 combine_instructions (rtx f
, unsigned int nregs
)
640 rtx links
, nextlinks
;
642 int new_direct_jump_p
= 0;
644 combine_attempts
= 0;
647 combine_successes
= 0;
649 combine_max_regno
= nregs
;
651 rtl_hooks
= combine_rtl_hooks
;
653 reg_stat
= xcalloc (nregs
, sizeof (struct reg_stat
));
655 init_recog_no_volatile ();
657 /* Compute maximum uid value so uid_cuid can be allocated. */
659 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
660 if (INSN_UID (insn
) > i
)
663 uid_cuid
= xmalloc ((i
+ 1) * sizeof (int));
666 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
668 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
669 problems when, for example, we have j <<= 1 in a loop. */
671 nonzero_sign_valid
= 0;
673 /* Compute the mapping from uids to cuids.
674 Cuids are numbers assigned to insns, like uids,
675 except that cuids increase monotonically through the code.
677 Scan all SETs and see if we can deduce anything about what
678 bits are known to be zero for some registers and how many copies
679 of the sign bit are known to exist for those registers.
681 Also set any known values so that we can use it while searching
682 for what bits are known to be set. */
686 setup_incoming_promotions ();
688 refresh_blocks
= sbitmap_alloc (last_basic_block
);
689 sbitmap_zero (refresh_blocks
);
691 /* Allocate array of current insn_rtx_costs. */
692 uid_insn_cost
= xcalloc (max_uid_cuid
+ 1, sizeof (int));
693 last_insn_cost
= max_uid_cuid
;
695 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
697 uid_cuid
[INSN_UID (insn
)] = ++i
;
703 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
705 record_dead_and_set_regs (insn
);
708 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
709 if (REG_NOTE_KIND (links
) == REG_INC
)
710 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
714 /* Record the current insn_rtx_cost of this instruction. */
715 if (NONJUMP_INSN_P (insn
))
716 uid_insn_cost
[INSN_UID (insn
)] = insn_rtx_cost (PATTERN (insn
));
718 fprintf(dump_file
, "insn_cost %d: %d\n",
719 INSN_UID (insn
), uid_insn_cost
[INSN_UID (insn
)]);
726 nonzero_sign_valid
= 1;
728 /* Now scan all the insns in forward order. */
734 setup_incoming_promotions ();
736 FOR_EACH_BB (this_basic_block
)
738 for (insn
= BB_HEAD (this_basic_block
);
739 insn
!= NEXT_INSN (BB_END (this_basic_block
));
740 insn
= next
? next
: NEXT_INSN (insn
))
747 else if (INSN_P (insn
))
749 /* See if we know about function return values before this
750 insn based upon SUBREG flags. */
751 check_promoted_subreg (insn
, PATTERN (insn
));
753 /* Try this insn with each insn it links back to. */
755 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
756 if ((next
= try_combine (insn
, XEXP (links
, 0),
757 NULL_RTX
, &new_direct_jump_p
)) != 0)
760 /* Try each sequence of three linked insns ending with this one. */
762 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
764 rtx link
= XEXP (links
, 0);
766 /* If the linked insn has been replaced by a note, then there
767 is no point in pursuing this chain any further. */
771 for (nextlinks
= LOG_LINKS (link
);
773 nextlinks
= XEXP (nextlinks
, 1))
774 if ((next
= try_combine (insn
, link
,
776 &new_direct_jump_p
)) != 0)
781 /* Try to combine a jump insn that uses CC0
782 with a preceding insn that sets CC0, and maybe with its
783 logical predecessor as well.
784 This is how we make decrement-and-branch insns.
785 We need this special code because data flow connections
786 via CC0 do not get entered in LOG_LINKS. */
789 && (prev
= prev_nonnote_insn (insn
)) != 0
790 && NONJUMP_INSN_P (prev
)
791 && sets_cc0_p (PATTERN (prev
)))
793 if ((next
= try_combine (insn
, prev
,
794 NULL_RTX
, &new_direct_jump_p
)) != 0)
797 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
798 nextlinks
= XEXP (nextlinks
, 1))
799 if ((next
= try_combine (insn
, prev
,
801 &new_direct_jump_p
)) != 0)
805 /* Do the same for an insn that explicitly references CC0. */
806 if (NONJUMP_INSN_P (insn
)
807 && (prev
= prev_nonnote_insn (insn
)) != 0
808 && NONJUMP_INSN_P (prev
)
809 && sets_cc0_p (PATTERN (prev
))
810 && GET_CODE (PATTERN (insn
)) == SET
811 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
813 if ((next
= try_combine (insn
, prev
,
814 NULL_RTX
, &new_direct_jump_p
)) != 0)
817 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
818 nextlinks
= XEXP (nextlinks
, 1))
819 if ((next
= try_combine (insn
, prev
,
821 &new_direct_jump_p
)) != 0)
825 /* Finally, see if any of the insns that this insn links to
826 explicitly references CC0. If so, try this insn, that insn,
827 and its predecessor if it sets CC0. */
828 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
829 if (NONJUMP_INSN_P (XEXP (links
, 0))
830 && GET_CODE (PATTERN (XEXP (links
, 0))) == SET
831 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (XEXP (links
, 0))))
832 && (prev
= prev_nonnote_insn (XEXP (links
, 0))) != 0
833 && NONJUMP_INSN_P (prev
)
834 && sets_cc0_p (PATTERN (prev
))
835 && (next
= try_combine (insn
, XEXP (links
, 0),
836 prev
, &new_direct_jump_p
)) != 0)
840 /* Try combining an insn with two different insns whose results it
842 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
843 for (nextlinks
= XEXP (links
, 1); nextlinks
;
844 nextlinks
= XEXP (nextlinks
, 1))
845 if ((next
= try_combine (insn
, XEXP (links
, 0),
847 &new_direct_jump_p
)) != 0)
850 /* Try this insn with each REG_EQUAL note it links back to. */
851 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
854 rtx temp
= XEXP (links
, 0);
855 if ((set
= single_set (temp
)) != 0
856 && (note
= find_reg_equal_equiv_note (temp
)) != 0
857 && GET_CODE (XEXP (note
, 0)) != EXPR_LIST
858 /* Avoid using a register that may already been marked
859 dead by an earlier instruction. */
860 && ! unmentioned_reg_p (XEXP (note
, 0), SET_SRC (set
)))
862 /* Temporarily replace the set's source with the
863 contents of the REG_EQUAL note. The insn will
864 be deleted or recognized by try_combine. */
865 rtx orig
= SET_SRC (set
);
866 SET_SRC (set
) = XEXP (note
, 0);
867 next
= try_combine (insn
, temp
, NULL_RTX
,
871 SET_SRC (set
) = orig
;
876 record_dead_and_set_regs (insn
);
885 EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks
, 0, i
,
886 BASIC_BLOCK (i
)->flags
|= BB_DIRTY
);
887 new_direct_jump_p
|= purge_all_dead_edges (0);
888 delete_noop_moves ();
890 update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES
,
891 PROP_DEATH_NOTES
| PROP_SCAN_DEAD_CODE
892 | PROP_KILL_DEAD_CODE
);
895 sbitmap_free (refresh_blocks
);
896 free (uid_insn_cost
);
901 struct undo
*undo
, *next
;
902 for (undo
= undobuf
.frees
; undo
; undo
= next
)
910 total_attempts
+= combine_attempts
;
911 total_merges
+= combine_merges
;
912 total_extras
+= combine_extras
;
913 total_successes
+= combine_successes
;
915 nonzero_sign_valid
= 0;
916 rtl_hooks
= general_rtl_hooks
;
918 /* Make recognizer allow volatile MEMs again. */
921 return new_direct_jump_p
;
924 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
930 for (i
= 0; i
< combine_max_regno
; i
++)
931 memset (reg_stat
+ i
, 0, offsetof (struct reg_stat
, sign_bit_copies
));
934 /* Set up any promoted values for incoming argument registers. */
937 setup_incoming_promotions (void)
941 enum machine_mode mode
;
943 rtx first
= get_insns ();
945 if (targetm
.calls
.promote_function_args (TREE_TYPE (cfun
->decl
)))
947 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
948 /* Check whether this register can hold an incoming pointer
949 argument. FUNCTION_ARG_REGNO_P tests outgoing register
950 numbers, so translate if necessary due to register windows. */
951 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno
))
952 && (reg
= promoted_input_arg (regno
, &mode
, &unsignedp
)) != 0)
955 (reg
, first
, gen_rtx_fmt_e ((unsignedp
? ZERO_EXTEND
958 gen_rtx_CLOBBER (mode
, const0_rtx
)));
963 /* Called via note_stores. If X is a pseudo that is narrower than
964 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
966 If we are setting only a portion of X and we can't figure out what
967 portion, assume all bits will be used since we don't know what will
970 Similarly, set how many bits of X are known to be copies of the sign bit
971 at all locations in the function. This is the smallest number implied
975 set_nonzero_bits_and_sign_copies (rtx x
, rtx set
,
976 void *data ATTRIBUTE_UNUSED
)
981 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
982 /* If this register is undefined at the start of the file, we can't
983 say what its contents were. */
984 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
, REGNO (x
))
985 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
987 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
989 reg_stat
[REGNO (x
)].nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
990 reg_stat
[REGNO (x
)].sign_bit_copies
= 1;
994 /* If this is a complex assignment, see if we can convert it into a
995 simple assignment. */
996 set
= expand_field_assignment (set
);
998 /* If this is a simple assignment, or we have a paradoxical SUBREG,
999 set what we know about X. */
1001 if (SET_DEST (set
) == x
1002 || (GET_CODE (SET_DEST (set
)) == SUBREG
1003 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set
)))
1004 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set
)))))
1005 && SUBREG_REG (SET_DEST (set
)) == x
))
1007 rtx src
= SET_SRC (set
);
1009 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1010 /* If X is narrower than a word and SRC is a non-negative
1011 constant that would appear negative in the mode of X,
1012 sign-extend it for use in reg_stat[].nonzero_bits because some
1013 machines (maybe most) will actually do the sign-extension
1014 and this is the conservative approach.
1016 ??? For 2.5, try to tighten up the MD files in this regard
1017 instead of this kludge. */
1019 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
1020 && GET_CODE (src
) == CONST_INT
1022 && 0 != (INTVAL (src
)
1023 & ((HOST_WIDE_INT
) 1
1024 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
1025 src
= GEN_INT (INTVAL (src
)
1026 | ((HOST_WIDE_INT
) (-1)
1027 << GET_MODE_BITSIZE (GET_MODE (x
))));
1030 /* Don't call nonzero_bits if it cannot change anything. */
1031 if (reg_stat
[REGNO (x
)].nonzero_bits
!= ~(unsigned HOST_WIDE_INT
) 0)
1032 reg_stat
[REGNO (x
)].nonzero_bits
1033 |= nonzero_bits (src
, nonzero_bits_mode
);
1034 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
1035 if (reg_stat
[REGNO (x
)].sign_bit_copies
== 0
1036 || reg_stat
[REGNO (x
)].sign_bit_copies
> num
)
1037 reg_stat
[REGNO (x
)].sign_bit_copies
= num
;
1041 reg_stat
[REGNO (x
)].nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1042 reg_stat
[REGNO (x
)].sign_bit_copies
= 1;
1047 /* See if INSN can be combined into I3. PRED and SUCC are optionally
1048 insns that were previously combined into I3 or that will be combined
1049 into the merger of INSN and I3.
1051 Return 0 if the combination is not allowed for any reason.
1053 If the combination is allowed, *PDEST will be set to the single
1054 destination of INSN and *PSRC to the single source, and this function
1058 can_combine_p (rtx insn
, rtx i3
, rtx pred ATTRIBUTE_UNUSED
, rtx succ
,
1059 rtx
*pdest
, rtx
*psrc
)
1062 rtx set
= 0, src
, dest
;
1067 int all_adjacent
= (succ
? (next_active_insn (insn
) == succ
1068 && next_active_insn (succ
) == i3
)
1069 : next_active_insn (insn
) == i3
);
1071 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1072 or a PARALLEL consisting of such a SET and CLOBBERs.
1074 If INSN has CLOBBER parallel parts, ignore them for our processing.
1075 By definition, these happen during the execution of the insn. When it
1076 is merged with another insn, all bets are off. If they are, in fact,
1077 needed and aren't also supplied in I3, they may be added by
1078 recog_for_combine. Otherwise, it won't match.
1080 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1083 Get the source and destination of INSN. If more than one, can't
1086 if (GET_CODE (PATTERN (insn
)) == SET
)
1087 set
= PATTERN (insn
);
1088 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
1089 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
1091 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
1093 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
1096 switch (GET_CODE (elt
))
1098 /* This is important to combine floating point insns
1099 for the SH4 port. */
1101 /* Combining an isolated USE doesn't make sense.
1102 We depend here on combinable_i3pat to reject them. */
1103 /* The code below this loop only verifies that the inputs of
1104 the SET in INSN do not change. We call reg_set_between_p
1105 to verify that the REG in the USE does not change between
1107 If the USE in INSN was for a pseudo register, the matching
1108 insn pattern will likely match any register; combining this
1109 with any other USE would only be safe if we knew that the
1110 used registers have identical values, or if there was
1111 something to tell them apart, e.g. different modes. For
1112 now, we forgo such complicated tests and simply disallow
1113 combining of USES of pseudo registers with any other USE. */
1114 if (REG_P (XEXP (elt
, 0))
1115 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
1117 rtx i3pat
= PATTERN (i3
);
1118 int i
= XVECLEN (i3pat
, 0) - 1;
1119 unsigned int regno
= REGNO (XEXP (elt
, 0));
1123 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
1125 if (GET_CODE (i3elt
) == USE
1126 && REG_P (XEXP (i3elt
, 0))
1127 && (REGNO (XEXP (i3elt
, 0)) == regno
1128 ? reg_set_between_p (XEXP (elt
, 0),
1129 PREV_INSN (insn
), i3
)
1130 : regno
>= FIRST_PSEUDO_REGISTER
))
1137 /* We can ignore CLOBBERs. */
1142 /* Ignore SETs whose result isn't used but not those that
1143 have side-effects. */
1144 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
1145 && (!(note
= find_reg_note (insn
, REG_EH_REGION
, NULL_RTX
))
1146 || INTVAL (XEXP (note
, 0)) <= 0)
1147 && ! side_effects_p (elt
))
1150 /* If we have already found a SET, this is a second one and
1151 so we cannot combine with this insn. */
1159 /* Anything else means we can't combine. */
1165 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1166 so don't do anything with it. */
1167 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1176 set
= expand_field_assignment (set
);
1177 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1179 /* Don't eliminate a store in the stack pointer. */
1180 if (dest
== stack_pointer_rtx
1181 /* Don't combine with an insn that sets a register to itself if it has
1182 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1183 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1184 /* Can't merge an ASM_OPERANDS. */
1185 || GET_CODE (src
) == ASM_OPERANDS
1186 /* Can't merge a function call. */
1187 || GET_CODE (src
) == CALL
1188 /* Don't eliminate a function call argument. */
1190 && (find_reg_fusage (i3
, USE
, dest
)
1192 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1193 && global_regs
[REGNO (dest
)])))
1194 /* Don't substitute into an incremented register. */
1195 || FIND_REG_INC_NOTE (i3
, dest
)
1196 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1197 /* Don't substitute into a non-local goto, this confuses CFG. */
1198 || (JUMP_P (i3
) && find_reg_note (i3
, REG_NON_LOCAL_GOTO
, NULL_RTX
))
1200 /* Don't combine the end of a libcall into anything. */
1201 /* ??? This gives worse code, and appears to be unnecessary, since no
1202 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1203 use REG_RETVAL notes for noconflict blocks, but other code here
1204 makes sure that those insns don't disappear. */
1205 || find_reg_note (insn
, REG_RETVAL
, NULL_RTX
)
1207 /* Make sure that DEST is not used after SUCC but before I3. */
1208 || (succ
&& ! all_adjacent
1209 && reg_used_between_p (dest
, succ
, i3
))
1210 /* Make sure that the value that is to be substituted for the register
1211 does not use any registers whose values alter in between. However,
1212 If the insns are adjacent, a use can't cross a set even though we
1213 think it might (this can happen for a sequence of insns each setting
1214 the same destination; last_set of that register might point to
1215 a NOTE). If INSN has a REG_EQUIV note, the register is always
1216 equivalent to the memory so the substitution is valid even if there
1217 are intervening stores. Also, don't move a volatile asm or
1218 UNSPEC_VOLATILE across any other insns. */
1221 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1222 && use_crosses_set_p (src
, INSN_CUID (insn
)))
1223 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
1224 || GET_CODE (src
) == UNSPEC_VOLATILE
))
1225 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1226 better register allocation by not doing the combine. */
1227 || find_reg_note (i3
, REG_NO_CONFLICT
, dest
)
1228 || (succ
&& find_reg_note (succ
, REG_NO_CONFLICT
, dest
))
1229 /* Don't combine across a CALL_INSN, because that would possibly
1230 change whether the life span of some REGs crosses calls or not,
1231 and it is a pain to update that information.
1232 Exception: if source is a constant, moving it later can't hurt.
1233 Accept that special case, because it helps -fforce-addr a lot. */
1234 || (INSN_CUID (insn
) < last_call_cuid
&& ! CONSTANT_P (src
)))
1237 /* DEST must either be a REG or CC0. */
1240 /* If register alignment is being enforced for multi-word items in all
1241 cases except for parameters, it is possible to have a register copy
1242 insn referencing a hard register that is not allowed to contain the
1243 mode being copied and which would not be valid as an operand of most
1244 insns. Eliminate this problem by not combining with such an insn.
1246 Also, on some machines we don't want to extend the life of a hard
1250 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
1251 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
1252 /* Don't extend the life of a hard register unless it is
1253 user variable (if we have few registers) or it can't
1254 fit into the desired register (meaning something special
1256 Also avoid substituting a return register into I3, because
1257 reload can't handle a conflict with constraints of other
1259 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
1260 && ! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
)))))
1263 else if (GET_CODE (dest
) != CC0
)
1267 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
1268 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
1269 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
)
1271 /* Don't substitute for a register intended as a clobberable
1273 rtx reg
= XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0);
1274 if (rtx_equal_p (reg
, dest
))
1277 /* If the clobber represents an earlyclobber operand, we must not
1278 substitute an expression containing the clobbered register.
1279 As we do not analyze the constraint strings here, we have to
1280 make the conservative assumption. However, if the register is
1281 a fixed hard reg, the clobber cannot represent any operand;
1282 we leave it up to the machine description to either accept or
1283 reject use-and-clobber patterns. */
1285 || REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1286 || !fixed_regs
[REGNO (reg
)])
1287 if (reg_overlap_mentioned_p (reg
, src
))
1291 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1292 or not), reject, unless nothing volatile comes between it and I3 */
1294 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
1296 /* Make sure succ doesn't contain a volatile reference. */
1297 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
1300 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1301 if (INSN_P (p
) && p
!= succ
&& volatile_refs_p (PATTERN (p
)))
1305 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1306 to be an explicit register variable, and was chosen for a reason. */
1308 if (GET_CODE (src
) == ASM_OPERANDS
1309 && REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
1312 /* If there are any volatile insns between INSN and I3, reject, because
1313 they might affect machine state. */
1315 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1316 if (INSN_P (p
) && p
!= succ
&& volatile_insn_p (PATTERN (p
)))
1319 /* If INSN contains an autoincrement or autodecrement, make sure that
1320 register is not used between there and I3, and not already used in
1321 I3 either. Neither must it be used in PRED or SUCC, if they exist.
1322 Also insist that I3 not be a jump; if it were one
1323 and the incremented register were spilled, we would lose. */
1326 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1327 if (REG_NOTE_KIND (link
) == REG_INC
1329 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
1330 || (pred
!= NULL_RTX
1331 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred
)))
1332 || (succ
!= NULL_RTX
1333 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ
)))
1334 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
1339 /* Don't combine an insn that follows a CC0-setting insn.
1340 An insn that uses CC0 must not be separated from the one that sets it.
1341 We do, however, allow I2 to follow a CC0-setting insn if that insn
1342 is passed as I1; in that case it will be deleted also.
1343 We also allow combining in this case if all the insns are adjacent
1344 because that would leave the two CC0 insns adjacent as well.
1345 It would be more logical to test whether CC0 occurs inside I1 or I2,
1346 but that would be much slower, and this ought to be equivalent. */
1348 p
= prev_nonnote_insn (insn
);
1349 if (p
&& p
!= pred
&& NONJUMP_INSN_P (p
) && sets_cc0_p (PATTERN (p
))
1354 /* If we get here, we have passed all the tests and the combination is
1363 /* LOC is the location within I3 that contains its pattern or the component
1364 of a PARALLEL of the pattern. We validate that it is valid for combining.
1366 One problem is if I3 modifies its output, as opposed to replacing it
1367 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1368 so would produce an insn that is not equivalent to the original insns.
1372 (set (reg:DI 101) (reg:DI 100))
1373 (set (subreg:SI (reg:DI 101) 0) <foo>)
1375 This is NOT equivalent to:
1377 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1378 (set (reg:DI 101) (reg:DI 100))])
1380 Not only does this modify 100 (in which case it might still be valid
1381 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1383 We can also run into a problem if I2 sets a register that I1
1384 uses and I1 gets directly substituted into I3 (not via I2). In that
1385 case, we would be getting the wrong value of I2DEST into I3, so we
1386 must reject the combination. This case occurs when I2 and I1 both
1387 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1388 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1389 of a SET must prevent combination from occurring.
1391 Before doing the above check, we first try to expand a field assignment
1392 into a set of logical operations.
1394 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1395 we place a register that is both set and used within I3. If more than one
1396 such register is detected, we fail.
1398 Return 1 if the combination is valid, zero otherwise. */
1401 combinable_i3pat (rtx i3
, rtx
*loc
, rtx i2dest
, rtx i1dest
,
1402 int i1_not_in_src
, rtx
*pi3dest_killed
)
1406 if (GET_CODE (x
) == SET
)
1409 rtx dest
= SET_DEST (set
);
1410 rtx src
= SET_SRC (set
);
1411 rtx inner_dest
= dest
;
1413 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
1414 || GET_CODE (inner_dest
) == SUBREG
1415 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
1416 inner_dest
= XEXP (inner_dest
, 0);
1418 /* Check for the case where I3 modifies its output, as discussed
1419 above. We don't want to prevent pseudos from being combined
1420 into the address of a MEM, so only prevent the combination if
1421 i1 or i2 set the same MEM. */
1422 if ((inner_dest
!= dest
&&
1423 (!MEM_P (inner_dest
)
1424 || rtx_equal_p (i2dest
, inner_dest
)
1425 || (i1dest
&& rtx_equal_p (i1dest
, inner_dest
)))
1426 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
1427 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))))
1429 /* This is the same test done in can_combine_p except we can't test
1430 all_adjacent; we don't have to, since this instruction will stay
1431 in place, thus we are not considering increasing the lifetime of
1434 Also, if this insn sets a function argument, combining it with
1435 something that might need a spill could clobber a previous
1436 function argument; the all_adjacent test in can_combine_p also
1437 checks this; here, we do a more specific test for this case. */
1439 || (REG_P (inner_dest
)
1440 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
1441 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
1442 GET_MODE (inner_dest
))))
1443 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
)))
1446 /* If DEST is used in I3, it is being killed in this insn,
1447 so record that for later.
1448 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1449 STACK_POINTER_REGNUM, since these are always considered to be
1450 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1451 if (pi3dest_killed
&& REG_P (dest
)
1452 && reg_referenced_p (dest
, PATTERN (i3
))
1453 && REGNO (dest
) != FRAME_POINTER_REGNUM
1454 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1455 && REGNO (dest
) != HARD_FRAME_POINTER_REGNUM
1457 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1458 && (REGNO (dest
) != ARG_POINTER_REGNUM
1459 || ! fixed_regs
[REGNO (dest
)])
1461 && REGNO (dest
) != STACK_POINTER_REGNUM
)
1463 if (*pi3dest_killed
)
1466 *pi3dest_killed
= dest
;
1470 else if (GET_CODE (x
) == PARALLEL
)
1474 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
1475 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
,
1476 i1_not_in_src
, pi3dest_killed
))
1483 /* Return 1 if X is an arithmetic expression that contains a multiplication
1484 and division. We don't count multiplications by powers of two here. */
1487 contains_muldiv (rtx x
)
1489 switch (GET_CODE (x
))
1491 case MOD
: case DIV
: case UMOD
: case UDIV
:
1495 return ! (GET_CODE (XEXP (x
, 1)) == CONST_INT
1496 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0);
1499 return contains_muldiv (XEXP (x
, 0))
1500 || contains_muldiv (XEXP (x
, 1));
1503 return contains_muldiv (XEXP (x
, 0));
1509 /* Determine whether INSN can be used in a combination. Return nonzero if
1510 not. This is used in try_combine to detect early some cases where we
1511 can't perform combinations. */
1514 cant_combine_insn_p (rtx insn
)
1519 /* If this isn't really an insn, we can't do anything.
1520 This can occur when flow deletes an insn that it has merged into an
1521 auto-increment address. */
1522 if (! INSN_P (insn
))
1525 /* Never combine loads and stores involving hard regs that are likely
1526 to be spilled. The register allocator can usually handle such
1527 reg-reg moves by tying. If we allow the combiner to make
1528 substitutions of likely-spilled regs, we may abort in reload.
1529 As an exception, we allow combinations involving fixed regs; these are
1530 not available to the register allocator so there's no risk involved. */
1532 set
= single_set (insn
);
1535 src
= SET_SRC (set
);
1536 dest
= SET_DEST (set
);
1537 if (GET_CODE (src
) == SUBREG
)
1538 src
= SUBREG_REG (src
);
1539 if (GET_CODE (dest
) == SUBREG
)
1540 dest
= SUBREG_REG (dest
);
1541 if (REG_P (src
) && REG_P (dest
)
1542 && ((REGNO (src
) < FIRST_PSEUDO_REGISTER
1543 && ! fixed_regs
[REGNO (src
)]
1544 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src
))))
1545 || (REGNO (dest
) < FIRST_PSEUDO_REGISTER
1546 && ! fixed_regs
[REGNO (dest
)]
1547 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest
))))))
1553 /* Adjust INSN after we made a change to its destination.
1555 Changing the destination can invalidate notes that say something about
1556 the results of the insn and a LOG_LINK pointing to the insn. */
1559 adjust_for_new_dest (rtx insn
)
1563 /* For notes, be conservative and simply remove them. */
1564 loc
= ®_NOTES (insn
);
1567 enum reg_note kind
= REG_NOTE_KIND (*loc
);
1568 if (kind
== REG_EQUAL
|| kind
== REG_EQUIV
)
1569 *loc
= XEXP (*loc
, 1);
1571 loc
= &XEXP (*loc
, 1);
1574 /* The new insn will have a destination that was previously the destination
1575 of an insn just above it. Call distribute_links to make a LOG_LINK from
1576 the next use of that destination. */
1577 distribute_links (gen_rtx_INSN_LIST (VOIDmode
, insn
, NULL_RTX
));
1580 /* Try to combine the insns I1 and I2 into I3.
1581 Here I1 and I2 appear earlier than I3.
1582 I1 can be zero; then we combine just I2 into I3.
1584 If we are combining three insns and the resulting insn is not recognized,
1585 try splitting it into two insns. If that happens, I2 and I3 are retained
1586 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1589 Return 0 if the combination does not work. Then nothing is changed.
1590 If we did the combination, return the insn at which combine should
1593 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
1594 new direct jump instruction. */
1597 try_combine (rtx i3
, rtx i2
, rtx i1
, int *new_direct_jump_p
)
1599 /* New patterns for I3 and I2, respectively. */
1600 rtx newpat
, newi2pat
= 0;
1601 int substed_i2
= 0, substed_i1
= 0;
1602 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1603 int added_sets_1
, added_sets_2
;
1604 /* Total number of SETs to put into I3. */
1606 /* Nonzero if I2's body now appears in I3. */
1608 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1609 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
1610 /* Contains I3 if the destination of I3 is used in its source, which means
1611 that the old life of I3 is being killed. If that usage is placed into
1612 I2 and not in I3, a REG_DEAD note must be made. */
1613 rtx i3dest_killed
= 0;
1614 /* SET_DEST and SET_SRC of I2 and I1. */
1615 rtx i2dest
, i2src
, i1dest
= 0, i1src
= 0;
1616 /* PATTERN (I2), or a copy of it in certain cases. */
1618 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1619 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
1620 int i1_feeds_i3
= 0;
1621 /* Notes that must be added to REG_NOTES in I3 and I2. */
1622 rtx new_i3_notes
, new_i2_notes
;
1623 /* Notes that we substituted I3 into I2 instead of the normal case. */
1624 int i3_subst_into_i2
= 0;
1625 /* Notes that I1, I2 or I3 is a MULT operation. */
1634 /* Exit early if one of the insns involved can't be used for
1636 if (cant_combine_insn_p (i3
)
1637 || cant_combine_insn_p (i2
)
1638 || (i1
&& cant_combine_insn_p (i1
))
1639 /* We also can't do anything if I3 has a
1640 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1643 /* ??? This gives worse code, and appears to be unnecessary, since no
1644 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1645 || find_reg_note (i3
, REG_LIBCALL
, NULL_RTX
)
1651 undobuf
.other_insn
= 0;
1653 /* Reset the hard register usage information. */
1654 CLEAR_HARD_REG_SET (newpat_used_regs
);
1656 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1657 code below, set I1 to be the earlier of the two insns. */
1658 if (i1
&& INSN_CUID (i1
) > INSN_CUID (i2
))
1659 temp
= i1
, i1
= i2
, i2
= temp
;
1661 added_links_insn
= 0;
1663 /* First check for one important special-case that the code below will
1664 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1665 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1666 we may be able to replace that destination with the destination of I3.
1667 This occurs in the common code where we compute both a quotient and
1668 remainder into a structure, in which case we want to do the computation
1669 directly into the structure to avoid register-register copies.
1671 Note that this case handles both multiple sets in I2 and also
1672 cases where I2 has a number of CLOBBER or PARALLELs.
1674 We make very conservative checks below and only try to handle the
1675 most common cases of this. For example, we only handle the case
1676 where I2 and I3 are adjacent to avoid making difficult register
1679 if (i1
== 0 && NONJUMP_INSN_P (i3
) && GET_CODE (PATTERN (i3
)) == SET
1680 && REG_P (SET_SRC (PATTERN (i3
)))
1681 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
1682 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
1683 && GET_CODE (PATTERN (i2
)) == PARALLEL
1684 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
1685 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1686 below would need to check what is inside (and reg_overlap_mentioned_p
1687 doesn't support those codes anyway). Don't allow those destinations;
1688 the resulting insn isn't likely to be recognized anyway. */
1689 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
1690 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
1691 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
1692 SET_DEST (PATTERN (i3
)))
1693 && next_real_insn (i2
) == i3
)
1695 rtx p2
= PATTERN (i2
);
1697 /* Make sure that the destination of I3,
1698 which we are going to substitute into one output of I2,
1699 is not used within another output of I2. We must avoid making this:
1700 (parallel [(set (mem (reg 69)) ...)
1701 (set (reg 69) ...)])
1702 which is not well-defined as to order of actions.
1703 (Besides, reload can't handle output reloads for this.)
1705 The problem can also happen if the dest of I3 is a memory ref,
1706 if another dest in I2 is an indirect memory ref. */
1707 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1708 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1709 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1710 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
1711 SET_DEST (XVECEXP (p2
, 0, i
))))
1714 if (i
== XVECLEN (p2
, 0))
1715 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1716 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1717 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1718 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
1723 subst_low_cuid
= INSN_CUID (i2
);
1725 added_sets_2
= added_sets_1
= 0;
1726 i2dest
= SET_SRC (PATTERN (i3
));
1728 /* Replace the dest in I2 with our dest and make the resulting
1729 insn the new pattern for I3. Then skip to where we
1730 validate the pattern. Everything was set up above. */
1731 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)),
1732 SET_DEST (PATTERN (i3
)));
1735 i3_subst_into_i2
= 1;
1736 goto validate_replacement
;
1740 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1741 one of those words to another constant, merge them by making a new
1744 && (temp
= single_set (i2
)) != 0
1745 && (GET_CODE (SET_SRC (temp
)) == CONST_INT
1746 || GET_CODE (SET_SRC (temp
)) == CONST_DOUBLE
)
1747 && REG_P (SET_DEST (temp
))
1748 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp
))) == MODE_INT
1749 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp
))) == 2 * UNITS_PER_WORD
1750 && GET_CODE (PATTERN (i3
)) == SET
1751 && GET_CODE (SET_DEST (PATTERN (i3
))) == SUBREG
1752 && SUBREG_REG (SET_DEST (PATTERN (i3
))) == SET_DEST (temp
)
1753 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3
)))) == MODE_INT
1754 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3
)))) == UNITS_PER_WORD
1755 && GET_CODE (SET_SRC (PATTERN (i3
))) == CONST_INT
)
1757 HOST_WIDE_INT lo
, hi
;
1759 if (GET_CODE (SET_SRC (temp
)) == CONST_INT
)
1760 lo
= INTVAL (SET_SRC (temp
)), hi
= lo
< 0 ? -1 : 0;
1763 lo
= CONST_DOUBLE_LOW (SET_SRC (temp
));
1764 hi
= CONST_DOUBLE_HIGH (SET_SRC (temp
));
1767 if (subreg_lowpart_p (SET_DEST (PATTERN (i3
))))
1769 /* We don't handle the case of the target word being wider
1770 than a host wide int. */
1771 gcc_assert (HOST_BITS_PER_WIDE_INT
>= BITS_PER_WORD
);
1773 lo
&= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
1774 lo
|= (INTVAL (SET_SRC (PATTERN (i3
)))
1775 & (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1777 else if (HOST_BITS_PER_WIDE_INT
== BITS_PER_WORD
)
1778 hi
= INTVAL (SET_SRC (PATTERN (i3
)));
1779 else if (HOST_BITS_PER_WIDE_INT
>= 2 * BITS_PER_WORD
)
1781 int sign
= -(int) ((unsigned HOST_WIDE_INT
) lo
1782 >> (HOST_BITS_PER_WIDE_INT
- 1));
1784 lo
&= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1785 (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1786 lo
|= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1787 (INTVAL (SET_SRC (PATTERN (i3
)))));
1789 hi
= lo
< 0 ? -1 : 0;
1792 /* We don't handle the case of the higher word not fitting
1793 entirely in either hi or lo. */
1798 subst_low_cuid
= INSN_CUID (i2
);
1799 added_sets_2
= added_sets_1
= 0;
1800 i2dest
= SET_DEST (temp
);
1802 SUBST (SET_SRC (temp
),
1803 immed_double_const (lo
, hi
, GET_MODE (SET_DEST (temp
))));
1805 newpat
= PATTERN (i2
);
1806 goto validate_replacement
;
1810 /* If we have no I1 and I2 looks like:
1811 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1813 make up a dummy I1 that is
1816 (set (reg:CC X) (compare:CC Y (const_int 0)))
1818 (We can ignore any trailing CLOBBERs.)
1820 This undoes a previous combination and allows us to match a branch-and-
1823 if (i1
== 0 && GET_CODE (PATTERN (i2
)) == PARALLEL
1824 && XVECLEN (PATTERN (i2
), 0) >= 2
1825 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 0)) == SET
1826 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
1828 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
1829 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
1830 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 1)) == SET
1831 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)))
1832 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
1833 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1))))
1835 for (i
= XVECLEN (PATTERN (i2
), 0) - 1; i
>= 2; i
--)
1836 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != CLOBBER
)
1841 /* We make I1 with the same INSN_UID as I2. This gives it
1842 the same INSN_CUID for value tracking. Our fake I1 will
1843 never appear in the insn stream so giving it the same INSN_UID
1844 as I2 will not cause a problem. */
1846 i1
= gen_rtx_INSN (VOIDmode
, INSN_UID (i2
), NULL_RTX
, i2
,
1847 BLOCK_FOR_INSN (i2
), INSN_LOCATOR (i2
),
1848 XVECEXP (PATTERN (i2
), 0, 1), -1, NULL_RTX
,
1851 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
1852 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
1853 SET_DEST (PATTERN (i1
)));
1858 /* Verify that I2 and I1 are valid for combining. */
1859 if (! can_combine_p (i2
, i3
, i1
, NULL_RTX
, &i2dest
, &i2src
)
1860 || (i1
&& ! can_combine_p (i1
, i3
, NULL_RTX
, i2
, &i1dest
, &i1src
)))
1866 /* Record whether I2DEST is used in I2SRC and similarly for the other
1867 cases. Knowing this will help in register status updating below. */
1868 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
1869 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
1870 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
1872 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1874 i1_feeds_i3
= i1
&& ! reg_overlap_mentioned_p (i1dest
, i2src
);
1876 /* Ensure that I3's pattern can be the destination of combines. */
1877 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
,
1878 i1
&& i2dest_in_i1src
&& i1_feeds_i3
,
1885 /* See if any of the insns is a MULT operation. Unless one is, we will
1886 reject a combination that is, since it must be slower. Be conservative
1888 if (GET_CODE (i2src
) == MULT
1889 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
1890 || (GET_CODE (PATTERN (i3
)) == SET
1891 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
1894 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1895 We used to do this EXCEPT in one case: I3 has a post-inc in an
1896 output operand. However, that exception can give rise to insns like
1898 which is a famous insn on the PDP-11 where the value of r3 used as the
1899 source was model-dependent. Avoid this sort of thing. */
1902 if (!(GET_CODE (PATTERN (i3
)) == SET
1903 && REG_P (SET_SRC (PATTERN (i3
)))
1904 && MEM_P (SET_DEST (PATTERN (i3
)))
1905 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
1906 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
1907 /* It's not the exception. */
1910 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
1911 if (REG_NOTE_KIND (link
) == REG_INC
1912 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
1914 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
1921 /* See if the SETs in I1 or I2 need to be kept around in the merged
1922 instruction: whenever the value set there is still needed past I3.
1923 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1925 For the SET in I1, we have two cases: If I1 and I2 independently
1926 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1927 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1928 in I1 needs to be kept around unless I1DEST dies or is set in either
1929 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1930 I1DEST. If so, we know I1 feeds into I2. */
1932 added_sets_2
= ! dead_or_set_p (i3
, i2dest
);
1935 = i1
&& ! (i1_feeds_i3
? dead_or_set_p (i3
, i1dest
)
1936 : (dead_or_set_p (i3
, i1dest
) || dead_or_set_p (i2
, i1dest
)));
1938 /* If the set in I2 needs to be kept around, we must make a copy of
1939 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1940 PATTERN (I2), we are only substituting for the original I1DEST, not into
1941 an already-substituted copy. This also prevents making self-referential
1942 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1945 i2pat
= (GET_CODE (PATTERN (i2
)) == PARALLEL
1946 ? gen_rtx_SET (VOIDmode
, i2dest
, i2src
)
1950 i2pat
= copy_rtx (i2pat
);
1954 /* Substitute in the latest insn for the regs set by the earlier ones. */
1956 maxreg
= max_reg_num ();
1960 /* It is possible that the source of I2 or I1 may be performing an
1961 unneeded operation, such as a ZERO_EXTEND of something that is known
1962 to have the high part zero. Handle that case by letting subst look at
1963 the innermost one of them.
1965 Another way to do this would be to have a function that tries to
1966 simplify a single insn instead of merging two or more insns. We don't
1967 do this because of the potential of infinite loops and because
1968 of the potential extra memory required. However, doing it the way
1969 we are is a bit of a kludge and doesn't catch all cases.
1971 But only do this if -fexpensive-optimizations since it slows things down
1972 and doesn't usually win. */
1974 if (flag_expensive_optimizations
)
1976 /* Pass pc_rtx so no substitutions are done, just simplifications. */
1979 subst_low_cuid
= INSN_CUID (i1
);
1980 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0);
1984 subst_low_cuid
= INSN_CUID (i2
);
1985 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0);
1990 /* Many machines that don't use CC0 have insns that can both perform an
1991 arithmetic operation and set the condition code. These operations will
1992 be represented as a PARALLEL with the first element of the vector
1993 being a COMPARE of an arithmetic operation with the constant zero.
1994 The second element of the vector will set some pseudo to the result
1995 of the same arithmetic operation. If we simplify the COMPARE, we won't
1996 match such a pattern and so will generate an extra insn. Here we test
1997 for this case, where both the comparison and the operation result are
1998 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1999 I2SRC. Later we will make the PARALLEL that contains I2. */
2001 if (i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
2002 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
2003 && XEXP (SET_SRC (PATTERN (i3
)), 1) == const0_rtx
2004 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
2006 #ifdef SELECT_CC_MODE
2008 enum machine_mode compare_mode
;
2011 newpat
= PATTERN (i3
);
2012 SUBST (XEXP (SET_SRC (newpat
), 0), i2src
);
2016 #ifdef SELECT_CC_MODE
2017 /* See if a COMPARE with the operand we substituted in should be done
2018 with the mode that is currently being used. If not, do the same
2019 processing we do in `subst' for a SET; namely, if the destination
2020 is used only once, try to replace it with a register of the proper
2021 mode and also replace the COMPARE. */
2022 if (undobuf
.other_insn
== 0
2023 && (cc_use
= find_single_use (SET_DEST (newpat
), i3
,
2024 &undobuf
.other_insn
))
2025 && ((compare_mode
= SELECT_CC_MODE (GET_CODE (*cc_use
),
2027 != GET_MODE (SET_DEST (newpat
))))
2029 unsigned int regno
= REGNO (SET_DEST (newpat
));
2030 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
2032 if (regno
< FIRST_PSEUDO_REGISTER
2033 || (REG_N_SETS (regno
) == 1 && ! added_sets_2
2034 && ! REG_USERVAR_P (SET_DEST (newpat
))))
2036 if (regno
>= FIRST_PSEUDO_REGISTER
)
2037 SUBST (regno_reg_rtx
[regno
], new_dest
);
2039 SUBST (SET_DEST (newpat
), new_dest
);
2040 SUBST (XEXP (*cc_use
, 0), new_dest
);
2041 SUBST (SET_SRC (newpat
),
2042 gen_rtx_COMPARE (compare_mode
, i2src
, const0_rtx
));
2045 undobuf
.other_insn
= 0;
2052 n_occurrences
= 0; /* `subst' counts here */
2054 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
2055 need to make a unique copy of I2SRC each time we substitute it
2056 to avoid self-referential rtl. */
2058 subst_low_cuid
= INSN_CUID (i2
);
2059 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0,
2060 ! i1_feeds_i3
&& i1dest_in_i1src
);
2063 /* Record whether i2's body now appears within i3's body. */
2064 i2_is_used
= n_occurrences
;
2067 /* If we already got a failure, don't try to do more. Otherwise,
2068 try to substitute in I1 if we have it. */
2070 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
2072 /* Before we can do this substitution, we must redo the test done
2073 above (see detailed comments there) that ensures that I1DEST
2074 isn't mentioned in any SETs in NEWPAT that are field assignments. */
2076 if (! combinable_i3pat (NULL_RTX
, &newpat
, i1dest
, NULL_RTX
,
2084 subst_low_cuid
= INSN_CUID (i1
);
2085 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0);
2089 /* Fail if an autoincrement side-effect has been duplicated. Be careful
2090 to count all the ways that I2SRC and I1SRC can be used. */
2091 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
2092 && i2_is_used
+ added_sets_2
> 1)
2093 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
2094 && (n_occurrences
+ added_sets_1
+ (added_sets_2
&& ! i1_feeds_i3
)
2096 /* Fail if we tried to make a new register (we used to abort, but there's
2097 really no reason to). */
2098 || max_reg_num () != maxreg
2099 /* Fail if we couldn't do something and have a CLOBBER. */
2100 || GET_CODE (newpat
) == CLOBBER
2101 /* Fail if this new pattern is a MULT and we didn't have one before
2102 at the outer level. */
2103 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
2110 /* If the actions of the earlier insns must be kept
2111 in addition to substituting them into the latest one,
2112 we must make a new PARALLEL for the latest insn
2113 to hold additional the SETs. */
2115 if (added_sets_1
|| added_sets_2
)
2119 if (GET_CODE (newpat
) == PARALLEL
)
2121 rtvec old
= XVEC (newpat
, 0);
2122 total_sets
= XVECLEN (newpat
, 0) + added_sets_1
+ added_sets_2
;
2123 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
2124 memcpy (XVEC (newpat
, 0)->elem
, &old
->elem
[0],
2125 sizeof (old
->elem
[0]) * old
->num_elem
);
2130 total_sets
= 1 + added_sets_1
+ added_sets_2
;
2131 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
2132 XVECEXP (newpat
, 0, 0) = old
;
2136 XVECEXP (newpat
, 0, --total_sets
)
2137 = (GET_CODE (PATTERN (i1
)) == PARALLEL
2138 ? gen_rtx_SET (VOIDmode
, i1dest
, i1src
) : PATTERN (i1
));
2142 /* If there is no I1, use I2's body as is. We used to also not do
2143 the subst call below if I2 was substituted into I3,
2144 but that could lose a simplification. */
2146 XVECEXP (newpat
, 0, --total_sets
) = i2pat
;
2148 /* See comment where i2pat is assigned. */
2149 XVECEXP (newpat
, 0, --total_sets
)
2150 = subst (i2pat
, i1dest
, i1src
, 0, 0);
2154 /* We come here when we are replacing a destination in I2 with the
2155 destination of I3. */
2156 validate_replacement
:
2158 /* Note which hard regs this insn has as inputs. */
2159 mark_used_regs_combine (newpat
);
2161 /* Is the result of combination a valid instruction? */
2162 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2164 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2165 the second SET's destination is a register that is unused and isn't
2166 marked as an instruction that might trap in an EH region. In that case,
2167 we just need the first SET. This can occur when simplifying a divmod
2168 insn. We *must* test for this case here because the code below that
2169 splits two independent SETs doesn't handle this case correctly when it
2170 updates the register status.
2172 It's pointless doing this if we originally had two sets, one from
2173 i3, and one from i2. Combining then splitting the parallel results
2174 in the original i2 again plus an invalid insn (which we delete).
2175 The net effect is only to move instructions around, which makes
2176 debug info less accurate.
2178 Also check the case where the first SET's destination is unused.
2179 That would not cause incorrect code, but does cause an unneeded
2182 if (insn_code_number
< 0
2183 && !(added_sets_2
&& i1
== 0)
2184 && GET_CODE (newpat
) == PARALLEL
2185 && XVECLEN (newpat
, 0) == 2
2186 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2187 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2188 && asm_noperands (newpat
) < 0)
2190 rtx set0
= XVECEXP (newpat
, 0, 0);
2191 rtx set1
= XVECEXP (newpat
, 0, 1);
2194 if (((REG_P (SET_DEST (set1
))
2195 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set1
)))
2196 || (GET_CODE (SET_DEST (set1
)) == SUBREG
2197 && find_reg_note (i3
, REG_UNUSED
, SUBREG_REG (SET_DEST (set1
)))))
2198 && (!(note
= find_reg_note (i3
, REG_EH_REGION
, NULL_RTX
))
2199 || INTVAL (XEXP (note
, 0)) <= 0)
2200 && ! side_effects_p (SET_SRC (set1
)))
2203 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2206 else if (((REG_P (SET_DEST (set0
))
2207 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set0
)))
2208 || (GET_CODE (SET_DEST (set0
)) == SUBREG
2209 && find_reg_note (i3
, REG_UNUSED
,
2210 SUBREG_REG (SET_DEST (set0
)))))
2211 && (!(note
= find_reg_note (i3
, REG_EH_REGION
, NULL_RTX
))
2212 || INTVAL (XEXP (note
, 0)) <= 0)
2213 && ! side_effects_p (SET_SRC (set0
)))
2216 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2218 if (insn_code_number
>= 0)
2220 /* If we will be able to accept this, we have made a
2221 change to the destination of I3. This requires us to
2222 do a few adjustments. */
2224 PATTERN (i3
) = newpat
;
2225 adjust_for_new_dest (i3
);
2230 /* If we were combining three insns and the result is a simple SET
2231 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2232 insns. There are two ways to do this. It can be split using a
2233 machine-specific method (like when you have an addition of a large
2234 constant) or by combine in the function find_split_point. */
2236 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
2237 && asm_noperands (newpat
) < 0)
2239 rtx m_split
, *split
;
2240 rtx ni2dest
= i2dest
;
2242 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2243 use I2DEST as a scratch register will help. In the latter case,
2244 convert I2DEST to the mode of the source of NEWPAT if we can. */
2246 m_split
= split_insns (newpat
, i3
);
2248 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2249 inputs of NEWPAT. */
2251 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2252 possible to try that as a scratch reg. This would require adding
2253 more code to make it work though. */
2255 if (m_split
== 0 && ! reg_overlap_mentioned_p (ni2dest
, newpat
))
2257 /* If I2DEST is a hard register or the only use of a pseudo,
2258 we can change its mode. */
2259 if (GET_MODE (SET_DEST (newpat
)) != GET_MODE (i2dest
)
2260 && GET_MODE (SET_DEST (newpat
)) != VOIDmode
2262 && (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
2263 || (REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
2264 && ! REG_USERVAR_P (i2dest
))))
2265 ni2dest
= gen_rtx_REG (GET_MODE (SET_DEST (newpat
)),
2268 m_split
= split_insns (gen_rtx_PARALLEL
2270 gen_rtvec (2, newpat
,
2271 gen_rtx_CLOBBER (VOIDmode
,
2274 /* If the split with the mode-changed register didn't work, try
2275 the original register. */
2276 if (! m_split
&& ni2dest
!= i2dest
)
2279 m_split
= split_insns (gen_rtx_PARALLEL
2281 gen_rtvec (2, newpat
,
2282 gen_rtx_CLOBBER (VOIDmode
,
2288 if (m_split
&& NEXT_INSN (m_split
) == NULL_RTX
)
2290 m_split
= PATTERN (m_split
);
2291 insn_code_number
= recog_for_combine (&m_split
, i3
, &new_i3_notes
);
2292 if (insn_code_number
>= 0)
2295 else if (m_split
&& NEXT_INSN (NEXT_INSN (m_split
)) == NULL_RTX
2296 && (next_real_insn (i2
) == i3
2297 || ! use_crosses_set_p (PATTERN (m_split
), INSN_CUID (i2
))))
2300 rtx newi3pat
= PATTERN (NEXT_INSN (m_split
));
2301 newi2pat
= PATTERN (m_split
);
2303 i3set
= single_set (NEXT_INSN (m_split
));
2304 i2set
= single_set (m_split
);
2306 /* In case we changed the mode of I2DEST, replace it in the
2307 pseudo-register table here. We can't do it above in case this
2308 code doesn't get executed and we do a split the other way. */
2310 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2311 SUBST (regno_reg_rtx
[REGNO (i2dest
)], ni2dest
);
2313 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2315 /* If I2 or I3 has multiple SETs, we won't know how to track
2316 register status, so don't use these insns. If I2's destination
2317 is used between I2 and I3, we also can't use these insns. */
2319 if (i2_code_number
>= 0 && i2set
&& i3set
2320 && (next_real_insn (i2
) == i3
2321 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
2322 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
2324 if (insn_code_number
>= 0)
2327 /* It is possible that both insns now set the destination of I3.
2328 If so, we must show an extra use of it. */
2330 if (insn_code_number
>= 0)
2332 rtx new_i3_dest
= SET_DEST (i3set
);
2333 rtx new_i2_dest
= SET_DEST (i2set
);
2335 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
2336 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
2337 || GET_CODE (new_i3_dest
) == SUBREG
)
2338 new_i3_dest
= XEXP (new_i3_dest
, 0);
2340 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
2341 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
2342 || GET_CODE (new_i2_dest
) == SUBREG
)
2343 new_i2_dest
= XEXP (new_i2_dest
, 0);
2345 if (REG_P (new_i3_dest
)
2346 && REG_P (new_i2_dest
)
2347 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
))
2348 REG_N_SETS (REGNO (new_i2_dest
))++;
2352 /* If we can split it and use I2DEST, go ahead and see if that
2353 helps things be recognized. Verify that none of the registers
2354 are set between I2 and I3. */
2355 if (insn_code_number
< 0 && (split
= find_split_point (&newpat
, i3
)) != 0
2359 /* We need I2DEST in the proper mode. If it is a hard register
2360 or the only use of a pseudo, we can change its mode. */
2361 && (GET_MODE (*split
) == GET_MODE (i2dest
)
2362 || GET_MODE (*split
) == VOIDmode
2363 || REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
2364 || (REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
2365 && ! REG_USERVAR_P (i2dest
)))
2366 && (next_real_insn (i2
) == i3
2367 || ! use_crosses_set_p (*split
, INSN_CUID (i2
)))
2368 /* We can't overwrite I2DEST if its value is still used by
2370 && ! reg_referenced_p (i2dest
, newpat
))
2372 rtx newdest
= i2dest
;
2373 enum rtx_code split_code
= GET_CODE (*split
);
2374 enum machine_mode split_mode
= GET_MODE (*split
);
2376 /* Get NEWDEST as a register in the proper mode. We have already
2377 validated that we can do this. */
2378 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
2380 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
2382 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2383 SUBST (regno_reg_rtx
[REGNO (i2dest
)], newdest
);
2386 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2387 an ASHIFT. This can occur if it was inside a PLUS and hence
2388 appeared to be a memory address. This is a kludge. */
2389 if (split_code
== MULT
2390 && GET_CODE (XEXP (*split
, 1)) == CONST_INT
2391 && INTVAL (XEXP (*split
, 1)) > 0
2392 && (i
= exact_log2 (INTVAL (XEXP (*split
, 1)))) >= 0)
2394 SUBST (*split
, gen_rtx_ASHIFT (split_mode
,
2395 XEXP (*split
, 0), GEN_INT (i
)));
2396 /* Update split_code because we may not have a multiply
2398 split_code
= GET_CODE (*split
);
2401 #ifdef INSN_SCHEDULING
2402 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2403 be written as a ZERO_EXTEND. */
2404 if (split_code
== SUBREG
&& MEM_P (SUBREG_REG (*split
)))
2406 #ifdef LOAD_EXTEND_OP
2407 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
2408 what it really is. */
2409 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split
)))
2411 SUBST (*split
, gen_rtx_SIGN_EXTEND (split_mode
,
2412 SUBREG_REG (*split
)));
2415 SUBST (*split
, gen_rtx_ZERO_EXTEND (split_mode
,
2416 SUBREG_REG (*split
)));
2420 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, *split
);
2421 SUBST (*split
, newdest
);
2422 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2424 /* recog_for_combine might have added CLOBBERs to newi2pat.
2425 Make sure NEWPAT does not depend on the clobbered regs. */
2426 if (GET_CODE (newi2pat
) == PARALLEL
)
2427 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
2428 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
2430 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
2431 if (reg_overlap_mentioned_p (reg
, newpat
))
2438 /* If the split point was a MULT and we didn't have one before,
2439 don't use one now. */
2440 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
2441 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2445 /* Check for a case where we loaded from memory in a narrow mode and
2446 then sign extended it, but we need both registers. In that case,
2447 we have a PARALLEL with both loads from the same memory location.
2448 We can split this into a load from memory followed by a register-register
2449 copy. This saves at least one insn, more if register allocation can
2452 We cannot do this if the destination of the first assignment is a
2453 condition code register or cc0. We eliminate this case by making sure
2454 the SET_DEST and SET_SRC have the same mode.
2456 We cannot do this if the destination of the second assignment is
2457 a register that we have already assumed is zero-extended. Similarly
2458 for a SUBREG of such a register. */
2460 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2461 && GET_CODE (newpat
) == PARALLEL
2462 && XVECLEN (newpat
, 0) == 2
2463 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2464 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
2465 && (GET_MODE (SET_DEST (XVECEXP (newpat
, 0, 0)))
2466 == GET_MODE (SET_SRC (XVECEXP (newpat
, 0, 0))))
2467 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2468 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2469 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
2470 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2472 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2473 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2474 && ! (temp
= SET_DEST (XVECEXP (newpat
, 0, 1)),
2476 && reg_stat
[REGNO (temp
)].nonzero_bits
!= 0
2477 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2478 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2479 && (reg_stat
[REGNO (temp
)].nonzero_bits
2480 != GET_MODE_MASK (word_mode
))))
2481 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
2482 && (temp
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
2484 && reg_stat
[REGNO (temp
)].nonzero_bits
!= 0
2485 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2486 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2487 && (reg_stat
[REGNO (temp
)].nonzero_bits
2488 != GET_MODE_MASK (word_mode
)))))
2489 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2490 SET_SRC (XVECEXP (newpat
, 0, 1)))
2491 && ! find_reg_note (i3
, REG_UNUSED
,
2492 SET_DEST (XVECEXP (newpat
, 0, 0))))
2496 newi2pat
= XVECEXP (newpat
, 0, 0);
2497 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
2498 newpat
= XVECEXP (newpat
, 0, 1);
2499 SUBST (SET_SRC (newpat
),
2500 gen_lowpart (GET_MODE (SET_SRC (newpat
)), ni2dest
));
2501 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2503 if (i2_code_number
>= 0)
2504 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2506 if (insn_code_number
>= 0)
2510 /* Similarly, check for a case where we have a PARALLEL of two independent
2511 SETs but we started with three insns. In this case, we can do the sets
2512 as two separate insns. This case occurs when some SET allows two
2513 other insns to combine, but the destination of that SET is still live. */
2515 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2516 && GET_CODE (newpat
) == PARALLEL
2517 && XVECLEN (newpat
, 0) == 2
2518 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2519 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
2520 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
2521 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2522 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2523 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2524 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2526 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2527 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != USE
2528 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != USE
2529 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2530 XVECEXP (newpat
, 0, 0))
2531 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
2532 XVECEXP (newpat
, 0, 1))
2533 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
2534 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
2536 /* Normally, it doesn't matter which of the two is done first,
2537 but it does if one references cc0. In that case, it has to
2540 if (reg_referenced_p (cc0_rtx
, XVECEXP (newpat
, 0, 0)))
2542 newi2pat
= XVECEXP (newpat
, 0, 0);
2543 newpat
= XVECEXP (newpat
, 0, 1);
2548 newi2pat
= XVECEXP (newpat
, 0, 1);
2549 newpat
= XVECEXP (newpat
, 0, 0);
2552 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2554 if (i2_code_number
>= 0)
2555 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2558 /* If it still isn't recognized, fail and change things back the way they
2560 if ((insn_code_number
< 0
2561 /* Is the result a reasonable ASM_OPERANDS? */
2562 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
2568 /* If we had to change another insn, make sure it is valid also. */
2569 if (undobuf
.other_insn
)
2571 rtx other_pat
= PATTERN (undobuf
.other_insn
);
2572 rtx new_other_notes
;
2575 CLEAR_HARD_REG_SET (newpat_used_regs
);
2577 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
2580 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
2586 PATTERN (undobuf
.other_insn
) = other_pat
;
2588 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2589 are still valid. Then add any non-duplicate notes added by
2590 recog_for_combine. */
2591 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
2593 next
= XEXP (note
, 1);
2595 if (REG_NOTE_KIND (note
) == REG_UNUSED
2596 && ! reg_set_p (XEXP (note
, 0), PATTERN (undobuf
.other_insn
)))
2598 if (REG_P (XEXP (note
, 0)))
2599 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
2601 remove_note (undobuf
.other_insn
, note
);
2605 for (note
= new_other_notes
; note
; note
= XEXP (note
, 1))
2606 if (REG_P (XEXP (note
, 0)))
2607 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
2609 distribute_notes (new_other_notes
, undobuf
.other_insn
,
2610 undobuf
.other_insn
, NULL_RTX
);
2613 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
2614 they are adjacent to each other or not. */
2616 rtx p
= prev_nonnote_insn (i3
);
2617 if (p
&& p
!= i2
&& NONJUMP_INSN_P (p
) && newi2pat
2618 && sets_cc0_p (newi2pat
))
2626 /* Only allow this combination if insn_rtx_costs reports that the
2627 replacement instructions are cheaper than the originals. */
2628 if (!combine_validate_cost (i1
, i2
, i3
, newpat
, newi2pat
))
2634 /* We now know that we can do this combination. Merge the insns and
2635 update the status of registers and LOG_LINKS. */
2643 /* I3 now uses what used to be its destination and which is now
2644 I2's destination. This requires us to do a few adjustments. */
2645 PATTERN (i3
) = newpat
;
2646 adjust_for_new_dest (i3
);
2648 /* We need a LOG_LINK from I3 to I2. But we used to have one,
2651 However, some later insn might be using I2's dest and have
2652 a LOG_LINK pointing at I3. We must remove this link.
2653 The simplest way to remove the link is to point it at I1,
2654 which we know will be a NOTE. */
2656 /* newi2pat is usually a SET here; however, recog_for_combine might
2657 have added some clobbers. */
2658 if (GET_CODE (newi2pat
) == PARALLEL
)
2659 ni2dest
= SET_DEST (XVECEXP (newi2pat
, 0, 0));
2661 ni2dest
= SET_DEST (newi2pat
);
2663 for (insn
= NEXT_INSN (i3
);
2664 insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
2665 || insn
!= BB_HEAD (this_basic_block
->next_bb
));
2666 insn
= NEXT_INSN (insn
))
2668 if (INSN_P (insn
) && reg_referenced_p (ni2dest
, PATTERN (insn
)))
2670 for (link
= LOG_LINKS (insn
); link
;
2671 link
= XEXP (link
, 1))
2672 if (XEXP (link
, 0) == i3
)
2673 XEXP (link
, 0) = i1
;
2681 rtx i3notes
, i2notes
, i1notes
= 0;
2682 rtx i3links
, i2links
, i1links
= 0;
2686 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2688 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
2689 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
2691 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
2693 /* Ensure that we do not have something that should not be shared but
2694 occurs multiple times in the new insns. Check this by first
2695 resetting all the `used' flags and then copying anything is shared. */
2697 reset_used_flags (i3notes
);
2698 reset_used_flags (i2notes
);
2699 reset_used_flags (i1notes
);
2700 reset_used_flags (newpat
);
2701 reset_used_flags (newi2pat
);
2702 if (undobuf
.other_insn
)
2703 reset_used_flags (PATTERN (undobuf
.other_insn
));
2705 i3notes
= copy_rtx_if_shared (i3notes
);
2706 i2notes
= copy_rtx_if_shared (i2notes
);
2707 i1notes
= copy_rtx_if_shared (i1notes
);
2708 newpat
= copy_rtx_if_shared (newpat
);
2709 newi2pat
= copy_rtx_if_shared (newi2pat
);
2710 if (undobuf
.other_insn
)
2711 reset_used_flags (PATTERN (undobuf
.other_insn
));
2713 INSN_CODE (i3
) = insn_code_number
;
2714 PATTERN (i3
) = newpat
;
2716 if (CALL_P (i3
) && CALL_INSN_FUNCTION_USAGE (i3
))
2718 rtx call_usage
= CALL_INSN_FUNCTION_USAGE (i3
);
2720 reset_used_flags (call_usage
);
2721 call_usage
= copy_rtx (call_usage
);
2724 replace_rtx (call_usage
, i2dest
, i2src
);
2727 replace_rtx (call_usage
, i1dest
, i1src
);
2729 CALL_INSN_FUNCTION_USAGE (i3
) = call_usage
;
2732 if (undobuf
.other_insn
)
2733 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
2735 /* We had one special case above where I2 had more than one set and
2736 we replaced a destination of one of those sets with the destination
2737 of I3. In that case, we have to update LOG_LINKS of insns later
2738 in this basic block. Note that this (expensive) case is rare.
2740 Also, in this case, we must pretend that all REG_NOTEs for I2
2741 actually came from I3, so that REG_UNUSED notes from I2 will be
2742 properly handled. */
2744 if (i3_subst_into_i2
)
2746 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
2747 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != USE
2748 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)))
2749 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
2750 && ! find_reg_note (i2
, REG_UNUSED
,
2751 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
2752 for (temp
= NEXT_INSN (i2
);
2753 temp
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
2754 || BB_HEAD (this_basic_block
) != temp
);
2755 temp
= NEXT_INSN (temp
))
2756 if (temp
!= i3
&& INSN_P (temp
))
2757 for (link
= LOG_LINKS (temp
); link
; link
= XEXP (link
, 1))
2758 if (XEXP (link
, 0) == i2
)
2759 XEXP (link
, 0) = i3
;
2764 while (XEXP (link
, 1))
2765 link
= XEXP (link
, 1);
2766 XEXP (link
, 1) = i2notes
;
2780 INSN_CODE (i2
) = i2_code_number
;
2781 PATTERN (i2
) = newi2pat
;
2784 SET_INSN_DELETED (i2
);
2790 SET_INSN_DELETED (i1
);
2793 /* Get death notes for everything that is now used in either I3 or
2794 I2 and used to die in a previous insn. If we built two new
2795 patterns, move from I1 to I2 then I2 to I3 so that we get the
2796 proper movement on registers that I2 modifies. */
2800 move_deaths (newi2pat
, NULL_RTX
, INSN_CUID (i1
), i2
, &midnotes
);
2801 move_deaths (newpat
, newi2pat
, INSN_CUID (i1
), i3
, &midnotes
);
2804 move_deaths (newpat
, NULL_RTX
, i1
? INSN_CUID (i1
) : INSN_CUID (i2
),
2807 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2809 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL_RTX
);
2811 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL_RTX
);
2813 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL_RTX
);
2815 distribute_notes (midnotes
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2817 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2818 know these are REG_UNUSED and want them to go to the desired insn,
2819 so we always pass it as i3. We have not counted the notes in
2820 reg_n_deaths yet, so we need to do so now. */
2822 if (newi2pat
&& new_i2_notes
)
2824 for (temp
= new_i2_notes
; temp
; temp
= XEXP (temp
, 1))
2825 if (REG_P (XEXP (temp
, 0)))
2826 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2828 distribute_notes (new_i2_notes
, i2
, i2
, NULL_RTX
);
2833 for (temp
= new_i3_notes
; temp
; temp
= XEXP (temp
, 1))
2834 if (REG_P (XEXP (temp
, 0)))
2835 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2837 distribute_notes (new_i3_notes
, i3
, i3
, NULL_RTX
);
2840 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2841 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2842 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2843 in that case, it might delete I2. Similarly for I2 and I1.
2844 Show an additional death due to the REG_DEAD note we make here. If
2845 we discard it in distribute_notes, we will decrement it again. */
2849 if (REG_P (i3dest_killed
))
2850 REG_N_DEATHS (REGNO (i3dest_killed
))++;
2852 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
2853 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2855 NULL_RTX
, i2
, NULL_RTX
);
2857 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2859 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2862 if (i2dest_in_i2src
)
2865 REG_N_DEATHS (REGNO (i2dest
))++;
2867 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
2868 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2869 NULL_RTX
, i2
, NULL_RTX
);
2871 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2872 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2875 if (i1dest_in_i1src
)
2878 REG_N_DEATHS (REGNO (i1dest
))++;
2880 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
2881 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
2882 NULL_RTX
, i2
, NULL_RTX
);
2884 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
2885 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2888 distribute_links (i3links
);
2889 distribute_links (i2links
);
2890 distribute_links (i1links
);
2895 rtx i2_insn
= 0, i2_val
= 0, set
;
2897 /* The insn that used to set this register doesn't exist, and
2898 this life of the register may not exist either. See if one of
2899 I3's links points to an insn that sets I2DEST. If it does,
2900 that is now the last known value for I2DEST. If we don't update
2901 this and I2 set the register to a value that depended on its old
2902 contents, we will get confused. If this insn is used, thing
2903 will be set correctly in combine_instructions. */
2905 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2906 if ((set
= single_set (XEXP (link
, 0))) != 0
2907 && rtx_equal_p (i2dest
, SET_DEST (set
)))
2908 i2_insn
= XEXP (link
, 0), i2_val
= SET_SRC (set
);
2910 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
2912 /* If the reg formerly set in I2 died only once and that was in I3,
2913 zero its use count so it won't make `reload' do any work. */
2915 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
2916 && ! i2dest_in_i2src
)
2918 regno
= REGNO (i2dest
);
2919 REG_N_SETS (regno
)--;
2923 if (i1
&& REG_P (i1dest
))
2926 rtx i1_insn
= 0, i1_val
= 0, set
;
2928 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2929 if ((set
= single_set (XEXP (link
, 0))) != 0
2930 && rtx_equal_p (i1dest
, SET_DEST (set
)))
2931 i1_insn
= XEXP (link
, 0), i1_val
= SET_SRC (set
);
2933 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
2935 regno
= REGNO (i1dest
);
2936 if (! added_sets_1
&& ! i1dest_in_i1src
)
2937 REG_N_SETS (regno
)--;
2940 /* Update reg_stat[].nonzero_bits et al for any changes that may have
2941 been made to this insn. The order of
2942 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
2943 can affect nonzero_bits of newpat */
2945 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
2946 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
2948 /* Set new_direct_jump_p if a new return or simple jump instruction
2951 If I3 is now an unconditional jump, ensure that it has a
2952 BARRIER following it since it may have initially been a
2953 conditional jump. It may also be the last nonnote insn. */
2955 if (returnjump_p (i3
) || any_uncondjump_p (i3
))
2957 *new_direct_jump_p
= 1;
2958 mark_jump_label (PATTERN (i3
), i3
, 0);
2960 if ((temp
= next_nonnote_insn (i3
)) == NULL_RTX
2961 || !BARRIER_P (temp
))
2962 emit_barrier_after (i3
);
2965 if (undobuf
.other_insn
!= NULL_RTX
2966 && (returnjump_p (undobuf
.other_insn
)
2967 || any_uncondjump_p (undobuf
.other_insn
)))
2969 *new_direct_jump_p
= 1;
2971 if ((temp
= next_nonnote_insn (undobuf
.other_insn
)) == NULL_RTX
2972 || !BARRIER_P (temp
))
2973 emit_barrier_after (undobuf
.other_insn
);
2976 /* An NOOP jump does not need barrier, but it does need cleaning up
2978 if (GET_CODE (newpat
) == SET
2979 && SET_SRC (newpat
) == pc_rtx
2980 && SET_DEST (newpat
) == pc_rtx
)
2981 *new_direct_jump_p
= 1;
2984 combine_successes
++;
2987 if (added_links_insn
2988 && (newi2pat
== 0 || INSN_CUID (added_links_insn
) < INSN_CUID (i2
))
2989 && INSN_CUID (added_links_insn
) < INSN_CUID (i3
))
2990 return added_links_insn
;
2992 return newi2pat
? i2
: i3
;
2995 /* Undo all the modifications recorded in undobuf. */
3000 struct undo
*undo
, *next
;
3002 for (undo
= undobuf
.undos
; undo
; undo
= next
)
3006 *undo
->where
.i
= undo
->old_contents
.i
;
3008 *undo
->where
.r
= undo
->old_contents
.r
;
3010 undo
->next
= undobuf
.frees
;
3011 undobuf
.frees
= undo
;
3017 /* We've committed to accepting the changes we made. Move all
3018 of the undos to the free list. */
3023 struct undo
*undo
, *next
;
3025 for (undo
= undobuf
.undos
; undo
; undo
= next
)
3028 undo
->next
= undobuf
.frees
;
3029 undobuf
.frees
= undo
;
3035 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
3036 where we have an arithmetic expression and return that point. LOC will
3039 try_combine will call this function to see if an insn can be split into
3043 find_split_point (rtx
*loc
, rtx insn
)
3046 enum rtx_code code
= GET_CODE (x
);
3048 unsigned HOST_WIDE_INT len
= 0;
3049 HOST_WIDE_INT pos
= 0;
3051 rtx inner
= NULL_RTX
;
3053 /* First special-case some codes. */
3057 #ifdef INSN_SCHEDULING
3058 /* If we are making a paradoxical SUBREG invalid, it becomes a split
3060 if (MEM_P (SUBREG_REG (x
)))
3063 return find_split_point (&SUBREG_REG (x
), insn
);
3067 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
3068 using LO_SUM and HIGH. */
3069 if (GET_CODE (XEXP (x
, 0)) == CONST
3070 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
3073 gen_rtx_LO_SUM (Pmode
,
3074 gen_rtx_HIGH (Pmode
, XEXP (x
, 0)),
3076 return &XEXP (XEXP (x
, 0), 0);
3080 /* If we have a PLUS whose second operand is a constant and the
3081 address is not valid, perhaps will can split it up using
3082 the machine-specific way to split large constants. We use
3083 the first pseudo-reg (one of the virtual regs) as a placeholder;
3084 it will not remain in the result. */
3085 if (GET_CODE (XEXP (x
, 0)) == PLUS
3086 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3087 && ! memory_address_p (GET_MODE (x
), XEXP (x
, 0)))
3089 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
3090 rtx seq
= split_insns (gen_rtx_SET (VOIDmode
, reg
, XEXP (x
, 0)),
3093 /* This should have produced two insns, each of which sets our
3094 placeholder. If the source of the second is a valid address,
3095 we can make put both sources together and make a split point
3099 && NEXT_INSN (seq
) != NULL_RTX
3100 && NEXT_INSN (NEXT_INSN (seq
)) == NULL_RTX
3101 && NONJUMP_INSN_P (seq
)
3102 && GET_CODE (PATTERN (seq
)) == SET
3103 && SET_DEST (PATTERN (seq
)) == reg
3104 && ! reg_mentioned_p (reg
,
3105 SET_SRC (PATTERN (seq
)))
3106 && NONJUMP_INSN_P (NEXT_INSN (seq
))
3107 && GET_CODE (PATTERN (NEXT_INSN (seq
))) == SET
3108 && SET_DEST (PATTERN (NEXT_INSN (seq
))) == reg
3109 && memory_address_p (GET_MODE (x
),
3110 SET_SRC (PATTERN (NEXT_INSN (seq
)))))
3112 rtx src1
= SET_SRC (PATTERN (seq
));
3113 rtx src2
= SET_SRC (PATTERN (NEXT_INSN (seq
)));
3115 /* Replace the placeholder in SRC2 with SRC1. If we can
3116 find where in SRC2 it was placed, that can become our
3117 split point and we can replace this address with SRC2.
3118 Just try two obvious places. */
3120 src2
= replace_rtx (src2
, reg
, src1
);
3122 if (XEXP (src2
, 0) == src1
)
3123 split
= &XEXP (src2
, 0);
3124 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
3125 && XEXP (XEXP (src2
, 0), 0) == src1
)
3126 split
= &XEXP (XEXP (src2
, 0), 0);
3130 SUBST (XEXP (x
, 0), src2
);
3135 /* If that didn't work, perhaps the first operand is complex and
3136 needs to be computed separately, so make a split point there.
3137 This will occur on machines that just support REG + CONST
3138 and have a constant moved through some previous computation. */
3140 else if (!OBJECT_P (XEXP (XEXP (x
, 0), 0))
3141 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
3142 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
3143 return &XEXP (XEXP (x
, 0), 0);
3149 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
3150 ZERO_EXTRACT, the most likely reason why this doesn't match is that
3151 we need to put the operand into a register. So split at that
3154 if (SET_DEST (x
) == cc0_rtx
3155 && GET_CODE (SET_SRC (x
)) != COMPARE
3156 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
3157 && !OBJECT_P (SET_SRC (x
))
3158 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
3159 && OBJECT_P (SUBREG_REG (SET_SRC (x
)))))
3160 return &SET_SRC (x
);
3163 /* See if we can split SET_SRC as it stands. */
3164 split
= find_split_point (&SET_SRC (x
), insn
);
3165 if (split
&& split
!= &SET_SRC (x
))
3168 /* See if we can split SET_DEST as it stands. */
3169 split
= find_split_point (&SET_DEST (x
), insn
);
3170 if (split
&& split
!= &SET_DEST (x
))
3173 /* See if this is a bitfield assignment with everything constant. If
3174 so, this is an IOR of an AND, so split it into that. */
3175 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
3176 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)))
3177 <= HOST_BITS_PER_WIDE_INT
)
3178 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
3179 && GET_CODE (XEXP (SET_DEST (x
), 2)) == CONST_INT
3180 && GET_CODE (SET_SRC (x
)) == CONST_INT
3181 && ((INTVAL (XEXP (SET_DEST (x
), 1))
3182 + INTVAL (XEXP (SET_DEST (x
), 2)))
3183 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0))))
3184 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
3186 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
3187 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
3188 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
));
3189 rtx dest
= XEXP (SET_DEST (x
), 0);
3190 enum machine_mode mode
= GET_MODE (dest
);
3191 unsigned HOST_WIDE_INT mask
= ((HOST_WIDE_INT
) 1 << len
) - 1;
3193 if (BITS_BIG_ENDIAN
)
3194 pos
= GET_MODE_BITSIZE (mode
) - len
- pos
;
3198 simplify_gen_binary (IOR
, mode
, dest
, GEN_INT (src
<< pos
)));
3201 rtx negmask
= gen_int_mode (~(mask
<< pos
), mode
);
3203 simplify_gen_binary (IOR
, mode
,
3204 simplify_gen_binary (AND
, mode
,
3206 GEN_INT (src
<< pos
)));
3209 SUBST (SET_DEST (x
), dest
);
3211 split
= find_split_point (&SET_SRC (x
), insn
);
3212 if (split
&& split
!= &SET_SRC (x
))
3216 /* Otherwise, see if this is an operation that we can split into two.
3217 If so, try to split that. */
3218 code
= GET_CODE (SET_SRC (x
));
3223 /* If we are AND'ing with a large constant that is only a single
3224 bit and the result is only being used in a context where we
3225 need to know if it is zero or nonzero, replace it with a bit
3226 extraction. This will avoid the large constant, which might
3227 have taken more than one insn to make. If the constant were
3228 not a valid argument to the AND but took only one insn to make,
3229 this is no worse, but if it took more than one insn, it will
3232 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
3233 && REG_P (XEXP (SET_SRC (x
), 0))
3234 && (pos
= exact_log2 (INTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
3235 && REG_P (SET_DEST (x
))
3236 && (split
= find_single_use (SET_DEST (x
), insn
, (rtx
*) 0)) != 0
3237 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
3238 && XEXP (*split
, 0) == SET_DEST (x
)
3239 && XEXP (*split
, 1) == const0_rtx
)
3241 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
3242 XEXP (SET_SRC (x
), 0),
3243 pos
, NULL_RTX
, 1, 1, 0, 0);
3244 if (extraction
!= 0)
3246 SUBST (SET_SRC (x
), extraction
);
3247 return find_split_point (loc
, insn
);
3253 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3254 is known to be on, this can be converted into a NEG of a shift. */
3255 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
3256 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
3257 && 1 <= (pos
= exact_log2
3258 (nonzero_bits (XEXP (SET_SRC (x
), 0),
3259 GET_MODE (XEXP (SET_SRC (x
), 0))))))
3261 enum machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
3265 gen_rtx_LSHIFTRT (mode
,
3266 XEXP (SET_SRC (x
), 0),
3269 split
= find_split_point (&SET_SRC (x
), insn
);
3270 if (split
&& split
!= &SET_SRC (x
))
3276 inner
= XEXP (SET_SRC (x
), 0);
3278 /* We can't optimize if either mode is a partial integer
3279 mode as we don't know how many bits are significant
3281 if (GET_MODE_CLASS (GET_MODE (inner
)) == MODE_PARTIAL_INT
3282 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
3286 len
= GET_MODE_BITSIZE (GET_MODE (inner
));
3292 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
3293 && GET_CODE (XEXP (SET_SRC (x
), 2)) == CONST_INT
)
3295 inner
= XEXP (SET_SRC (x
), 0);
3296 len
= INTVAL (XEXP (SET_SRC (x
), 1));
3297 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
3299 if (BITS_BIG_ENDIAN
)
3300 pos
= GET_MODE_BITSIZE (GET_MODE (inner
)) - len
- pos
;
3301 unsignedp
= (code
== ZERO_EXTRACT
);
3309 if (len
&& pos
>= 0 && pos
+ len
<= GET_MODE_BITSIZE (GET_MODE (inner
)))
3311 enum machine_mode mode
= GET_MODE (SET_SRC (x
));
3313 /* For unsigned, we have a choice of a shift followed by an
3314 AND or two shifts. Use two shifts for field sizes where the
3315 constant might be too large. We assume here that we can
3316 always at least get 8-bit constants in an AND insn, which is
3317 true for every current RISC. */
3319 if (unsignedp
&& len
<= 8)
3324 (mode
, gen_lowpart (mode
, inner
),
3326 GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1)));
3328 split
= find_split_point (&SET_SRC (x
), insn
);
3329 if (split
&& split
!= &SET_SRC (x
))
3336 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
3337 gen_rtx_ASHIFT (mode
,
3338 gen_lowpart (mode
, inner
),
3339 GEN_INT (GET_MODE_BITSIZE (mode
)
3341 GEN_INT (GET_MODE_BITSIZE (mode
) - len
)));
3343 split
= find_split_point (&SET_SRC (x
), insn
);
3344 if (split
&& split
!= &SET_SRC (x
))
3349 /* See if this is a simple operation with a constant as the second
3350 operand. It might be that this constant is out of range and hence
3351 could be used as a split point. */
3352 if (BINARY_P (SET_SRC (x
))
3353 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
3354 && (OBJECT_P (XEXP (SET_SRC (x
), 0))
3355 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
3356 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x
), 0))))))
3357 return &XEXP (SET_SRC (x
), 1);
3359 /* Finally, see if this is a simple operation with its first operand
3360 not in a register. The operation might require this operand in a
3361 register, so return it as a split point. We can always do this
3362 because if the first operand were another operation, we would have
3363 already found it as a split point. */
3364 if ((BINARY_P (SET_SRC (x
)) || UNARY_P (SET_SRC (x
)))
3365 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
3366 return &XEXP (SET_SRC (x
), 0);
3372 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3373 it is better to write this as (not (ior A B)) so we can split it.
3374 Similarly for IOR. */
3375 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
3378 gen_rtx_NOT (GET_MODE (x
),
3379 gen_rtx_fmt_ee (code
== IOR
? AND
: IOR
,
3381 XEXP (XEXP (x
, 0), 0),
3382 XEXP (XEXP (x
, 1), 0))));
3383 return find_split_point (loc
, insn
);
3386 /* Many RISC machines have a large set of logical insns. If the
3387 second operand is a NOT, put it first so we will try to split the
3388 other operand first. */
3389 if (GET_CODE (XEXP (x
, 1)) == NOT
)
3391 rtx tem
= XEXP (x
, 0);
3392 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3393 SUBST (XEXP (x
, 1), tem
);
3401 /* Otherwise, select our actions depending on our rtx class. */
3402 switch (GET_RTX_CLASS (code
))
3404 case RTX_BITFIELD_OPS
: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3406 split
= find_split_point (&XEXP (x
, 2), insn
);
3409 /* ... fall through ... */
3411 case RTX_COMM_ARITH
:
3413 case RTX_COMM_COMPARE
:
3414 split
= find_split_point (&XEXP (x
, 1), insn
);
3417 /* ... fall through ... */
3419 /* Some machines have (and (shift ...) ...) insns. If X is not
3420 an AND, but XEXP (X, 0) is, use it as our split point. */
3421 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
3422 return &XEXP (x
, 0);
3424 split
= find_split_point (&XEXP (x
, 0), insn
);
3430 /* Otherwise, we don't have a split point. */
3435 /* Throughout X, replace FROM with TO, and return the result.
3436 The result is TO if X is FROM;
3437 otherwise the result is X, but its contents may have been modified.
3438 If they were modified, a record was made in undobuf so that
3439 undo_all will (among other things) return X to its original state.
3441 If the number of changes necessary is too much to record to undo,
3442 the excess changes are not made, so the result is invalid.
3443 The changes already made can still be undone.
3444 undobuf.num_undo is incremented for such changes, so by testing that
3445 the caller can tell whether the result is valid.
3447 `n_occurrences' is incremented each time FROM is replaced.
3449 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
3451 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
3452 by copying if `n_occurrences' is nonzero. */
3455 subst (rtx x
, rtx from
, rtx to
, int in_dest
, int unique_copy
)
3457 enum rtx_code code
= GET_CODE (x
);
3458 enum machine_mode op0_mode
= VOIDmode
;
3463 /* Two expressions are equal if they are identical copies of a shared
3464 RTX or if they are both registers with the same register number
3467 #define COMBINE_RTX_EQUAL_P(X,Y) \
3469 || (REG_P (X) && REG_P (Y) \
3470 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3472 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
3475 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
3478 /* If X and FROM are the same register but different modes, they will
3479 not have been seen as equal above. However, flow.c will make a
3480 LOG_LINKS entry for that case. If we do nothing, we will try to
3481 rerecognize our original insn and, when it succeeds, we will
3482 delete the feeding insn, which is incorrect.
3484 So force this insn not to match in this (rare) case. */
3485 if (! in_dest
&& code
== REG
&& REG_P (from
)
3486 && REGNO (x
) == REGNO (from
))
3487 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
3489 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3490 of which may contain things that can be combined. */
3491 if (code
!= MEM
&& code
!= LO_SUM
&& OBJECT_P (x
))
3494 /* It is possible to have a subexpression appear twice in the insn.
3495 Suppose that FROM is a register that appears within TO.
3496 Then, after that subexpression has been scanned once by `subst',
3497 the second time it is scanned, TO may be found. If we were
3498 to scan TO here, we would find FROM within it and create a
3499 self-referent rtl structure which is completely wrong. */
3500 if (COMBINE_RTX_EQUAL_P (x
, to
))
3503 /* Parallel asm_operands need special attention because all of the
3504 inputs are shared across the arms. Furthermore, unsharing the
3505 rtl results in recognition failures. Failure to handle this case
3506 specially can result in circular rtl.
3508 Solve this by doing a normal pass across the first entry of the
3509 parallel, and only processing the SET_DESTs of the subsequent
3512 if (code
== PARALLEL
3513 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
3514 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
3516 new = subst (XVECEXP (x
, 0, 0), from
, to
, 0, unique_copy
);
3518 /* If this substitution failed, this whole thing fails. */
3519 if (GET_CODE (new) == CLOBBER
3520 && XEXP (new, 0) == const0_rtx
)
3523 SUBST (XVECEXP (x
, 0, 0), new);
3525 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
3527 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
3530 && GET_CODE (dest
) != CC0
3531 && GET_CODE (dest
) != PC
)
3533 new = subst (dest
, from
, to
, 0, unique_copy
);
3535 /* If this substitution failed, this whole thing fails. */
3536 if (GET_CODE (new) == CLOBBER
3537 && XEXP (new, 0) == const0_rtx
)
3540 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new);
3546 len
= GET_RTX_LENGTH (code
);
3547 fmt
= GET_RTX_FORMAT (code
);
3549 /* We don't need to process a SET_DEST that is a register, CC0,
3550 or PC, so set up to skip this common case. All other cases
3551 where we want to suppress replacing something inside a
3552 SET_SRC are handled via the IN_DEST operand. */
3554 && (REG_P (SET_DEST (x
))
3555 || GET_CODE (SET_DEST (x
)) == CC0
3556 || GET_CODE (SET_DEST (x
)) == PC
))
3559 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3562 op0_mode
= GET_MODE (XEXP (x
, 0));
3564 for (i
= 0; i
< len
; i
++)
3569 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3571 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
3573 new = (unique_copy
&& n_occurrences
3574 ? copy_rtx (to
) : to
);
3579 new = subst (XVECEXP (x
, i
, j
), from
, to
, 0,
3582 /* If this substitution failed, this whole thing
3584 if (GET_CODE (new) == CLOBBER
3585 && XEXP (new, 0) == const0_rtx
)
3589 SUBST (XVECEXP (x
, i
, j
), new);
3592 else if (fmt
[i
] == 'e')
3594 /* If this is a register being set, ignore it. */
3598 && (((code
== SUBREG
|| code
== ZERO_EXTRACT
)
3600 || code
== STRICT_LOW_PART
))
3603 else if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
3605 /* In general, don't install a subreg involving two
3606 modes not tieable. It can worsen register
3607 allocation, and can even make invalid reload
3608 insns, since the reg inside may need to be copied
3609 from in the outside mode, and that may be invalid
3610 if it is an fp reg copied in integer mode.
3612 We allow two exceptions to this: It is valid if
3613 it is inside another SUBREG and the mode of that
3614 SUBREG and the mode of the inside of TO is
3615 tieable and it is valid if X is a SET that copies
3618 if (GET_CODE (to
) == SUBREG
3619 && ! MODES_TIEABLE_P (GET_MODE (to
),
3620 GET_MODE (SUBREG_REG (to
)))
3621 && ! (code
== SUBREG
3622 && MODES_TIEABLE_P (GET_MODE (x
),
3623 GET_MODE (SUBREG_REG (to
))))
3625 && ! (code
== SET
&& i
== 1 && XEXP (x
, 0) == cc0_rtx
)
3628 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
3630 #ifdef CANNOT_CHANGE_MODE_CLASS
3633 && REGNO (to
) < FIRST_PSEUDO_REGISTER
3634 && REG_CANNOT_CHANGE_MODE_P (REGNO (to
),
3637 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
3640 new = (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
3644 /* If we are in a SET_DEST, suppress most cases unless we
3645 have gone inside a MEM, in which case we want to
3646 simplify the address. We assume here that things that
3647 are actually part of the destination have their inner
3648 parts in the first expression. This is true for SUBREG,
3649 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3650 things aside from REG and MEM that should appear in a
3652 new = subst (XEXP (x
, i
), from
, to
,
3654 && (code
== SUBREG
|| code
== STRICT_LOW_PART
3655 || code
== ZERO_EXTRACT
))
3657 && i
== 0), unique_copy
);
3659 /* If we found that we will have to reject this combination,
3660 indicate that by returning the CLOBBER ourselves, rather than
3661 an expression containing it. This will speed things up as
3662 well as prevent accidents where two CLOBBERs are considered
3663 to be equal, thus producing an incorrect simplification. */
3665 if (GET_CODE (new) == CLOBBER
&& XEXP (new, 0) == const0_rtx
)
3668 if (GET_CODE (x
) == SUBREG
3669 && (GET_CODE (new) == CONST_INT
3670 || GET_CODE (new) == CONST_DOUBLE
))
3672 enum machine_mode mode
= GET_MODE (x
);
3674 x
= simplify_subreg (GET_MODE (x
), new,
3675 GET_MODE (SUBREG_REG (x
)),
3678 x
= gen_rtx_CLOBBER (mode
, const0_rtx
);
3680 else if (GET_CODE (new) == CONST_INT
3681 && GET_CODE (x
) == ZERO_EXTEND
)
3683 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
3684 new, GET_MODE (XEXP (x
, 0)));
3688 SUBST (XEXP (x
, i
), new);
3693 /* Try to simplify X. If the simplification changed the code, it is likely
3694 that further simplification will help, so loop, but limit the number
3695 of repetitions that will be performed. */
3697 for (i
= 0; i
< 4; i
++)
3699 /* If X is sufficiently simple, don't bother trying to do anything
3701 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
3702 x
= combine_simplify_rtx (x
, op0_mode
, in_dest
);
3704 if (GET_CODE (x
) == code
)
3707 code
= GET_CODE (x
);
3709 /* We no longer know the original mode of operand 0 since we
3710 have changed the form of X) */
3711 op0_mode
= VOIDmode
;
3717 /* Simplify X, a piece of RTL. We just operate on the expression at the
3718 outer level; call `subst' to simplify recursively. Return the new
3721 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
3722 if we are inside a SET_DEST. */
3725 combine_simplify_rtx (rtx x
, enum machine_mode op0_mode
, int in_dest
)
3727 enum rtx_code code
= GET_CODE (x
);
3728 enum machine_mode mode
= GET_MODE (x
);
3733 /* If this is a commutative operation, put a constant last and a complex
3734 expression first. We don't need to do this for comparisons here. */
3735 if (COMMUTATIVE_ARITH_P (x
)
3736 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
3739 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3740 SUBST (XEXP (x
, 1), temp
);
3743 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3744 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3745 things. Check for cases where both arms are testing the same
3748 Don't do anything if all operands are very simple. */
3751 && ((!OBJECT_P (XEXP (x
, 0))
3752 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3753 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))
3754 || (!OBJECT_P (XEXP (x
, 1))
3755 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
3756 && OBJECT_P (SUBREG_REG (XEXP (x
, 1)))))))
3758 && (!OBJECT_P (XEXP (x
, 0))
3759 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3760 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))))
3762 rtx cond
, true_rtx
, false_rtx
;
3764 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
3766 /* If everything is a comparison, what we have is highly unlikely
3767 to be simpler, so don't use it. */
3768 && ! (COMPARISON_P (x
)
3769 && (COMPARISON_P (true_rtx
) || COMPARISON_P (false_rtx
))))
3771 rtx cop1
= const0_rtx
;
3772 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
3774 if (cond_code
== NE
&& COMPARISON_P (cond
))
3777 /* Simplify the alternative arms; this may collapse the true and
3778 false arms to store-flag values. Be careful to use copy_rtx
3779 here since true_rtx or false_rtx might share RTL with x as a
3780 result of the if_then_else_cond call above. */
3781 true_rtx
= subst (copy_rtx (true_rtx
), pc_rtx
, pc_rtx
, 0, 0);
3782 false_rtx
= subst (copy_rtx (false_rtx
), pc_rtx
, pc_rtx
, 0, 0);
3784 /* If true_rtx and false_rtx are not general_operands, an if_then_else
3785 is unlikely to be simpler. */
3786 if (general_operand (true_rtx
, VOIDmode
)
3787 && general_operand (false_rtx
, VOIDmode
))
3789 enum rtx_code reversed
;
3791 /* Restarting if we generate a store-flag expression will cause
3792 us to loop. Just drop through in this case. */
3794 /* If the result values are STORE_FLAG_VALUE and zero, we can
3795 just make the comparison operation. */
3796 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
3797 x
= simplify_gen_relational (cond_code
, mode
, VOIDmode
,
3799 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
3800 && ((reversed
= reversed_comparison_code_parts
3801 (cond_code
, cond
, cop1
, NULL
))
3803 x
= simplify_gen_relational (reversed
, mode
, VOIDmode
,
3806 /* Likewise, we can make the negate of a comparison operation
3807 if the result values are - STORE_FLAG_VALUE and zero. */
3808 else if (GET_CODE (true_rtx
) == CONST_INT
3809 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
3810 && false_rtx
== const0_rtx
)
3811 x
= simplify_gen_unary (NEG
, mode
,
3812 simplify_gen_relational (cond_code
,
3816 else if (GET_CODE (false_rtx
) == CONST_INT
3817 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
3818 && true_rtx
== const0_rtx
3819 && ((reversed
= reversed_comparison_code_parts
3820 (cond_code
, cond
, cop1
, NULL
))
3822 x
= simplify_gen_unary (NEG
, mode
,
3823 simplify_gen_relational (reversed
,
3828 return gen_rtx_IF_THEN_ELSE (mode
,
3829 simplify_gen_relational (cond_code
,
3834 true_rtx
, false_rtx
);
3836 code
= GET_CODE (x
);
3837 op0_mode
= VOIDmode
;
3842 /* Try to fold this expression in case we have constants that weren't
3845 switch (GET_RTX_CLASS (code
))
3848 if (op0_mode
== VOIDmode
)
3849 op0_mode
= GET_MODE (XEXP (x
, 0));
3850 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
3853 case RTX_COMM_COMPARE
:
3855 enum machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
3856 if (cmp_mode
== VOIDmode
)
3858 cmp_mode
= GET_MODE (XEXP (x
, 1));
3859 if (cmp_mode
== VOIDmode
)
3860 cmp_mode
= op0_mode
;
3862 temp
= simplify_relational_operation (code
, mode
, cmp_mode
,
3863 XEXP (x
, 0), XEXP (x
, 1));
3866 case RTX_COMM_ARITH
:
3868 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
3870 case RTX_BITFIELD_OPS
:
3872 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
3873 XEXP (x
, 1), XEXP (x
, 2));
3882 code
= GET_CODE (temp
);
3883 op0_mode
= VOIDmode
;
3884 mode
= GET_MODE (temp
);
3887 /* First see if we can apply the inverse distributive law. */
3888 if (code
== PLUS
|| code
== MINUS
3889 || code
== AND
|| code
== IOR
|| code
== XOR
)
3891 x
= apply_distributive_law (x
);
3892 code
= GET_CODE (x
);
3893 op0_mode
= VOIDmode
;
3896 /* If CODE is an associative operation not otherwise handled, see if we
3897 can associate some operands. This can win if they are constants or
3898 if they are logically related (i.e. (a & b) & a). */
3899 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
|| code
== DIV
3900 || code
== AND
|| code
== IOR
|| code
== XOR
3901 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
3902 && ((INTEGRAL_MODE_P (mode
) && code
!= DIV
)
3903 || (flag_unsafe_math_optimizations
&& FLOAT_MODE_P (mode
))))
3905 if (GET_CODE (XEXP (x
, 0)) == code
)
3907 rtx other
= XEXP (XEXP (x
, 0), 0);
3908 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
3909 rtx inner_op1
= XEXP (x
, 1);
3912 /* Make sure we pass the constant operand if any as the second
3913 one if this is a commutative operation. */
3914 if (CONSTANT_P (inner_op0
) && COMMUTATIVE_ARITH_P (x
))
3916 rtx tem
= inner_op0
;
3917 inner_op0
= inner_op1
;
3920 inner
= simplify_binary_operation (code
== MINUS
? PLUS
3921 : code
== DIV
? MULT
3923 mode
, inner_op0
, inner_op1
);
3925 /* For commutative operations, try the other pair if that one
3927 if (inner
== 0 && COMMUTATIVE_ARITH_P (x
))
3929 other
= XEXP (XEXP (x
, 0), 1);
3930 inner
= simplify_binary_operation (code
, mode
,
3931 XEXP (XEXP (x
, 0), 0),
3936 return simplify_gen_binary (code
, mode
, other
, inner
);
3940 /* A little bit of algebraic simplification here. */
3944 /* Ensure that our address has any ASHIFTs converted to MULT in case
3945 address-recognizing predicates are called later. */
3946 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
3947 SUBST (XEXP (x
, 0), temp
);
3951 if (op0_mode
== VOIDmode
)
3952 op0_mode
= GET_MODE (SUBREG_REG (x
));
3954 /* See if this can be moved to simplify_subreg. */
3955 if (CONSTANT_P (SUBREG_REG (x
))
3956 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
3957 /* Don't call gen_lowpart if the inner mode
3958 is VOIDmode and we cannot simplify it, as SUBREG without
3959 inner mode is invalid. */
3960 && (GET_MODE (SUBREG_REG (x
)) != VOIDmode
3961 || gen_lowpart_common (mode
, SUBREG_REG (x
))))
3962 return gen_lowpart (mode
, SUBREG_REG (x
));
3964 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_CC
)
3968 temp
= simplify_subreg (mode
, SUBREG_REG (x
), op0_mode
,
3974 /* Don't change the mode of the MEM if that would change the meaning
3976 if (MEM_P (SUBREG_REG (x
))
3977 && (MEM_VOLATILE_P (SUBREG_REG (x
))
3978 || mode_dependent_address_p (XEXP (SUBREG_REG (x
), 0))))
3979 return gen_rtx_CLOBBER (mode
, const0_rtx
);
3981 /* Note that we cannot do any narrowing for non-constants since
3982 we might have been counting on using the fact that some bits were
3983 zero. We now do this in the SET. */
3988 if (GET_CODE (XEXP (x
, 0)) == SUBREG
3989 && subreg_lowpart_p (XEXP (x
, 0))
3990 && (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0)))
3991 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x
, 0)))))
3992 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == ASHIFT
3993 && XEXP (SUBREG_REG (XEXP (x
, 0)), 0) == const1_rtx
)
3995 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (XEXP (x
, 0)));
3997 x
= gen_rtx_ROTATE (inner_mode
,
3998 simplify_gen_unary (NOT
, inner_mode
, const1_rtx
,
4000 XEXP (SUBREG_REG (XEXP (x
, 0)), 1));
4001 return gen_lowpart (mode
, x
);
4004 /* Apply De Morgan's laws to reduce number of patterns for machines
4005 with negating logical insns (and-not, nand, etc.). If result has
4006 only one NOT, put it first, since that is how the patterns are
4009 if (GET_CODE (XEXP (x
, 0)) == IOR
|| GET_CODE (XEXP (x
, 0)) == AND
)
4011 rtx in1
= XEXP (XEXP (x
, 0), 0), in2
= XEXP (XEXP (x
, 0), 1);
4012 enum machine_mode op_mode
;
4014 op_mode
= GET_MODE (in1
);
4015 in1
= simplify_gen_unary (NOT
, op_mode
, in1
, op_mode
);
4017 op_mode
= GET_MODE (in2
);
4018 if (op_mode
== VOIDmode
)
4020 in2
= simplify_gen_unary (NOT
, op_mode
, in2
, op_mode
);
4022 if (GET_CODE (in2
) == NOT
&& GET_CODE (in1
) != NOT
)
4025 in2
= in1
; in1
= tem
;
4028 return gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)) == IOR
? AND
: IOR
,
4034 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
4035 if (GET_CODE (XEXP (x
, 0)) == XOR
4036 && XEXP (XEXP (x
, 0), 1) == const1_rtx
4037 && nonzero_bits (XEXP (XEXP (x
, 0), 0), mode
) == 1)
4038 return simplify_gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0),
4041 temp
= expand_compound_operation (XEXP (x
, 0));
4043 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4044 replaced by (lshiftrt X C). This will convert
4045 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
4047 if (GET_CODE (temp
) == ASHIFTRT
4048 && GET_CODE (XEXP (temp
, 1)) == CONST_INT
4049 && INTVAL (XEXP (temp
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
4050 return simplify_shift_const (temp
, LSHIFTRT
, mode
, XEXP (temp
, 0),
4051 INTVAL (XEXP (temp
, 1)));
4053 /* If X has only a single bit that might be nonzero, say, bit I, convert
4054 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4055 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
4056 (sign_extract X 1 Y). But only do this if TEMP isn't a register
4057 or a SUBREG of one since we'd be making the expression more
4058 complex if it was just a register. */
4061 && ! (GET_CODE (temp
) == SUBREG
4062 && REG_P (SUBREG_REG (temp
)))
4063 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
4065 rtx temp1
= simplify_shift_const
4066 (NULL_RTX
, ASHIFTRT
, mode
,
4067 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
4068 GET_MODE_BITSIZE (mode
) - 1 - i
),
4069 GET_MODE_BITSIZE (mode
) - 1 - i
);
4071 /* If all we did was surround TEMP with the two shifts, we
4072 haven't improved anything, so don't use it. Otherwise,
4073 we are better off with TEMP1. */
4074 if (GET_CODE (temp1
) != ASHIFTRT
4075 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
4076 || XEXP (XEXP (temp1
, 0), 0) != temp
)
4082 /* We can't handle truncation to a partial integer mode here
4083 because we don't know the real bitsize of the partial
4085 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
4088 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4089 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
4090 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))))
4092 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
4093 GET_MODE_MASK (mode
), NULL_RTX
, 0));
4095 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
4096 if ((GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
4097 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4098 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
4099 return XEXP (XEXP (x
, 0), 0);
4101 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
4102 (OP:SI foo:SI) if OP is NEG or ABS. */
4103 if ((GET_CODE (XEXP (x
, 0)) == ABS
4104 || GET_CODE (XEXP (x
, 0)) == NEG
)
4105 && (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SIGN_EXTEND
4106 || GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
)
4107 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
4108 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
4109 XEXP (XEXP (XEXP (x
, 0), 0), 0), mode
);
4111 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
4113 if (GET_CODE (XEXP (x
, 0)) == SUBREG
4114 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == TRUNCATE
4115 && subreg_lowpart_p (XEXP (x
, 0)))
4116 return SUBREG_REG (XEXP (x
, 0));
4118 /* If we know that the value is already truncated, we can
4119 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
4120 is nonzero for the corresponding modes. But don't do this
4121 for an (LSHIFTRT (MULT ...)) since this will cause problems
4122 with the umulXi3_highpart patterns. */
4123 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
4124 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
4125 && num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
4126 >= (unsigned int) (GET_MODE_BITSIZE (mode
) + 1)
4127 && ! (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4128 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
))
4129 return gen_lowpart (mode
, XEXP (x
, 0));
4131 /* A truncate of a comparison can be replaced with a subreg if
4132 STORE_FLAG_VALUE permits. This is like the previous test,
4133 but it works even if the comparison is done in a mode larger
4134 than HOST_BITS_PER_WIDE_INT. */
4135 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4136 && COMPARISON_P (XEXP (x
, 0))
4137 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0)
4138 return gen_lowpart (mode
, XEXP (x
, 0));
4140 /* Similarly, a truncate of a register whose value is a
4141 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4143 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4144 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
4145 && (temp
= get_last_value (XEXP (x
, 0)))
4146 && COMPARISON_P (temp
))
4147 return gen_lowpart (mode
, XEXP (x
, 0));
4151 case FLOAT_TRUNCATE
:
4152 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4153 if (GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
4154 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
4155 return XEXP (XEXP (x
, 0), 0);
4157 /* (float_truncate:SF (float_truncate:DF foo:XF))
4158 = (float_truncate:SF foo:XF).
4159 This may eliminate double rounding, so it is unsafe.
4161 (float_truncate:SF (float_extend:XF foo:DF))
4162 = (float_truncate:SF foo:DF).
4164 (float_truncate:DF (float_extend:XF foo:SF))
4165 = (float_extend:SF foo:DF). */
4166 if ((GET_CODE (XEXP (x
, 0)) == FLOAT_TRUNCATE
4167 && flag_unsafe_math_optimizations
)
4168 || GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
)
4169 return simplify_gen_unary (GET_MODE_SIZE (GET_MODE (XEXP (XEXP (x
, 0),
4171 > GET_MODE_SIZE (mode
)
4172 ? FLOAT_TRUNCATE
: FLOAT_EXTEND
,
4174 XEXP (XEXP (x
, 0), 0), mode
);
4176 /* (float_truncate (float x)) is (float x) */
4177 if (GET_CODE (XEXP (x
, 0)) == FLOAT
4178 && (flag_unsafe_math_optimizations
4179 || ((unsigned)significand_size (GET_MODE (XEXP (x
, 0)))
4180 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x
, 0), 0)))
4181 - num_sign_bit_copies (XEXP (XEXP (x
, 0), 0),
4182 GET_MODE (XEXP (XEXP (x
, 0), 0)))))))
4183 return simplify_gen_unary (FLOAT
, mode
,
4184 XEXP (XEXP (x
, 0), 0),
4185 GET_MODE (XEXP (XEXP (x
, 0), 0)));
4187 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4188 (OP:SF foo:SF) if OP is NEG or ABS. */
4189 if ((GET_CODE (XEXP (x
, 0)) == ABS
4190 || GET_CODE (XEXP (x
, 0)) == NEG
)
4191 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == FLOAT_EXTEND
4192 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
4193 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
4194 XEXP (XEXP (XEXP (x
, 0), 0), 0), mode
);
4196 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4197 is (float_truncate:SF x). */
4198 if (GET_CODE (XEXP (x
, 0)) == SUBREG
4199 && subreg_lowpart_p (XEXP (x
, 0))
4200 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == FLOAT_TRUNCATE
)
4201 return SUBREG_REG (XEXP (x
, 0));
4204 /* (float_extend (float_extend x)) is (float_extend x)
4206 (float_extend (float x)) is (float x) assuming that double
4207 rounding can't happen.
4209 if (GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
4210 || (GET_CODE (XEXP (x
, 0)) == FLOAT
4211 && ((unsigned)significand_size (GET_MODE (XEXP (x
, 0)))
4212 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x
, 0), 0)))
4213 - num_sign_bit_copies (XEXP (XEXP (x
, 0), 0),
4214 GET_MODE (XEXP (XEXP (x
, 0), 0)))))))
4215 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
4216 XEXP (XEXP (x
, 0), 0),
4217 GET_MODE (XEXP (XEXP (x
, 0), 0)));
4222 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4223 using cc0, in which case we want to leave it as a COMPARE
4224 so we can distinguish it from a register-register-copy. */
4225 if (XEXP (x
, 1) == const0_rtx
)
4228 /* x - 0 is the same as x unless x's mode has signed zeros and
4229 allows rounding towards -infinity. Under those conditions,
4231 if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x
, 0)))
4232 && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x
, 0))))
4233 && XEXP (x
, 1) == CONST0_RTX (GET_MODE (XEXP (x
, 0))))
4239 /* (const (const X)) can become (const X). Do it this way rather than
4240 returning the inner CONST since CONST can be shared with a
4242 if (GET_CODE (XEXP (x
, 0)) == CONST
)
4243 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4248 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4249 can add in an offset. find_split_point will split this address up
4250 again if it doesn't match. */
4251 if (GET_CODE (XEXP (x
, 0)) == HIGH
4252 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
4258 /* Canonicalize (plus (mult (neg B) C) A) to (minus A (mult B C)).
4260 if (GET_CODE (XEXP (x
, 0)) == MULT
4261 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == NEG
)
4265 in1
= XEXP (XEXP (XEXP (x
, 0), 0), 0);
4266 in2
= XEXP (XEXP (x
, 0), 1);
4267 return simplify_gen_binary (MINUS
, mode
, XEXP (x
, 1),
4268 simplify_gen_binary (MULT
, mode
,
4272 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4273 outermost. That's because that's the way indexed addresses are
4274 supposed to appear. This code used to check many more cases, but
4275 they are now checked elsewhere. */
4276 if (GET_CODE (XEXP (x
, 0)) == PLUS
4277 && CONSTANT_ADDRESS_P (XEXP (XEXP (x
, 0), 1)))
4278 return simplify_gen_binary (PLUS
, mode
,
4279 simplify_gen_binary (PLUS
, mode
,
4280 XEXP (XEXP (x
, 0), 0),
4282 XEXP (XEXP (x
, 0), 1));
4284 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4285 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4286 bit-field and can be replaced by either a sign_extend or a
4287 sign_extract. The `and' may be a zero_extend and the two
4288 <c>, -<c> constants may be reversed. */
4289 if (GET_CODE (XEXP (x
, 0)) == XOR
4290 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4291 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4292 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
4293 && ((i
= exact_log2 (INTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
4294 || (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
4295 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4296 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
4297 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
4298 && (INTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
4299 == ((HOST_WIDE_INT
) 1 << (i
+ 1)) - 1))
4300 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
4301 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
4302 == (unsigned int) i
+ 1))))
4303 return simplify_shift_const
4304 (NULL_RTX
, ASHIFTRT
, mode
,
4305 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4306 XEXP (XEXP (XEXP (x
, 0), 0), 0),
4307 GET_MODE_BITSIZE (mode
) - (i
+ 1)),
4308 GET_MODE_BITSIZE (mode
) - (i
+ 1));
4310 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4311 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4312 is 1. This produces better code than the alternative immediately
4314 if (COMPARISON_P (XEXP (x
, 0))
4315 && ((STORE_FLAG_VALUE
== -1 && XEXP (x
, 1) == const1_rtx
)
4316 || (STORE_FLAG_VALUE
== 1 && XEXP (x
, 1) == constm1_rtx
))
4317 && (reversed
= reversed_comparison (XEXP (x
, 0), mode
,
4318 XEXP (XEXP (x
, 0), 0),
4319 XEXP (XEXP (x
, 0), 1))))
4321 simplify_gen_unary (NEG
, mode
, reversed
, mode
);
4323 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4324 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4325 the bitsize of the mode - 1. This allows simplification of
4326 "a = (b & 8) == 0;" */
4327 if (XEXP (x
, 1) == constm1_rtx
4328 && !REG_P (XEXP (x
, 0))
4329 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
4330 && REG_P (SUBREG_REG (XEXP (x
, 0))))
4331 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
4332 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
4333 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4334 gen_rtx_XOR (mode
, XEXP (x
, 0), const1_rtx
),
4335 GET_MODE_BITSIZE (mode
) - 1),
4336 GET_MODE_BITSIZE (mode
) - 1);
4338 /* If we are adding two things that have no bits in common, convert
4339 the addition into an IOR. This will often be further simplified,
4340 for example in cases like ((a & 1) + (a & 2)), which can
4343 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4344 && (nonzero_bits (XEXP (x
, 0), mode
)
4345 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
4347 /* Try to simplify the expression further. */
4348 rtx tor
= simplify_gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
4349 temp
= combine_simplify_rtx (tor
, mode
, in_dest
);
4351 /* If we could, great. If not, do not go ahead with the IOR
4352 replacement, since PLUS appears in many special purpose
4353 address arithmetic instructions. */
4354 if (GET_CODE (temp
) != CLOBBER
&& temp
!= tor
)
4360 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4361 by reversing the comparison code if valid. */
4362 if (STORE_FLAG_VALUE
== 1
4363 && XEXP (x
, 0) == const1_rtx
4364 && COMPARISON_P (XEXP (x
, 1))
4365 && (reversed
= reversed_comparison (XEXP (x
, 1), mode
,
4366 XEXP (XEXP (x
, 1), 0),
4367 XEXP (XEXP (x
, 1), 1))))
4370 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4371 (and <foo> (const_int pow2-1)) */
4372 if (GET_CODE (XEXP (x
, 1)) == AND
4373 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
4374 && exact_log2 (-INTVAL (XEXP (XEXP (x
, 1), 1))) >= 0
4375 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
4376 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
4377 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
4379 /* Canonicalize (minus A (mult (neg B) C)) to (plus (mult B C) A).
4381 if (GET_CODE (XEXP (x
, 1)) == MULT
4382 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == NEG
)
4386 in1
= XEXP (XEXP (XEXP (x
, 1), 0), 0);
4387 in2
= XEXP (XEXP (x
, 1), 1);
4388 return simplify_gen_binary (PLUS
, mode
,
4389 simplify_gen_binary (MULT
, mode
,
4394 /* Canonicalize (minus (neg A) (mult B C)) to
4395 (minus (mult (neg B) C) A). */
4396 if (GET_CODE (XEXP (x
, 1)) == MULT
4397 && GET_CODE (XEXP (x
, 0)) == NEG
)
4401 in1
= simplify_gen_unary (NEG
, mode
, XEXP (XEXP (x
, 1), 0), mode
);
4402 in2
= XEXP (XEXP (x
, 1), 1);
4403 return simplify_gen_binary (MINUS
, mode
,
4404 simplify_gen_binary (MULT
, mode
,
4406 XEXP (XEXP (x
, 0), 0));
4409 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4411 if (GET_CODE (XEXP (x
, 1)) == PLUS
&& INTEGRAL_MODE_P (mode
))
4412 return simplify_gen_binary (MINUS
, mode
,
4413 simplify_gen_binary (MINUS
, mode
,
4415 XEXP (XEXP (x
, 1), 0)),
4416 XEXP (XEXP (x
, 1), 1));
4420 /* If we have (mult (plus A B) C), apply the distributive law and then
4421 the inverse distributive law to see if things simplify. This
4422 occurs mostly in addresses, often when unrolling loops. */
4424 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
4426 rtx result
= distribute_and_simplify_rtx (x
, 0);
4431 /* Try simplify a*(b/c) as (a*b)/c. */
4432 if (FLOAT_MODE_P (mode
) && flag_unsafe_math_optimizations
4433 && GET_CODE (XEXP (x
, 0)) == DIV
)
4435 rtx tem
= simplify_binary_operation (MULT
, mode
,
4436 XEXP (XEXP (x
, 0), 0),
4439 return simplify_gen_binary (DIV
, mode
, tem
, XEXP (XEXP (x
, 0), 1));
4444 /* If this is a divide by a power of two, treat it as a shift if
4445 its first operand is a shift. */
4446 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
4447 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0
4448 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
4449 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4450 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
4451 || GET_CODE (XEXP (x
, 0)) == ROTATE
4452 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
4453 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
4457 case GT
: case GTU
: case GE
: case GEU
:
4458 case LT
: case LTU
: case LE
: case LEU
:
4459 case UNEQ
: case LTGT
:
4460 case UNGT
: case UNGE
:
4461 case UNLT
: case UNLE
:
4462 case UNORDERED
: case ORDERED
:
4463 /* If the first operand is a condition code, we can't do anything
4465 if (GET_CODE (XEXP (x
, 0)) == COMPARE
4466 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
4467 && ! CC0_P (XEXP (x
, 0))))
4469 rtx op0
= XEXP (x
, 0);
4470 rtx op1
= XEXP (x
, 1);
4471 enum rtx_code new_code
;
4473 if (GET_CODE (op0
) == COMPARE
)
4474 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
4476 /* Simplify our comparison, if possible. */
4477 new_code
= simplify_comparison (code
, &op0
, &op1
);
4479 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4480 if only the low-order bit is possibly nonzero in X (such as when
4481 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4482 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4483 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4486 Remove any ZERO_EXTRACT we made when thinking this was a
4487 comparison. It may now be simpler to use, e.g., an AND. If a
4488 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4489 the call to make_compound_operation in the SET case. */
4491 if (STORE_FLAG_VALUE
== 1
4492 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4493 && op1
== const0_rtx
4494 && mode
== GET_MODE (op0
)
4495 && nonzero_bits (op0
, mode
) == 1)
4496 return gen_lowpart (mode
,
4497 expand_compound_operation (op0
));
4499 else if (STORE_FLAG_VALUE
== 1
4500 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4501 && op1
== const0_rtx
4502 && mode
== GET_MODE (op0
)
4503 && (num_sign_bit_copies (op0
, mode
)
4504 == GET_MODE_BITSIZE (mode
)))
4506 op0
= expand_compound_operation (op0
);
4507 return simplify_gen_unary (NEG
, mode
,
4508 gen_lowpart (mode
, op0
),
4512 else if (STORE_FLAG_VALUE
== 1
4513 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4514 && op1
== const0_rtx
4515 && mode
== GET_MODE (op0
)
4516 && nonzero_bits (op0
, mode
) == 1)
4518 op0
= expand_compound_operation (op0
);
4519 return simplify_gen_binary (XOR
, mode
,
4520 gen_lowpart (mode
, op0
),
4524 else if (STORE_FLAG_VALUE
== 1
4525 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4526 && op1
== const0_rtx
4527 && mode
== GET_MODE (op0
)
4528 && (num_sign_bit_copies (op0
, mode
)
4529 == GET_MODE_BITSIZE (mode
)))
4531 op0
= expand_compound_operation (op0
);
4532 return plus_constant (gen_lowpart (mode
, op0
), 1);
4535 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4537 if (STORE_FLAG_VALUE
== -1
4538 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4539 && op1
== const0_rtx
4540 && (num_sign_bit_copies (op0
, mode
)
4541 == GET_MODE_BITSIZE (mode
)))
4542 return gen_lowpart (mode
,
4543 expand_compound_operation (op0
));
4545 else if (STORE_FLAG_VALUE
== -1
4546 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4547 && op1
== const0_rtx
4548 && mode
== GET_MODE (op0
)
4549 && nonzero_bits (op0
, mode
) == 1)
4551 op0
= expand_compound_operation (op0
);
4552 return simplify_gen_unary (NEG
, mode
,
4553 gen_lowpart (mode
, op0
),
4557 else if (STORE_FLAG_VALUE
== -1
4558 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4559 && op1
== const0_rtx
4560 && mode
== GET_MODE (op0
)
4561 && (num_sign_bit_copies (op0
, mode
)
4562 == GET_MODE_BITSIZE (mode
)))
4564 op0
= expand_compound_operation (op0
);
4565 return simplify_gen_unary (NOT
, mode
,
4566 gen_lowpart (mode
, op0
),
4570 /* If X is 0/1, (eq X 0) is X-1. */
4571 else if (STORE_FLAG_VALUE
== -1
4572 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4573 && op1
== const0_rtx
4574 && mode
== GET_MODE (op0
)
4575 && nonzero_bits (op0
, mode
) == 1)
4577 op0
= expand_compound_operation (op0
);
4578 return plus_constant (gen_lowpart (mode
, op0
), -1);
4581 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4582 one bit that might be nonzero, we can convert (ne x 0) to
4583 (ashift x c) where C puts the bit in the sign bit. Remove any
4584 AND with STORE_FLAG_VALUE when we are done, since we are only
4585 going to test the sign bit. */
4586 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4587 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4588 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
4589 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
4590 && op1
== const0_rtx
4591 && mode
== GET_MODE (op0
)
4592 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
4594 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4595 expand_compound_operation (op0
),
4596 GET_MODE_BITSIZE (mode
) - 1 - i
);
4597 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
4603 /* If the code changed, return a whole new comparison. */
4604 if (new_code
!= code
)
4605 return gen_rtx_fmt_ee (new_code
, mode
, op0
, op1
);
4607 /* Otherwise, keep this operation, but maybe change its operands.
4608 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4609 SUBST (XEXP (x
, 0), op0
);
4610 SUBST (XEXP (x
, 1), op1
);
4615 return simplify_if_then_else (x
);
4621 /* If we are processing SET_DEST, we are done. */
4625 return expand_compound_operation (x
);
4628 return simplify_set (x
);
4633 return simplify_logical (x
);
4636 /* (abs (neg <foo>)) -> (abs <foo>) */
4637 if (GET_CODE (XEXP (x
, 0)) == NEG
)
4638 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4640 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4642 if (GET_MODE (XEXP (x
, 0)) == VOIDmode
)
4645 /* If operand is something known to be positive, ignore the ABS. */
4646 if (GET_CODE (XEXP (x
, 0)) == FFS
|| GET_CODE (XEXP (x
, 0)) == ABS
4647 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
4648 <= HOST_BITS_PER_WIDE_INT
)
4649 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
4650 & ((HOST_WIDE_INT
) 1
4651 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1)))
4655 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4656 if (num_sign_bit_copies (XEXP (x
, 0), mode
) == GET_MODE_BITSIZE (mode
))
4657 return gen_rtx_NEG (mode
, XEXP (x
, 0));
4662 /* (ffs (*_extend <X>)) = (ffs <X>) */
4663 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
4664 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4665 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4670 /* (pop* (zero_extend <X>)) = (pop* <X>) */
4671 if (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4672 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4676 /* (float (sign_extend <X>)) = (float <X>). */
4677 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
4678 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4686 /* If this is a shift by a constant amount, simplify it. */
4687 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4688 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
4689 INTVAL (XEXP (x
, 1)));
4691 else if (SHIFT_COUNT_TRUNCATED
&& !REG_P (XEXP (x
, 1)))
4693 force_to_mode (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)),
4695 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
4702 rtx op0
= XEXP (x
, 0);
4703 rtx op1
= XEXP (x
, 1);
4706 gcc_assert (GET_CODE (op1
) == PARALLEL
);
4707 len
= XVECLEN (op1
, 0);
4709 && GET_CODE (XVECEXP (op1
, 0, 0)) == CONST_INT
4710 && GET_CODE (op0
) == VEC_CONCAT
)
4712 int offset
= INTVAL (XVECEXP (op1
, 0, 0)) * GET_MODE_SIZE (GET_MODE (x
));
4714 /* Try to find the element in the VEC_CONCAT. */
4717 if (GET_MODE (op0
) == GET_MODE (x
))
4719 if (GET_CODE (op0
) == VEC_CONCAT
)
4721 HOST_WIDE_INT op0_size
= GET_MODE_SIZE (GET_MODE (XEXP (op0
, 0)));
4722 if (offset
< op0_size
)
4723 op0
= XEXP (op0
, 0);
4727 op0
= XEXP (op0
, 1);
4745 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4748 simplify_if_then_else (rtx x
)
4750 enum machine_mode mode
= GET_MODE (x
);
4751 rtx cond
= XEXP (x
, 0);
4752 rtx true_rtx
= XEXP (x
, 1);
4753 rtx false_rtx
= XEXP (x
, 2);
4754 enum rtx_code true_code
= GET_CODE (cond
);
4755 int comparison_p
= COMPARISON_P (cond
);
4758 enum rtx_code false_code
;
4761 /* Simplify storing of the truth value. */
4762 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
4763 return simplify_gen_relational (true_code
, mode
, VOIDmode
,
4764 XEXP (cond
, 0), XEXP (cond
, 1));
4766 /* Also when the truth value has to be reversed. */
4768 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
4769 && (reversed
= reversed_comparison (cond
, mode
, XEXP (cond
, 0),
4773 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4774 in it is being compared against certain values. Get the true and false
4775 comparisons and see if that says anything about the value of each arm. */
4778 && ((false_code
= combine_reversed_comparison_code (cond
))
4780 && REG_P (XEXP (cond
, 0)))
4783 rtx from
= XEXP (cond
, 0);
4784 rtx true_val
= XEXP (cond
, 1);
4785 rtx false_val
= true_val
;
4788 /* If FALSE_CODE is EQ, swap the codes and arms. */
4790 if (false_code
== EQ
)
4792 swapped
= 1, true_code
= EQ
, false_code
= NE
;
4793 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
4796 /* If we are comparing against zero and the expression being tested has
4797 only a single bit that might be nonzero, that is its value when it is
4798 not equal to zero. Similarly if it is known to be -1 or 0. */
4800 if (true_code
== EQ
&& true_val
== const0_rtx
4801 && exact_log2 (nzb
= nonzero_bits (from
, GET_MODE (from
))) >= 0)
4802 false_code
= EQ
, false_val
= GEN_INT (nzb
);
4803 else if (true_code
== EQ
&& true_val
== const0_rtx
4804 && (num_sign_bit_copies (from
, GET_MODE (from
))
4805 == GET_MODE_BITSIZE (GET_MODE (from
))))
4806 false_code
= EQ
, false_val
= constm1_rtx
;
4808 /* Now simplify an arm if we know the value of the register in the
4809 branch and it is used in the arm. Be careful due to the potential
4810 of locally-shared RTL. */
4812 if (reg_mentioned_p (from
, true_rtx
))
4813 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
4815 pc_rtx
, pc_rtx
, 0, 0);
4816 if (reg_mentioned_p (from
, false_rtx
))
4817 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
4819 pc_rtx
, pc_rtx
, 0, 0);
4821 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
4822 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
4824 true_rtx
= XEXP (x
, 1);
4825 false_rtx
= XEXP (x
, 2);
4826 true_code
= GET_CODE (cond
);
4829 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4830 reversed, do so to avoid needing two sets of patterns for
4831 subtract-and-branch insns. Similarly if we have a constant in the true
4832 arm, the false arm is the same as the first operand of the comparison, or
4833 the false arm is more complicated than the true arm. */
4836 && combine_reversed_comparison_code (cond
) != UNKNOWN
4837 && (true_rtx
== pc_rtx
4838 || (CONSTANT_P (true_rtx
)
4839 && GET_CODE (false_rtx
) != CONST_INT
&& false_rtx
!= pc_rtx
)
4840 || true_rtx
== const0_rtx
4841 || (OBJECT_P (true_rtx
) && !OBJECT_P (false_rtx
))
4842 || (GET_CODE (true_rtx
) == SUBREG
&& OBJECT_P (SUBREG_REG (true_rtx
))
4843 && !OBJECT_P (false_rtx
))
4844 || reg_mentioned_p (true_rtx
, false_rtx
)
4845 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
4847 true_code
= reversed_comparison_code (cond
, NULL
);
4849 reversed_comparison (cond
, GET_MODE (cond
), XEXP (cond
, 0),
4852 SUBST (XEXP (x
, 1), false_rtx
);
4853 SUBST (XEXP (x
, 2), true_rtx
);
4855 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
4858 /* It is possible that the conditional has been simplified out. */
4859 true_code
= GET_CODE (cond
);
4860 comparison_p
= COMPARISON_P (cond
);
4863 /* If the two arms are identical, we don't need the comparison. */
4865 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
4868 /* Convert a == b ? b : a to "a". */
4869 if (true_code
== EQ
&& ! side_effects_p (cond
)
4870 && !HONOR_NANS (mode
)
4871 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
4872 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
4874 else if (true_code
== NE
&& ! side_effects_p (cond
)
4875 && !HONOR_NANS (mode
)
4876 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
4877 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
4880 /* Look for cases where we have (abs x) or (neg (abs X)). */
4882 if (GET_MODE_CLASS (mode
) == MODE_INT
4883 && GET_CODE (false_rtx
) == NEG
4884 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
4886 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
4887 && ! side_effects_p (true_rtx
))
4892 return simplify_gen_unary (ABS
, mode
, true_rtx
, mode
);
4896 simplify_gen_unary (NEG
, mode
,
4897 simplify_gen_unary (ABS
, mode
, true_rtx
, mode
),
4903 /* Look for MIN or MAX. */
4905 if ((! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
4907 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
4908 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
4909 && ! side_effects_p (cond
))
4914 return simplify_gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
4917 return simplify_gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
4920 return simplify_gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
4923 return simplify_gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
4928 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4929 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4930 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4931 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4932 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4933 neither 1 or -1, but it isn't worth checking for. */
4935 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
4937 && GET_MODE_CLASS (mode
) == MODE_INT
4938 && ! side_effects_p (x
))
4940 rtx t
= make_compound_operation (true_rtx
, SET
);
4941 rtx f
= make_compound_operation (false_rtx
, SET
);
4942 rtx cond_op0
= XEXP (cond
, 0);
4943 rtx cond_op1
= XEXP (cond
, 1);
4944 enum rtx_code op
= UNKNOWN
, extend_op
= UNKNOWN
;
4945 enum machine_mode m
= mode
;
4946 rtx z
= 0, c1
= NULL_RTX
;
4948 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
4949 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
4950 || GET_CODE (t
) == ASHIFT
4951 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
4952 && rtx_equal_p (XEXP (t
, 0), f
))
4953 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
4955 /* If an identity-zero op is commutative, check whether there
4956 would be a match if we swapped the operands. */
4957 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
4958 || GET_CODE (t
) == XOR
)
4959 && rtx_equal_p (XEXP (t
, 1), f
))
4960 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
4961 else if (GET_CODE (t
) == SIGN_EXTEND
4962 && (GET_CODE (XEXP (t
, 0)) == PLUS
4963 || GET_CODE (XEXP (t
, 0)) == MINUS
4964 || GET_CODE (XEXP (t
, 0)) == IOR
4965 || GET_CODE (XEXP (t
, 0)) == XOR
4966 || GET_CODE (XEXP (t
, 0)) == ASHIFT
4967 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
4968 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
4969 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
4970 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
4971 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
4972 && (num_sign_bit_copies (f
, GET_MODE (f
))
4974 (GET_MODE_BITSIZE (mode
)
4975 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
4977 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4978 extend_op
= SIGN_EXTEND
;
4979 m
= GET_MODE (XEXP (t
, 0));
4981 else if (GET_CODE (t
) == SIGN_EXTEND
4982 && (GET_CODE (XEXP (t
, 0)) == PLUS
4983 || GET_CODE (XEXP (t
, 0)) == IOR
4984 || GET_CODE (XEXP (t
, 0)) == XOR
)
4985 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
4986 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
4987 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
4988 && (num_sign_bit_copies (f
, GET_MODE (f
))
4990 (GET_MODE_BITSIZE (mode
)
4991 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
4993 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4994 extend_op
= SIGN_EXTEND
;
4995 m
= GET_MODE (XEXP (t
, 0));
4997 else if (GET_CODE (t
) == ZERO_EXTEND
4998 && (GET_CODE (XEXP (t
, 0)) == PLUS
4999 || GET_CODE (XEXP (t
, 0)) == MINUS
5000 || GET_CODE (XEXP (t
, 0)) == IOR
5001 || GET_CODE (XEXP (t
, 0)) == XOR
5002 || GET_CODE (XEXP (t
, 0)) == ASHIFT
5003 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
5004 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
5005 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
5006 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5007 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
5008 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
5009 && ((nonzero_bits (f
, GET_MODE (f
))
5010 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
5013 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
5014 extend_op
= ZERO_EXTEND
;
5015 m
= GET_MODE (XEXP (t
, 0));
5017 else if (GET_CODE (t
) == ZERO_EXTEND
5018 && (GET_CODE (XEXP (t
, 0)) == PLUS
5019 || GET_CODE (XEXP (t
, 0)) == IOR
5020 || GET_CODE (XEXP (t
, 0)) == XOR
)
5021 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
5022 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5023 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
5024 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
5025 && ((nonzero_bits (f
, GET_MODE (f
))
5026 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
5029 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
5030 extend_op
= ZERO_EXTEND
;
5031 m
= GET_MODE (XEXP (t
, 0));
5036 temp
= subst (simplify_gen_relational (true_code
, m
, VOIDmode
,
5037 cond_op0
, cond_op1
),
5038 pc_rtx
, pc_rtx
, 0, 0);
5039 temp
= simplify_gen_binary (MULT
, m
, temp
,
5040 simplify_gen_binary (MULT
, m
, c1
,
5042 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0);
5043 temp
= simplify_gen_binary (op
, m
, gen_lowpart (m
, z
), temp
);
5045 if (extend_op
!= UNKNOWN
)
5046 temp
= simplify_gen_unary (extend_op
, mode
, temp
, m
);
5052 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
5053 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
5054 negation of a single bit, we can convert this operation to a shift. We
5055 can actually do this more generally, but it doesn't seem worth it. */
5057 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
5058 && false_rtx
== const0_rtx
&& GET_CODE (true_rtx
) == CONST_INT
5059 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
5060 && (i
= exact_log2 (INTVAL (true_rtx
))) >= 0)
5061 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
5062 == GET_MODE_BITSIZE (mode
))
5063 && (i
= exact_log2 (-INTVAL (true_rtx
))) >= 0)))
5065 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5066 gen_lowpart (mode
, XEXP (cond
, 0)), i
);
5068 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
5069 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
5070 && false_rtx
== const0_rtx
&& GET_CODE (true_rtx
) == CONST_INT
5071 && GET_MODE (XEXP (cond
, 0)) == mode
5072 && (INTVAL (true_rtx
) & GET_MODE_MASK (mode
))
5073 == nonzero_bits (XEXP (cond
, 0), mode
)
5074 && (i
= exact_log2 (INTVAL (true_rtx
) & GET_MODE_MASK (mode
))) >= 0)
5075 return XEXP (cond
, 0);
5080 /* Simplify X, a SET expression. Return the new expression. */
5083 simplify_set (rtx x
)
5085 rtx src
= SET_SRC (x
);
5086 rtx dest
= SET_DEST (x
);
5087 enum machine_mode mode
5088 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
5092 /* (set (pc) (return)) gets written as (return). */
5093 if (GET_CODE (dest
) == PC
&& GET_CODE (src
) == RETURN
)
5096 /* Now that we know for sure which bits of SRC we are using, see if we can
5097 simplify the expression for the object knowing that we only need the
5100 if (GET_MODE_CLASS (mode
) == MODE_INT
5101 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
5103 src
= force_to_mode (src
, mode
, ~(HOST_WIDE_INT
) 0, NULL_RTX
, 0);
5104 SUBST (SET_SRC (x
), src
);
5107 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5108 the comparison result and try to simplify it unless we already have used
5109 undobuf.other_insn. */
5110 if ((GET_MODE_CLASS (mode
) == MODE_CC
5111 || GET_CODE (src
) == COMPARE
5113 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
5114 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
5115 && COMPARISON_P (*cc_use
)
5116 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
5118 enum rtx_code old_code
= GET_CODE (*cc_use
);
5119 enum rtx_code new_code
;
5121 int other_changed
= 0;
5122 enum machine_mode compare_mode
= GET_MODE (dest
);
5124 if (GET_CODE (src
) == COMPARE
)
5125 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
5127 op0
= src
, op1
= CONST0_RTX (GET_MODE (src
));
5129 tmp
= simplify_relational_operation (old_code
, compare_mode
, VOIDmode
,
5132 new_code
= old_code
;
5133 else if (!CONSTANT_P (tmp
))
5135 new_code
= GET_CODE (tmp
);
5136 op0
= XEXP (tmp
, 0);
5137 op1
= XEXP (tmp
, 1);
5141 rtx pat
= PATTERN (other_insn
);
5142 undobuf
.other_insn
= other_insn
;
5143 SUBST (*cc_use
, tmp
);
5145 /* Attempt to simplify CC user. */
5146 if (GET_CODE (pat
) == SET
)
5148 rtx
new = simplify_rtx (SET_SRC (pat
));
5149 if (new != NULL_RTX
)
5150 SUBST (SET_SRC (pat
), new);
5153 /* Convert X into a no-op move. */
5154 SUBST (SET_DEST (x
), pc_rtx
);
5155 SUBST (SET_SRC (x
), pc_rtx
);
5159 /* Simplify our comparison, if possible. */
5160 new_code
= simplify_comparison (new_code
, &op0
, &op1
);
5162 #ifdef SELECT_CC_MODE
5163 /* If this machine has CC modes other than CCmode, check to see if we
5164 need to use a different CC mode here. */
5165 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
5166 compare_mode
= GET_MODE (op0
);
5168 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
5171 /* If the mode changed, we have to change SET_DEST, the mode in the
5172 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5173 a hard register, just build new versions with the proper mode. If it
5174 is a pseudo, we lose unless it is only time we set the pseudo, in
5175 which case we can safely change its mode. */
5176 if (compare_mode
!= GET_MODE (dest
))
5178 unsigned int regno
= REGNO (dest
);
5179 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
5181 if (regno
< FIRST_PSEUDO_REGISTER
5182 || (REG_N_SETS (regno
) == 1 && ! REG_USERVAR_P (dest
)))
5184 if (regno
>= FIRST_PSEUDO_REGISTER
)
5185 SUBST (regno_reg_rtx
[regno
], new_dest
);
5187 SUBST (SET_DEST (x
), new_dest
);
5188 SUBST (XEXP (*cc_use
, 0), new_dest
);
5195 #endif /* SELECT_CC_MODE */
5197 /* If the code changed, we have to build a new comparison in
5198 undobuf.other_insn. */
5199 if (new_code
!= old_code
)
5201 int other_changed_previously
= other_changed
;
5202 unsigned HOST_WIDE_INT mask
;
5204 SUBST (*cc_use
, gen_rtx_fmt_ee (new_code
, GET_MODE (*cc_use
),
5208 /* If the only change we made was to change an EQ into an NE or
5209 vice versa, OP0 has only one bit that might be nonzero, and OP1
5210 is zero, check if changing the user of the condition code will
5211 produce a valid insn. If it won't, we can keep the original code
5212 in that insn by surrounding our operation with an XOR. */
5214 if (((old_code
== NE
&& new_code
== EQ
)
5215 || (old_code
== EQ
&& new_code
== NE
))
5216 && ! other_changed_previously
&& op1
== const0_rtx
5217 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
5218 && exact_log2 (mask
= nonzero_bits (op0
, GET_MODE (op0
))) >= 0)
5220 rtx pat
= PATTERN (other_insn
), note
= 0;
5222 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
5223 && ! check_asm_operands (pat
)))
5225 PUT_CODE (*cc_use
, old_code
);
5228 op0
= simplify_gen_binary (XOR
, GET_MODE (op0
),
5229 op0
, GEN_INT (mask
));
5235 undobuf
.other_insn
= other_insn
;
5238 /* If we are now comparing against zero, change our source if
5239 needed. If we do not use cc0, we always have a COMPARE. */
5240 if (op1
== const0_rtx
&& dest
== cc0_rtx
)
5242 SUBST (SET_SRC (x
), op0
);
5248 /* Otherwise, if we didn't previously have a COMPARE in the
5249 correct mode, we need one. */
5250 if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
)
5252 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
5257 /* Otherwise, update the COMPARE if needed. */
5258 SUBST (XEXP (src
, 0), op0
);
5259 SUBST (XEXP (src
, 1), op1
);
5264 /* Get SET_SRC in a form where we have placed back any
5265 compound expressions. Then do the checks below. */
5266 src
= make_compound_operation (src
, SET
);
5267 SUBST (SET_SRC (x
), src
);
5270 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5271 and X being a REG or (subreg (reg)), we may be able to convert this to
5272 (set (subreg:m2 x) (op)).
5274 We can always do this if M1 is narrower than M2 because that means that
5275 we only care about the low bits of the result.
5277 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5278 perform a narrower operation than requested since the high-order bits will
5279 be undefined. On machine where it is defined, this transformation is safe
5280 as long as M1 and M2 have the same number of words. */
5282 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5283 && !OBJECT_P (SUBREG_REG (src
))
5284 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
5286 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
5287 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
5288 #ifndef WORD_REGISTER_OPERATIONS
5289 && (GET_MODE_SIZE (GET_MODE (src
))
5290 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
5292 #ifdef CANNOT_CHANGE_MODE_CLASS
5293 && ! (REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
5294 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest
),
5295 GET_MODE (SUBREG_REG (src
)),
5299 || (GET_CODE (dest
) == SUBREG
5300 && REG_P (SUBREG_REG (dest
)))))
5302 SUBST (SET_DEST (x
),
5303 gen_lowpart (GET_MODE (SUBREG_REG (src
)),
5305 SUBST (SET_SRC (x
), SUBREG_REG (src
));
5307 src
= SET_SRC (x
), dest
= SET_DEST (x
);
5311 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5314 && GET_CODE (src
) == SUBREG
5315 && subreg_lowpart_p (src
)
5316 && (GET_MODE_BITSIZE (GET_MODE (src
))
5317 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src
)))))
5319 rtx inner
= SUBREG_REG (src
);
5320 enum machine_mode inner_mode
= GET_MODE (inner
);
5322 /* Here we make sure that we don't have a sign bit on. */
5323 if (GET_MODE_BITSIZE (inner_mode
) <= HOST_BITS_PER_WIDE_INT
5324 && (nonzero_bits (inner
, inner_mode
)
5325 < ((unsigned HOST_WIDE_INT
) 1
5326 << (GET_MODE_BITSIZE (GET_MODE (src
)) - 1))))
5328 SUBST (SET_SRC (x
), inner
);
5334 #ifdef LOAD_EXTEND_OP
5335 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5336 would require a paradoxical subreg. Replace the subreg with a
5337 zero_extend to avoid the reload that would otherwise be required. */
5339 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5340 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))) != UNKNOWN
5341 && SUBREG_BYTE (src
) == 0
5342 && (GET_MODE_SIZE (GET_MODE (src
))
5343 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
5344 && MEM_P (SUBREG_REG (src
)))
5347 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))),
5348 GET_MODE (src
), SUBREG_REG (src
)));
5354 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5355 are comparing an item known to be 0 or -1 against 0, use a logical
5356 operation instead. Check for one of the arms being an IOR of the other
5357 arm with some value. We compute three terms to be IOR'ed together. In
5358 practice, at most two will be nonzero. Then we do the IOR's. */
5360 if (GET_CODE (dest
) != PC
5361 && GET_CODE (src
) == IF_THEN_ELSE
5362 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
5363 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
5364 && XEXP (XEXP (src
, 0), 1) == const0_rtx
5365 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
5366 #ifdef HAVE_conditional_move
5367 && ! can_conditionally_move_p (GET_MODE (src
))
5369 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
5370 GET_MODE (XEXP (XEXP (src
, 0), 0)))
5371 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src
, 0), 0))))
5372 && ! side_effects_p (src
))
5374 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
5375 ? XEXP (src
, 1) : XEXP (src
, 2));
5376 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
5377 ? XEXP (src
, 2) : XEXP (src
, 1));
5378 rtx term1
= const0_rtx
, term2
, term3
;
5380 if (GET_CODE (true_rtx
) == IOR
5381 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
5382 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 1), false_rtx
= const0_rtx
;
5383 else if (GET_CODE (true_rtx
) == IOR
5384 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
5385 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 0), false_rtx
= const0_rtx
;
5386 else if (GET_CODE (false_rtx
) == IOR
5387 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
5388 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 1), true_rtx
= const0_rtx
;
5389 else if (GET_CODE (false_rtx
) == IOR
5390 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
5391 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 0), true_rtx
= const0_rtx
;
5393 term2
= simplify_gen_binary (AND
, GET_MODE (src
),
5394 XEXP (XEXP (src
, 0), 0), true_rtx
);
5395 term3
= simplify_gen_binary (AND
, GET_MODE (src
),
5396 simplify_gen_unary (NOT
, GET_MODE (src
),
5397 XEXP (XEXP (src
, 0), 0),
5402 simplify_gen_binary (IOR
, GET_MODE (src
),
5403 simplify_gen_binary (IOR
, GET_MODE (src
),
5410 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5411 whole thing fail. */
5412 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
5414 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
5417 /* Convert this into a field assignment operation, if possible. */
5418 return make_field_assignment (x
);
5421 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5425 simplify_logical (rtx x
)
5427 enum machine_mode mode
= GET_MODE (x
);
5428 rtx op0
= XEXP (x
, 0);
5429 rtx op1
= XEXP (x
, 1);
5432 switch (GET_CODE (x
))
5435 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5436 insn (and may simplify more). */
5437 if (GET_CODE (op0
) == XOR
5438 && rtx_equal_p (XEXP (op0
, 0), op1
)
5439 && ! side_effects_p (op1
))
5440 x
= simplify_gen_binary (AND
, mode
,
5441 simplify_gen_unary (NOT
, mode
,
5442 XEXP (op0
, 1), mode
),
5445 if (GET_CODE (op0
) == XOR
5446 && rtx_equal_p (XEXP (op0
, 1), op1
)
5447 && ! side_effects_p (op1
))
5448 x
= simplify_gen_binary (AND
, mode
,
5449 simplify_gen_unary (NOT
, mode
,
5450 XEXP (op0
, 0), mode
),
5453 /* Similarly for (~(A ^ B)) & A. */
5454 if (GET_CODE (op0
) == NOT
5455 && GET_CODE (XEXP (op0
, 0)) == XOR
5456 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), op1
)
5457 && ! side_effects_p (op1
))
5458 x
= simplify_gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 1), op1
);
5460 if (GET_CODE (op0
) == NOT
5461 && GET_CODE (XEXP (op0
, 0)) == XOR
5462 && rtx_equal_p (XEXP (XEXP (op0
, 0), 1), op1
)
5463 && ! side_effects_p (op1
))
5464 x
= simplify_gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 0), op1
);
5466 /* We can call simplify_and_const_int only if we don't lose
5467 any (sign) bits when converting INTVAL (op1) to
5468 "unsigned HOST_WIDE_INT". */
5469 if (GET_CODE (op1
) == CONST_INT
5470 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5471 || INTVAL (op1
) > 0))
5473 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
5475 /* If we have (ior (and (X C1) C2)) and the next restart would be
5476 the last, simplify this by making C1 as small as possible
5477 and then exit. Only do this if C1 actually changes: for now
5478 this only saves memory but, should this transformation be
5479 moved to simplify-rtx.c, we'd risk unbounded recursion there. */
5480 if (GET_CODE (x
) == IOR
&& GET_CODE (op0
) == AND
5481 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5482 && GET_CODE (op1
) == CONST_INT
5483 && (INTVAL (XEXP (op0
, 1)) & INTVAL (op1
)) != 0)
5484 return simplify_gen_binary (IOR
, mode
,
5486 (AND
, mode
, XEXP (op0
, 0),
5487 GEN_INT (INTVAL (XEXP (op0
, 1))
5488 & ~INTVAL (op1
))), op1
);
5490 if (GET_CODE (x
) != AND
)
5497 /* Convert (A | B) & A to A. */
5498 if (GET_CODE (op0
) == IOR
5499 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5500 || rtx_equal_p (XEXP (op0
, 1), op1
))
5501 && ! side_effects_p (XEXP (op0
, 0))
5502 && ! side_effects_p (XEXP (op0
, 1)))
5505 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
5506 apply the distributive law and then the inverse distributive
5507 law to see if things simplify. */
5508 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
5510 rtx result
= distribute_and_simplify_rtx (x
, 0);
5514 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
5516 rtx result
= distribute_and_simplify_rtx (x
, 1);
5523 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5524 if (GET_CODE (op1
) == CONST_INT
5525 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5526 && (nonzero_bits (op0
, mode
) & ~INTVAL (op1
)) == 0)
5529 /* Convert (A & B) | A to A. */
5530 if (GET_CODE (op0
) == AND
5531 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5532 || rtx_equal_p (XEXP (op0
, 1), op1
))
5533 && ! side_effects_p (XEXP (op0
, 0))
5534 && ! side_effects_p (XEXP (op0
, 1)))
5537 /* If we have (ior (and A B) C), apply the distributive law and then
5538 the inverse distributive law to see if things simplify. */
5540 if (GET_CODE (op0
) == AND
)
5542 rtx result
= distribute_and_simplify_rtx (x
, 0);
5547 if (GET_CODE (op1
) == AND
)
5549 rtx result
= distribute_and_simplify_rtx (x
, 1);
5554 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5555 mode size to (rotate A CX). */
5557 if (((GET_CODE (op0
) == ASHIFT
&& GET_CODE (op1
) == LSHIFTRT
)
5558 || (GET_CODE (op1
) == ASHIFT
&& GET_CODE (op0
) == LSHIFTRT
))
5559 && rtx_equal_p (XEXP (op0
, 0), XEXP (op1
, 0))
5560 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5561 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
5562 && (INTVAL (XEXP (op0
, 1)) + INTVAL (XEXP (op1
, 1))
5563 == GET_MODE_BITSIZE (mode
)))
5564 return gen_rtx_ROTATE (mode
, XEXP (op0
, 0),
5565 (GET_CODE (op0
) == ASHIFT
5566 ? XEXP (op0
, 1) : XEXP (op1
, 1)));
5568 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5569 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5570 does not affect any of the bits in OP1, it can really be done
5571 as a PLUS and we can associate. We do this by seeing if OP1
5572 can be safely shifted left C bits. */
5573 if (GET_CODE (op1
) == CONST_INT
&& GET_CODE (op0
) == ASHIFTRT
5574 && GET_CODE (XEXP (op0
, 0)) == PLUS
5575 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
5576 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5577 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
)
5579 int count
= INTVAL (XEXP (op0
, 1));
5580 HOST_WIDE_INT mask
= INTVAL (op1
) << count
;
5582 if (mask
>> count
== INTVAL (op1
)
5583 && (mask
& nonzero_bits (XEXP (op0
, 0), mode
)) == 0)
5585 SUBST (XEXP (XEXP (op0
, 0), 1),
5586 GEN_INT (INTVAL (XEXP (XEXP (op0
, 0), 1)) | mask
));
5593 /* If we are XORing two things that have no bits in common,
5594 convert them into an IOR. This helps to detect rotation encoded
5595 using those methods and possibly other simplifications. */
5597 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5598 && (nonzero_bits (op0
, mode
)
5599 & nonzero_bits (op1
, mode
)) == 0)
5600 return (simplify_gen_binary (IOR
, mode
, op0
, op1
));
5602 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5603 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5606 int num_negated
= 0;
5608 if (GET_CODE (op0
) == NOT
)
5609 num_negated
++, op0
= XEXP (op0
, 0);
5610 if (GET_CODE (op1
) == NOT
)
5611 num_negated
++, op1
= XEXP (op1
, 0);
5613 if (num_negated
== 2)
5615 SUBST (XEXP (x
, 0), op0
);
5616 SUBST (XEXP (x
, 1), op1
);
5618 else if (num_negated
== 1)
5620 simplify_gen_unary (NOT
, mode
,
5621 simplify_gen_binary (XOR
, mode
, op0
, op1
),
5625 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5626 correspond to a machine insn or result in further simplifications
5627 if B is a constant. */
5629 if (GET_CODE (op0
) == AND
5630 && rtx_equal_p (XEXP (op0
, 1), op1
)
5631 && ! side_effects_p (op1
))
5632 return simplify_gen_binary (AND
, mode
,
5633 simplify_gen_unary (NOT
, mode
,
5634 XEXP (op0
, 0), mode
),
5637 else if (GET_CODE (op0
) == AND
5638 && rtx_equal_p (XEXP (op0
, 0), op1
)
5639 && ! side_effects_p (op1
))
5640 return simplify_gen_binary (AND
, mode
,
5641 simplify_gen_unary (NOT
, mode
,
5642 XEXP (op0
, 1), mode
),
5645 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5646 comparison if STORE_FLAG_VALUE is 1. */
5647 if (STORE_FLAG_VALUE
== 1
5648 && op1
== const1_rtx
5649 && COMPARISON_P (op0
)
5650 && (reversed
= reversed_comparison (op0
, mode
, XEXP (op0
, 0),
5654 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5655 is (lt foo (const_int 0)), so we can perform the above
5656 simplification if STORE_FLAG_VALUE is 1. */
5658 if (STORE_FLAG_VALUE
== 1
5659 && op1
== const1_rtx
5660 && GET_CODE (op0
) == LSHIFTRT
5661 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5662 && INTVAL (XEXP (op0
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
5663 return gen_rtx_GE (mode
, XEXP (op0
, 0), const0_rtx
);
5665 /* (xor (comparison foo bar) (const_int sign-bit))
5666 when STORE_FLAG_VALUE is the sign bit. */
5667 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5668 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
5669 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
5670 && op1
== const_true_rtx
5671 && COMPARISON_P (op0
)
5672 && (reversed
= reversed_comparison (op0
, mode
, XEXP (op0
, 0),
5685 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5686 operations" because they can be replaced with two more basic operations.
5687 ZERO_EXTEND is also considered "compound" because it can be replaced with
5688 an AND operation, which is simpler, though only one operation.
5690 The function expand_compound_operation is called with an rtx expression
5691 and will convert it to the appropriate shifts and AND operations,
5692 simplifying at each stage.
5694 The function make_compound_operation is called to convert an expression
5695 consisting of shifts and ANDs into the equivalent compound expression.
5696 It is the inverse of this function, loosely speaking. */
5699 expand_compound_operation (rtx x
)
5701 unsigned HOST_WIDE_INT pos
= 0, len
;
5703 unsigned int modewidth
;
5706 switch (GET_CODE (x
))
5711 /* We can't necessarily use a const_int for a multiword mode;
5712 it depends on implicitly extending the value.
5713 Since we don't know the right way to extend it,
5714 we can't tell whether the implicit way is right.
5716 Even for a mode that is no wider than a const_int,
5717 we can't win, because we need to sign extend one of its bits through
5718 the rest of it, and we don't know which bit. */
5719 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
5722 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5723 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5724 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5725 reloaded. If not for that, MEM's would very rarely be safe.
5727 Reject MODEs bigger than a word, because we might not be able
5728 to reference a two-register group starting with an arbitrary register
5729 (and currently gen_lowpart might crash for a SUBREG). */
5731 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
5734 /* Reject MODEs that aren't scalar integers because turning vector
5735 or complex modes into shifts causes problems. */
5737 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
5740 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)));
5741 /* If the inner object has VOIDmode (the only way this can happen
5742 is if it is an ASM_OPERANDS), we can't do anything since we don't
5743 know how much masking to do. */
5752 /* ... fall through ... */
5755 /* If the operand is a CLOBBER, just return it. */
5756 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
5759 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
5760 || GET_CODE (XEXP (x
, 2)) != CONST_INT
5761 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
5764 /* Reject MODEs that aren't scalar integers because turning vector
5765 or complex modes into shifts causes problems. */
5767 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
5770 len
= INTVAL (XEXP (x
, 1));
5771 pos
= INTVAL (XEXP (x
, 2));
5773 /* If this goes outside the object being extracted, replace the object
5774 with a (use (mem ...)) construct that only combine understands
5775 and is used only for this purpose. */
5776 if (len
+ pos
> GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
5777 SUBST (XEXP (x
, 0), gen_rtx_USE (GET_MODE (x
), XEXP (x
, 0)));
5779 if (BITS_BIG_ENDIAN
)
5780 pos
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - len
- pos
;
5787 /* Convert sign extension to zero extension, if we know that the high
5788 bit is not set, as this is easier to optimize. It will be converted
5789 back to cheaper alternative in make_extraction. */
5790 if (GET_CODE (x
) == SIGN_EXTEND
5791 && (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5792 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
5793 & ~(((unsigned HOST_WIDE_INT
)
5794 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
5798 rtx temp
= gen_rtx_ZERO_EXTEND (GET_MODE (x
), XEXP (x
, 0));
5799 rtx temp2
= expand_compound_operation (temp
);
5801 /* Make sure this is a profitable operation. */
5802 if (rtx_cost (x
, SET
) > rtx_cost (temp2
, SET
))
5804 else if (rtx_cost (x
, SET
) > rtx_cost (temp
, SET
))
5810 /* We can optimize some special cases of ZERO_EXTEND. */
5811 if (GET_CODE (x
) == ZERO_EXTEND
)
5813 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5814 know that the last value didn't have any inappropriate bits
5816 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5817 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5818 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5819 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
5820 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5821 return XEXP (XEXP (x
, 0), 0);
5823 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5824 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5825 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5826 && subreg_lowpart_p (XEXP (x
, 0))
5827 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5828 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
5829 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5830 return SUBREG_REG (XEXP (x
, 0));
5832 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5833 is a comparison and STORE_FLAG_VALUE permits. This is like
5834 the first case, but it works even when GET_MODE (x) is larger
5835 than HOST_WIDE_INT. */
5836 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5837 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5838 && COMPARISON_P (XEXP (XEXP (x
, 0), 0))
5839 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5840 <= HOST_BITS_PER_WIDE_INT
)
5841 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5842 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5843 return XEXP (XEXP (x
, 0), 0);
5845 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5846 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5847 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5848 && subreg_lowpart_p (XEXP (x
, 0))
5849 && COMPARISON_P (SUBREG_REG (XEXP (x
, 0)))
5850 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5851 <= HOST_BITS_PER_WIDE_INT
)
5852 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5853 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5854 return SUBREG_REG (XEXP (x
, 0));
5858 /* If we reach here, we want to return a pair of shifts. The inner
5859 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5860 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5861 logical depending on the value of UNSIGNEDP.
5863 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5864 converted into an AND of a shift.
5866 We must check for the case where the left shift would have a negative
5867 count. This can happen in a case like (x >> 31) & 255 on machines
5868 that can't shift by a constant. On those machines, we would first
5869 combine the shift with the AND to produce a variable-position
5870 extraction. Then the constant of 31 would be substituted in to produce
5871 a such a position. */
5873 modewidth
= GET_MODE_BITSIZE (GET_MODE (x
));
5874 if (modewidth
+ len
>= pos
)
5875 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
5877 simplify_shift_const (NULL_RTX
, ASHIFT
,
5880 modewidth
- pos
- len
),
5883 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
5884 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
5885 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
5888 ((HOST_WIDE_INT
) 1 << len
) - 1);
5890 /* Any other cases we can't handle. */
5893 /* If we couldn't do this for some reason, return the original
5895 if (GET_CODE (tem
) == CLOBBER
)
5901 /* X is a SET which contains an assignment of one object into
5902 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5903 or certain SUBREGS). If possible, convert it into a series of
5906 We half-heartedly support variable positions, but do not at all
5907 support variable lengths. */
5910 expand_field_assignment (rtx x
)
5913 rtx pos
; /* Always counts from low bit. */
5915 rtx mask
, cleared
, masked
;
5916 enum machine_mode compute_mode
;
5918 /* Loop until we find something we can't simplify. */
5921 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
5922 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
5924 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
5925 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)));
5926 pos
= GEN_INT (subreg_lsb (XEXP (SET_DEST (x
), 0)));
5928 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
5929 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
)
5931 inner
= XEXP (SET_DEST (x
), 0);
5932 len
= INTVAL (XEXP (SET_DEST (x
), 1));
5933 pos
= XEXP (SET_DEST (x
), 2);
5935 /* If the position is constant and spans the width of INNER,
5936 surround INNER with a USE to indicate this. */
5937 if (GET_CODE (pos
) == CONST_INT
5938 && INTVAL (pos
) + len
> GET_MODE_BITSIZE (GET_MODE (inner
)))
5939 inner
= gen_rtx_USE (GET_MODE (SET_DEST (x
)), inner
);
5941 if (BITS_BIG_ENDIAN
)
5943 if (GET_CODE (pos
) == CONST_INT
)
5944 pos
= GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
)) - len
5946 else if (GET_CODE (pos
) == MINUS
5947 && GET_CODE (XEXP (pos
, 1)) == CONST_INT
5948 && (INTVAL (XEXP (pos
, 1))
5949 == GET_MODE_BITSIZE (GET_MODE (inner
)) - len
))
5950 /* If position is ADJUST - X, new position is X. */
5951 pos
= XEXP (pos
, 0);
5953 pos
= simplify_gen_binary (MINUS
, GET_MODE (pos
),
5954 GEN_INT (GET_MODE_BITSIZE (
5961 /* A SUBREG between two modes that occupy the same numbers of words
5962 can be done by moving the SUBREG to the source. */
5963 else if (GET_CODE (SET_DEST (x
)) == SUBREG
5964 /* We need SUBREGs to compute nonzero_bits properly. */
5965 && nonzero_sign_valid
5966 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
5967 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
5968 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
5969 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
5971 x
= gen_rtx_SET (VOIDmode
, SUBREG_REG (SET_DEST (x
)),
5973 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
5980 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
5981 inner
= SUBREG_REG (inner
);
5983 compute_mode
= GET_MODE (inner
);
5985 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
5986 if (! SCALAR_INT_MODE_P (compute_mode
))
5988 enum machine_mode imode
;
5990 /* Don't do anything for vector or complex integral types. */
5991 if (! FLOAT_MODE_P (compute_mode
))
5994 /* Try to find an integral mode to pun with. */
5995 imode
= mode_for_size (GET_MODE_BITSIZE (compute_mode
), MODE_INT
, 0);
5996 if (imode
== BLKmode
)
5999 compute_mode
= imode
;
6000 inner
= gen_lowpart (imode
, inner
);
6003 /* Compute a mask of LEN bits, if we can do this on the host machine. */
6004 if (len
>= HOST_BITS_PER_WIDE_INT
)
6007 /* Now compute the equivalent expression. Make a copy of INNER
6008 for the SET_DEST in case it is a MEM into which we will substitute;
6009 we don't want shared RTL in that case. */
6010 mask
= GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1);
6011 cleared
= simplify_gen_binary (AND
, compute_mode
,
6012 simplify_gen_unary (NOT
, compute_mode
,
6013 simplify_gen_binary (ASHIFT
,
6018 masked
= simplify_gen_binary (ASHIFT
, compute_mode
,
6019 simplify_gen_binary (
6021 gen_lowpart (compute_mode
, SET_SRC (x
)),
6025 x
= gen_rtx_SET (VOIDmode
, copy_rtx (inner
),
6026 simplify_gen_binary (IOR
, compute_mode
,
6033 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
6034 it is an RTX that represents a variable starting position; otherwise,
6035 POS is the (constant) starting bit position (counted from the LSB).
6037 INNER may be a USE. This will occur when we started with a bitfield
6038 that went outside the boundary of the object in memory, which is
6039 allowed on most machines. To isolate this case, we produce a USE
6040 whose mode is wide enough and surround the MEM with it. The only
6041 code that understands the USE is this routine. If it is not removed,
6042 it will cause the resulting insn not to match.
6044 UNSIGNEDP is nonzero for an unsigned reference and zero for a
6047 IN_DEST is nonzero if this is a reference in the destination of a
6048 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
6049 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6052 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
6053 ZERO_EXTRACT should be built even for bits starting at bit 0.
6055 MODE is the desired mode of the result (if IN_DEST == 0).
6057 The result is an RTX for the extraction or NULL_RTX if the target
6061 make_extraction (enum machine_mode mode
, rtx inner
, HOST_WIDE_INT pos
,
6062 rtx pos_rtx
, unsigned HOST_WIDE_INT len
, int unsignedp
,
6063 int in_dest
, int in_compare
)
6065 /* This mode describes the size of the storage area
6066 to fetch the overall value from. Within that, we
6067 ignore the POS lowest bits, etc. */
6068 enum machine_mode is_mode
= GET_MODE (inner
);
6069 enum machine_mode inner_mode
;
6070 enum machine_mode wanted_inner_mode
= byte_mode
;
6071 enum machine_mode wanted_inner_reg_mode
= word_mode
;
6072 enum machine_mode pos_mode
= word_mode
;
6073 enum machine_mode extraction_mode
= word_mode
;
6074 enum machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
6077 rtx orig_pos_rtx
= pos_rtx
;
6078 HOST_WIDE_INT orig_pos
;
6080 /* Get some information about INNER and get the innermost object. */
6081 if (GET_CODE (inner
) == USE
)
6082 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
6083 /* We don't need to adjust the position because we set up the USE
6084 to pretend that it was a full-word object. */
6085 spans_byte
= 1, inner
= XEXP (inner
, 0);
6086 else if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
6088 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
6089 consider just the QI as the memory to extract from.
6090 The subreg adds or removes high bits; its mode is
6091 irrelevant to the meaning of this extraction,
6092 since POS and LEN count from the lsb. */
6093 if (MEM_P (SUBREG_REG (inner
)))
6094 is_mode
= GET_MODE (SUBREG_REG (inner
));
6095 inner
= SUBREG_REG (inner
);
6097 else if (GET_CODE (inner
) == ASHIFT
6098 && GET_CODE (XEXP (inner
, 1)) == CONST_INT
6099 && pos_rtx
== 0 && pos
== 0
6100 && len
> (unsigned HOST_WIDE_INT
) INTVAL (XEXP (inner
, 1)))
6102 /* We're extracting the least significant bits of an rtx
6103 (ashift X (const_int C)), where LEN > C. Extract the
6104 least significant (LEN - C) bits of X, giving an rtx
6105 whose mode is MODE, then shift it left C times. */
6106 new = make_extraction (mode
, XEXP (inner
, 0),
6107 0, 0, len
- INTVAL (XEXP (inner
, 1)),
6108 unsignedp
, in_dest
, in_compare
);
6110 return gen_rtx_ASHIFT (mode
, new, XEXP (inner
, 1));
6113 inner_mode
= GET_MODE (inner
);
6115 if (pos_rtx
&& GET_CODE (pos_rtx
) == CONST_INT
)
6116 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
6118 /* See if this can be done without an extraction. We never can if the
6119 width of the field is not the same as that of some integer mode. For
6120 registers, we can only avoid the extraction if the position is at the
6121 low-order bit and this is either not in the destination or we have the
6122 appropriate STRICT_LOW_PART operation available.
6124 For MEM, we can avoid an extract if the field starts on an appropriate
6125 boundary and we can change the mode of the memory reference. However,
6126 we cannot directly access the MEM if we have a USE and the underlying
6127 MEM is not TMODE. This combination means that MEM was being used in a
6128 context where bits outside its mode were being referenced; that is only
6129 valid in bit-field insns. */
6131 if (tmode
!= BLKmode
6132 && ! (spans_byte
&& inner_mode
!= tmode
)
6133 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
6137 && have_insn_for (STRICT_LOW_PART
, tmode
))))
6138 || (MEM_P (inner
) && pos_rtx
== 0
6140 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
6141 : BITS_PER_UNIT
)) == 0
6142 /* We can't do this if we are widening INNER_MODE (it
6143 may not be aligned, for one thing). */
6144 && GET_MODE_BITSIZE (inner_mode
) >= GET_MODE_BITSIZE (tmode
)
6145 && (inner_mode
== tmode
6146 || (! mode_dependent_address_p (XEXP (inner
, 0))
6147 && ! MEM_VOLATILE_P (inner
))))))
6149 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6150 field. If the original and current mode are the same, we need not
6151 adjust the offset. Otherwise, we do if bytes big endian.
6153 If INNER is not a MEM, get a piece consisting of just the field
6154 of interest (in this case POS % BITS_PER_WORD must be 0). */
6158 HOST_WIDE_INT offset
;
6160 /* POS counts from lsb, but make OFFSET count in memory order. */
6161 if (BYTES_BIG_ENDIAN
)
6162 offset
= (GET_MODE_BITSIZE (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
6164 offset
= pos
/ BITS_PER_UNIT
;
6166 new = adjust_address_nv (inner
, tmode
, offset
);
6168 else if (REG_P (inner
))
6170 if (tmode
!= inner_mode
)
6172 /* We can't call gen_lowpart in a DEST since we
6173 always want a SUBREG (see below) and it would sometimes
6174 return a new hard register. */
6177 HOST_WIDE_INT final_word
= pos
/ BITS_PER_WORD
;
6179 if (WORDS_BIG_ENDIAN
6180 && GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
)
6181 final_word
= ((GET_MODE_SIZE (inner_mode
)
6182 - GET_MODE_SIZE (tmode
))
6183 / UNITS_PER_WORD
) - final_word
;
6185 final_word
*= UNITS_PER_WORD
;
6186 if (BYTES_BIG_ENDIAN
&&
6187 GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (tmode
))
6188 final_word
+= (GET_MODE_SIZE (inner_mode
)
6189 - GET_MODE_SIZE (tmode
)) % UNITS_PER_WORD
;
6191 /* Avoid creating invalid subregs, for example when
6192 simplifying (x>>32)&255. */
6193 if (final_word
>= GET_MODE_SIZE (inner_mode
))
6196 new = gen_rtx_SUBREG (tmode
, inner
, final_word
);
6199 new = gen_lowpart (tmode
, inner
);
6205 new = force_to_mode (inner
, tmode
,
6206 len
>= HOST_BITS_PER_WIDE_INT
6207 ? ~(unsigned HOST_WIDE_INT
) 0
6208 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
6211 /* If this extraction is going into the destination of a SET,
6212 make a STRICT_LOW_PART unless we made a MEM. */
6215 return (MEM_P (new) ? new
6216 : (GET_CODE (new) != SUBREG
6217 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
6218 : gen_rtx_STRICT_LOW_PART (VOIDmode
, new)));
6223 if (GET_CODE (new) == CONST_INT
)
6224 return gen_int_mode (INTVAL (new), mode
);
6226 /* If we know that no extraneous bits are set, and that the high
6227 bit is not set, convert the extraction to the cheaper of
6228 sign and zero extension, that are equivalent in these cases. */
6229 if (flag_expensive_optimizations
6230 && (GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
6231 && ((nonzero_bits (new, tmode
)
6232 & ~(((unsigned HOST_WIDE_INT
)
6233 GET_MODE_MASK (tmode
))
6237 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new);
6238 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new);
6240 /* Prefer ZERO_EXTENSION, since it gives more information to
6242 if (rtx_cost (temp
, SET
) <= rtx_cost (temp1
, SET
))
6247 /* Otherwise, sign- or zero-extend unless we already are in the
6250 return (gen_rtx_fmt_e (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
6254 /* Unless this is a COMPARE or we have a funny memory reference,
6255 don't do anything with zero-extending field extracts starting at
6256 the low-order bit since they are simple AND operations. */
6257 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
6258 && ! in_compare
&& ! spans_byte
&& unsignedp
)
6261 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6262 we would be spanning bytes or if the position is not a constant and the
6263 length is not 1. In all other cases, we would only be going outside
6264 our object in cases when an original shift would have been
6266 if (! spans_byte
&& MEM_P (inner
)
6267 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_BITSIZE (is_mode
))
6268 || (pos_rtx
!= 0 && len
!= 1)))
6271 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6272 and the mode for the result. */
6273 if (in_dest
&& mode_for_extraction (EP_insv
, -1) != MAX_MACHINE_MODE
)
6275 wanted_inner_reg_mode
= mode_for_extraction (EP_insv
, 0);
6276 pos_mode
= mode_for_extraction (EP_insv
, 2);
6277 extraction_mode
= mode_for_extraction (EP_insv
, 3);
6280 if (! in_dest
&& unsignedp
6281 && mode_for_extraction (EP_extzv
, -1) != MAX_MACHINE_MODE
)
6283 wanted_inner_reg_mode
= mode_for_extraction (EP_extzv
, 1);
6284 pos_mode
= mode_for_extraction (EP_extzv
, 3);
6285 extraction_mode
= mode_for_extraction (EP_extzv
, 0);
6288 if (! in_dest
&& ! unsignedp
6289 && mode_for_extraction (EP_extv
, -1) != MAX_MACHINE_MODE
)
6291 wanted_inner_reg_mode
= mode_for_extraction (EP_extv
, 1);
6292 pos_mode
= mode_for_extraction (EP_extv
, 3);
6293 extraction_mode
= mode_for_extraction (EP_extv
, 0);
6296 /* Never narrow an object, since that might not be safe. */
6298 if (mode
!= VOIDmode
6299 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
6300 extraction_mode
= mode
;
6302 if (pos_rtx
&& GET_MODE (pos_rtx
) != VOIDmode
6303 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6304 pos_mode
= GET_MODE (pos_rtx
);
6306 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6307 if we have to change the mode of memory and cannot, the desired mode is
6310 wanted_inner_mode
= wanted_inner_reg_mode
;
6311 else if (inner_mode
!= wanted_inner_mode
6312 && (mode_dependent_address_p (XEXP (inner
, 0))
6313 || MEM_VOLATILE_P (inner
)))
6314 wanted_inner_mode
= extraction_mode
;
6318 if (BITS_BIG_ENDIAN
)
6320 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6321 BITS_BIG_ENDIAN style. If position is constant, compute new
6322 position. Otherwise, build subtraction.
6323 Note that POS is relative to the mode of the original argument.
6324 If it's a MEM we need to recompute POS relative to that.
6325 However, if we're extracting from (or inserting into) a register,
6326 we want to recompute POS relative to wanted_inner_mode. */
6327 int width
= (MEM_P (inner
)
6328 ? GET_MODE_BITSIZE (is_mode
)
6329 : GET_MODE_BITSIZE (wanted_inner_mode
));
6332 pos
= width
- len
- pos
;
6335 = gen_rtx_MINUS (GET_MODE (pos_rtx
), GEN_INT (width
- len
), pos_rtx
);
6336 /* POS may be less than 0 now, but we check for that below.
6337 Note that it can only be less than 0 if !MEM_P (inner). */
6340 /* If INNER has a wider mode, make it smaller. If this is a constant
6341 extract, try to adjust the byte to point to the byte containing
6343 if (wanted_inner_mode
!= VOIDmode
6344 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
6346 && (inner_mode
== wanted_inner_mode
6347 || (! mode_dependent_address_p (XEXP (inner
, 0))
6348 && ! MEM_VOLATILE_P (inner
))))))
6352 /* The computations below will be correct if the machine is big
6353 endian in both bits and bytes or little endian in bits and bytes.
6354 If it is mixed, we must adjust. */
6356 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6357 adjust OFFSET to compensate. */
6358 if (BYTES_BIG_ENDIAN
6360 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
6361 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
6363 /* If this is a constant position, we can move to the desired byte. */
6366 offset
+= pos
/ BITS_PER_UNIT
;
6367 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
6370 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
6372 && is_mode
!= wanted_inner_mode
)
6373 offset
= (GET_MODE_SIZE (is_mode
)
6374 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
6376 if (offset
!= 0 || inner_mode
!= wanted_inner_mode
)
6377 inner
= adjust_address_nv (inner
, wanted_inner_mode
, offset
);
6380 /* If INNER is not memory, we can always get it into the proper mode. If we
6381 are changing its mode, POS must be a constant and smaller than the size
6383 else if (!MEM_P (inner
))
6385 if (GET_MODE (inner
) != wanted_inner_mode
6387 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
6390 inner
= force_to_mode (inner
, wanted_inner_mode
,
6392 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
6393 ? ~(unsigned HOST_WIDE_INT
) 0
6394 : ((((unsigned HOST_WIDE_INT
) 1 << len
) - 1)
6399 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6400 have to zero extend. Otherwise, we can just use a SUBREG. */
6402 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6404 rtx temp
= gen_rtx_ZERO_EXTEND (pos_mode
, pos_rtx
);
6406 /* If we know that no extraneous bits are set, and that the high
6407 bit is not set, convert extraction to cheaper one - either
6408 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6410 if (flag_expensive_optimizations
6411 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx
)) <= HOST_BITS_PER_WIDE_INT
6412 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
6413 & ~(((unsigned HOST_WIDE_INT
)
6414 GET_MODE_MASK (GET_MODE (pos_rtx
)))
6418 rtx temp1
= gen_rtx_SIGN_EXTEND (pos_mode
, pos_rtx
);
6420 /* Prefer ZERO_EXTENSION, since it gives more information to
6422 if (rtx_cost (temp1
, SET
) < rtx_cost (temp
, SET
))
6427 else if (pos_rtx
!= 0
6428 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6429 pos_rtx
= gen_lowpart (pos_mode
, pos_rtx
);
6431 /* Make POS_RTX unless we already have it and it is correct. If we don't
6432 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6434 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
6435 pos_rtx
= orig_pos_rtx
;
6437 else if (pos_rtx
== 0)
6438 pos_rtx
= GEN_INT (pos
);
6440 /* Make the required operation. See if we can use existing rtx. */
6441 new = gen_rtx_fmt_eee (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
6442 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
6444 new = gen_lowpart (mode
, new);
6449 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6450 with any other operations in X. Return X without that shift if so. */
6453 extract_left_shift (rtx x
, int count
)
6455 enum rtx_code code
= GET_CODE (x
);
6456 enum machine_mode mode
= GET_MODE (x
);
6462 /* This is the shift itself. If it is wide enough, we will return
6463 either the value being shifted if the shift count is equal to
6464 COUNT or a shift for the difference. */
6465 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6466 && INTVAL (XEXP (x
, 1)) >= count
)
6467 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
6468 INTVAL (XEXP (x
, 1)) - count
);
6472 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6473 return simplify_gen_unary (code
, mode
, tem
, mode
);
6477 case PLUS
: case IOR
: case XOR
: case AND
:
6478 /* If we can safely shift this constant and we find the inner shift,
6479 make a new operation. */
6480 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6481 && (INTVAL (XEXP (x
, 1)) & ((((HOST_WIDE_INT
) 1 << count
)) - 1)) == 0
6482 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6483 return simplify_gen_binary (code
, mode
, tem
,
6484 GEN_INT (INTVAL (XEXP (x
, 1)) >> count
));
6495 /* Look at the expression rooted at X. Look for expressions
6496 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6497 Form these expressions.
6499 Return the new rtx, usually just X.
6501 Also, for machines like the VAX that don't have logical shift insns,
6502 try to convert logical to arithmetic shift operations in cases where
6503 they are equivalent. This undoes the canonicalizations to logical
6504 shifts done elsewhere.
6506 We try, as much as possible, to re-use rtl expressions to save memory.
6508 IN_CODE says what kind of expression we are processing. Normally, it is
6509 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6510 being kludges), it is MEM. When processing the arguments of a comparison
6511 or a COMPARE against zero, it is COMPARE. */
6514 make_compound_operation (rtx x
, enum rtx_code in_code
)
6516 enum rtx_code code
= GET_CODE (x
);
6517 enum machine_mode mode
= GET_MODE (x
);
6518 int mode_width
= GET_MODE_BITSIZE (mode
);
6520 enum rtx_code next_code
;
6526 /* Select the code to be used in recursive calls. Once we are inside an
6527 address, we stay there. If we have a comparison, set to COMPARE,
6528 but once inside, go back to our default of SET. */
6530 next_code
= (code
== MEM
|| code
== PLUS
|| code
== MINUS
? MEM
6531 : ((code
== COMPARE
|| COMPARISON_P (x
))
6532 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
6533 : in_code
== COMPARE
? SET
: in_code
);
6535 /* Process depending on the code of this operation. If NEW is set
6536 nonzero, it will be returned. */
6541 /* Convert shifts by constants into multiplications if inside
6543 if (in_code
== MEM
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6544 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
6545 && INTVAL (XEXP (x
, 1)) >= 0)
6547 new = make_compound_operation (XEXP (x
, 0), next_code
);
6548 new = gen_rtx_MULT (mode
, new,
6549 GEN_INT ((HOST_WIDE_INT
) 1
6550 << INTVAL (XEXP (x
, 1))));
6555 /* If the second operand is not a constant, we can't do anything
6557 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
6560 /* If the constant is a power of two minus one and the first operand
6561 is a logical right shift, make an extraction. */
6562 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6563 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6565 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6566 new = make_extraction (mode
, new, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
6567 0, in_code
== COMPARE
);
6570 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6571 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
6572 && subreg_lowpart_p (XEXP (x
, 0))
6573 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
6574 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6576 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x
, 0)), 0),
6578 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x
, 0))), new, 0,
6579 XEXP (SUBREG_REG (XEXP (x
, 0)), 1), i
, 1,
6580 0, in_code
== COMPARE
);
6582 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6583 else if ((GET_CODE (XEXP (x
, 0)) == XOR
6584 || GET_CODE (XEXP (x
, 0)) == IOR
)
6585 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
6586 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
6587 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6589 /* Apply the distributive law, and then try to make extractions. */
6590 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)), mode
,
6591 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
6593 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
6595 new = make_compound_operation (new, in_code
);
6598 /* If we are have (and (rotate X C) M) and C is larger than the number
6599 of bits in M, this is an extraction. */
6601 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
6602 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6603 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0
6604 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
6606 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6607 new = make_extraction (mode
, new,
6608 (GET_MODE_BITSIZE (mode
)
6609 - INTVAL (XEXP (XEXP (x
, 0), 1))),
6610 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6613 /* On machines without logical shifts, if the operand of the AND is
6614 a logical shift and our mask turns off all the propagated sign
6615 bits, we can replace the logical shift with an arithmetic shift. */
6616 else if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6617 && !have_insn_for (LSHIFTRT
, mode
)
6618 && have_insn_for (ASHIFTRT
, mode
)
6619 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6620 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
6621 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
6622 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
6624 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
6626 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
6627 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
6629 gen_rtx_ASHIFTRT (mode
,
6630 make_compound_operation
6631 (XEXP (XEXP (x
, 0), 0), next_code
),
6632 XEXP (XEXP (x
, 0), 1)));
6635 /* If the constant is one less than a power of two, this might be
6636 representable by an extraction even if no shift is present.
6637 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6638 we are in a COMPARE. */
6639 else if ((i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6640 new = make_extraction (mode
,
6641 make_compound_operation (XEXP (x
, 0),
6643 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6645 /* If we are in a comparison and this is an AND with a power of two,
6646 convert this into the appropriate bit extract. */
6647 else if (in_code
== COMPARE
6648 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
6649 new = make_extraction (mode
,
6650 make_compound_operation (XEXP (x
, 0),
6652 i
, NULL_RTX
, 1, 1, 0, 1);
6657 /* If the sign bit is known to be zero, replace this with an
6658 arithmetic shift. */
6659 if (have_insn_for (ASHIFTRT
, mode
)
6660 && ! have_insn_for (LSHIFTRT
, mode
)
6661 && mode_width
<= HOST_BITS_PER_WIDE_INT
6662 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
6664 new = gen_rtx_ASHIFTRT (mode
,
6665 make_compound_operation (XEXP (x
, 0),
6671 /* ... fall through ... */
6677 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6678 this is a SIGN_EXTRACT. */
6679 if (GET_CODE (rhs
) == CONST_INT
6680 && GET_CODE (lhs
) == ASHIFT
6681 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
6682 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1)))
6684 new = make_compound_operation (XEXP (lhs
, 0), next_code
);
6685 new = make_extraction (mode
, new,
6686 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
6687 NULL_RTX
, mode_width
- INTVAL (rhs
),
6688 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6692 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6693 If so, try to merge the shifts into a SIGN_EXTEND. We could
6694 also do this for some cases of SIGN_EXTRACT, but it doesn't
6695 seem worth the effort; the case checked for occurs on Alpha. */
6698 && ! (GET_CODE (lhs
) == SUBREG
6699 && (OBJECT_P (SUBREG_REG (lhs
))))
6700 && GET_CODE (rhs
) == CONST_INT
6701 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
6702 && (new = extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
6703 new = make_extraction (mode
, make_compound_operation (new, next_code
),
6704 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
6705 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6710 /* Call ourselves recursively on the inner expression. If we are
6711 narrowing the object and it has a different RTL code from
6712 what it originally did, do this SUBREG as a force_to_mode. */
6714 tem
= make_compound_operation (SUBREG_REG (x
), in_code
);
6715 if (GET_CODE (tem
) != GET_CODE (SUBREG_REG (x
))
6716 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (tem
))
6717 && subreg_lowpart_p (x
))
6719 rtx newer
= force_to_mode (tem
, mode
, ~(HOST_WIDE_INT
) 0,
6722 /* If we have something other than a SUBREG, we might have
6723 done an expansion, so rerun ourselves. */
6724 if (GET_CODE (newer
) != SUBREG
)
6725 newer
= make_compound_operation (newer
, in_code
);
6730 /* If this is a paradoxical subreg, and the new code is a sign or
6731 zero extension, omit the subreg and widen the extension. If it
6732 is a regular subreg, we can still get rid of the subreg by not
6733 widening so much, or in fact removing the extension entirely. */
6734 if ((GET_CODE (tem
) == SIGN_EXTEND
6735 || GET_CODE (tem
) == ZERO_EXTEND
)
6736 && subreg_lowpart_p (x
))
6738 if (GET_MODE_SIZE (mode
) > GET_MODE_SIZE (GET_MODE (tem
))
6739 || (GET_MODE_SIZE (mode
) >
6740 GET_MODE_SIZE (GET_MODE (XEXP (tem
, 0)))))
6742 if (! SCALAR_INT_MODE_P (mode
))
6744 tem
= gen_rtx_fmt_e (GET_CODE (tem
), mode
, XEXP (tem
, 0));
6747 tem
= gen_lowpart (mode
, XEXP (tem
, 0));
6758 x
= gen_lowpart (mode
, new);
6759 code
= GET_CODE (x
);
6762 /* Now recursively process each operand of this operation. */
6763 fmt
= GET_RTX_FORMAT (code
);
6764 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
6767 new = make_compound_operation (XEXP (x
, i
), next_code
);
6768 SUBST (XEXP (x
, i
), new);
6774 /* Given M see if it is a value that would select a field of bits
6775 within an item, but not the entire word. Return -1 if not.
6776 Otherwise, return the starting position of the field, where 0 is the
6779 *PLEN is set to the length of the field. */
6782 get_pos_from_mask (unsigned HOST_WIDE_INT m
, unsigned HOST_WIDE_INT
*plen
)
6784 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6785 int pos
= exact_log2 (m
& -m
);
6789 /* Now shift off the low-order zero bits and see if we have a
6790 power of two minus 1. */
6791 len
= exact_log2 ((m
>> pos
) + 1);
6800 /* See if X can be simplified knowing that we will only refer to it in
6801 MODE and will only refer to those bits that are nonzero in MASK.
6802 If other bits are being computed or if masking operations are done
6803 that select a superset of the bits in MASK, they can sometimes be
6806 Return a possibly simplified expression, but always convert X to
6807 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6809 Also, if REG is nonzero and X is a register equal in value to REG,
6812 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6813 are all off in X. This is used when X will be complemented, by either
6814 NOT, NEG, or XOR. */
6817 force_to_mode (rtx x
, enum machine_mode mode
, unsigned HOST_WIDE_INT mask
,
6818 rtx reg
, int just_select
)
6820 enum rtx_code code
= GET_CODE (x
);
6821 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
6822 enum machine_mode op_mode
;
6823 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
6826 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6827 code below will do the wrong thing since the mode of such an
6828 expression is VOIDmode.
6830 Also do nothing if X is a CLOBBER; this can happen if X was
6831 the return value from a call to gen_lowpart. */
6832 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
6835 /* We want to perform the operation is its present mode unless we know
6836 that the operation is valid in MODE, in which case we do the operation
6838 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
6839 && have_insn_for (code
, mode
))
6840 ? mode
: GET_MODE (x
));
6842 /* It is not valid to do a right-shift in a narrower mode
6843 than the one it came in with. */
6844 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
6845 && GET_MODE_BITSIZE (mode
) < GET_MODE_BITSIZE (GET_MODE (x
)))
6846 op_mode
= GET_MODE (x
);
6848 /* Truncate MASK to fit OP_MODE. */
6850 mask
&= GET_MODE_MASK (op_mode
);
6852 /* When we have an arithmetic operation, or a shift whose count we
6853 do not know, we need to assume that all bits up to the highest-order
6854 bit in MASK will be needed. This is how we form such a mask. */
6855 if (mask
& ((unsigned HOST_WIDE_INT
) 1 << (HOST_BITS_PER_WIDE_INT
- 1)))
6856 fuller_mask
= ~(unsigned HOST_WIDE_INT
) 0;
6858 fuller_mask
= (((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mask
) + 1))
6861 /* Determine what bits of X are guaranteed to be (non)zero. */
6862 nonzero
= nonzero_bits (x
, mode
);
6864 /* If none of the bits in X are needed, return a zero. */
6865 if (! just_select
&& (nonzero
& mask
) == 0)
6868 /* If X is a CONST_INT, return a new one. Do this here since the
6869 test below will fail. */
6870 if (GET_CODE (x
) == CONST_INT
)
6872 if (SCALAR_INT_MODE_P (mode
))
6873 return gen_int_mode (INTVAL (x
) & mask
, mode
);
6876 x
= GEN_INT (INTVAL (x
) & mask
);
6877 return gen_lowpart_common (mode
, x
);
6881 /* If X is narrower than MODE and we want all the bits in X's mode, just
6882 get X in the proper mode. */
6883 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
6884 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
6885 return gen_lowpart (mode
, x
);
6890 /* If X is a (clobber (const_int)), return it since we know we are
6891 generating something that won't match. */
6895 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6896 spanned the boundary of the MEM. If we are now masking so it is
6897 within that boundary, we don't need the USE any more. */
6898 if (! BITS_BIG_ENDIAN
6899 && (mask
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6900 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
6907 x
= expand_compound_operation (x
);
6908 if (GET_CODE (x
) != code
)
6909 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6913 if (reg
!= 0 && (rtx_equal_p (get_last_value (reg
), x
)
6914 || rtx_equal_p (reg
, get_last_value (x
))))
6919 if (subreg_lowpart_p (x
)
6920 /* We can ignore the effect of this SUBREG if it narrows the mode or
6921 if the constant masks to zero all the bits the mode doesn't
6923 && ((GET_MODE_SIZE (GET_MODE (x
))
6924 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
6926 & GET_MODE_MASK (GET_MODE (x
))
6927 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
6928 return force_to_mode (SUBREG_REG (x
), mode
, mask
, reg
, next_select
);
6932 /* If this is an AND with a constant, convert it into an AND
6933 whose constant is the AND of that constant with MASK. If it
6934 remains an AND of MASK, delete it since it is redundant. */
6936 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
6938 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
6939 mask
& INTVAL (XEXP (x
, 1)));
6941 /* If X is still an AND, see if it is an AND with a mask that
6942 is just some low-order bits. If so, and it is MASK, we don't
6945 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6946 && ((INTVAL (XEXP (x
, 1)) & GET_MODE_MASK (GET_MODE (x
)))
6950 /* If it remains an AND, try making another AND with the bits
6951 in the mode mask that aren't in MASK turned on. If the
6952 constant in the AND is wide enough, this might make a
6953 cheaper constant. */
6955 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6956 && GET_MODE_MASK (GET_MODE (x
)) != mask
6957 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
6959 HOST_WIDE_INT cval
= (INTVAL (XEXP (x
, 1))
6960 | (GET_MODE_MASK (GET_MODE (x
)) & ~mask
));
6961 int width
= GET_MODE_BITSIZE (GET_MODE (x
));
6964 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
6965 number, sign extend it. */
6966 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
6967 && (cval
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6968 cval
|= (HOST_WIDE_INT
) -1 << width
;
6970 y
= simplify_gen_binary (AND
, GET_MODE (x
),
6971 XEXP (x
, 0), GEN_INT (cval
));
6972 if (rtx_cost (y
, SET
) < rtx_cost (x
, SET
))
6982 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6983 low-order bits (as in an alignment operation) and FOO is already
6984 aligned to that boundary, mask C1 to that boundary as well.
6985 This may eliminate that PLUS and, later, the AND. */
6988 unsigned int width
= GET_MODE_BITSIZE (mode
);
6989 unsigned HOST_WIDE_INT smask
= mask
;
6991 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6992 number, sign extend it. */
6994 if (width
< HOST_BITS_PER_WIDE_INT
6995 && (smask
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6996 smask
|= (HOST_WIDE_INT
) -1 << width
;
6998 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6999 && exact_log2 (- smask
) >= 0
7000 && (nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
7001 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
7002 return force_to_mode (plus_constant (XEXP (x
, 0),
7003 (INTVAL (XEXP (x
, 1)) & smask
)),
7004 mode
, smask
, reg
, next_select
);
7007 /* ... fall through ... */
7010 /* For PLUS, MINUS and MULT, we need any bits less significant than the
7011 most significant bit in MASK since carries from those bits will
7012 affect the bits we are interested in. */
7017 /* If X is (minus C Y) where C's least set bit is larger than any bit
7018 in the mask, then we may replace with (neg Y). */
7019 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
7020 && (((unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 0))
7021 & -INTVAL (XEXP (x
, 0))))
7024 x
= simplify_gen_unary (NEG
, GET_MODE (x
), XEXP (x
, 1),
7026 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7029 /* Similarly, if C contains every bit in the fuller_mask, then we may
7030 replace with (not Y). */
7031 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
7032 && ((INTVAL (XEXP (x
, 0)) | (HOST_WIDE_INT
) fuller_mask
)
7033 == INTVAL (XEXP (x
, 0))))
7035 x
= simplify_gen_unary (NOT
, GET_MODE (x
),
7036 XEXP (x
, 1), GET_MODE (x
));
7037 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7045 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
7046 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
7047 operation which may be a bitfield extraction. Ensure that the
7048 constant we form is not wider than the mode of X. */
7050 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7051 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7052 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7053 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
7054 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7055 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
7056 + floor_log2 (INTVAL (XEXP (x
, 1))))
7057 < GET_MODE_BITSIZE (GET_MODE (x
)))
7058 && (INTVAL (XEXP (x
, 1))
7059 & ~nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
7061 temp
= GEN_INT ((INTVAL (XEXP (x
, 1)) & mask
)
7062 << INTVAL (XEXP (XEXP (x
, 0), 1)));
7063 temp
= simplify_gen_binary (GET_CODE (x
), GET_MODE (x
),
7064 XEXP (XEXP (x
, 0), 0), temp
);
7065 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
7066 XEXP (XEXP (x
, 0), 1));
7067 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7071 /* For most binary operations, just propagate into the operation and
7072 change the mode if we have an operation of that mode. */
7074 op0
= gen_lowpart (op_mode
,
7075 force_to_mode (XEXP (x
, 0), mode
, mask
,
7077 op1
= gen_lowpart (op_mode
,
7078 force_to_mode (XEXP (x
, 1), mode
, mask
,
7081 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
7082 x
= simplify_gen_binary (code
, op_mode
, op0
, op1
);
7086 /* For left shifts, do the same, but just for the first operand.
7087 However, we cannot do anything with shifts where we cannot
7088 guarantee that the counts are smaller than the size of the mode
7089 because such a count will have a different meaning in a
7092 if (! (GET_CODE (XEXP (x
, 1)) == CONST_INT
7093 && INTVAL (XEXP (x
, 1)) >= 0
7094 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (mode
))
7095 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
7096 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
7097 < (unsigned HOST_WIDE_INT
) GET_MODE_BITSIZE (mode
))))
7100 /* If the shift count is a constant and we can do arithmetic in
7101 the mode of the shift, refine which bits we need. Otherwise, use the
7102 conservative form of the mask. */
7103 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7104 && INTVAL (XEXP (x
, 1)) >= 0
7105 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (op_mode
)
7106 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
7107 mask
>>= INTVAL (XEXP (x
, 1));
7111 op0
= gen_lowpart (op_mode
,
7112 force_to_mode (XEXP (x
, 0), op_mode
,
7113 mask
, reg
, next_select
));
7115 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
7116 x
= simplify_gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
7120 /* Here we can only do something if the shift count is a constant,
7121 this shift constant is valid for the host, and we can do arithmetic
7124 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7125 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
7126 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
7128 rtx inner
= XEXP (x
, 0);
7129 unsigned HOST_WIDE_INT inner_mask
;
7131 /* Select the mask of the bits we need for the shift operand. */
7132 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
7134 /* We can only change the mode of the shift if we can do arithmetic
7135 in the mode of the shift and INNER_MASK is no wider than the
7136 width of X's mode. */
7137 if ((inner_mask
& ~GET_MODE_MASK (GET_MODE (x
))) != 0)
7138 op_mode
= GET_MODE (x
);
7140 inner
= force_to_mode (inner
, op_mode
, inner_mask
, reg
, next_select
);
7142 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
7143 x
= simplify_gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
7146 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7147 shift and AND produces only copies of the sign bit (C2 is one less
7148 than a power of two), we can do this with just a shift. */
7150 if (GET_CODE (x
) == LSHIFTRT
7151 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7152 /* The shift puts one of the sign bit copies in the least significant
7154 && ((INTVAL (XEXP (x
, 1))
7155 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
7156 >= GET_MODE_BITSIZE (GET_MODE (x
)))
7157 && exact_log2 (mask
+ 1) >= 0
7158 /* Number of bits left after the shift must be more than the mask
7160 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
7161 <= GET_MODE_BITSIZE (GET_MODE (x
)))
7162 /* Must be more sign bit copies than the mask needs. */
7163 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
7164 >= exact_log2 (mask
+ 1)))
7165 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
7166 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x
))
7167 - exact_log2 (mask
+ 1)));
7172 /* If we are just looking for the sign bit, we don't need this shift at
7173 all, even if it has a variable count. */
7174 if (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
7175 && (mask
== ((unsigned HOST_WIDE_INT
) 1
7176 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
7177 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
7179 /* If this is a shift by a constant, get a mask that contains those bits
7180 that are not copies of the sign bit. We then have two cases: If
7181 MASK only includes those bits, this can be a logical shift, which may
7182 allow simplifications. If MASK is a single-bit field not within
7183 those bits, we are requesting a copy of the sign bit and hence can
7184 shift the sign bit to the appropriate location. */
7186 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) >= 0
7187 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
7191 /* If the considered data is wider than HOST_WIDE_INT, we can't
7192 represent a mask for all its bits in a single scalar.
7193 But we only care about the lower bits, so calculate these. */
7195 if (GET_MODE_BITSIZE (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
7197 nonzero
= ~(HOST_WIDE_INT
) 0;
7199 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7200 is the number of bits a full-width mask would have set.
7201 We need only shift if these are fewer than nonzero can
7202 hold. If not, we must keep all bits set in nonzero. */
7204 if (GET_MODE_BITSIZE (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
7205 < HOST_BITS_PER_WIDE_INT
)
7206 nonzero
>>= INTVAL (XEXP (x
, 1))
7207 + HOST_BITS_PER_WIDE_INT
7208 - GET_MODE_BITSIZE (GET_MODE (x
)) ;
7212 nonzero
= GET_MODE_MASK (GET_MODE (x
));
7213 nonzero
>>= INTVAL (XEXP (x
, 1));
7216 if ((mask
& ~nonzero
) == 0
7217 || (i
= exact_log2 (mask
)) >= 0)
7219 x
= simplify_shift_const
7220 (x
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
7221 i
< 0 ? INTVAL (XEXP (x
, 1))
7222 : GET_MODE_BITSIZE (GET_MODE (x
)) - 1 - i
);
7224 if (GET_CODE (x
) != ASHIFTRT
)
7225 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7229 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7230 even if the shift count isn't a constant. */
7232 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
7233 XEXP (x
, 0), XEXP (x
, 1));
7237 /* If this is a zero- or sign-extension operation that just affects bits
7238 we don't care about, remove it. Be sure the call above returned
7239 something that is still a shift. */
7241 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
7242 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7243 && INTVAL (XEXP (x
, 1)) >= 0
7244 && (INTVAL (XEXP (x
, 1))
7245 <= GET_MODE_BITSIZE (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
7246 && GET_CODE (XEXP (x
, 0)) == ASHIFT
7247 && XEXP (XEXP (x
, 0), 1) == XEXP (x
, 1))
7248 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
7255 /* If the shift count is constant and we can do computations
7256 in the mode of X, compute where the bits we care about are.
7257 Otherwise, we can't do anything. Don't change the mode of
7258 the shift or propagate MODE into the shift, though. */
7259 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7260 && INTVAL (XEXP (x
, 1)) >= 0)
7262 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
7263 GET_MODE (x
), GEN_INT (mask
),
7265 if (temp
&& GET_CODE (temp
) == CONST_INT
)
7267 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
7268 INTVAL (temp
), reg
, next_select
));
7273 /* If we just want the low-order bit, the NEG isn't needed since it
7274 won't change the low-order bit. */
7276 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, just_select
);
7278 /* We need any bits less significant than the most significant bit in
7279 MASK since carries from those bits will affect the bits we are
7285 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7286 same as the XOR case above. Ensure that the constant we form is not
7287 wider than the mode of X. */
7289 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7290 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7291 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7292 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
7293 < GET_MODE_BITSIZE (GET_MODE (x
)))
7294 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
7296 temp
= gen_int_mode (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)),
7298 temp
= simplify_gen_binary (XOR
, GET_MODE (x
),
7299 XEXP (XEXP (x
, 0), 0), temp
);
7300 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
7301 temp
, XEXP (XEXP (x
, 0), 1));
7303 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7306 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7307 use the full mask inside the NOT. */
7311 op0
= gen_lowpart (op_mode
,
7312 force_to_mode (XEXP (x
, 0), mode
, mask
,
7314 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
7315 x
= simplify_gen_unary (code
, op_mode
, op0
, op_mode
);
7319 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7320 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7321 which is equal to STORE_FLAG_VALUE. */
7322 if ((mask
& ~STORE_FLAG_VALUE
) == 0 && XEXP (x
, 1) == const0_rtx
7323 && GET_MODE (XEXP (x
, 0)) == mode
7324 && exact_log2 (nonzero_bits (XEXP (x
, 0), mode
)) >= 0
7325 && (nonzero_bits (XEXP (x
, 0), mode
)
7326 == (unsigned HOST_WIDE_INT
) STORE_FLAG_VALUE
))
7327 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
7332 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7333 written in a narrower mode. We play it safe and do not do so. */
7336 gen_lowpart (GET_MODE (x
),
7337 force_to_mode (XEXP (x
, 1), mode
,
7338 mask
, reg
, next_select
)));
7340 gen_lowpart (GET_MODE (x
),
7341 force_to_mode (XEXP (x
, 2), mode
,
7342 mask
, reg
, next_select
)));
7349 /* Ensure we return a value of the proper mode. */
7350 return gen_lowpart (mode
, x
);
7353 /* Return nonzero if X is an expression that has one of two values depending on
7354 whether some other value is zero or nonzero. In that case, we return the
7355 value that is being tested, *PTRUE is set to the value if the rtx being
7356 returned has a nonzero value, and *PFALSE is set to the other alternative.
7358 If we return zero, we set *PTRUE and *PFALSE to X. */
7361 if_then_else_cond (rtx x
, rtx
*ptrue
, rtx
*pfalse
)
7363 enum machine_mode mode
= GET_MODE (x
);
7364 enum rtx_code code
= GET_CODE (x
);
7365 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
7366 unsigned HOST_WIDE_INT nz
;
7368 /* If we are comparing a value against zero, we are done. */
7369 if ((code
== NE
|| code
== EQ
)
7370 && XEXP (x
, 1) == const0_rtx
)
7372 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
7373 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
7377 /* If this is a unary operation whose operand has one of two values, apply
7378 our opcode to compute those values. */
7379 else if (UNARY_P (x
)
7380 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
7382 *ptrue
= simplify_gen_unary (code
, mode
, true0
, GET_MODE (XEXP (x
, 0)));
7383 *pfalse
= simplify_gen_unary (code
, mode
, false0
,
7384 GET_MODE (XEXP (x
, 0)));
7388 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7389 make can't possibly match and would suppress other optimizations. */
7390 else if (code
== COMPARE
)
7393 /* If this is a binary operation, see if either side has only one of two
7394 values. If either one does or if both do and they are conditional on
7395 the same value, compute the new true and false values. */
7396 else if (BINARY_P (x
))
7398 cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
);
7399 cond1
= if_then_else_cond (XEXP (x
, 1), &true1
, &false1
);
7401 if ((cond0
!= 0 || cond1
!= 0)
7402 && ! (cond0
!= 0 && cond1
!= 0 && ! rtx_equal_p (cond0
, cond1
)))
7404 /* If if_then_else_cond returned zero, then true/false are the
7405 same rtl. We must copy one of them to prevent invalid rtl
7408 true0
= copy_rtx (true0
);
7409 else if (cond1
== 0)
7410 true1
= copy_rtx (true1
);
7412 if (COMPARISON_P (x
))
7414 *ptrue
= simplify_gen_relational (code
, mode
, VOIDmode
,
7416 *pfalse
= simplify_gen_relational (code
, mode
, VOIDmode
,
7421 *ptrue
= simplify_gen_binary (code
, mode
, true0
, true1
);
7422 *pfalse
= simplify_gen_binary (code
, mode
, false0
, false1
);
7425 return cond0
? cond0
: cond1
;
7428 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7429 operands is zero when the other is nonzero, and vice-versa,
7430 and STORE_FLAG_VALUE is 1 or -1. */
7432 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7433 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
7435 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7437 rtx op0
= XEXP (XEXP (x
, 0), 1);
7438 rtx op1
= XEXP (XEXP (x
, 1), 1);
7440 cond0
= XEXP (XEXP (x
, 0), 0);
7441 cond1
= XEXP (XEXP (x
, 1), 0);
7443 if (COMPARISON_P (cond0
)
7444 && COMPARISON_P (cond1
)
7445 && ((GET_CODE (cond0
) == combine_reversed_comparison_code (cond1
)
7446 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7447 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7448 || ((swap_condition (GET_CODE (cond0
))
7449 == combine_reversed_comparison_code (cond1
))
7450 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7451 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7452 && ! side_effects_p (x
))
7454 *ptrue
= simplify_gen_binary (MULT
, mode
, op0
, const_true_rtx
);
7455 *pfalse
= simplify_gen_binary (MULT
, mode
,
7457 ? simplify_gen_unary (NEG
, mode
,
7465 /* Similarly for MULT, AND and UMIN, except that for these the result
7467 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7468 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
7469 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7471 cond0
= XEXP (XEXP (x
, 0), 0);
7472 cond1
= XEXP (XEXP (x
, 1), 0);
7474 if (COMPARISON_P (cond0
)
7475 && COMPARISON_P (cond1
)
7476 && ((GET_CODE (cond0
) == combine_reversed_comparison_code (cond1
)
7477 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7478 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7479 || ((swap_condition (GET_CODE (cond0
))
7480 == combine_reversed_comparison_code (cond1
))
7481 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7482 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7483 && ! side_effects_p (x
))
7485 *ptrue
= *pfalse
= const0_rtx
;
7491 else if (code
== IF_THEN_ELSE
)
7493 /* If we have IF_THEN_ELSE already, extract the condition and
7494 canonicalize it if it is NE or EQ. */
7495 cond0
= XEXP (x
, 0);
7496 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
7497 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
7498 return XEXP (cond0
, 0);
7499 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
7501 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
7502 return XEXP (cond0
, 0);
7508 /* If X is a SUBREG, we can narrow both the true and false values
7509 if the inner expression, if there is a condition. */
7510 else if (code
== SUBREG
7511 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
7514 true0
= simplify_gen_subreg (mode
, true0
,
7515 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
7516 false0
= simplify_gen_subreg (mode
, false0
,
7517 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
7518 if (true0
&& false0
)
7526 /* If X is a constant, this isn't special and will cause confusions
7527 if we treat it as such. Likewise if it is equivalent to a constant. */
7528 else if (CONSTANT_P (x
)
7529 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
7532 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7533 will be least confusing to the rest of the compiler. */
7534 else if (mode
== BImode
)
7536 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
7540 /* If X is known to be either 0 or -1, those are the true and
7541 false values when testing X. */
7542 else if (x
== constm1_rtx
|| x
== const0_rtx
7543 || (mode
!= VOIDmode
7544 && num_sign_bit_copies (x
, mode
) == GET_MODE_BITSIZE (mode
)))
7546 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
7550 /* Likewise for 0 or a single bit. */
7551 else if (SCALAR_INT_MODE_P (mode
)
7552 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
7553 && exact_log2 (nz
= nonzero_bits (x
, mode
)) >= 0)
7555 *ptrue
= gen_int_mode (nz
, mode
), *pfalse
= const0_rtx
;
7559 /* Otherwise fail; show no condition with true and false values the same. */
7560 *ptrue
= *pfalse
= x
;
7564 /* Return the value of expression X given the fact that condition COND
7565 is known to be true when applied to REG as its first operand and VAL
7566 as its second. X is known to not be shared and so can be modified in
7569 We only handle the simplest cases, and specifically those cases that
7570 arise with IF_THEN_ELSE expressions. */
7573 known_cond (rtx x
, enum rtx_code cond
, rtx reg
, rtx val
)
7575 enum rtx_code code
= GET_CODE (x
);
7580 if (side_effects_p (x
))
7583 /* If either operand of the condition is a floating point value,
7584 then we have to avoid collapsing an EQ comparison. */
7586 && rtx_equal_p (x
, reg
)
7587 && ! FLOAT_MODE_P (GET_MODE (x
))
7588 && ! FLOAT_MODE_P (GET_MODE (val
)))
7591 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
7594 /* If X is (abs REG) and we know something about REG's relationship
7595 with zero, we may be able to simplify this. */
7597 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
7600 case GE
: case GT
: case EQ
:
7603 return simplify_gen_unary (NEG
, GET_MODE (XEXP (x
, 0)),
7605 GET_MODE (XEXP (x
, 0)));
7610 /* The only other cases we handle are MIN, MAX, and comparisons if the
7611 operands are the same as REG and VAL. */
7613 else if (COMPARISON_P (x
) || COMMUTATIVE_ARITH_P (x
))
7615 if (rtx_equal_p (XEXP (x
, 0), val
))
7616 cond
= swap_condition (cond
), temp
= val
, val
= reg
, reg
= temp
;
7618 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
7620 if (COMPARISON_P (x
))
7622 if (comparison_dominates_p (cond
, code
))
7623 return const_true_rtx
;
7625 code
= combine_reversed_comparison_code (x
);
7627 && comparison_dominates_p (cond
, code
))
7632 else if (code
== SMAX
|| code
== SMIN
7633 || code
== UMIN
|| code
== UMAX
)
7635 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
7637 /* Do not reverse the condition when it is NE or EQ.
7638 This is because we cannot conclude anything about
7639 the value of 'SMAX (x, y)' when x is not equal to y,
7640 but we can when x equals y. */
7641 if ((code
== SMAX
|| code
== UMAX
)
7642 && ! (cond
== EQ
|| cond
== NE
))
7643 cond
= reverse_condition (cond
);
7648 return unsignedp
? x
: XEXP (x
, 1);
7650 return unsignedp
? x
: XEXP (x
, 0);
7652 return unsignedp
? XEXP (x
, 1) : x
;
7654 return unsignedp
? XEXP (x
, 0) : x
;
7661 else if (code
== SUBREG
)
7663 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (x
));
7664 rtx
new, r
= known_cond (SUBREG_REG (x
), cond
, reg
, val
);
7666 if (SUBREG_REG (x
) != r
)
7668 /* We must simplify subreg here, before we lose track of the
7669 original inner_mode. */
7670 new = simplify_subreg (GET_MODE (x
), r
,
7671 inner_mode
, SUBREG_BYTE (x
));
7675 SUBST (SUBREG_REG (x
), r
);
7680 /* We don't have to handle SIGN_EXTEND here, because even in the
7681 case of replacing something with a modeless CONST_INT, a
7682 CONST_INT is already (supposed to be) a valid sign extension for
7683 its narrower mode, which implies it's already properly
7684 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
7685 story is different. */
7686 else if (code
== ZERO_EXTEND
)
7688 enum machine_mode inner_mode
= GET_MODE (XEXP (x
, 0));
7689 rtx
new, r
= known_cond (XEXP (x
, 0), cond
, reg
, val
);
7691 if (XEXP (x
, 0) != r
)
7693 /* We must simplify the zero_extend here, before we lose
7694 track of the original inner_mode. */
7695 new = simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
7700 SUBST (XEXP (x
, 0), r
);
7706 fmt
= GET_RTX_FORMAT (code
);
7707 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7710 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
7711 else if (fmt
[i
] == 'E')
7712 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
7713 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
7720 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7721 assignment as a field assignment. */
7724 rtx_equal_for_field_assignment_p (rtx x
, rtx y
)
7726 if (x
== y
|| rtx_equal_p (x
, y
))
7729 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
7732 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7733 Note that all SUBREGs of MEM are paradoxical; otherwise they
7734 would have been rewritten. */
7735 if (MEM_P (x
) && GET_CODE (y
) == SUBREG
7736 && MEM_P (SUBREG_REG (y
))
7737 && rtx_equal_p (SUBREG_REG (y
),
7738 gen_lowpart (GET_MODE (SUBREG_REG (y
)), x
)))
7741 if (MEM_P (y
) && GET_CODE (x
) == SUBREG
7742 && MEM_P (SUBREG_REG (x
))
7743 && rtx_equal_p (SUBREG_REG (x
),
7744 gen_lowpart (GET_MODE (SUBREG_REG (x
)), y
)))
7747 /* We used to see if get_last_value of X and Y were the same but that's
7748 not correct. In one direction, we'll cause the assignment to have
7749 the wrong destination and in the case, we'll import a register into this
7750 insn that might have already have been dead. So fail if none of the
7751 above cases are true. */
7755 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7756 Return that assignment if so.
7758 We only handle the most common cases. */
7761 make_field_assignment (rtx x
)
7763 rtx dest
= SET_DEST (x
);
7764 rtx src
= SET_SRC (x
);
7769 unsigned HOST_WIDE_INT len
;
7771 enum machine_mode mode
;
7773 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7774 a clear of a one-bit field. We will have changed it to
7775 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7778 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
7779 && GET_CODE (XEXP (XEXP (src
, 0), 0)) == CONST_INT
7780 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
7781 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7783 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7786 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7790 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
7791 && subreg_lowpart_p (XEXP (src
, 0))
7792 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
7793 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
7794 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
7795 && GET_CODE (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == CONST_INT
7796 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
7797 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7799 assign
= make_extraction (VOIDmode
, dest
, 0,
7800 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
7803 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7807 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7809 if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
7810 && XEXP (XEXP (src
, 0), 0) == const1_rtx
7811 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7813 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7816 return gen_rtx_SET (VOIDmode
, assign
, const1_rtx
);
7820 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
7821 SRC is an AND with all bits of that field set, then we can discard
7823 if (GET_CODE (dest
) == ZERO_EXTRACT
7824 && GET_CODE (XEXP (dest
, 1)) == CONST_INT
7825 && GET_CODE (src
) == AND
7826 && GET_CODE (XEXP (src
, 1)) == CONST_INT
)
7828 HOST_WIDE_INT width
= INTVAL (XEXP (dest
, 1));
7829 unsigned HOST_WIDE_INT and_mask
= INTVAL (XEXP (src
, 1));
7830 unsigned HOST_WIDE_INT ze_mask
;
7832 if (width
>= HOST_BITS_PER_WIDE_INT
)
7835 ze_mask
= ((unsigned HOST_WIDE_INT
)1 << width
) - 1;
7837 /* Complete overlap. We can remove the source AND. */
7838 if ((and_mask
& ze_mask
) == ze_mask
)
7839 return gen_rtx_SET (VOIDmode
, dest
, XEXP (src
, 0));
7841 /* Partial overlap. We can reduce the source AND. */
7842 if ((and_mask
& ze_mask
) != and_mask
)
7844 mode
= GET_MODE (src
);
7845 src
= gen_rtx_AND (mode
, XEXP (src
, 0),
7846 gen_int_mode (and_mask
& ze_mask
, mode
));
7847 return gen_rtx_SET (VOIDmode
, dest
, src
);
7851 /* The other case we handle is assignments into a constant-position
7852 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7853 a mask that has all one bits except for a group of zero bits and
7854 OTHER is known to have zeros where C1 has ones, this is such an
7855 assignment. Compute the position and length from C1. Shift OTHER
7856 to the appropriate position, force it to the required mode, and
7857 make the extraction. Check for the AND in both operands. */
7859 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
7862 rhs
= expand_compound_operation (XEXP (src
, 0));
7863 lhs
= expand_compound_operation (XEXP (src
, 1));
7865 if (GET_CODE (rhs
) == AND
7866 && GET_CODE (XEXP (rhs
, 1)) == CONST_INT
7867 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
7868 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
7869 else if (GET_CODE (lhs
) == AND
7870 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
7871 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
7872 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
7876 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
7877 if (pos
< 0 || pos
+ len
> GET_MODE_BITSIZE (GET_MODE (dest
))
7878 || GET_MODE_BITSIZE (GET_MODE (dest
)) > HOST_BITS_PER_WIDE_INT
7879 || (c1
& nonzero_bits (other
, GET_MODE (dest
))) != 0)
7882 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
7886 /* The mode to use for the source is the mode of the assignment, or of
7887 what is inside a possible STRICT_LOW_PART. */
7888 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
7889 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
7891 /* Shift OTHER right POS places and make it the source, restricting it
7892 to the proper length and mode. */
7894 src
= force_to_mode (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
7895 GET_MODE (src
), other
, pos
),
7897 GET_MODE_BITSIZE (mode
) >= HOST_BITS_PER_WIDE_INT
7898 ? ~(unsigned HOST_WIDE_INT
) 0
7899 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
7902 /* If SRC is masked by an AND that does not make a difference in
7903 the value being stored, strip it. */
7904 if (GET_CODE (assign
) == ZERO_EXTRACT
7905 && GET_CODE (XEXP (assign
, 1)) == CONST_INT
7906 && INTVAL (XEXP (assign
, 1)) < HOST_BITS_PER_WIDE_INT
7907 && GET_CODE (src
) == AND
7908 && GET_CODE (XEXP (src
, 1)) == CONST_INT
7909 && ((unsigned HOST_WIDE_INT
) INTVAL (XEXP (src
, 1))
7910 == ((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (assign
, 1))) - 1))
7911 src
= XEXP (src
, 0);
7913 return gen_rtx_SET (VOIDmode
, assign
, src
);
7916 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7920 apply_distributive_law (rtx x
)
7922 enum rtx_code code
= GET_CODE (x
);
7923 enum rtx_code inner_code
;
7924 rtx lhs
, rhs
, other
;
7927 /* Distributivity is not true for floating point as it can change the
7928 value. So we don't do it unless -funsafe-math-optimizations. */
7929 if (FLOAT_MODE_P (GET_MODE (x
))
7930 && ! flag_unsafe_math_optimizations
)
7933 /* The outer operation can only be one of the following: */
7934 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
7935 && code
!= PLUS
&& code
!= MINUS
)
7941 /* If either operand is a primitive we can't do anything, so get out
7943 if (OBJECT_P (lhs
) || OBJECT_P (rhs
))
7946 lhs
= expand_compound_operation (lhs
);
7947 rhs
= expand_compound_operation (rhs
);
7948 inner_code
= GET_CODE (lhs
);
7949 if (inner_code
!= GET_CODE (rhs
))
7952 /* See if the inner and outer operations distribute. */
7959 /* These all distribute except over PLUS. */
7960 if (code
== PLUS
|| code
== MINUS
)
7965 if (code
!= PLUS
&& code
!= MINUS
)
7970 /* This is also a multiply, so it distributes over everything. */
7974 /* Non-paradoxical SUBREGs distributes over all operations, provided
7975 the inner modes and byte offsets are the same, this is an extraction
7976 of a low-order part, we don't convert an fp operation to int or
7977 vice versa, and we would not be converting a single-word
7978 operation into a multi-word operation. The latter test is not
7979 required, but it prevents generating unneeded multi-word operations.
7980 Some of the previous tests are redundant given the latter test, but
7981 are retained because they are required for correctness.
7983 We produce the result slightly differently in this case. */
7985 if (GET_MODE (SUBREG_REG (lhs
)) != GET_MODE (SUBREG_REG (rhs
))
7986 || SUBREG_BYTE (lhs
) != SUBREG_BYTE (rhs
)
7987 || ! subreg_lowpart_p (lhs
)
7988 || (GET_MODE_CLASS (GET_MODE (lhs
))
7989 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs
))))
7990 || (GET_MODE_SIZE (GET_MODE (lhs
))
7991 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))))
7992 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))) > UNITS_PER_WORD
)
7995 tem
= simplify_gen_binary (code
, GET_MODE (SUBREG_REG (lhs
)),
7996 SUBREG_REG (lhs
), SUBREG_REG (rhs
));
7997 return gen_lowpart (GET_MODE (x
), tem
);
8003 /* Set LHS and RHS to the inner operands (A and B in the example
8004 above) and set OTHER to the common operand (C in the example).
8005 There is only one way to do this unless the inner operation is
8007 if (COMMUTATIVE_ARITH_P (lhs
)
8008 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
8009 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
8010 else if (COMMUTATIVE_ARITH_P (lhs
)
8011 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
8012 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
8013 else if (COMMUTATIVE_ARITH_P (lhs
)
8014 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
8015 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
8016 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
8017 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
8021 /* Form the new inner operation, seeing if it simplifies first. */
8022 tem
= simplify_gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
8024 /* There is one exception to the general way of distributing:
8025 (a | c) ^ (b | c) -> (a ^ b) & ~c */
8026 if (code
== XOR
&& inner_code
== IOR
)
8029 other
= simplify_gen_unary (NOT
, GET_MODE (x
), other
, GET_MODE (x
));
8032 /* We may be able to continuing distributing the result, so call
8033 ourselves recursively on the inner operation before forming the
8034 outer operation, which we return. */
8035 return simplify_gen_binary (inner_code
, GET_MODE (x
),
8036 apply_distributive_law (tem
), other
);
8039 /* See if X is of the form (* (+ A B) C), and if so convert to
8040 (+ (* A C) (* B C)) and try to simplify.
8042 Most of the time, this results in no change. However, if some of
8043 the operands are the same or inverses of each other, simplifications
8046 For example, (and (ior A B) (not B)) can occur as the result of
8047 expanding a bit field assignment. When we apply the distributive
8048 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
8049 which then simplifies to (and (A (not B))).
8051 Note that no checks happen on the validity of applying the inverse
8052 distributive law. This is pointless since we can do it in the
8053 few places where this routine is called.
8055 N is the index of the term that is decomposed (the arithmetic operation,
8056 i.e. (+ A B) in the first example above). !N is the index of the term that
8057 is distributed, i.e. of C in the first example above. */
8059 distribute_and_simplify_rtx (rtx x
, int n
)
8061 enum machine_mode mode
;
8062 enum rtx_code outer_code
, inner_code
;
8063 rtx decomposed
, distributed
, inner_op0
, inner_op1
, new_op0
, new_op1
, tmp
;
8065 decomposed
= XEXP (x
, n
);
8066 if (!ARITHMETIC_P (decomposed
))
8069 mode
= GET_MODE (x
);
8070 outer_code
= GET_CODE (x
);
8071 distributed
= XEXP (x
, !n
);
8073 inner_code
= GET_CODE (decomposed
);
8074 inner_op0
= XEXP (decomposed
, 0);
8075 inner_op1
= XEXP (decomposed
, 1);
8077 /* Special case (and (xor B C) (not A)), which is equivalent to
8078 (xor (ior A B) (ior A C)) */
8079 if (outer_code
== AND
&& inner_code
== XOR
&& GET_CODE (distributed
) == NOT
)
8081 distributed
= XEXP (distributed
, 0);
8087 /* Distribute the second term. */
8088 new_op0
= simplify_gen_binary (outer_code
, mode
, inner_op0
, distributed
);
8089 new_op1
= simplify_gen_binary (outer_code
, mode
, inner_op1
, distributed
);
8093 /* Distribute the first term. */
8094 new_op0
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op0
);
8095 new_op1
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op1
);
8098 tmp
= apply_distributive_law (simplify_gen_binary (inner_code
, mode
,
8100 if (GET_CODE (tmp
) != outer_code
8101 && rtx_cost (tmp
, SET
) < rtx_cost (x
, SET
))
8107 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
8110 Return an equivalent form, if different from X. Otherwise, return X. If
8111 X is zero, we are to always construct the equivalent form. */
8114 simplify_and_const_int (rtx x
, enum machine_mode mode
, rtx varop
,
8115 unsigned HOST_WIDE_INT constop
)
8117 unsigned HOST_WIDE_INT nonzero
;
8120 /* Simplify VAROP knowing that we will be only looking at some of the
8123 Note by passing in CONSTOP, we guarantee that the bits not set in
8124 CONSTOP are not significant and will never be examined. We must
8125 ensure that is the case by explicitly masking out those bits
8126 before returning. */
8127 varop
= force_to_mode (varop
, mode
, constop
, NULL_RTX
, 0);
8129 /* If VAROP is a CLOBBER, we will fail so return it. */
8130 if (GET_CODE (varop
) == CLOBBER
)
8133 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
8134 to VAROP and return the new constant. */
8135 if (GET_CODE (varop
) == CONST_INT
)
8136 return GEN_INT (trunc_int_for_mode (INTVAL (varop
) & constop
, mode
));
8138 /* See what bits may be nonzero in VAROP. Unlike the general case of
8139 a call to nonzero_bits, here we don't care about bits outside
8142 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
8144 /* Turn off all bits in the constant that are known to already be zero.
8145 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
8146 which is tested below. */
8150 /* If we don't have any bits left, return zero. */
8154 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
8155 a power of two, we can replace this with an ASHIFT. */
8156 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
8157 && (i
= exact_log2 (constop
)) >= 0)
8158 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
8160 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
8161 or XOR, then try to apply the distributive law. This may eliminate
8162 operations if either branch can be simplified because of the AND.
8163 It may also make some cases more complex, but those cases probably
8164 won't match a pattern either with or without this. */
8166 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
8170 apply_distributive_law
8171 (simplify_gen_binary (GET_CODE (varop
), GET_MODE (varop
),
8172 simplify_and_const_int (NULL_RTX
,
8176 simplify_and_const_int (NULL_RTX
,
8181 /* If VAROP is PLUS, and the constant is a mask of low bite, distribute
8182 the AND and see if one of the operands simplifies to zero. If so, we
8183 may eliminate it. */
8185 if (GET_CODE (varop
) == PLUS
8186 && exact_log2 (constop
+ 1) >= 0)
8190 o0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 0), constop
);
8191 o1
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 1), constop
);
8192 if (o0
== const0_rtx
)
8194 if (o1
== const0_rtx
)
8198 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
8199 if we already had one (just check for the simplest cases). */
8200 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
8201 && GET_MODE (XEXP (x
, 0)) == mode
8202 && SUBREG_REG (XEXP (x
, 0)) == varop
)
8203 varop
= XEXP (x
, 0);
8205 varop
= gen_lowpart (mode
, varop
);
8207 /* If we can't make the SUBREG, try to return what we were given. */
8208 if (GET_CODE (varop
) == CLOBBER
)
8209 return x
? x
: varop
;
8211 /* If we are only masking insignificant bits, return VAROP. */
8212 if (constop
== nonzero
)
8216 /* Otherwise, return an AND. */
8217 constop
= trunc_int_for_mode (constop
, mode
);
8218 /* See how much, if any, of X we can use. */
8219 if (x
== 0 || GET_CODE (x
) != AND
|| GET_MODE (x
) != mode
)
8220 x
= simplify_gen_binary (AND
, mode
, varop
, GEN_INT (constop
));
8224 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
8225 || (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) != constop
)
8226 SUBST (XEXP (x
, 1), GEN_INT (constop
));
8228 SUBST (XEXP (x
, 0), varop
);
8235 /* Given a REG, X, compute which bits in X can be nonzero.
8236 We don't care about bits outside of those defined in MODE.
8238 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8239 a shift, AND, or zero_extract, we can do better. */
8242 reg_nonzero_bits_for_combine (rtx x
, enum machine_mode mode
,
8243 rtx known_x ATTRIBUTE_UNUSED
,
8244 enum machine_mode known_mode ATTRIBUTE_UNUSED
,
8245 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED
,
8246 unsigned HOST_WIDE_INT
*nonzero
)
8250 /* If X is a register whose nonzero bits value is current, use it.
8251 Otherwise, if X is a register whose value we can find, use that
8252 value. Otherwise, use the previously-computed global nonzero bits
8253 for this register. */
8255 if (reg_stat
[REGNO (x
)].last_set_value
!= 0
8256 && (reg_stat
[REGNO (x
)].last_set_mode
== mode
8257 || (GET_MODE_CLASS (reg_stat
[REGNO (x
)].last_set_mode
) == MODE_INT
8258 && GET_MODE_CLASS (mode
) == MODE_INT
))
8259 && (reg_stat
[REGNO (x
)].last_set_label
== label_tick
8260 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8261 && REG_N_SETS (REGNO (x
)) == 1
8262 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
,
8264 && INSN_CUID (reg_stat
[REGNO (x
)].last_set
) < subst_low_cuid
)
8266 *nonzero
&= reg_stat
[REGNO (x
)].last_set_nonzero_bits
;
8270 tem
= get_last_value (x
);
8274 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8275 /* If X is narrower than MODE and TEM is a non-negative
8276 constant that would appear negative in the mode of X,
8277 sign-extend it for use in reg_nonzero_bits because some
8278 machines (maybe most) will actually do the sign-extension
8279 and this is the conservative approach.
8281 ??? For 2.5, try to tighten up the MD files in this regard
8282 instead of this kludge. */
8284 if (GET_MODE_BITSIZE (GET_MODE (x
)) < GET_MODE_BITSIZE (mode
)
8285 && GET_CODE (tem
) == CONST_INT
8287 && 0 != (INTVAL (tem
)
8288 & ((HOST_WIDE_INT
) 1
8289 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
8290 tem
= GEN_INT (INTVAL (tem
)
8291 | ((HOST_WIDE_INT
) (-1)
8292 << GET_MODE_BITSIZE (GET_MODE (x
))));
8296 else if (nonzero_sign_valid
&& reg_stat
[REGNO (x
)].nonzero_bits
)
8298 unsigned HOST_WIDE_INT mask
= reg_stat
[REGNO (x
)].nonzero_bits
;
8300 if (GET_MODE_BITSIZE (GET_MODE (x
)) < GET_MODE_BITSIZE (mode
))
8301 /* We don't know anything about the upper bits. */
8302 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (GET_MODE (x
));
8309 /* Return the number of bits at the high-order end of X that are known to
8310 be equal to the sign bit. X will be used in mode MODE; if MODE is
8311 VOIDmode, X will be used in its own mode. The returned value will always
8312 be between 1 and the number of bits in MODE. */
8315 reg_num_sign_bit_copies_for_combine (rtx x
, enum machine_mode mode
,
8316 rtx known_x ATTRIBUTE_UNUSED
,
8317 enum machine_mode known_mode
8319 unsigned int known_ret ATTRIBUTE_UNUSED
,
8320 unsigned int *result
)
8324 if (reg_stat
[REGNO (x
)].last_set_value
!= 0
8325 && reg_stat
[REGNO (x
)].last_set_mode
== mode
8326 && (reg_stat
[REGNO (x
)].last_set_label
== label_tick
8327 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8328 && REG_N_SETS (REGNO (x
)) == 1
8329 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
,
8331 && INSN_CUID (reg_stat
[REGNO (x
)].last_set
) < subst_low_cuid
)
8333 *result
= reg_stat
[REGNO (x
)].last_set_sign_bit_copies
;
8337 tem
= get_last_value (x
);
8341 if (nonzero_sign_valid
&& reg_stat
[REGNO (x
)].sign_bit_copies
!= 0
8342 && GET_MODE_BITSIZE (GET_MODE (x
)) == GET_MODE_BITSIZE (mode
))
8343 *result
= reg_stat
[REGNO (x
)].sign_bit_copies
;
8348 /* Return the number of "extended" bits there are in X, when interpreted
8349 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8350 unsigned quantities, this is the number of high-order zero bits.
8351 For signed quantities, this is the number of copies of the sign bit
8352 minus 1. In both case, this function returns the number of "spare"
8353 bits. For example, if two quantities for which this function returns
8354 at least 1 are added, the addition is known not to overflow.
8356 This function will always return 0 unless called during combine, which
8357 implies that it must be called from a define_split. */
8360 extended_count (rtx x
, enum machine_mode mode
, int unsignedp
)
8362 if (nonzero_sign_valid
== 0)
8366 ? (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
8367 ? (unsigned int) (GET_MODE_BITSIZE (mode
) - 1
8368 - floor_log2 (nonzero_bits (x
, mode
)))
8370 : num_sign_bit_copies (x
, mode
) - 1);
8373 /* This function is called from `simplify_shift_const' to merge two
8374 outer operations. Specifically, we have already found that we need
8375 to perform operation *POP0 with constant *PCONST0 at the outermost
8376 position. We would now like to also perform OP1 with constant CONST1
8377 (with *POP0 being done last).
8379 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8380 the resulting operation. *PCOMP_P is set to 1 if we would need to
8381 complement the innermost operand, otherwise it is unchanged.
8383 MODE is the mode in which the operation will be done. No bits outside
8384 the width of this mode matter. It is assumed that the width of this mode
8385 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8387 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
8388 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8389 result is simply *PCONST0.
8391 If the resulting operation cannot be expressed as one operation, we
8392 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8395 merge_outer_ops (enum rtx_code
*pop0
, HOST_WIDE_INT
*pconst0
, enum rtx_code op1
, HOST_WIDE_INT const1
, enum machine_mode mode
, int *pcomp_p
)
8397 enum rtx_code op0
= *pop0
;
8398 HOST_WIDE_INT const0
= *pconst0
;
8400 const0
&= GET_MODE_MASK (mode
);
8401 const1
&= GET_MODE_MASK (mode
);
8403 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8407 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
8410 if (op1
== UNKNOWN
|| op0
== SET
)
8413 else if (op0
== UNKNOWN
)
8414 op0
= op1
, const0
= const1
;
8416 else if (op0
== op1
)
8440 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8441 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
8444 /* If the two constants aren't the same, we can't do anything. The
8445 remaining six cases can all be done. */
8446 else if (const0
!= const1
)
8454 /* (a & b) | b == b */
8456 else /* op1 == XOR */
8457 /* (a ^ b) | b == a | b */
8463 /* (a & b) ^ b == (~a) & b */
8464 op0
= AND
, *pcomp_p
= 1;
8465 else /* op1 == IOR */
8466 /* (a | b) ^ b == a & ~b */
8467 op0
= AND
, const0
= ~const0
;
8472 /* (a | b) & b == b */
8474 else /* op1 == XOR */
8475 /* (a ^ b) & b) == (~a) & b */
8482 /* Check for NO-OP cases. */
8483 const0
&= GET_MODE_MASK (mode
);
8485 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
8487 else if (const0
== 0 && op0
== AND
)
8489 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
8493 /* ??? Slightly redundant with the above mask, but not entirely.
8494 Moving this above means we'd have to sign-extend the mode mask
8495 for the final test. */
8496 const0
= trunc_int_for_mode (const0
, mode
);
8504 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8505 The result of the shift is RESULT_MODE. X, if nonzero, is an expression
8506 that we started with.
8508 The shift is normally computed in the widest mode we find in VAROP, as
8509 long as it isn't a different number of words than RESULT_MODE. Exceptions
8510 are ASHIFTRT and ROTATE, which are always done in their original mode, */
8513 simplify_shift_const (rtx x
, enum rtx_code code
,
8514 enum machine_mode result_mode
, rtx varop
,
8517 enum rtx_code orig_code
= code
;
8520 enum machine_mode mode
= result_mode
;
8521 enum machine_mode shift_mode
, tmode
;
8522 unsigned int mode_words
8523 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
8524 /* We form (outer_op (code varop count) (outer_const)). */
8525 enum rtx_code outer_op
= UNKNOWN
;
8526 HOST_WIDE_INT outer_const
= 0;
8528 int complement_p
= 0;
8531 /* Make sure and truncate the "natural" shift on the way in. We don't
8532 want to do this inside the loop as it makes it more difficult to
8534 if (SHIFT_COUNT_TRUNCATED
)
8535 orig_count
&= GET_MODE_BITSIZE (mode
) - 1;
8537 /* If we were given an invalid count, don't do anything except exactly
8538 what was requested. */
8540 if (orig_count
< 0 || orig_count
>= (int) GET_MODE_BITSIZE (mode
))
8545 return gen_rtx_fmt_ee (code
, mode
, varop
, GEN_INT (orig_count
));
8550 /* Unless one of the branches of the `if' in this loop does a `continue',
8551 we will `break' the loop after the `if'. */
8555 /* If we have an operand of (clobber (const_int 0)), just return that
8557 if (GET_CODE (varop
) == CLOBBER
)
8560 /* If we discovered we had to complement VAROP, leave. Making a NOT
8561 here would cause an infinite loop. */
8565 /* Convert ROTATERT to ROTATE. */
8566 if (code
== ROTATERT
)
8568 unsigned int bitsize
= GET_MODE_BITSIZE (result_mode
);;
8570 if (VECTOR_MODE_P (result_mode
))
8571 count
= bitsize
/ GET_MODE_NUNITS (result_mode
) - count
;
8573 count
= bitsize
- count
;
8576 /* We need to determine what mode we will do the shift in. If the
8577 shift is a right shift or a ROTATE, we must always do it in the mode
8578 it was originally done in. Otherwise, we can do it in MODE, the
8579 widest mode encountered. */
8581 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
8582 ? result_mode
: mode
);
8584 /* Handle cases where the count is greater than the size of the mode
8585 minus 1. For ASHIFT, use the size minus one as the count (this can
8586 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
8587 take the count modulo the size. For other shifts, the result is
8590 Since these shifts are being produced by the compiler by combining
8591 multiple operations, each of which are defined, we know what the
8592 result is supposed to be. */
8594 if (count
> (unsigned int) (GET_MODE_BITSIZE (shift_mode
) - 1))
8596 if (code
== ASHIFTRT
)
8597 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
8598 else if (code
== ROTATE
|| code
== ROTATERT
)
8599 count
%= GET_MODE_BITSIZE (shift_mode
);
8602 /* We can't simply return zero because there may be an
8610 /* An arithmetic right shift of a quantity known to be -1 or 0
8612 if (code
== ASHIFTRT
8613 && (num_sign_bit_copies (varop
, shift_mode
)
8614 == GET_MODE_BITSIZE (shift_mode
)))
8620 /* If we are doing an arithmetic right shift and discarding all but
8621 the sign bit copies, this is equivalent to doing a shift by the
8622 bitsize minus one. Convert it into that shift because it will often
8623 allow other simplifications. */
8625 if (code
== ASHIFTRT
8626 && (count
+ num_sign_bit_copies (varop
, shift_mode
)
8627 >= GET_MODE_BITSIZE (shift_mode
)))
8628 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
8630 /* We simplify the tests below and elsewhere by converting
8631 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8632 `make_compound_operation' will convert it to an ASHIFTRT for
8633 those machines (such as VAX) that don't have an LSHIFTRT. */
8634 if (GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
8636 && ((nonzero_bits (varop
, shift_mode
)
8637 & ((HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (shift_mode
) - 1)))
8641 if (code
== LSHIFTRT
8642 && GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
8643 && !(nonzero_bits (varop
, shift_mode
) >> count
))
8646 && GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
8647 && !((nonzero_bits (varop
, shift_mode
) << count
)
8648 & GET_MODE_MASK (shift_mode
)))
8651 switch (GET_CODE (varop
))
8657 new = expand_compound_operation (varop
);
8666 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8667 minus the width of a smaller mode, we can do this with a
8668 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
8669 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
8670 && ! mode_dependent_address_p (XEXP (varop
, 0))
8671 && ! MEM_VOLATILE_P (varop
)
8672 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
8673 MODE_INT
, 1)) != BLKmode
)
8675 new = adjust_address_nv (varop
, tmode
,
8676 BYTES_BIG_ENDIAN
? 0
8677 : count
/ BITS_PER_UNIT
);
8679 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
8680 : ZERO_EXTEND
, mode
, new);
8687 /* Similar to the case above, except that we can only do this if
8688 the resulting mode is the same as that of the underlying
8689 MEM and adjust the address depending on the *bits* endianness
8690 because of the way that bit-field extract insns are defined. */
8691 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
8692 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
8693 MODE_INT
, 1)) != BLKmode
8694 && tmode
== GET_MODE (XEXP (varop
, 0)))
8696 if (BITS_BIG_ENDIAN
)
8697 new = XEXP (varop
, 0);
8700 new = copy_rtx (XEXP (varop
, 0));
8701 SUBST (XEXP (new, 0),
8702 plus_constant (XEXP (new, 0),
8703 count
/ BITS_PER_UNIT
));
8706 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
8707 : ZERO_EXTEND
, mode
, new);
8714 /* If VAROP is a SUBREG, strip it as long as the inner operand has
8715 the same number of words as what we've seen so far. Then store
8716 the widest mode in MODE. */
8717 if (subreg_lowpart_p (varop
)
8718 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
8719 > GET_MODE_SIZE (GET_MODE (varop
)))
8720 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
8721 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
8724 varop
= SUBREG_REG (varop
);
8725 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
8726 mode
= GET_MODE (varop
);
8732 /* Some machines use MULT instead of ASHIFT because MULT
8733 is cheaper. But it is still better on those machines to
8734 merge two shifts into one. */
8735 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
8736 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
8739 = simplify_gen_binary (ASHIFT
, GET_MODE (varop
),
8741 GEN_INT (exact_log2 (
8742 INTVAL (XEXP (varop
, 1)))));
8748 /* Similar, for when divides are cheaper. */
8749 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
8750 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
8753 = simplify_gen_binary (LSHIFTRT
, GET_MODE (varop
),
8755 GEN_INT (exact_log2 (
8756 INTVAL (XEXP (varop
, 1)))));
8762 /* If we are extracting just the sign bit of an arithmetic
8763 right shift, that shift is not needed. However, the sign
8764 bit of a wider mode may be different from what would be
8765 interpreted as the sign bit in a narrower mode, so, if
8766 the result is narrower, don't discard the shift. */
8767 if (code
== LSHIFTRT
8768 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
8769 && (GET_MODE_BITSIZE (result_mode
)
8770 >= GET_MODE_BITSIZE (GET_MODE (varop
))))
8772 varop
= XEXP (varop
, 0);
8776 /* ... fall through ... */
8781 /* Here we have two nested shifts. The result is usually the
8782 AND of a new shift with a mask. We compute the result below. */
8783 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
8784 && INTVAL (XEXP (varop
, 1)) >= 0
8785 && INTVAL (XEXP (varop
, 1)) < GET_MODE_BITSIZE (GET_MODE (varop
))
8786 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
8787 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
8789 enum rtx_code first_code
= GET_CODE (varop
);
8790 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
8791 unsigned HOST_WIDE_INT mask
;
8794 /* We have one common special case. We can't do any merging if
8795 the inner code is an ASHIFTRT of a smaller mode. However, if
8796 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
8797 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
8798 we can convert it to
8799 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
8800 This simplifies certain SIGN_EXTEND operations. */
8801 if (code
== ASHIFT
&& first_code
== ASHIFTRT
8802 && count
== (unsigned int)
8803 (GET_MODE_BITSIZE (result_mode
)
8804 - GET_MODE_BITSIZE (GET_MODE (varop
))))
8806 /* C3 has the low-order C1 bits zero. */
8808 mask
= (GET_MODE_MASK (mode
)
8809 & ~(((HOST_WIDE_INT
) 1 << first_count
) - 1));
8811 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
8812 XEXP (varop
, 0), mask
);
8813 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
8815 count
= first_count
;
8820 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
8821 than C1 high-order bits equal to the sign bit, we can convert
8822 this to either an ASHIFT or an ASHIFTRT depending on the
8825 We cannot do this if VAROP's mode is not SHIFT_MODE. */
8827 if (code
== ASHIFTRT
&& first_code
== ASHIFT
8828 && GET_MODE (varop
) == shift_mode
8829 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
8832 varop
= XEXP (varop
, 0);
8834 signed_count
= count
- first_count
;
8835 if (signed_count
< 0)
8836 count
= -signed_count
, code
= ASHIFT
;
8838 count
= signed_count
;
8843 /* There are some cases we can't do. If CODE is ASHIFTRT,
8844 we can only do this if FIRST_CODE is also ASHIFTRT.
8846 We can't do the case when CODE is ROTATE and FIRST_CODE is
8849 If the mode of this shift is not the mode of the outer shift,
8850 we can't do this if either shift is a right shift or ROTATE.
8852 Finally, we can't do any of these if the mode is too wide
8853 unless the codes are the same.
8855 Handle the case where the shift codes are the same
8858 if (code
== first_code
)
8860 if (GET_MODE (varop
) != result_mode
8861 && (code
== ASHIFTRT
|| code
== LSHIFTRT
8865 count
+= first_count
;
8866 varop
= XEXP (varop
, 0);
8870 if (code
== ASHIFTRT
8871 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
8872 || GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
8873 || (GET_MODE (varop
) != result_mode
8874 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
8875 || first_code
== ROTATE
8876 || code
== ROTATE
)))
8879 /* To compute the mask to apply after the shift, shift the
8880 nonzero bits of the inner shift the same way the
8881 outer shift will. */
8883 mask_rtx
= GEN_INT (nonzero_bits (varop
, GET_MODE (varop
)));
8886 = simplify_binary_operation (code
, result_mode
, mask_rtx
,
8889 /* Give up if we can't compute an outer operation to use. */
8891 || GET_CODE (mask_rtx
) != CONST_INT
8892 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
8894 result_mode
, &complement_p
))
8897 /* If the shifts are in the same direction, we add the
8898 counts. Otherwise, we subtract them. */
8899 signed_count
= count
;
8900 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
8901 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
8902 signed_count
+= first_count
;
8904 signed_count
-= first_count
;
8906 /* If COUNT is positive, the new shift is usually CODE,
8907 except for the two exceptions below, in which case it is
8908 FIRST_CODE. If the count is negative, FIRST_CODE should
8910 if (signed_count
> 0
8911 && ((first_code
== ROTATE
&& code
== ASHIFT
)
8912 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
8913 code
= first_code
, count
= signed_count
;
8914 else if (signed_count
< 0)
8915 code
= first_code
, count
= -signed_count
;
8917 count
= signed_count
;
8919 varop
= XEXP (varop
, 0);
8923 /* If we have (A << B << C) for any shift, we can convert this to
8924 (A << C << B). This wins if A is a constant. Only try this if
8925 B is not a constant. */
8927 else if (GET_CODE (varop
) == code
8928 && GET_CODE (XEXP (varop
, 1)) != CONST_INT
8930 = simplify_binary_operation (code
, mode
,
8934 varop
= gen_rtx_fmt_ee (code
, mode
, new, XEXP (varop
, 1));
8941 /* Make this fit the case below. */
8942 varop
= gen_rtx_XOR (mode
, XEXP (varop
, 0),
8943 GEN_INT (GET_MODE_MASK (mode
)));
8949 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
8950 with C the size of VAROP - 1 and the shift is logical if
8951 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8952 we have an (le X 0) operation. If we have an arithmetic shift
8953 and STORE_FLAG_VALUE is 1 or we have a logical shift with
8954 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
8956 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
8957 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
8958 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
8959 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
8960 && count
== (unsigned int)
8961 (GET_MODE_BITSIZE (GET_MODE (varop
)) - 1)
8962 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
8965 varop
= gen_rtx_LE (GET_MODE (varop
), XEXP (varop
, 1),
8968 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
8969 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
8974 /* If we have (shift (logical)), move the logical to the outside
8975 to allow it to possibly combine with another logical and the
8976 shift to combine with another shift. This also canonicalizes to
8977 what a ZERO_EXTRACT looks like. Also, some machines have
8978 (and (shift)) insns. */
8980 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
8981 /* We can't do this if we have (ashiftrt (xor)) and the
8982 constant has its sign bit set in shift_mode. */
8983 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
8984 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
8986 && (new = simplify_binary_operation (code
, result_mode
,
8988 GEN_INT (count
))) != 0
8989 && GET_CODE (new) == CONST_INT
8990 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
8991 INTVAL (new), result_mode
, &complement_p
))
8993 varop
= XEXP (varop
, 0);
8997 /* If we can't do that, try to simplify the shift in each arm of the
8998 logical expression, make a new logical expression, and apply
8999 the inverse distributive law. This also can't be done
9000 for some (ashiftrt (xor)). */
9001 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9002 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
9003 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
9006 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
9007 XEXP (varop
, 0), count
);
9008 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
9009 XEXP (varop
, 1), count
);
9011 varop
= simplify_gen_binary (GET_CODE (varop
), shift_mode
,
9013 varop
= apply_distributive_law (varop
);
9021 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9022 says that the sign bit can be tested, FOO has mode MODE, C is
9023 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9024 that may be nonzero. */
9025 if (code
== LSHIFTRT
9026 && XEXP (varop
, 1) == const0_rtx
9027 && GET_MODE (XEXP (varop
, 0)) == result_mode
9028 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9029 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9030 && ((STORE_FLAG_VALUE
9031 & ((HOST_WIDE_INT
) 1
9032 < (GET_MODE_BITSIZE (result_mode
) - 1))))
9033 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9034 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9035 (HOST_WIDE_INT
) 1, result_mode
,
9038 varop
= XEXP (varop
, 0);
9045 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9046 than the number of bits in the mode is equivalent to A. */
9047 if (code
== LSHIFTRT
9048 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9049 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
9051 varop
= XEXP (varop
, 0);
9056 /* NEG commutes with ASHIFT since it is multiplication. Move the
9057 NEG outside to allow shifts to combine. */
9059 && merge_outer_ops (&outer_op
, &outer_const
, NEG
,
9060 (HOST_WIDE_INT
) 0, result_mode
,
9063 varop
= XEXP (varop
, 0);
9069 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9070 is one less than the number of bits in the mode is
9071 equivalent to (xor A 1). */
9072 if (code
== LSHIFTRT
9073 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9074 && XEXP (varop
, 1) == constm1_rtx
9075 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9076 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9077 (HOST_WIDE_INT
) 1, result_mode
,
9081 varop
= XEXP (varop
, 0);
9085 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9086 that might be nonzero in BAR are those being shifted out and those
9087 bits are known zero in FOO, we can replace the PLUS with FOO.
9088 Similarly in the other operand order. This code occurs when
9089 we are computing the size of a variable-size array. */
9091 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9092 && count
< HOST_BITS_PER_WIDE_INT
9093 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
9094 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
9095 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
9097 varop
= XEXP (varop
, 0);
9100 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9101 && count
< HOST_BITS_PER_WIDE_INT
9102 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9103 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9105 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9106 & nonzero_bits (XEXP (varop
, 1),
9109 varop
= XEXP (varop
, 1);
9113 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9115 && GET_CODE (XEXP (varop
, 1)) == CONST_INT
9116 && (new = simplify_binary_operation (ASHIFT
, result_mode
,
9118 GEN_INT (count
))) != 0
9119 && GET_CODE (new) == CONST_INT
9120 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
9121 INTVAL (new), result_mode
, &complement_p
))
9123 varop
= XEXP (varop
, 0);
9127 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
9128 signbit', and attempt to change the PLUS to an XOR and move it to
9129 the outer operation as is done above in the AND/IOR/XOR case
9130 leg for shift(logical). See details in logical handling above
9131 for reasoning in doing so. */
9132 if (code
== LSHIFTRT
9133 && GET_CODE (XEXP (varop
, 1)) == CONST_INT
9134 && mode_signbit_p (result_mode
, XEXP (varop
, 1))
9135 && (new = simplify_binary_operation (code
, result_mode
,
9137 GEN_INT (count
))) != 0
9138 && GET_CODE (new) == CONST_INT
9139 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9140 INTVAL (new), result_mode
, &complement_p
))
9142 varop
= XEXP (varop
, 0);
9149 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9150 with C the size of VAROP - 1 and the shift is logical if
9151 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9152 we have a (gt X 0) operation. If the shift is arithmetic with
9153 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9154 we have a (neg (gt X 0)) operation. */
9156 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9157 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
9158 && count
== (unsigned int)
9159 (GET_MODE_BITSIZE (GET_MODE (varop
)) - 1)
9160 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9161 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9162 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (XEXP (varop
, 0), 1))
9164 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9167 varop
= gen_rtx_GT (GET_MODE (varop
), XEXP (varop
, 1),
9170 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9171 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
9178 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9179 if the truncate does not affect the value. */
9180 if (code
== LSHIFTRT
9181 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
9182 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9183 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
9184 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop
, 0)))
9185 - GET_MODE_BITSIZE (GET_MODE (varop
)))))
9187 rtx varop_inner
= XEXP (varop
, 0);
9190 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner
),
9191 XEXP (varop_inner
, 0),
9193 (count
+ INTVAL (XEXP (varop_inner
, 1))));
9194 varop
= gen_rtx_TRUNCATE (GET_MODE (varop
), varop_inner
);
9207 /* We need to determine what mode to do the shift in. If the shift is
9208 a right shift or ROTATE, we must always do it in the mode it was
9209 originally done in. Otherwise, we can do it in MODE, the widest mode
9210 encountered. The code we care about is that of the shift that will
9211 actually be done, not the shift that was originally requested. */
9213 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
9214 ? result_mode
: mode
);
9216 /* We have now finished analyzing the shift. The result should be
9217 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9218 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
9219 to the result of the shift. OUTER_CONST is the relevant constant,
9220 but we must turn off all bits turned off in the shift.
9222 If we were passed a value for X, see if we can use any pieces of
9223 it. If not, make new rtx. */
9225 if (x
&& GET_RTX_CLASS (GET_CODE (x
)) == RTX_BIN_ARITH
9226 && GET_CODE (XEXP (x
, 1)) == CONST_INT
9227 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) == count
)
9228 const_rtx
= XEXP (x
, 1);
9230 const_rtx
= GEN_INT (count
);
9232 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
9233 && GET_MODE (XEXP (x
, 0)) == shift_mode
9234 && SUBREG_REG (XEXP (x
, 0)) == varop
)
9235 varop
= XEXP (x
, 0);
9236 else if (GET_MODE (varop
) != shift_mode
)
9237 varop
= gen_lowpart (shift_mode
, varop
);
9239 /* If we can't make the SUBREG, try to return what we were given. */
9240 if (GET_CODE (varop
) == CLOBBER
)
9241 return x
? x
: varop
;
9243 new = simplify_binary_operation (code
, shift_mode
, varop
, const_rtx
);
9247 x
= gen_rtx_fmt_ee (code
, shift_mode
, varop
, const_rtx
);
9249 /* If we have an outer operation and we just made a shift, it is
9250 possible that we could have simplified the shift were it not
9251 for the outer operation. So try to do the simplification
9254 if (outer_op
!= UNKNOWN
&& GET_CODE (x
) == code
9255 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
9256 x
= simplify_shift_const (x
, code
, shift_mode
, XEXP (x
, 0),
9257 INTVAL (XEXP (x
, 1)));
9259 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9260 turn off all the bits that the shift would have turned off. */
9261 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
9262 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
9263 GET_MODE_MASK (result_mode
) >> orig_count
);
9265 /* Do the remainder of the processing in RESULT_MODE. */
9266 x
= gen_lowpart (result_mode
, x
);
9268 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9271 x
= simplify_gen_unary (NOT
, result_mode
, x
, result_mode
);
9273 if (outer_op
!= UNKNOWN
)
9275 if (GET_MODE_BITSIZE (result_mode
) < HOST_BITS_PER_WIDE_INT
)
9276 outer_const
= trunc_int_for_mode (outer_const
, result_mode
);
9278 if (outer_op
== AND
)
9279 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
9280 else if (outer_op
== SET
)
9281 /* This means that we have determined that the result is
9282 equivalent to a constant. This should be rare. */
9283 x
= GEN_INT (outer_const
);
9284 else if (GET_RTX_CLASS (outer_op
) == RTX_UNARY
)
9285 x
= simplify_gen_unary (outer_op
, result_mode
, x
, result_mode
);
9287 x
= simplify_gen_binary (outer_op
, result_mode
, x
,
9288 GEN_INT (outer_const
));
9294 /* Like recog, but we receive the address of a pointer to a new pattern.
9295 We try to match the rtx that the pointer points to.
9296 If that fails, we may try to modify or replace the pattern,
9297 storing the replacement into the same pointer object.
9299 Modifications include deletion or addition of CLOBBERs.
9301 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9302 the CLOBBERs are placed.
9304 The value is the final insn code from the pattern ultimately matched,
9308 recog_for_combine (rtx
*pnewpat
, rtx insn
, rtx
*pnotes
)
9311 int insn_code_number
;
9312 int num_clobbers_to_add
= 0;
9315 rtx old_notes
, old_pat
;
9317 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9318 we use to indicate that something didn't match. If we find such a
9319 thing, force rejection. */
9320 if (GET_CODE (pat
) == PARALLEL
)
9321 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
9322 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
9323 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
9326 old_pat
= PATTERN (insn
);
9327 old_notes
= REG_NOTES (insn
);
9328 PATTERN (insn
) = pat
;
9329 REG_NOTES (insn
) = 0;
9331 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
9333 /* If it isn't, there is the possibility that we previously had an insn
9334 that clobbered some register as a side effect, but the combined
9335 insn doesn't need to do that. So try once more without the clobbers
9336 unless this represents an ASM insn. */
9338 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
9339 && GET_CODE (pat
) == PARALLEL
)
9343 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
9344 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
9347 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
9351 SUBST_INT (XVECLEN (pat
, 0), pos
);
9354 pat
= XVECEXP (pat
, 0, 0);
9356 PATTERN (insn
) = pat
;
9357 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
9359 PATTERN (insn
) = old_pat
;
9360 REG_NOTES (insn
) = old_notes
;
9362 /* Recognize all noop sets, these will be killed by followup pass. */
9363 if (insn_code_number
< 0 && GET_CODE (pat
) == SET
&& set_noop_p (pat
))
9364 insn_code_number
= NOOP_MOVE_INSN_CODE
, num_clobbers_to_add
= 0;
9366 /* If we had any clobbers to add, make a new pattern than contains
9367 them. Then check to make sure that all of them are dead. */
9368 if (num_clobbers_to_add
)
9370 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
9371 rtvec_alloc (GET_CODE (pat
) == PARALLEL
9373 + num_clobbers_to_add
)
9374 : num_clobbers_to_add
+ 1));
9376 if (GET_CODE (pat
) == PARALLEL
)
9377 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
9378 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
9380 XVECEXP (newpat
, 0, 0) = pat
;
9382 add_clobbers (newpat
, insn_code_number
);
9384 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
9385 i
< XVECLEN (newpat
, 0); i
++)
9387 if (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0))
9388 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
9390 notes
= gen_rtx_EXPR_LIST (REG_UNUSED
,
9391 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
9399 return insn_code_number
;
9402 /* Like gen_lowpart_general but for use by combine. In combine it
9403 is not possible to create any new pseudoregs. However, it is
9404 safe to create invalid memory addresses, because combine will
9405 try to recognize them and all they will do is make the combine
9408 If for some reason this cannot do its job, an rtx
9409 (clobber (const_int 0)) is returned.
9410 An insn containing that will not be recognized. */
9413 gen_lowpart_for_combine (enum machine_mode omode
, rtx x
)
9415 enum machine_mode imode
= GET_MODE (x
);
9416 unsigned int osize
= GET_MODE_SIZE (omode
);
9417 unsigned int isize
= GET_MODE_SIZE (imode
);
9423 /* Return identity if this is a CONST or symbolic reference. */
9425 && (GET_CODE (x
) == CONST
9426 || GET_CODE (x
) == SYMBOL_REF
9427 || GET_CODE (x
) == LABEL_REF
))
9430 /* We can only support MODE being wider than a word if X is a
9431 constant integer or has a mode the same size. */
9432 if (GET_MODE_SIZE (omode
) > UNITS_PER_WORD
9433 && ! ((imode
== VOIDmode
9434 && (GET_CODE (x
) == CONST_INT
9435 || GET_CODE (x
) == CONST_DOUBLE
))
9439 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9440 won't know what to do. So we will strip off the SUBREG here and
9441 process normally. */
9442 if (GET_CODE (x
) == SUBREG
&& MEM_P (SUBREG_REG (x
)))
9446 /* For use in case we fall down into the address adjustments
9447 further below, we need to adjust the known mode and size of
9448 x; imode and isize, since we just adjusted x. */
9449 imode
= GET_MODE (x
);
9454 isize
= GET_MODE_SIZE (imode
);
9457 result
= gen_lowpart_common (omode
, x
);
9459 #ifdef CANNOT_CHANGE_MODE_CLASS
9460 if (result
!= 0 && GET_CODE (result
) == SUBREG
)
9461 record_subregs_of_mode (result
);
9471 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9473 if (MEM_VOLATILE_P (x
) || mode_dependent_address_p (XEXP (x
, 0)))
9476 /* If we want to refer to something bigger than the original memref,
9477 generate a paradoxical subreg instead. That will force a reload
9478 of the original memref X. */
9480 return gen_rtx_SUBREG (omode
, x
, 0);
9482 if (WORDS_BIG_ENDIAN
)
9483 offset
= MAX (isize
, UNITS_PER_WORD
) - MAX (osize
, UNITS_PER_WORD
);
9485 /* Adjust the address so that the address-after-the-data is unchanged. */
9486 if (BYTES_BIG_ENDIAN
)
9487 offset
-= MIN (UNITS_PER_WORD
, osize
) - MIN (UNITS_PER_WORD
, isize
);
9489 return adjust_address_nv (x
, omode
, offset
);
9492 /* If X is a comparison operator, rewrite it in a new mode. This
9493 probably won't match, but may allow further simplifications. */
9494 else if (COMPARISON_P (x
))
9495 return gen_rtx_fmt_ee (GET_CODE (x
), omode
, XEXP (x
, 0), XEXP (x
, 1));
9497 /* If we couldn't simplify X any other way, just enclose it in a
9498 SUBREG. Normally, this SUBREG won't match, but some patterns may
9499 include an explicit SUBREG or we may simplify it further in combine. */
9505 offset
= subreg_lowpart_offset (omode
, imode
);
9506 if (imode
== VOIDmode
)
9508 imode
= int_mode_for_mode (omode
);
9509 x
= gen_lowpart_common (imode
, x
);
9513 res
= simplify_gen_subreg (omode
, x
, imode
, offset
);
9519 return gen_rtx_CLOBBER (imode
, const0_rtx
);
9522 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9523 comparison code that will be tested.
9525 The result is a possibly different comparison code to use. *POP0 and
9526 *POP1 may be updated.
9528 It is possible that we might detect that a comparison is either always
9529 true or always false. However, we do not perform general constant
9530 folding in combine, so this knowledge isn't useful. Such tautologies
9531 should have been detected earlier. Hence we ignore all such cases. */
9533 static enum rtx_code
9534 simplify_comparison (enum rtx_code code
, rtx
*pop0
, rtx
*pop1
)
9540 enum machine_mode mode
, tmode
;
9542 /* Try a few ways of applying the same transformation to both operands. */
9545 #ifndef WORD_REGISTER_OPERATIONS
9546 /* The test below this one won't handle SIGN_EXTENDs on these machines,
9547 so check specially. */
9548 if (code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
9549 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
9550 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
9551 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
9552 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
9553 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
9554 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
9555 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
9556 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9557 && XEXP (op0
, 1) == XEXP (op1
, 1)
9558 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
9559 && XEXP (op0
, 1) == XEXP (XEXP (op1
, 0), 1)
9560 && (INTVAL (XEXP (op0
, 1))
9561 == (GET_MODE_BITSIZE (GET_MODE (op0
))
9563 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
9565 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
9566 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
9570 /* If both operands are the same constant shift, see if we can ignore the
9571 shift. We can if the shift is a rotate or if the bits shifted out of
9572 this shift are known to be zero for both inputs and if the type of
9573 comparison is compatible with the shift. */
9574 if (GET_CODE (op0
) == GET_CODE (op1
)
9575 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
9576 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
9577 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
9578 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
9579 || (GET_CODE (op0
) == ASHIFTRT
9580 && (code
!= GTU
&& code
!= LTU
9581 && code
!= GEU
&& code
!= LEU
)))
9582 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9583 && INTVAL (XEXP (op0
, 1)) >= 0
9584 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
9585 && XEXP (op0
, 1) == XEXP (op1
, 1))
9587 enum machine_mode mode
= GET_MODE (op0
);
9588 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
9589 int shift_count
= INTVAL (XEXP (op0
, 1));
9591 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
9592 mask
&= (mask
>> shift_count
) << shift_count
;
9593 else if (GET_CODE (op0
) == ASHIFT
)
9594 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
9596 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
9597 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
9598 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
9603 /* If both operands are AND's of a paradoxical SUBREG by constant, the
9604 SUBREGs are of the same mode, and, in both cases, the AND would
9605 be redundant if the comparison was done in the narrower mode,
9606 do the comparison in the narrower mode (e.g., we are AND'ing with 1
9607 and the operand's possibly nonzero bits are 0xffffff01; in that case
9608 if we only care about QImode, we don't need the AND). This case
9609 occurs if the output mode of an scc insn is not SImode and
9610 STORE_FLAG_VALUE == 1 (e.g., the 386).
9612 Similarly, check for a case where the AND's are ZERO_EXTEND
9613 operations from some narrower mode even though a SUBREG is not
9616 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
9617 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9618 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
)
9620 rtx inner_op0
= XEXP (op0
, 0);
9621 rtx inner_op1
= XEXP (op1
, 0);
9622 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
9623 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
9626 if (GET_CODE (inner_op0
) == SUBREG
&& GET_CODE (inner_op1
) == SUBREG
9627 && (GET_MODE_SIZE (GET_MODE (inner_op0
))
9628 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0
))))
9629 && (GET_MODE (SUBREG_REG (inner_op0
))
9630 == GET_MODE (SUBREG_REG (inner_op1
)))
9631 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0
)))
9632 <= HOST_BITS_PER_WIDE_INT
)
9633 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
9634 GET_MODE (SUBREG_REG (inner_op0
)))))
9635 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
9636 GET_MODE (SUBREG_REG (inner_op1
))))))
9638 op0
= SUBREG_REG (inner_op0
);
9639 op1
= SUBREG_REG (inner_op1
);
9641 /* The resulting comparison is always unsigned since we masked
9642 off the original sign bit. */
9643 code
= unsigned_condition (code
);
9649 for (tmode
= GET_CLASS_NARROWEST_MODE
9650 (GET_MODE_CLASS (GET_MODE (op0
)));
9651 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
9652 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
9654 op0
= gen_lowpart (tmode
, inner_op0
);
9655 op1
= gen_lowpart (tmode
, inner_op1
);
9656 code
= unsigned_condition (code
);
9665 /* If both operands are NOT, we can strip off the outer operation
9666 and adjust the comparison code for swapped operands; similarly for
9667 NEG, except that this must be an equality comparison. */
9668 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
9669 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
9670 && (code
== EQ
|| code
== NE
)))
9671 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
9677 /* If the first operand is a constant, swap the operands and adjust the
9678 comparison code appropriately, but don't do this if the second operand
9679 is already a constant integer. */
9680 if (swap_commutative_operands_p (op0
, op1
))
9682 tem
= op0
, op0
= op1
, op1
= tem
;
9683 code
= swap_condition (code
);
9686 /* We now enter a loop during which we will try to simplify the comparison.
9687 For the most part, we only are concerned with comparisons with zero,
9688 but some things may really be comparisons with zero but not start
9689 out looking that way. */
9691 while (GET_CODE (op1
) == CONST_INT
)
9693 enum machine_mode mode
= GET_MODE (op0
);
9694 unsigned int mode_width
= GET_MODE_BITSIZE (mode
);
9695 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
9696 int equality_comparison_p
;
9697 int sign_bit_comparison_p
;
9698 int unsigned_comparison_p
;
9699 HOST_WIDE_INT const_op
;
9701 /* We only want to handle integral modes. This catches VOIDmode,
9702 CCmode, and the floating-point modes. An exception is that we
9703 can handle VOIDmode if OP0 is a COMPARE or a comparison
9706 if (GET_MODE_CLASS (mode
) != MODE_INT
9707 && ! (mode
== VOIDmode
9708 && (GET_CODE (op0
) == COMPARE
|| COMPARISON_P (op0
))))
9711 /* Get the constant we are comparing against and turn off all bits
9712 not on in our mode. */
9713 const_op
= INTVAL (op1
);
9714 if (mode
!= VOIDmode
)
9715 const_op
= trunc_int_for_mode (const_op
, mode
);
9716 op1
= GEN_INT (const_op
);
9718 /* If we are comparing against a constant power of two and the value
9719 being compared can only have that single bit nonzero (e.g., it was
9720 `and'ed with that bit), we can replace this with a comparison
9723 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
9724 || code
== LT
|| code
== LTU
)
9725 && mode_width
<= HOST_BITS_PER_WIDE_INT
9726 && exact_log2 (const_op
) >= 0
9727 && nonzero_bits (op0
, mode
) == (unsigned HOST_WIDE_INT
) const_op
)
9729 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
9730 op1
= const0_rtx
, const_op
= 0;
9733 /* Similarly, if we are comparing a value known to be either -1 or
9734 0 with -1, change it to the opposite comparison against zero. */
9737 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
9738 || code
== GEU
|| code
== LTU
)
9739 && num_sign_bit_copies (op0
, mode
) == mode_width
)
9741 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
9742 op1
= const0_rtx
, const_op
= 0;
9745 /* Do some canonicalizations based on the comparison code. We prefer
9746 comparisons against zero and then prefer equality comparisons.
9747 If we can reduce the size of a constant, we will do that too. */
9752 /* < C is equivalent to <= (C - 1) */
9756 op1
= GEN_INT (const_op
);
9758 /* ... fall through to LE case below. */
9764 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
9768 op1
= GEN_INT (const_op
);
9772 /* If we are doing a <= 0 comparison on a value known to have
9773 a zero sign bit, we can replace this with == 0. */
9774 else if (const_op
== 0
9775 && mode_width
<= HOST_BITS_PER_WIDE_INT
9776 && (nonzero_bits (op0
, mode
)
9777 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
9782 /* >= C is equivalent to > (C - 1). */
9786 op1
= GEN_INT (const_op
);
9788 /* ... fall through to GT below. */
9794 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
9798 op1
= GEN_INT (const_op
);
9802 /* If we are doing a > 0 comparison on a value known to have
9803 a zero sign bit, we can replace this with != 0. */
9804 else if (const_op
== 0
9805 && mode_width
<= HOST_BITS_PER_WIDE_INT
9806 && (nonzero_bits (op0
, mode
)
9807 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
9812 /* < C is equivalent to <= (C - 1). */
9816 op1
= GEN_INT (const_op
);
9818 /* ... fall through ... */
9821 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
9822 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
9823 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
9825 const_op
= 0, op1
= const0_rtx
;
9833 /* unsigned <= 0 is equivalent to == 0 */
9837 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
9838 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
9839 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
9841 const_op
= 0, op1
= const0_rtx
;
9847 /* >= C is equivalent to > (C - 1). */
9851 op1
= GEN_INT (const_op
);
9853 /* ... fall through ... */
9856 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
9857 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
9858 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
9860 const_op
= 0, op1
= const0_rtx
;
9868 /* unsigned > 0 is equivalent to != 0 */
9872 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
9873 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
9874 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
9876 const_op
= 0, op1
= const0_rtx
;
9885 /* Compute some predicates to simplify code below. */
9887 equality_comparison_p
= (code
== EQ
|| code
== NE
);
9888 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
9889 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
9892 /* If this is a sign bit comparison and we can do arithmetic in
9893 MODE, say that we will only be needing the sign bit of OP0. */
9894 if (sign_bit_comparison_p
9895 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
9896 op0
= force_to_mode (op0
, mode
,
9898 << (GET_MODE_BITSIZE (mode
) - 1)),
9901 /* Now try cases based on the opcode of OP0. If none of the cases
9902 does a "continue", we exit this loop immediately after the
9905 switch (GET_CODE (op0
))
9908 /* If we are extracting a single bit from a variable position in
9909 a constant that has only a single bit set and are comparing it
9910 with zero, we can convert this into an equality comparison
9911 between the position and the location of the single bit. */
9912 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
9913 have already reduced the shift count modulo the word size. */
9914 if (!SHIFT_COUNT_TRUNCATED
9915 && GET_CODE (XEXP (op0
, 0)) == CONST_INT
9916 && XEXP (op0
, 1) == const1_rtx
9917 && equality_comparison_p
&& const_op
== 0
9918 && (i
= exact_log2 (INTVAL (XEXP (op0
, 0)))) >= 0)
9920 if (BITS_BIG_ENDIAN
)
9922 enum machine_mode new_mode
9923 = mode_for_extraction (EP_extzv
, 1);
9924 if (new_mode
== MAX_MACHINE_MODE
)
9925 i
= BITS_PER_WORD
- 1 - i
;
9929 i
= (GET_MODE_BITSIZE (mode
) - 1 - i
);
9933 op0
= XEXP (op0
, 2);
9937 /* Result is nonzero iff shift count is equal to I. */
9938 code
= reverse_condition (code
);
9942 /* ... fall through ... */
9945 tem
= expand_compound_operation (op0
);
9954 /* If testing for equality, we can take the NOT of the constant. */
9955 if (equality_comparison_p
9956 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
9958 op0
= XEXP (op0
, 0);
9963 /* If just looking at the sign bit, reverse the sense of the
9965 if (sign_bit_comparison_p
)
9967 op0
= XEXP (op0
, 0);
9968 code
= (code
== GE
? LT
: GE
);
9974 /* If testing for equality, we can take the NEG of the constant. */
9975 if (equality_comparison_p
9976 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
9978 op0
= XEXP (op0
, 0);
9983 /* The remaining cases only apply to comparisons with zero. */
9987 /* When X is ABS or is known positive,
9988 (neg X) is < 0 if and only if X != 0. */
9990 if (sign_bit_comparison_p
9991 && (GET_CODE (XEXP (op0
, 0)) == ABS
9992 || (mode_width
<= HOST_BITS_PER_WIDE_INT
9993 && (nonzero_bits (XEXP (op0
, 0), mode
)
9994 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)))
9996 op0
= XEXP (op0
, 0);
9997 code
= (code
== LT
? NE
: EQ
);
10001 /* If we have NEG of something whose two high-order bits are the
10002 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10003 if (num_sign_bit_copies (op0
, mode
) >= 2)
10005 op0
= XEXP (op0
, 0);
10006 code
= swap_condition (code
);
10012 /* If we are testing equality and our count is a constant, we
10013 can perform the inverse operation on our RHS. */
10014 if (equality_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
10015 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
10016 op1
, XEXP (op0
, 1))) != 0)
10018 op0
= XEXP (op0
, 0);
10023 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10024 a particular bit. Convert it to an AND of a constant of that
10025 bit. This will be converted into a ZERO_EXTRACT. */
10026 if (const_op
== 0 && sign_bit_comparison_p
10027 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10028 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
10030 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10033 - INTVAL (XEXP (op0
, 1)))));
10034 code
= (code
== LT
? NE
: EQ
);
10038 /* Fall through. */
10041 /* ABS is ignorable inside an equality comparison with zero. */
10042 if (const_op
== 0 && equality_comparison_p
)
10044 op0
= XEXP (op0
, 0);
10050 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
10051 (compare FOO CONST) if CONST fits in FOO's mode and we
10052 are either testing inequality or have an unsigned
10053 comparison with ZERO_EXTEND or a signed comparison with
10054 SIGN_EXTEND. But don't do it if we don't have a compare
10055 insn of the given mode, since we'd have to revert it
10056 later on, and then we wouldn't know whether to sign- or
10058 mode
= GET_MODE (XEXP (op0
, 0));
10059 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
10060 && ! unsigned_comparison_p
10061 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10062 && ((unsigned HOST_WIDE_INT
) const_op
10063 < (((unsigned HOST_WIDE_INT
) 1
10064 << (GET_MODE_BITSIZE (mode
) - 1))))
10065 && cmp_optab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
)
10067 op0
= XEXP (op0
, 0);
10073 /* Check for the case where we are comparing A - C1 with C2, that is
10075 (subreg:MODE (plus (A) (-C1))) op (C2)
10077 with C1 a constant, and try to lift the SUBREG, i.e. to do the
10078 comparison in the wider mode. One of the following two conditions
10079 must be true in order for this to be valid:
10081 1. The mode extension results in the same bit pattern being added
10082 on both sides and the comparison is equality or unsigned. As
10083 C2 has been truncated to fit in MODE, the pattern can only be
10086 2. The mode extension results in the sign bit being copied on
10089 The difficulty here is that we have predicates for A but not for
10090 (A - C1) so we need to check that C1 is within proper bounds so
10091 as to perturbate A as little as possible. */
10093 if (mode_width
<= HOST_BITS_PER_WIDE_INT
10094 && subreg_lowpart_p (op0
)
10095 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
))) > mode_width
10096 && GET_CODE (SUBREG_REG (op0
)) == PLUS
10097 && GET_CODE (XEXP (SUBREG_REG (op0
), 1)) == CONST_INT
)
10099 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (op0
));
10100 rtx a
= XEXP (SUBREG_REG (op0
), 0);
10101 HOST_WIDE_INT c1
= -INTVAL (XEXP (SUBREG_REG (op0
), 1));
10104 && (unsigned HOST_WIDE_INT
) c1
10105 < (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)
10106 && (equality_comparison_p
|| unsigned_comparison_p
)
10107 /* (A - C1) zero-extends if it is positive and sign-extends
10108 if it is negative, C2 both zero- and sign-extends. */
10109 && ((0 == (nonzero_bits (a
, inner_mode
)
10110 & ~GET_MODE_MASK (mode
))
10112 /* (A - C1) sign-extends if it is positive and 1-extends
10113 if it is negative, C2 both sign- and 1-extends. */
10114 || (num_sign_bit_copies (a
, inner_mode
)
10115 > (unsigned int) (GET_MODE_BITSIZE (inner_mode
)
10118 || ((unsigned HOST_WIDE_INT
) c1
10119 < (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 2)
10120 /* (A - C1) always sign-extends, like C2. */
10121 && num_sign_bit_copies (a
, inner_mode
)
10122 > (unsigned int) (GET_MODE_BITSIZE (inner_mode
)
10123 - mode_width
- 1)))
10125 op0
= SUBREG_REG (op0
);
10130 /* If the inner mode is narrower and we are extracting the low part,
10131 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10132 if (subreg_lowpart_p (op0
)
10133 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
10134 /* Fall through */ ;
10138 /* ... fall through ... */
10141 mode
= GET_MODE (XEXP (op0
, 0));
10142 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
10143 && (unsigned_comparison_p
|| equality_comparison_p
)
10144 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10145 && ((unsigned HOST_WIDE_INT
) const_op
< GET_MODE_MASK (mode
))
10146 && cmp_optab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
)
10148 op0
= XEXP (op0
, 0);
10154 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10155 this for equality comparisons due to pathological cases involving
10157 if (equality_comparison_p
10158 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10159 op1
, XEXP (op0
, 1))))
10161 op0
= XEXP (op0
, 0);
10166 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10167 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
10168 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
10170 op0
= XEXP (XEXP (op0
, 0), 0);
10171 code
= (code
== LT
? EQ
: NE
);
10177 /* We used to optimize signed comparisons against zero, but that
10178 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10179 arrive here as equality comparisons, or (GEU, LTU) are
10180 optimized away. No need to special-case them. */
10182 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10183 (eq B (minus A C)), whichever simplifies. We can only do
10184 this for equality comparisons due to pathological cases involving
10186 if (equality_comparison_p
10187 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
10188 XEXP (op0
, 1), op1
)))
10190 op0
= XEXP (op0
, 0);
10195 if (equality_comparison_p
10196 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10197 XEXP (op0
, 0), op1
)))
10199 op0
= XEXP (op0
, 1);
10204 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10205 of bits in X minus 1, is one iff X > 0. */
10206 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
10207 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10208 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (XEXP (op0
, 0), 1))
10210 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10212 op0
= XEXP (op0
, 1);
10213 code
= (code
== GE
? LE
: GT
);
10219 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10220 if C is zero or B is a constant. */
10221 if (equality_comparison_p
10222 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
10223 XEXP (op0
, 1), op1
)))
10225 op0
= XEXP (op0
, 0);
10232 case UNEQ
: case LTGT
:
10233 case LT
: case LTU
: case UNLT
: case LE
: case LEU
: case UNLE
:
10234 case GT
: case GTU
: case UNGT
: case GE
: case GEU
: case UNGE
:
10235 case UNORDERED
: case ORDERED
:
10236 /* We can't do anything if OP0 is a condition code value, rather
10237 than an actual data value. */
10239 || CC0_P (XEXP (op0
, 0))
10240 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
10243 /* Get the two operands being compared. */
10244 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
10245 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
10247 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
10249 /* Check for the cases where we simply want the result of the
10250 earlier test or the opposite of that result. */
10251 if (code
== NE
|| code
== EQ
10252 || (GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
10253 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
10254 && (STORE_FLAG_VALUE
10255 & (((HOST_WIDE_INT
) 1
10256 << (GET_MODE_BITSIZE (GET_MODE (op0
)) - 1))))
10257 && (code
== LT
|| code
== GE
)))
10259 enum rtx_code new_code
;
10260 if (code
== LT
|| code
== NE
)
10261 new_code
= GET_CODE (op0
);
10263 new_code
= combine_reversed_comparison_code (op0
);
10265 if (new_code
!= UNKNOWN
)
10276 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10278 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
10279 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
10280 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10282 op0
= XEXP (op0
, 1);
10283 code
= (code
== GE
? GT
: LE
);
10289 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10290 will be converted to a ZERO_EXTRACT later. */
10291 if (const_op
== 0 && equality_comparison_p
10292 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10293 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
10295 op0
= simplify_and_const_int
10296 (op0
, mode
, gen_rtx_LSHIFTRT (mode
,
10298 XEXP (XEXP (op0
, 0), 1)),
10299 (HOST_WIDE_INT
) 1);
10303 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10304 zero and X is a comparison and C1 and C2 describe only bits set
10305 in STORE_FLAG_VALUE, we can compare with X. */
10306 if (const_op
== 0 && equality_comparison_p
10307 && mode_width
<= HOST_BITS_PER_WIDE_INT
10308 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10309 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
10310 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10311 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
10312 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
10314 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10315 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
10316 if ((~STORE_FLAG_VALUE
& mask
) == 0
10317 && (COMPARISON_P (XEXP (XEXP (op0
, 0), 0))
10318 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
10319 && COMPARISON_P (tem
))))
10321 op0
= XEXP (XEXP (op0
, 0), 0);
10326 /* If we are doing an equality comparison of an AND of a bit equal
10327 to the sign bit, replace this with a LT or GE comparison of
10328 the underlying value. */
10329 if (equality_comparison_p
10331 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10332 && mode_width
<= HOST_BITS_PER_WIDE_INT
10333 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10334 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10336 op0
= XEXP (op0
, 0);
10337 code
= (code
== EQ
? GE
: LT
);
10341 /* If this AND operation is really a ZERO_EXTEND from a narrower
10342 mode, the constant fits within that mode, and this is either an
10343 equality or unsigned comparison, try to do this comparison in
10344 the narrower mode. */
10345 if ((equality_comparison_p
|| unsigned_comparison_p
)
10346 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10347 && (i
= exact_log2 ((INTVAL (XEXP (op0
, 1))
10348 & GET_MODE_MASK (mode
))
10350 && const_op
>> i
== 0
10351 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
)
10353 op0
= gen_lowpart (tmode
, XEXP (op0
, 0));
10357 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
10358 fits in both M1 and M2 and the SUBREG is either paradoxical
10359 or represents the low part, permute the SUBREG and the AND
10361 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
)
10363 unsigned HOST_WIDE_INT c1
;
10364 tmode
= GET_MODE (SUBREG_REG (XEXP (op0
, 0)));
10365 /* Require an integral mode, to avoid creating something like
10367 if (SCALAR_INT_MODE_P (tmode
)
10368 /* It is unsafe to commute the AND into the SUBREG if the
10369 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
10370 not defined. As originally written the upper bits
10371 have a defined value due to the AND operation.
10372 However, if we commute the AND inside the SUBREG then
10373 they no longer have defined values and the meaning of
10374 the code has been changed. */
10376 #ifdef WORD_REGISTER_OPERATIONS
10377 || (mode_width
> GET_MODE_BITSIZE (tmode
)
10378 && mode_width
<= BITS_PER_WORD
)
10380 || (mode_width
<= GET_MODE_BITSIZE (tmode
)
10381 && subreg_lowpart_p (XEXP (op0
, 0))))
10382 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10383 && mode_width
<= HOST_BITS_PER_WIDE_INT
10384 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
10385 && ((c1
= INTVAL (XEXP (op0
, 1))) & ~mask
) == 0
10386 && (c1
& ~GET_MODE_MASK (tmode
)) == 0
10388 && c1
!= GET_MODE_MASK (tmode
))
10390 op0
= simplify_gen_binary (AND
, tmode
,
10391 SUBREG_REG (XEXP (op0
, 0)),
10392 gen_int_mode (c1
, tmode
));
10393 op0
= gen_lowpart (mode
, op0
);
10398 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
10399 if (const_op
== 0 && equality_comparison_p
10400 && XEXP (op0
, 1) == const1_rtx
10401 && GET_CODE (XEXP (op0
, 0)) == NOT
)
10403 op0
= simplify_and_const_int
10404 (NULL_RTX
, mode
, XEXP (XEXP (op0
, 0), 0), (HOST_WIDE_INT
) 1);
10405 code
= (code
== NE
? EQ
: NE
);
10409 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10410 (eq (and (lshiftrt X) 1) 0).
10411 Also handle the case where (not X) is expressed using xor. */
10412 if (const_op
== 0 && equality_comparison_p
10413 && XEXP (op0
, 1) == const1_rtx
10414 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
)
10416 rtx shift_op
= XEXP (XEXP (op0
, 0), 0);
10417 rtx shift_count
= XEXP (XEXP (op0
, 0), 1);
10419 if (GET_CODE (shift_op
) == NOT
10420 || (GET_CODE (shift_op
) == XOR
10421 && GET_CODE (XEXP (shift_op
, 1)) == CONST_INT
10422 && GET_CODE (shift_count
) == CONST_INT
10423 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
10424 && (INTVAL (XEXP (shift_op
, 1))
10425 == (HOST_WIDE_INT
) 1 << INTVAL (shift_count
))))
10427 op0
= simplify_and_const_int
10429 gen_rtx_LSHIFTRT (mode
, XEXP (shift_op
, 0), shift_count
),
10430 (HOST_WIDE_INT
) 1);
10431 code
= (code
== NE
? EQ
: NE
);
10438 /* If we have (compare (ashift FOO N) (const_int C)) and
10439 the high order N bits of FOO (N+1 if an inequality comparison)
10440 are known to be zero, we can do this by comparing FOO with C
10441 shifted right N bits so long as the low-order N bits of C are
10443 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
10444 && INTVAL (XEXP (op0
, 1)) >= 0
10445 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
10446 < HOST_BITS_PER_WIDE_INT
)
10448 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0)
10449 && mode_width
<= HOST_BITS_PER_WIDE_INT
10450 && (nonzero_bits (XEXP (op0
, 0), mode
)
10451 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
10452 + ! equality_comparison_p
))) == 0)
10454 /* We must perform a logical shift, not an arithmetic one,
10455 as we want the top N bits of C to be zero. */
10456 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
10458 temp
>>= INTVAL (XEXP (op0
, 1));
10459 op1
= gen_int_mode (temp
, mode
);
10460 op0
= XEXP (op0
, 0);
10464 /* If we are doing a sign bit comparison, it means we are testing
10465 a particular bit. Convert it to the appropriate AND. */
10466 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
10467 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
10469 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10472 - INTVAL (XEXP (op0
, 1)))));
10473 code
= (code
== LT
? NE
: EQ
);
10477 /* If this an equality comparison with zero and we are shifting
10478 the low bit to the sign bit, we can convert this to an AND of the
10480 if (const_op
== 0 && equality_comparison_p
10481 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10482 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
10485 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10486 (HOST_WIDE_INT
) 1);
10492 /* If this is an equality comparison with zero, we can do this
10493 as a logical shift, which might be much simpler. */
10494 if (equality_comparison_p
&& const_op
== 0
10495 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
)
10497 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
10499 INTVAL (XEXP (op0
, 1)));
10503 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10504 do the comparison in a narrower mode. */
10505 if (! unsigned_comparison_p
10506 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10507 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10508 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
10509 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
10510 MODE_INT
, 1)) != BLKmode
10511 && (((unsigned HOST_WIDE_INT
) const_op
10512 + (GET_MODE_MASK (tmode
) >> 1) + 1)
10513 <= GET_MODE_MASK (tmode
)))
10515 op0
= gen_lowpart (tmode
, XEXP (XEXP (op0
, 0), 0));
10519 /* Likewise if OP0 is a PLUS of a sign extension with a
10520 constant, which is usually represented with the PLUS
10521 between the shifts. */
10522 if (! unsigned_comparison_p
10523 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10524 && GET_CODE (XEXP (op0
, 0)) == PLUS
10525 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10526 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
10527 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
10528 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
10529 MODE_INT
, 1)) != BLKmode
10530 && (((unsigned HOST_WIDE_INT
) const_op
10531 + (GET_MODE_MASK (tmode
) >> 1) + 1)
10532 <= GET_MODE_MASK (tmode
)))
10534 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
10535 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
10536 rtx new_const
= simplify_gen_binary (ASHIFTRT
, GET_MODE (op0
),
10537 add_const
, XEXP (op0
, 1));
10539 op0
= simplify_gen_binary (PLUS
, tmode
,
10540 gen_lowpart (tmode
, inner
),
10545 /* ... fall through ... */
10547 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10548 the low order N bits of FOO are known to be zero, we can do this
10549 by comparing FOO with C shifted left N bits so long as no
10550 overflow occurs. */
10551 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
10552 && INTVAL (XEXP (op0
, 1)) >= 0
10553 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
10554 && mode_width
<= HOST_BITS_PER_WIDE_INT
10555 && (nonzero_bits (XEXP (op0
, 0), mode
)
10556 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0
10557 && (((unsigned HOST_WIDE_INT
) const_op
10558 + (GET_CODE (op0
) != LSHIFTRT
10559 ? ((GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1)) >> 1)
10562 <= GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1))))
10564 /* If the shift was logical, then we must make the condition
10566 if (GET_CODE (op0
) == LSHIFTRT
)
10567 code
= unsigned_condition (code
);
10569 const_op
<<= INTVAL (XEXP (op0
, 1));
10570 op1
= GEN_INT (const_op
);
10571 op0
= XEXP (op0
, 0);
10575 /* If we are using this shift to extract just the sign bit, we
10576 can replace this with an LT or GE comparison. */
10578 && (equality_comparison_p
|| sign_bit_comparison_p
)
10579 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10580 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
10583 op0
= XEXP (op0
, 0);
10584 code
= (code
== NE
|| code
== GT
? LT
: GE
);
10596 /* Now make any compound operations involved in this comparison. Then,
10597 check for an outmost SUBREG on OP0 that is not doing anything or is
10598 paradoxical. The latter transformation must only be performed when
10599 it is known that the "extra" bits will be the same in op0 and op1 or
10600 that they don't matter. There are three cases to consider:
10602 1. SUBREG_REG (op0) is a register. In this case the bits are don't
10603 care bits and we can assume they have any convenient value. So
10604 making the transformation is safe.
10606 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
10607 In this case the upper bits of op0 are undefined. We should not make
10608 the simplification in that case as we do not know the contents of
10611 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
10612 UNKNOWN. In that case we know those bits are zeros or ones. We must
10613 also be sure that they are the same as the upper bits of op1.
10615 We can never remove a SUBREG for a non-equality comparison because
10616 the sign bit is in a different place in the underlying object. */
10618 op0
= make_compound_operation (op0
, op1
== const0_rtx
? COMPARE
: SET
);
10619 op1
= make_compound_operation (op1
, SET
);
10621 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
10622 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
10623 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0
))) == MODE_INT
10624 && (code
== NE
|| code
== EQ
))
10626 if (GET_MODE_SIZE (GET_MODE (op0
))
10627 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0
))))
10629 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
10631 if (REG_P (SUBREG_REG (op0
)))
10633 op0
= SUBREG_REG (op0
);
10634 op1
= gen_lowpart (GET_MODE (op0
), op1
);
10637 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
10638 <= HOST_BITS_PER_WIDE_INT
)
10639 && (nonzero_bits (SUBREG_REG (op0
),
10640 GET_MODE (SUBREG_REG (op0
)))
10641 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
10643 tem
= gen_lowpart (GET_MODE (SUBREG_REG (op0
)), op1
);
10645 if ((nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
10646 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
10647 op0
= SUBREG_REG (op0
), op1
= tem
;
10651 /* We now do the opposite procedure: Some machines don't have compare
10652 insns in all modes. If OP0's mode is an integer mode smaller than a
10653 word and we can't do a compare in that mode, see if there is a larger
10654 mode for which we can do the compare. There are a number of cases in
10655 which we can use the wider mode. */
10657 mode
= GET_MODE (op0
);
10658 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
10659 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
10660 && ! have_insn_for (COMPARE
, mode
))
10661 for (tmode
= GET_MODE_WIDER_MODE (mode
);
10663 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
);
10664 tmode
= GET_MODE_WIDER_MODE (tmode
))
10665 if (have_insn_for (COMPARE
, tmode
))
10669 /* If the only nonzero bits in OP0 and OP1 are those in the
10670 narrower mode and this is an equality or unsigned comparison,
10671 we can use the wider mode. Similarly for sign-extended
10672 values, in which case it is true for all comparisons. */
10673 zero_extended
= ((code
== EQ
|| code
== NE
10674 || code
== GEU
|| code
== GTU
10675 || code
== LEU
|| code
== LTU
)
10676 && (nonzero_bits (op0
, tmode
)
10677 & ~GET_MODE_MASK (mode
)) == 0
10678 && ((GET_CODE (op1
) == CONST_INT
10679 || (nonzero_bits (op1
, tmode
)
10680 & ~GET_MODE_MASK (mode
)) == 0)));
10683 || ((num_sign_bit_copies (op0
, tmode
)
10684 > (unsigned int) (GET_MODE_BITSIZE (tmode
)
10685 - GET_MODE_BITSIZE (mode
)))
10686 && (num_sign_bit_copies (op1
, tmode
)
10687 > (unsigned int) (GET_MODE_BITSIZE (tmode
)
10688 - GET_MODE_BITSIZE (mode
)))))
10690 /* If OP0 is an AND and we don't have an AND in MODE either,
10691 make a new AND in the proper mode. */
10692 if (GET_CODE (op0
) == AND
10693 && !have_insn_for (AND
, mode
))
10694 op0
= simplify_gen_binary (AND
, tmode
,
10695 gen_lowpart (tmode
,
10697 gen_lowpart (tmode
,
10700 op0
= gen_lowpart (tmode
, op0
);
10701 if (zero_extended
&& GET_CODE (op1
) == CONST_INT
)
10702 op1
= GEN_INT (INTVAL (op1
) & GET_MODE_MASK (mode
));
10703 op1
= gen_lowpart (tmode
, op1
);
10707 /* If this is a test for negative, we can make an explicit
10708 test of the sign bit. */
10710 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
10711 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10713 op0
= simplify_gen_binary (AND
, tmode
,
10714 gen_lowpart (tmode
, op0
),
10715 GEN_INT ((HOST_WIDE_INT
) 1
10716 << (GET_MODE_BITSIZE (mode
)
10718 code
= (code
== LT
) ? NE
: EQ
;
10723 #ifdef CANONICALIZE_COMPARISON
10724 /* If this machine only supports a subset of valid comparisons, see if we
10725 can convert an unsupported one into a supported one. */
10726 CANONICALIZE_COMPARISON (code
, op0
, op1
);
10735 /* Like jump.c' reversed_comparison_code, but use combine infrastructure for
10736 searching backward. */
10737 static enum rtx_code
10738 combine_reversed_comparison_code (rtx exp
)
10740 enum rtx_code code1
= reversed_comparison_code (exp
, NULL
);
10743 if (code1
!= UNKNOWN
10744 || GET_MODE_CLASS (GET_MODE (XEXP (exp
, 0))) != MODE_CC
)
10746 /* Otherwise try and find where the condition codes were last set and
10748 x
= get_last_value (XEXP (exp
, 0));
10749 if (!x
|| GET_CODE (x
) != COMPARE
)
10751 return reversed_comparison_code_parts (GET_CODE (exp
),
10752 XEXP (x
, 0), XEXP (x
, 1), NULL
);
10755 /* Return comparison with reversed code of EXP and operands OP0 and OP1.
10756 Return NULL_RTX in case we fail to do the reversal. */
10758 reversed_comparison (rtx exp
, enum machine_mode mode
, rtx op0
, rtx op1
)
10760 enum rtx_code reversed_code
= combine_reversed_comparison_code (exp
);
10761 if (reversed_code
== UNKNOWN
)
10764 return simplify_gen_relational (reversed_code
, mode
, VOIDmode
, op0
, op1
);
10767 /* Utility function for record_value_for_reg. Count number of
10772 enum rtx_code code
= GET_CODE (x
);
10776 if (GET_RTX_CLASS (code
) == '2'
10777 || GET_RTX_CLASS (code
) == 'c')
10779 rtx x0
= XEXP (x
, 0);
10780 rtx x1
= XEXP (x
, 1);
10783 return 1 + 2 * count_rtxs (x0
);
10785 if ((GET_RTX_CLASS (GET_CODE (x1
)) == '2'
10786 || GET_RTX_CLASS (GET_CODE (x1
)) == 'c')
10787 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
10788 return 2 + 2 * count_rtxs (x0
)
10789 + count_rtxs (x
== XEXP (x1
, 0)
10790 ? XEXP (x1
, 1) : XEXP (x1
, 0));
10792 if ((GET_RTX_CLASS (GET_CODE (x0
)) == '2'
10793 || GET_RTX_CLASS (GET_CODE (x0
)) == 'c')
10794 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
10795 return 2 + 2 * count_rtxs (x1
)
10796 + count_rtxs (x
== XEXP (x0
, 0)
10797 ? XEXP (x0
, 1) : XEXP (x0
, 0));
10800 fmt
= GET_RTX_FORMAT (code
);
10801 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
10803 ret
+= count_rtxs (XEXP (x
, i
));
10808 /* Utility function for following routine. Called when X is part of a value
10809 being stored into last_set_value. Sets last_set_table_tick
10810 for each register mentioned. Similar to mention_regs in cse.c */
10813 update_table_tick (rtx x
)
10815 enum rtx_code code
= GET_CODE (x
);
10816 const char *fmt
= GET_RTX_FORMAT (code
);
10821 unsigned int regno
= REGNO (x
);
10822 unsigned int endregno
10823 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
10824 ? hard_regno_nregs
[regno
][GET_MODE (x
)] : 1);
10827 for (r
= regno
; r
< endregno
; r
++)
10828 reg_stat
[r
].last_set_table_tick
= label_tick
;
10833 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
10834 /* Note that we can't have an "E" in values stored; see
10835 get_last_value_validate. */
10838 /* Check for identical subexpressions. If x contains
10839 identical subexpression we only have to traverse one of
10841 if (i
== 0 && ARITHMETIC_P (x
))
10843 /* Note that at this point x1 has already been
10845 rtx x0
= XEXP (x
, 0);
10846 rtx x1
= XEXP (x
, 1);
10848 /* If x0 and x1 are identical then there is no need to
10853 /* If x0 is identical to a subexpression of x1 then while
10854 processing x1, x0 has already been processed. Thus we
10855 are done with x. */
10856 if (ARITHMETIC_P (x1
)
10857 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
10860 /* If x1 is identical to a subexpression of x0 then we
10861 still have to process the rest of x0. */
10862 if (ARITHMETIC_P (x0
)
10863 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
10865 update_table_tick (XEXP (x0
, x1
== XEXP (x0
, 0) ? 1 : 0));
10870 update_table_tick (XEXP (x
, i
));
10874 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
10875 are saying that the register is clobbered and we no longer know its
10876 value. If INSN is zero, don't update reg_stat[].last_set; this is
10877 only permitted with VALUE also zero and is used to invalidate the
10881 record_value_for_reg (rtx reg
, rtx insn
, rtx value
)
10883 unsigned int regno
= REGNO (reg
);
10884 unsigned int endregno
10885 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
10886 ? hard_regno_nregs
[regno
][GET_MODE (reg
)] : 1);
10889 /* If VALUE contains REG and we have a previous value for REG, substitute
10890 the previous value. */
10891 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
10895 /* Set things up so get_last_value is allowed to see anything set up to
10897 subst_low_cuid
= INSN_CUID (insn
);
10898 tem
= get_last_value (reg
);
10900 /* If TEM is simply a binary operation with two CLOBBERs as operands,
10901 it isn't going to be useful and will take a lot of time to process,
10902 so just use the CLOBBER. */
10906 if (ARITHMETIC_P (tem
)
10907 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
10908 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
10909 tem
= XEXP (tem
, 0);
10910 else if (count_occurrences (value
, reg
, 1) >= 2)
10912 /* If there are two or more occurrences of REG in VALUE,
10913 prevent the value from growing too much. */
10914 if (count_rtxs (tem
) > MAX_LAST_VALUE_RTL
)
10915 tem
= gen_rtx_CLOBBER (GET_MODE (tem
), const0_rtx
);
10918 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
10922 /* For each register modified, show we don't know its value, that
10923 we don't know about its bitwise content, that its value has been
10924 updated, and that we don't know the location of the death of the
10926 for (i
= regno
; i
< endregno
; i
++)
10929 reg_stat
[i
].last_set
= insn
;
10931 reg_stat
[i
].last_set_value
= 0;
10932 reg_stat
[i
].last_set_mode
= 0;
10933 reg_stat
[i
].last_set_nonzero_bits
= 0;
10934 reg_stat
[i
].last_set_sign_bit_copies
= 0;
10935 reg_stat
[i
].last_death
= 0;
10938 /* Mark registers that are being referenced in this value. */
10940 update_table_tick (value
);
10942 /* Now update the status of each register being set.
10943 If someone is using this register in this block, set this register
10944 to invalid since we will get confused between the two lives in this
10945 basic block. This makes using this register always invalid. In cse, we
10946 scan the table to invalidate all entries using this register, but this
10947 is too much work for us. */
10949 for (i
= regno
; i
< endregno
; i
++)
10951 reg_stat
[i
].last_set_label
= label_tick
;
10952 if (value
&& reg_stat
[i
].last_set_table_tick
== label_tick
)
10953 reg_stat
[i
].last_set_invalid
= 1;
10955 reg_stat
[i
].last_set_invalid
= 0;
10958 /* The value being assigned might refer to X (like in "x++;"). In that
10959 case, we must replace it with (clobber (const_int 0)) to prevent
10961 if (value
&& ! get_last_value_validate (&value
, insn
,
10962 reg_stat
[regno
].last_set_label
, 0))
10964 value
= copy_rtx (value
);
10965 if (! get_last_value_validate (&value
, insn
,
10966 reg_stat
[regno
].last_set_label
, 1))
10970 /* For the main register being modified, update the value, the mode, the
10971 nonzero bits, and the number of sign bit copies. */
10973 reg_stat
[regno
].last_set_value
= value
;
10977 enum machine_mode mode
= GET_MODE (reg
);
10978 subst_low_cuid
= INSN_CUID (insn
);
10979 reg_stat
[regno
].last_set_mode
= mode
;
10980 if (GET_MODE_CLASS (mode
) == MODE_INT
10981 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10982 mode
= nonzero_bits_mode
;
10983 reg_stat
[regno
].last_set_nonzero_bits
= nonzero_bits (value
, mode
);
10984 reg_stat
[regno
].last_set_sign_bit_copies
10985 = num_sign_bit_copies (value
, GET_MODE (reg
));
10989 /* Called via note_stores from record_dead_and_set_regs to handle one
10990 SET or CLOBBER in an insn. DATA is the instruction in which the
10991 set is occurring. */
10994 record_dead_and_set_regs_1 (rtx dest
, rtx setter
, void *data
)
10996 rtx record_dead_insn
= (rtx
) data
;
10998 if (GET_CODE (dest
) == SUBREG
)
10999 dest
= SUBREG_REG (dest
);
11003 /* If we are setting the whole register, we know its value. Otherwise
11004 show that we don't know the value. We can handle SUBREG in
11006 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
11007 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
11008 else if (GET_CODE (setter
) == SET
11009 && GET_CODE (SET_DEST (setter
)) == SUBREG
11010 && SUBREG_REG (SET_DEST (setter
)) == dest
11011 && GET_MODE_BITSIZE (GET_MODE (dest
)) <= BITS_PER_WORD
11012 && subreg_lowpart_p (SET_DEST (setter
)))
11013 record_value_for_reg (dest
, record_dead_insn
,
11014 gen_lowpart (GET_MODE (dest
),
11015 SET_SRC (setter
)));
11017 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
11019 else if (MEM_P (dest
)
11020 /* Ignore pushes, they clobber nothing. */
11021 && ! push_operand (dest
, GET_MODE (dest
)))
11022 mem_last_set
= INSN_CUID (record_dead_insn
);
11025 /* Update the records of when each REG was most recently set or killed
11026 for the things done by INSN. This is the last thing done in processing
11027 INSN in the combiner loop.
11029 We update reg_stat[], in particular fields last_set, last_set_value,
11030 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
11031 last_death, and also the similar information mem_last_set (which insn
11032 most recently modified memory) and last_call_cuid (which insn was the
11033 most recent subroutine call). */
11036 record_dead_and_set_regs (rtx insn
)
11041 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
11043 if (REG_NOTE_KIND (link
) == REG_DEAD
11044 && REG_P (XEXP (link
, 0)))
11046 unsigned int regno
= REGNO (XEXP (link
, 0));
11047 unsigned int endregno
11048 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11049 ? hard_regno_nregs
[regno
][GET_MODE (XEXP (link
, 0))]
11052 for (i
= regno
; i
< endregno
; i
++)
11053 reg_stat
[i
].last_death
= insn
;
11055 else if (REG_NOTE_KIND (link
) == REG_INC
)
11056 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
11061 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
11062 if (TEST_HARD_REG_BIT (regs_invalidated_by_call
, i
))
11064 reg_stat
[i
].last_set_value
= 0;
11065 reg_stat
[i
].last_set_mode
= 0;
11066 reg_stat
[i
].last_set_nonzero_bits
= 0;
11067 reg_stat
[i
].last_set_sign_bit_copies
= 0;
11068 reg_stat
[i
].last_death
= 0;
11071 last_call_cuid
= mem_last_set
= INSN_CUID (insn
);
11073 /* Don't bother recording what this insn does. It might set the
11074 return value register, but we can't combine into a call
11075 pattern anyway, so there's no point trying (and it may cause
11076 a crash, if e.g. we wind up asking for last_set_value of a
11077 SUBREG of the return value register). */
11081 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
11084 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11085 register present in the SUBREG, so for each such SUBREG go back and
11086 adjust nonzero and sign bit information of the registers that are
11087 known to have some zero/sign bits set.
11089 This is needed because when combine blows the SUBREGs away, the
11090 information on zero/sign bits is lost and further combines can be
11091 missed because of that. */
11094 record_promoted_value (rtx insn
, rtx subreg
)
11097 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
11098 enum machine_mode mode
= GET_MODE (subreg
);
11100 if (GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
)
11103 for (links
= LOG_LINKS (insn
); links
;)
11105 insn
= XEXP (links
, 0);
11106 set
= single_set (insn
);
11108 if (! set
|| !REG_P (SET_DEST (set
))
11109 || REGNO (SET_DEST (set
)) != regno
11110 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
11112 links
= XEXP (links
, 1);
11116 if (reg_stat
[regno
].last_set
== insn
)
11118 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
) > 0)
11119 reg_stat
[regno
].last_set_nonzero_bits
&= GET_MODE_MASK (mode
);
11122 if (REG_P (SET_SRC (set
)))
11124 regno
= REGNO (SET_SRC (set
));
11125 links
= LOG_LINKS (insn
);
11132 /* Scan X for promoted SUBREGs. For each one found,
11133 note what it implies to the registers used in it. */
11136 check_promoted_subreg (rtx insn
, rtx x
)
11138 if (GET_CODE (x
) == SUBREG
&& SUBREG_PROMOTED_VAR_P (x
)
11139 && REG_P (SUBREG_REG (x
)))
11140 record_promoted_value (insn
, x
);
11143 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
11146 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
11150 check_promoted_subreg (insn
, XEXP (x
, i
));
11154 if (XVEC (x
, i
) != 0)
11155 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
11156 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
11162 /* Utility routine for the following function. Verify that all the registers
11163 mentioned in *LOC are valid when *LOC was part of a value set when
11164 label_tick == TICK. Return 0 if some are not.
11166 If REPLACE is nonzero, replace the invalid reference with
11167 (clobber (const_int 0)) and return 1. This replacement is useful because
11168 we often can get useful information about the form of a value (e.g., if
11169 it was produced by a shift that always produces -1 or 0) even though
11170 we don't know exactly what registers it was produced from. */
11173 get_last_value_validate (rtx
*loc
, rtx insn
, int tick
, int replace
)
11176 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
11177 int len
= GET_RTX_LENGTH (GET_CODE (x
));
11182 unsigned int regno
= REGNO (x
);
11183 unsigned int endregno
11184 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11185 ? hard_regno_nregs
[regno
][GET_MODE (x
)] : 1);
11188 for (j
= regno
; j
< endregno
; j
++)
11189 if (reg_stat
[j
].last_set_invalid
11190 /* If this is a pseudo-register that was only set once and not
11191 live at the beginning of the function, it is always valid. */
11192 || (! (regno
>= FIRST_PSEUDO_REGISTER
11193 && REG_N_SETS (regno
) == 1
11194 && (! REGNO_REG_SET_P
11195 (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
, regno
)))
11196 && reg_stat
[j
].last_set_label
> tick
))
11199 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11205 /* If this is a memory reference, make sure that there were
11206 no stores after it that might have clobbered the value. We don't
11207 have alias info, so we assume any store invalidates it. */
11208 else if (MEM_P (x
) && !MEM_READONLY_P (x
)
11209 && INSN_CUID (insn
) <= mem_last_set
)
11212 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11216 for (i
= 0; i
< len
; i
++)
11220 /* Check for identical subexpressions. If x contains
11221 identical subexpression we only have to traverse one of
11223 if (i
== 1 && ARITHMETIC_P (x
))
11225 /* Note that at this point x0 has already been checked
11226 and found valid. */
11227 rtx x0
= XEXP (x
, 0);
11228 rtx x1
= XEXP (x
, 1);
11230 /* If x0 and x1 are identical then x is also valid. */
11234 /* If x1 is identical to a subexpression of x0 then
11235 while checking x0, x1 has already been checked. Thus
11236 it is valid and so as x. */
11237 if (ARITHMETIC_P (x0
)
11238 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
11241 /* If x0 is identical to a subexpression of x1 then x is
11242 valid iff the rest of x1 is valid. */
11243 if (ARITHMETIC_P (x1
)
11244 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
11246 get_last_value_validate (&XEXP (x1
,
11247 x0
== XEXP (x1
, 0) ? 1 : 0),
11248 insn
, tick
, replace
);
11251 if (get_last_value_validate (&XEXP (x
, i
), insn
, tick
,
11255 /* Don't bother with these. They shouldn't occur anyway. */
11256 else if (fmt
[i
] == 'E')
11260 /* If we haven't found a reason for it to be invalid, it is valid. */
11264 /* Get the last value assigned to X, if known. Some registers
11265 in the value may be replaced with (clobber (const_int 0)) if their value
11266 is known longer known reliably. */
11269 get_last_value (rtx x
)
11271 unsigned int regno
;
11274 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11275 then convert it to the desired mode. If this is a paradoxical SUBREG,
11276 we cannot predict what values the "extra" bits might have. */
11277 if (GET_CODE (x
) == SUBREG
11278 && subreg_lowpart_p (x
)
11279 && (GET_MODE_SIZE (GET_MODE (x
))
11280 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
11281 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
11282 return gen_lowpart (GET_MODE (x
), value
);
11288 value
= reg_stat
[regno
].last_set_value
;
11290 /* If we don't have a value, or if it isn't for this basic block and
11291 it's either a hard register, set more than once, or it's a live
11292 at the beginning of the function, return 0.
11294 Because if it's not live at the beginning of the function then the reg
11295 is always set before being used (is never used without being set).
11296 And, if it's set only once, and it's always set before use, then all
11297 uses must have the same last value, even if it's not from this basic
11301 || (reg_stat
[regno
].last_set_label
!= label_tick
11302 && (regno
< FIRST_PSEUDO_REGISTER
11303 || REG_N_SETS (regno
) != 1
11304 || (REGNO_REG_SET_P
11305 (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
, regno
)))))
11308 /* If the value was set in a later insn than the ones we are processing,
11309 we can't use it even if the register was only set once. */
11310 if (INSN_CUID (reg_stat
[regno
].last_set
) >= subst_low_cuid
)
11313 /* If the value has all its registers valid, return it. */
11314 if (get_last_value_validate (&value
, reg_stat
[regno
].last_set
,
11315 reg_stat
[regno
].last_set_label
, 0))
11318 /* Otherwise, make a copy and replace any invalid register with
11319 (clobber (const_int 0)). If that fails for some reason, return 0. */
11321 value
= copy_rtx (value
);
11322 if (get_last_value_validate (&value
, reg_stat
[regno
].last_set
,
11323 reg_stat
[regno
].last_set_label
, 1))
11329 /* Return nonzero if expression X refers to a REG or to memory
11330 that is set in an instruction more recent than FROM_CUID. */
11333 use_crosses_set_p (rtx x
, int from_cuid
)
11337 enum rtx_code code
= GET_CODE (x
);
11341 unsigned int regno
= REGNO (x
);
11342 unsigned endreg
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11343 ? hard_regno_nregs
[regno
][GET_MODE (x
)] : 1);
11345 #ifdef PUSH_ROUNDING
11346 /* Don't allow uses of the stack pointer to be moved,
11347 because we don't know whether the move crosses a push insn. */
11348 if (regno
== STACK_POINTER_REGNUM
&& PUSH_ARGS
)
11351 for (; regno
< endreg
; regno
++)
11352 if (reg_stat
[regno
].last_set
11353 && INSN_CUID (reg_stat
[regno
].last_set
) > from_cuid
)
11358 if (code
== MEM
&& mem_last_set
> from_cuid
)
11361 fmt
= GET_RTX_FORMAT (code
);
11363 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11368 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
11369 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_cuid
))
11372 else if (fmt
[i
] == 'e'
11373 && use_crosses_set_p (XEXP (x
, i
), from_cuid
))
11379 /* Define three variables used for communication between the following
11382 static unsigned int reg_dead_regno
, reg_dead_endregno
;
11383 static int reg_dead_flag
;
11385 /* Function called via note_stores from reg_dead_at_p.
11387 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11388 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11391 reg_dead_at_p_1 (rtx dest
, rtx x
, void *data ATTRIBUTE_UNUSED
)
11393 unsigned int regno
, endregno
;
11398 regno
= REGNO (dest
);
11399 endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11400 ? hard_regno_nregs
[regno
][GET_MODE (dest
)] : 1);
11402 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
11403 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
11406 /* Return nonzero if REG is known to be dead at INSN.
11408 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11409 referencing REG, it is dead. If we hit a SET referencing REG, it is
11410 live. Otherwise, see if it is live or dead at the start of the basic
11411 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11412 must be assumed to be always live. */
11415 reg_dead_at_p (rtx reg
, rtx insn
)
11420 /* Set variables for reg_dead_at_p_1. */
11421 reg_dead_regno
= REGNO (reg
);
11422 reg_dead_endregno
= reg_dead_regno
+ (reg_dead_regno
< FIRST_PSEUDO_REGISTER
11423 ? hard_regno_nregs
[reg_dead_regno
]
11429 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
11430 we allow the machine description to decide whether use-and-clobber
11431 patterns are OK. */
11432 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
11434 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
11435 if (!fixed_regs
[i
] && TEST_HARD_REG_BIT (newpat_used_regs
, i
))
11439 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11440 beginning of function. */
11441 for (; insn
&& !LABEL_P (insn
) && !BARRIER_P (insn
);
11442 insn
= prev_nonnote_insn (insn
))
11444 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
11446 return reg_dead_flag
== 1 ? 1 : 0;
11448 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
11452 /* Get the basic block that we were in. */
11454 block
= ENTRY_BLOCK_PTR
->next_bb
;
11457 FOR_EACH_BB (block
)
11458 if (insn
== BB_HEAD (block
))
11461 if (block
== EXIT_BLOCK_PTR
)
11465 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
11466 if (REGNO_REG_SET_P (block
->global_live_at_start
, i
))
11472 /* Note hard registers in X that are used. This code is similar to
11473 that in flow.c, but much simpler since we don't care about pseudos. */
11476 mark_used_regs_combine (rtx x
)
11478 RTX_CODE code
= GET_CODE (x
);
11479 unsigned int regno
;
11492 case ADDR_DIFF_VEC
:
11495 /* CC0 must die in the insn after it is set, so we don't need to take
11496 special note of it here. */
11502 /* If we are clobbering a MEM, mark any hard registers inside the
11503 address as used. */
11504 if (MEM_P (XEXP (x
, 0)))
11505 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
11510 /* A hard reg in a wide mode may really be multiple registers.
11511 If so, mark all of them just like the first. */
11512 if (regno
< FIRST_PSEUDO_REGISTER
)
11514 unsigned int endregno
, r
;
11516 /* None of this applies to the stack, frame or arg pointers. */
11517 if (regno
== STACK_POINTER_REGNUM
11518 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11519 || regno
== HARD_FRAME_POINTER_REGNUM
11521 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11522 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
11524 || regno
== FRAME_POINTER_REGNUM
)
11527 endregno
= regno
+ hard_regno_nregs
[regno
][GET_MODE (x
)];
11528 for (r
= regno
; r
< endregno
; r
++)
11529 SET_HARD_REG_BIT (newpat_used_regs
, r
);
11535 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11537 rtx testreg
= SET_DEST (x
);
11539 while (GET_CODE (testreg
) == SUBREG
11540 || GET_CODE (testreg
) == ZERO_EXTRACT
11541 || GET_CODE (testreg
) == STRICT_LOW_PART
)
11542 testreg
= XEXP (testreg
, 0);
11544 if (MEM_P (testreg
))
11545 mark_used_regs_combine (XEXP (testreg
, 0));
11547 mark_used_regs_combine (SET_SRC (x
));
11555 /* Recursively scan the operands of this expression. */
11558 const char *fmt
= GET_RTX_FORMAT (code
);
11560 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11563 mark_used_regs_combine (XEXP (x
, i
));
11564 else if (fmt
[i
] == 'E')
11568 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
11569 mark_used_regs_combine (XVECEXP (x
, i
, j
));
11575 /* Remove register number REGNO from the dead registers list of INSN.
11577 Return the note used to record the death, if there was one. */
11580 remove_death (unsigned int regno
, rtx insn
)
11582 rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
11586 REG_N_DEATHS (regno
)--;
11587 remove_note (insn
, note
);
11593 /* For each register (hardware or pseudo) used within expression X, if its
11594 death is in an instruction with cuid between FROM_CUID (inclusive) and
11595 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11596 list headed by PNOTES.
11598 That said, don't move registers killed by maybe_kill_insn.
11600 This is done when X is being merged by combination into TO_INSN. These
11601 notes will then be distributed as needed. */
11604 move_deaths (rtx x
, rtx maybe_kill_insn
, int from_cuid
, rtx to_insn
,
11609 enum rtx_code code
= GET_CODE (x
);
11613 unsigned int regno
= REGNO (x
);
11614 rtx where_dead
= reg_stat
[regno
].last_death
;
11615 rtx before_dead
, after_dead
;
11617 /* Don't move the register if it gets killed in between from and to. */
11618 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
11619 && ! reg_referenced_p (x
, maybe_kill_insn
))
11622 /* WHERE_DEAD could be a USE insn made by combine, so first we
11623 make sure that we have insns with valid INSN_CUID values. */
11624 before_dead
= where_dead
;
11625 while (before_dead
&& INSN_UID (before_dead
) > max_uid_cuid
)
11626 before_dead
= PREV_INSN (before_dead
);
11628 after_dead
= where_dead
;
11629 while (after_dead
&& INSN_UID (after_dead
) > max_uid_cuid
)
11630 after_dead
= NEXT_INSN (after_dead
);
11632 if (before_dead
&& after_dead
11633 && INSN_CUID (before_dead
) >= from_cuid
11634 && (INSN_CUID (after_dead
) < INSN_CUID (to_insn
)
11635 || (where_dead
!= after_dead
11636 && INSN_CUID (after_dead
) == INSN_CUID (to_insn
))))
11638 rtx note
= remove_death (regno
, where_dead
);
11640 /* It is possible for the call above to return 0. This can occur
11641 when last_death points to I2 or I1 that we combined with.
11642 In that case make a new note.
11644 We must also check for the case where X is a hard register
11645 and NOTE is a death note for a range of hard registers
11646 including X. In that case, we must put REG_DEAD notes for
11647 the remaining registers in place of NOTE. */
11649 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
11650 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
11651 > GET_MODE_SIZE (GET_MODE (x
))))
11653 unsigned int deadregno
= REGNO (XEXP (note
, 0));
11654 unsigned int deadend
11655 = (deadregno
+ hard_regno_nregs
[deadregno
]
11656 [GET_MODE (XEXP (note
, 0))]);
11657 unsigned int ourend
11658 = regno
+ hard_regno_nregs
[regno
][GET_MODE (x
)];
11661 for (i
= deadregno
; i
< deadend
; i
++)
11662 if (i
< regno
|| i
>= ourend
)
11663 REG_NOTES (where_dead
)
11664 = gen_rtx_EXPR_LIST (REG_DEAD
,
11666 REG_NOTES (where_dead
));
11669 /* If we didn't find any note, or if we found a REG_DEAD note that
11670 covers only part of the given reg, and we have a multi-reg hard
11671 register, then to be safe we must check for REG_DEAD notes
11672 for each register other than the first. They could have
11673 their own REG_DEAD notes lying around. */
11674 else if ((note
== 0
11676 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
11677 < GET_MODE_SIZE (GET_MODE (x
)))))
11678 && regno
< FIRST_PSEUDO_REGISTER
11679 && hard_regno_nregs
[regno
][GET_MODE (x
)] > 1)
11681 unsigned int ourend
11682 = regno
+ hard_regno_nregs
[regno
][GET_MODE (x
)];
11683 unsigned int i
, offset
;
11687 offset
= hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))];
11691 for (i
= regno
+ offset
; i
< ourend
; i
++)
11692 move_deaths (regno_reg_rtx
[i
],
11693 maybe_kill_insn
, from_cuid
, to_insn
, &oldnotes
);
11696 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
11698 XEXP (note
, 1) = *pnotes
;
11702 *pnotes
= gen_rtx_EXPR_LIST (REG_DEAD
, x
, *pnotes
);
11704 REG_N_DEATHS (regno
)++;
11710 else if (GET_CODE (x
) == SET
)
11712 rtx dest
= SET_DEST (x
);
11714 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
11716 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11717 that accesses one word of a multi-word item, some
11718 piece of everything register in the expression is used by
11719 this insn, so remove any old death. */
11720 /* ??? So why do we test for equality of the sizes? */
11722 if (GET_CODE (dest
) == ZERO_EXTRACT
11723 || GET_CODE (dest
) == STRICT_LOW_PART
11724 || (GET_CODE (dest
) == SUBREG
11725 && (((GET_MODE_SIZE (GET_MODE (dest
))
11726 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
11727 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
11728 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
11730 move_deaths (dest
, maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
11734 /* If this is some other SUBREG, we know it replaces the entire
11735 value, so use that as the destination. */
11736 if (GET_CODE (dest
) == SUBREG
)
11737 dest
= SUBREG_REG (dest
);
11739 /* If this is a MEM, adjust deaths of anything used in the address.
11740 For a REG (the only other possibility), the entire value is
11741 being replaced so the old value is not used in this insn. */
11744 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_cuid
,
11749 else if (GET_CODE (x
) == CLOBBER
)
11752 len
= GET_RTX_LENGTH (code
);
11753 fmt
= GET_RTX_FORMAT (code
);
11755 for (i
= 0; i
< len
; i
++)
11760 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
11761 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_cuid
,
11764 else if (fmt
[i
] == 'e')
11765 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
11769 /* Return 1 if X is the target of a bit-field assignment in BODY, the
11770 pattern of an insn. X must be a REG. */
11773 reg_bitfield_target_p (rtx x
, rtx body
)
11777 if (GET_CODE (body
) == SET
)
11779 rtx dest
= SET_DEST (body
);
11781 unsigned int regno
, tregno
, endregno
, endtregno
;
11783 if (GET_CODE (dest
) == ZERO_EXTRACT
)
11784 target
= XEXP (dest
, 0);
11785 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
11786 target
= SUBREG_REG (XEXP (dest
, 0));
11790 if (GET_CODE (target
) == SUBREG
)
11791 target
= SUBREG_REG (target
);
11793 if (!REG_P (target
))
11796 tregno
= REGNO (target
), regno
= REGNO (x
);
11797 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
11798 return target
== x
;
11800 endtregno
= tregno
+ hard_regno_nregs
[tregno
][GET_MODE (target
)];
11801 endregno
= regno
+ hard_regno_nregs
[regno
][GET_MODE (x
)];
11803 return endregno
> tregno
&& regno
< endtregno
;
11806 else if (GET_CODE (body
) == PARALLEL
)
11807 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
11808 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
11814 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
11815 as appropriate. I3 and I2 are the insns resulting from the combination
11816 insns including FROM (I2 may be zero).
11818 Each note in the list is either ignored or placed on some insns, depending
11819 on the type of note. */
11822 distribute_notes (rtx notes
, rtx from_insn
, rtx i3
, rtx i2
)
11824 rtx note
, next_note
;
11827 for (note
= notes
; note
; note
= next_note
)
11829 rtx place
= 0, place2
= 0;
11831 /* If this NOTE references a pseudo register, ensure it references
11832 the latest copy of that register. */
11833 if (XEXP (note
, 0) && REG_P (XEXP (note
, 0))
11834 && REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
)
11835 XEXP (note
, 0) = regno_reg_rtx
[REGNO (XEXP (note
, 0))];
11837 next_note
= XEXP (note
, 1);
11838 switch (REG_NOTE_KIND (note
))
11842 /* Doesn't matter much where we put this, as long as it's somewhere.
11843 It is preferable to keep these notes on branches, which is most
11844 likely to be i3. */
11848 case REG_VALUE_PROFILE
:
11849 /* Just get rid of this note, as it is unused later anyway. */
11852 case REG_NON_LOCAL_GOTO
:
11857 gcc_assert (i2
&& JUMP_P (i2
));
11862 case REG_EH_REGION
:
11863 /* These notes must remain with the call or trapping instruction. */
11866 else if (i2
&& CALL_P (i2
))
11870 gcc_assert (flag_non_call_exceptions
);
11871 if (may_trap_p (i3
))
11873 else if (i2
&& may_trap_p (i2
))
11875 /* ??? Otherwise assume we've combined things such that we
11876 can now prove that the instructions can't trap. Drop the
11877 note in this case. */
11881 case REG_ALWAYS_RETURN
:
11884 /* These notes must remain with the call. It should not be
11885 possible for both I2 and I3 to be a call. */
11890 gcc_assert (i2
&& CALL_P (i2
));
11896 /* Any clobbers for i3 may still exist, and so we must process
11897 REG_UNUSED notes from that insn.
11899 Any clobbers from i2 or i1 can only exist if they were added by
11900 recog_for_combine. In that case, recog_for_combine created the
11901 necessary REG_UNUSED notes. Trying to keep any original
11902 REG_UNUSED notes from these insns can cause incorrect output
11903 if it is for the same register as the original i3 dest.
11904 In that case, we will notice that the register is set in i3,
11905 and then add a REG_UNUSED note for the destination of i3, which
11906 is wrong. However, it is possible to have REG_UNUSED notes from
11907 i2 or i1 for register which were both used and clobbered, so
11908 we keep notes from i2 or i1 if they will turn into REG_DEAD
11911 /* If this register is set or clobbered in I3, put the note there
11912 unless there is one already. */
11913 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
11915 if (from_insn
!= i3
)
11918 if (! (REG_P (XEXP (note
, 0))
11919 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
11920 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
11923 /* Otherwise, if this register is used by I3, then this register
11924 now dies here, so we must put a REG_DEAD note here unless there
11926 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
11927 && ! (REG_P (XEXP (note
, 0))
11928 ? find_regno_note (i3
, REG_DEAD
,
11929 REGNO (XEXP (note
, 0)))
11930 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
11932 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
11940 /* These notes say something about results of an insn. We can
11941 only support them if they used to be on I3 in which case they
11942 remain on I3. Otherwise they are ignored.
11944 If the note refers to an expression that is not a constant, we
11945 must also ignore the note since we cannot tell whether the
11946 equivalence is still true. It might be possible to do
11947 slightly better than this (we only have a problem if I2DEST
11948 or I1DEST is present in the expression), but it doesn't
11949 seem worth the trouble. */
11951 if (from_insn
== i3
11952 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
11957 case REG_NO_CONFLICT
:
11958 /* These notes say something about how a register is used. They must
11959 be present on any use of the register in I2 or I3. */
11960 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
11963 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
11973 /* This can show up in several ways -- either directly in the
11974 pattern, or hidden off in the constant pool with (or without?)
11975 a REG_EQUAL note. */
11976 /* ??? Ignore the without-reg_equal-note problem for now. */
11977 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
11978 || ((tem
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
11979 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
11980 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0)))
11984 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
11985 || ((tem
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
11986 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
11987 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0))))
11995 /* Don't attach REG_LABEL note to a JUMP_INSN. Add
11996 a JUMP_LABEL instead or decrement LABEL_NUSES. */
11997 if (place
&& JUMP_P (place
))
11999 rtx label
= JUMP_LABEL (place
);
12002 JUMP_LABEL (place
) = XEXP (note
, 0);
12005 gcc_assert (label
== XEXP (note
, 0));
12006 if (LABEL_P (label
))
12007 LABEL_NUSES (label
)--;
12011 if (place2
&& JUMP_P (place2
))
12013 rtx label
= JUMP_LABEL (place2
);
12016 JUMP_LABEL (place2
) = XEXP (note
, 0);
12019 gcc_assert (label
== XEXP (note
, 0));
12020 if (LABEL_P (label
))
12021 LABEL_NUSES (label
)--;
12028 /* This note says something about the value of a register prior
12029 to the execution of an insn. It is too much trouble to see
12030 if the note is still correct in all situations. It is better
12031 to simply delete it. */
12035 /* If the insn previously containing this note still exists,
12036 put it back where it was. Otherwise move it to the previous
12037 insn. Adjust the corresponding REG_LIBCALL note. */
12038 if (!NOTE_P (from_insn
))
12042 tem
= find_reg_note (XEXP (note
, 0), REG_LIBCALL
, NULL_RTX
);
12043 place
= prev_real_insn (from_insn
);
12045 XEXP (tem
, 0) = place
;
12046 /* If we're deleting the last remaining instruction of a
12047 libcall sequence, don't add the notes. */
12048 else if (XEXP (note
, 0) == from_insn
)
12050 /* Don't add the dangling REG_RETVAL note. */
12057 /* This is handled similarly to REG_RETVAL. */
12058 if (!NOTE_P (from_insn
))
12062 tem
= find_reg_note (XEXP (note
, 0), REG_RETVAL
, NULL_RTX
);
12063 place
= next_real_insn (from_insn
);
12065 XEXP (tem
, 0) = place
;
12066 /* If we're deleting the last remaining instruction of a
12067 libcall sequence, don't add the notes. */
12068 else if (XEXP (note
, 0) == from_insn
)
12070 /* Don't add the dangling REG_LIBCALL note. */
12077 /* If the register is used as an input in I3, it dies there.
12078 Similarly for I2, if it is nonzero and adjacent to I3.
12080 If the register is not used as an input in either I3 or I2
12081 and it is not one of the registers we were supposed to eliminate,
12082 there are two possibilities. We might have a non-adjacent I2
12083 or we might have somehow eliminated an additional register
12084 from a computation. For example, we might have had A & B where
12085 we discover that B will always be zero. In this case we will
12086 eliminate the reference to A.
12088 In both cases, we must search to see if we can find a previous
12089 use of A and put the death note there. */
12092 && CALL_P (from_insn
)
12093 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
12095 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
12097 else if (i2
!= 0 && next_nonnote_insn (i2
) == i3
12098 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12103 basic_block bb
= this_basic_block
;
12105 for (tem
= PREV_INSN (i3
); place
== 0; tem
= PREV_INSN (tem
))
12107 if (! INSN_P (tem
))
12109 if (tem
== BB_HEAD (bb
))
12114 /* If the register is being set at TEM, see if that is all
12115 TEM is doing. If so, delete TEM. Otherwise, make this
12116 into a REG_UNUSED note instead. Don't delete sets to
12117 global register vars. */
12118 if ((REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
12119 || !global_regs
[REGNO (XEXP (note
, 0))])
12120 && reg_set_p (XEXP (note
, 0), PATTERN (tem
)))
12122 rtx set
= single_set (tem
);
12123 rtx inner_dest
= 0;
12125 rtx cc0_setter
= NULL_RTX
;
12129 for (inner_dest
= SET_DEST (set
);
12130 (GET_CODE (inner_dest
) == STRICT_LOW_PART
12131 || GET_CODE (inner_dest
) == SUBREG
12132 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
12133 inner_dest
= XEXP (inner_dest
, 0))
12136 /* Verify that it was the set, and not a clobber that
12137 modified the register.
12139 CC0 targets must be careful to maintain setter/user
12140 pairs. If we cannot delete the setter due to side
12141 effects, mark the user with an UNUSED note instead
12144 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
12145 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
12147 && (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
12148 || ((cc0_setter
= prev_cc0_setter (tem
)) != NULL
12149 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))
12153 /* Move the notes and links of TEM elsewhere.
12154 This might delete other dead insns recursively.
12155 First set the pattern to something that won't use
12157 rtx old_notes
= REG_NOTES (tem
);
12159 PATTERN (tem
) = pc_rtx
;
12160 REG_NOTES (tem
) = NULL
;
12162 distribute_notes (old_notes
, tem
, tem
, NULL_RTX
);
12163 distribute_links (LOG_LINKS (tem
));
12165 SET_INSN_DELETED (tem
);
12168 /* Delete the setter too. */
12171 PATTERN (cc0_setter
) = pc_rtx
;
12172 old_notes
= REG_NOTES (cc0_setter
);
12173 REG_NOTES (cc0_setter
) = NULL
;
12175 distribute_notes (old_notes
, cc0_setter
,
12176 cc0_setter
, NULL_RTX
);
12177 distribute_links (LOG_LINKS (cc0_setter
));
12179 SET_INSN_DELETED (cc0_setter
);
12185 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
12187 /* If there isn't already a REG_UNUSED note, put one
12188 here. Do not place a REG_DEAD note, even if
12189 the register is also used here; that would not
12190 match the algorithm used in lifetime analysis
12191 and can cause the consistency check in the
12192 scheduler to fail. */
12193 if (! find_regno_note (tem
, REG_UNUSED
,
12194 REGNO (XEXP (note
, 0))))
12199 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem
))
12201 && find_reg_fusage (tem
, USE
, XEXP (note
, 0))))
12205 /* If we are doing a 3->2 combination, and we have a
12206 register which formerly died in i3 and was not used
12207 by i2, which now no longer dies in i3 and is used in
12208 i2 but does not die in i2, and place is between i2
12209 and i3, then we may need to move a link from place to
12211 if (i2
&& INSN_UID (place
) <= max_uid_cuid
12212 && INSN_CUID (place
) > INSN_CUID (i2
)
12214 && INSN_CUID (from_insn
) > INSN_CUID (i2
)
12215 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12217 rtx links
= LOG_LINKS (place
);
12218 LOG_LINKS (place
) = 0;
12219 distribute_links (links
);
12224 if (tem
== BB_HEAD (bb
))
12228 /* We haven't found an insn for the death note and it
12229 is still a REG_DEAD note, but we have hit the beginning
12230 of the block. If the existing life info says the reg
12231 was dead, there's nothing left to do. Otherwise, we'll
12232 need to do a global life update after combine. */
12233 if (REG_NOTE_KIND (note
) == REG_DEAD
&& place
== 0
12234 && REGNO_REG_SET_P (bb
->global_live_at_start
,
12235 REGNO (XEXP (note
, 0))))
12236 SET_BIT (refresh_blocks
, this_basic_block
->index
);
12239 /* If the register is set or already dead at PLACE, we needn't do
12240 anything with this note if it is still a REG_DEAD note.
12241 We check here if it is set at all, not if is it totally replaced,
12242 which is what `dead_or_set_p' checks, so also check for it being
12245 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
12247 unsigned int regno
= REGNO (XEXP (note
, 0));
12249 /* Similarly, if the instruction on which we want to place
12250 the note is a noop, we'll need do a global live update
12251 after we remove them in delete_noop_moves. */
12252 if (noop_move_p (place
))
12253 SET_BIT (refresh_blocks
, this_basic_block
->index
);
12255 if (dead_or_set_p (place
, XEXP (note
, 0))
12256 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
12258 /* Unless the register previously died in PLACE, clear
12259 last_death. [I no longer understand why this is
12261 if (reg_stat
[regno
].last_death
!= place
)
12262 reg_stat
[regno
].last_death
= 0;
12266 reg_stat
[regno
].last_death
= place
;
12268 /* If this is a death note for a hard reg that is occupying
12269 multiple registers, ensure that we are still using all
12270 parts of the object. If we find a piece of the object
12271 that is unused, we must arrange for an appropriate REG_DEAD
12272 note to be added for it. However, we can't just emit a USE
12273 and tag the note to it, since the register might actually
12274 be dead; so we recourse, and the recursive call then finds
12275 the previous insn that used this register. */
12277 if (place
&& regno
< FIRST_PSEUDO_REGISTER
12278 && hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))] > 1)
12280 unsigned int endregno
12281 = regno
+ hard_regno_nregs
[regno
]
12282 [GET_MODE (XEXP (note
, 0))];
12286 for (i
= regno
; i
< endregno
; i
++)
12287 if ((! refers_to_regno_p (i
, i
+ 1, PATTERN (place
), 0)
12288 && ! find_regno_fusage (place
, USE
, i
))
12289 || dead_or_set_regno_p (place
, i
))
12294 /* Put only REG_DEAD notes for pieces that are
12295 not already dead or set. */
12297 for (i
= regno
; i
< endregno
;
12298 i
+= hard_regno_nregs
[i
][reg_raw_mode
[i
]])
12300 rtx piece
= regno_reg_rtx
[i
];
12301 basic_block bb
= this_basic_block
;
12303 if (! dead_or_set_p (place
, piece
)
12304 && ! reg_bitfield_target_p (piece
,
12308 = gen_rtx_EXPR_LIST (REG_DEAD
, piece
, NULL_RTX
);
12310 distribute_notes (new_note
, place
, place
,
12313 else if (! refers_to_regno_p (i
, i
+ 1,
12314 PATTERN (place
), 0)
12315 && ! find_regno_fusage (place
, USE
, i
))
12316 for (tem
= PREV_INSN (place
); ;
12317 tem
= PREV_INSN (tem
))
12319 if (! INSN_P (tem
))
12321 if (tem
== BB_HEAD (bb
))
12323 SET_BIT (refresh_blocks
,
12324 this_basic_block
->index
);
12329 if (dead_or_set_p (tem
, piece
)
12330 || reg_bitfield_target_p (piece
,
12334 = gen_rtx_EXPR_LIST (REG_UNUSED
, piece
,
12349 /* Any other notes should not be present at this point in the
12351 gcc_unreachable ();
12356 XEXP (note
, 1) = REG_NOTES (place
);
12357 REG_NOTES (place
) = note
;
12359 else if ((REG_NOTE_KIND (note
) == REG_DEAD
12360 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12361 && REG_P (XEXP (note
, 0)))
12362 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
12366 if ((REG_NOTE_KIND (note
) == REG_DEAD
12367 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12368 && REG_P (XEXP (note
, 0)))
12369 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
12371 REG_NOTES (place2
) = gen_rtx_fmt_ee (GET_CODE (note
),
12372 REG_NOTE_KIND (note
),
12374 REG_NOTES (place2
));
12379 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12380 I3, I2, and I1 to new locations. This is also called to add a link
12381 pointing at I3 when I3's destination is changed. */
12384 distribute_links (rtx links
)
12386 rtx link
, next_link
;
12388 for (link
= links
; link
; link
= next_link
)
12394 next_link
= XEXP (link
, 1);
12396 /* If the insn that this link points to is a NOTE or isn't a single
12397 set, ignore it. In the latter case, it isn't clear what we
12398 can do other than ignore the link, since we can't tell which
12399 register it was for. Such links wouldn't be used by combine
12402 It is not possible for the destination of the target of the link to
12403 have been changed by combine. The only potential of this is if we
12404 replace I3, I2, and I1 by I3 and I2. But in that case the
12405 destination of I2 also remains unchanged. */
12407 if (NOTE_P (XEXP (link
, 0))
12408 || (set
= single_set (XEXP (link
, 0))) == 0)
12411 reg
= SET_DEST (set
);
12412 while (GET_CODE (reg
) == SUBREG
|| GET_CODE (reg
) == ZERO_EXTRACT
12413 || GET_CODE (reg
) == STRICT_LOW_PART
)
12414 reg
= XEXP (reg
, 0);
12416 /* A LOG_LINK is defined as being placed on the first insn that uses
12417 a register and points to the insn that sets the register. Start
12418 searching at the next insn after the target of the link and stop
12419 when we reach a set of the register or the end of the basic block.
12421 Note that this correctly handles the link that used to point from
12422 I3 to I2. Also note that not much searching is typically done here
12423 since most links don't point very far away. */
12425 for (insn
= NEXT_INSN (XEXP (link
, 0));
12426 (insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
12427 || BB_HEAD (this_basic_block
->next_bb
) != insn
));
12428 insn
= NEXT_INSN (insn
))
12429 if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
12431 if (reg_referenced_p (reg
, PATTERN (insn
)))
12435 else if (CALL_P (insn
)
12436 && find_reg_fusage (insn
, USE
, reg
))
12441 else if (INSN_P (insn
) && reg_set_p (reg
, insn
))
12444 /* If we found a place to put the link, place it there unless there
12445 is already a link to the same insn as LINK at that point. */
12451 for (link2
= LOG_LINKS (place
); link2
; link2
= XEXP (link2
, 1))
12452 if (XEXP (link2
, 0) == XEXP (link
, 0))
12457 XEXP (link
, 1) = LOG_LINKS (place
);
12458 LOG_LINKS (place
) = link
;
12460 /* Set added_links_insn to the earliest insn we added a
12462 if (added_links_insn
== 0
12463 || INSN_CUID (added_links_insn
) > INSN_CUID (place
))
12464 added_links_insn
= place
;
12470 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
12471 Check whether the expression pointer to by LOC is a register or
12472 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
12473 Otherwise return zero. */
12476 unmentioned_reg_p_1 (rtx
*loc
, void *expr
)
12481 && (REG_P (x
) || MEM_P (x
))
12482 && ! reg_mentioned_p (x
, (rtx
) expr
))
12487 /* Check for any register or memory mentioned in EQUIV that is not
12488 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
12489 of EXPR where some registers may have been replaced by constants. */
12492 unmentioned_reg_p (rtx equiv
, rtx expr
)
12494 return for_each_rtx (&equiv
, unmentioned_reg_p_1
, expr
);
12497 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
12500 insn_cuid (rtx insn
)
12502 while (insn
!= 0 && INSN_UID (insn
) > max_uid_cuid
12503 && NONJUMP_INSN_P (insn
) && GET_CODE (PATTERN (insn
)) == USE
)
12504 insn
= NEXT_INSN (insn
);
12506 gcc_assert (INSN_UID (insn
) <= max_uid_cuid
);
12508 return INSN_CUID (insn
);
12512 dump_combine_stats (FILE *file
)
12516 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12517 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
12521 dump_combine_total_stats (FILE *file
)
12525 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12526 total_attempts
, total_merges
, total_extras
, total_successes
);