sys/platform/vkernel/i386/npx.c

   1 /*
   2  * Copyright (c) 2006 The DragonFly Project.  All rights reserved.
   3  * Copyright (c) 1990 William Jolitz.
   4  * Copyright (c) 1991 The Regents of the University of California.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to The DragonFly Project
   8  * by Matthew Dillon <dillon@backplane.com>
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  *
  14  * 1. Redistributions of source code must retain the above copyright
  15  *    notice, this list of conditions and the following disclaimer.
  16  * 2. Redistributions in binary form must reproduce the above copyright
  17  *    notice, this list of conditions and the following disclaimer in
  18  *    the documentation and/or other materials provided with the
  19  *    distribution.
  20  * 3. Neither the name of The DragonFly Project nor the names of its
  21  *    contributors may be used to endorse or promote products derived
  22  *    from this software without specific, prior written permission.
  23  *
  24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  25  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  26  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  27  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
  28  * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  29  * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
  30  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  31  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  32  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  33  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  34  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  35  * SUCH DAMAGE.
  36  *
  37  * from: @(#)npx.c      7.2 (Berkeley) 5/12/91
  38  * $FreeBSD: src/sys/i386/isa/npx.c,v 1.80.2.3 2001/10/20 19:04:38 tegge Exp $
  39  * $DragonFly: src/sys/platform/vkernel/i386/npx.c,v 1.8 2008/01/29 19:54:56 dillon Exp $
  40  */
  41
  42 #include "opt_debug_npx.h"
  43
  44 #include <sys/param.h>
  45 #include <sys/systm.h>
  46 #include <sys/bus.h>
  47 #include <sys/kernel.h>
  48 #include <sys/malloc.h>
  49 #include <sys/module.h>
  50 #include <sys/sysctl.h>
  51 #include <sys/proc.h>
  52 #include <sys/rman.h>
  53 #ifdef NPX_DEBUG
  54 #include <sys/syslog.h>
  55 #endif
  56 #include <sys/signalvar.h>
  57
  58 #include <sys/thread2.h>
  59 #include <sys/mplock2.h>
  60
  61 #ifndef SMP
  62 #include <machine/asmacros.h>
  63 #endif
  64 #include <machine/cputypes.h>
  65 #include <machine/frame.h>
  66 #include <machine/md_var.h>
  67 #include <machine/pcb.h>
  68 #include <machine/psl.h>
  69 #ifndef SMP
  70 #include <machine/clock.h>
  71 #endif
  72 #include <machine/specialreg.h>
  73 #include <machine/segments.h>
  74 #include <machine/globaldata.h>
  75
  76 #define fldcw(addr)             __asm("fldcw %0" : : "m" (*(addr)))
  77 #define fnclex()                __asm("fnclex")
  78 #define fninit()                __asm("fninit")
  79 #define fnop()                  __asm("fnop")
  80 #define fnsave(addr)            __asm __volatile("fnsave %0" : "=m" (*(addr)))
  81 #define fnstcw(addr)            __asm __volatile("fnstcw %0" : "=m" (*(addr)))
  82 #define fnstsw(addr)            __asm __volatile("fnstsw %0" : "=m" (*(addr)))
  83 #define frstor(addr)            __asm("frstor %0" : : "m" (*(addr)))
  84 #ifndef CPU_DISABLE_SSE
  85 #define fxrstor(addr)           __asm("fxrstor %0" : : "m" (*(addr)))
  86 #define fxsave(addr)            __asm __volatile("fxsave %0" : "=m" (*(addr)))
  87 #endif
  88
  89 #ifndef CPU_DISABLE_SSE
  90 #define GET_FPU_EXSW_PTR(td) \
  91         (cpu_fxsr ? \
  92                 &(td)->td_savefpu->sv_xmm.sv_ex_sw : \
  93                 &(td)->td_savefpu->sv_87.sv_ex_sw)
  94 #else /* CPU_DISABLE_SSE */
  95 #define GET_FPU_EXSW_PTR(td) \
  96         (&(td)->td_savefpu->sv_87.sv_ex_sw)
  97 #endif /* CPU_DISABLE_SSE */
  98
  99 typedef u_char bool_t;
 100 #ifndef CPU_DISABLE_SSE
 101 static  void    fpu_clean_state(void);
 102 #endif
 103
 104 int cpu_fxsr = 0;
 105
 106 static struct krate badfprate = { 1 };
 107
 108 /*static        int     npx_attach      (device_t dev);*/
 109 static  void    fpusave         (union savefpu *);
 110 static  void    fpurstor        (union savefpu *);
 111
 112 #if (defined(I586_CPU) || defined(I686_CPU)) && !defined(CPU_DISABLE_SSE)
 113 int mmxopt = 1;
 114 SYSCTL_INT(_kern, OID_AUTO, mmxopt, CTLFLAG_RD, &mmxopt, 0,
 115         "MMX/XMM optimized bcopy/copyin/copyout support");
 116 #endif
 117
 118 static int      hw_instruction_sse;
 119 SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD,
 120     &hw_instruction_sse, 0, "SIMD/MMX2 instructions available in CPU");
 121
 122 #if 0
 123 /*
 124  * Attach routine - announce which it is, and wire into system
 125  */
 126 int
 127 npx_attach(device_t dev)
 128 {
 129         npxinit(__INITIAL_NPXCW__);
 130         return (0);
 131 }
 132 #endif
 133
 134 void
 135 init_fpu(int supports_sse)
 136 {
 137         cpu_fxsr = hw_instruction_sse = supports_sse;
 138 }
 139
 140 /*
 141  * Initialize the floating point unit.
 142  */
 143 void
 144 npxinit(u_short control)
 145 {
 146         static union savefpu dummy __aligned(16);
 147
 148         /*
 149          * fninit has the same h/w bugs as fnsave.  Use the detoxified
 150          * fnsave to throw away any junk in the fpu.  npxsave() initializes
 151          * the fpu and sets npxthread = NULL as important side effects.
 152          */
 153         npxsave(&dummy);
 154         crit_enter();
 155         /*stop_emulating();*/
 156         fldcw(&control);
 157         fpusave(curthread->td_savefpu);
 158         mdcpu->gd_npxthread = NULL;
 159         /*start_emulating();*/
 160         crit_exit();
 161 }
 162
 163 /*
 164  * Free coprocessor (if we have it).
 165  */
 166 void
 167 npxexit(void)
 168 {
 169         if (curthread == mdcpu->gd_npxthread)
 170                 npxsave(curthread->td_savefpu);
 171 }
 172
 173 #if 0
 174 /*
 175  * The following mechanism is used to ensure that the FPE_... value
 176  * that is passed as a trapcode to the signal handler of the user
 177  * process does not have more than one bit set.
 178  *
 179  * Multiple bits may be set if the user process modifies the control
 180  * word while a status word bit is already set.  While this is a sign
 181  * of bad coding, we have no choise than to narrow them down to one
 182  * bit, since we must not send a trapcode that is not exactly one of
 183  * the FPE_ macros.
 184  *
 185  * The mechanism has a static table with 127 entries.  Each combination
 186  * of the 7 FPU status word exception bits directly translates to a
 187  * position in this table, where a single FPE_... value is stored.
 188  * This FPE_... value stored there is considered the "most important"
 189  * of the exception bits and will be sent as the signal code.  The
 190  * precedence of the bits is based upon Intel Document "Numerical
 191  * Applications", Chapter "Special Computational Situations".
 192  *
 193  * The macro to choose one of these values does these steps: 1) Throw
 194  * away status word bits that cannot be masked.  2) Throw away the bits
 195  * currently masked in the control word, assuming the user isn't
 196  * interested in them anymore.  3) Reinsert status word bit 7 (stack
 197  * fault) if it is set, which cannot be masked but must be presered.
 198  * 4) Use the remaining bits to point into the trapcode table.
 199  *
 200  * The 6 maskable bits in order of their preference, as stated in the
 201  * above referenced Intel manual:
 202  * 1  Invalid operation (FP_X_INV)
 203  * 1a   Stack underflow
 204  * 1b   Stack overflow
 205  * 1c   Operand of unsupported format
 206  * 1d   SNaN operand.
 207  * 2  QNaN operand (not an exception, irrelavant here)
 208  * 3  Any other invalid-operation not mentioned above or zero divide
 209  *      (FP_X_INV, FP_X_DZ)
 210  * 4  Denormal operand (FP_X_DNML)
 211  * 5  Numeric over/underflow (FP_X_OFL, FP_X_UFL)
 212  * 6  Inexact result (FP_X_IMP)
 213  */
 214 static char fpetable[128] = {
 215         0,
 216         FPE_FLTINV,     /*  1 - INV */
 217         FPE_FLTUND,     /*  2 - DNML */
 218         FPE_FLTINV,     /*  3 - INV | DNML */
 219         FPE_FLTDIV,     /*  4 - DZ */
 220         FPE_FLTINV,     /*  5 - INV | DZ */
 221         FPE_FLTDIV,     /*  6 - DNML | DZ */
 222         FPE_FLTINV,     /*  7 - INV | DNML | DZ */
 223         FPE_FLTOVF,     /*  8 - OFL */
 224         FPE_FLTINV,     /*  9 - INV | OFL */
 225         FPE_FLTUND,     /*  A - DNML | OFL */
 226         FPE_FLTINV,     /*  B - INV | DNML | OFL */
 227         FPE_FLTDIV,     /*  C - DZ | OFL */
 228         FPE_FLTINV,     /*  D - INV | DZ | OFL */
 229         FPE_FLTDIV,     /*  E - DNML | DZ | OFL */
 230         FPE_FLTINV,     /*  F - INV | DNML | DZ | OFL */
 231         FPE_FLTUND,     /* 10 - UFL */
 232         FPE_FLTINV,     /* 11 - INV | UFL */
 233         FPE_FLTUND,     /* 12 - DNML | UFL */
 234         FPE_FLTINV,     /* 13 - INV | DNML | UFL */
 235         FPE_FLTDIV,     /* 14 - DZ | UFL */
 236         FPE_FLTINV,     /* 15 - INV | DZ | UFL */
 237         FPE_FLTDIV,     /* 16 - DNML | DZ | UFL */
 238         FPE_FLTINV,     /* 17 - INV | DNML | DZ | UFL */
 239         FPE_FLTOVF,     /* 18 - OFL | UFL */
 240         FPE_FLTINV,     /* 19 - INV | OFL | UFL */
 241         FPE_FLTUND,     /* 1A - DNML | OFL | UFL */
 242         FPE_FLTINV,     /* 1B - INV | DNML | OFL | UFL */
 243         FPE_FLTDIV,     /* 1C - DZ | OFL | UFL */
 244         FPE_FLTINV,     /* 1D - INV | DZ | OFL | UFL */
 245         FPE_FLTDIV,     /* 1E - DNML | DZ | OFL | UFL */
 246         FPE_FLTINV,     /* 1F - INV | DNML | DZ | OFL | UFL */
 247         FPE_FLTRES,     /* 20 - IMP */
 248         FPE_FLTINV,     /* 21 - INV | IMP */
 249         FPE_FLTUND,     /* 22 - DNML | IMP */
 250         FPE_FLTINV,     /* 23 - INV | DNML | IMP */
 251         FPE_FLTDIV,     /* 24 - DZ | IMP */
 252         FPE_FLTINV,     /* 25 - INV | DZ | IMP */
 253         FPE_FLTDIV,     /* 26 - DNML | DZ | IMP */
 254         FPE_FLTINV,     /* 27 - INV | DNML | DZ | IMP */
 255         FPE_FLTOVF,     /* 28 - OFL | IMP */
 256         FPE_FLTINV,     /* 29 - INV | OFL | IMP */
 257         FPE_FLTUND,     /* 2A - DNML | OFL | IMP */
 258         FPE_FLTINV,     /* 2B - INV | DNML | OFL | IMP */
 259         FPE_FLTDIV,     /* 2C - DZ | OFL | IMP */
 260         FPE_FLTINV,     /* 2D - INV | DZ | OFL | IMP */
 261         FPE_FLTDIV,     /* 2E - DNML | DZ | OFL | IMP */
 262         FPE_FLTINV,     /* 2F - INV | DNML | DZ | OFL | IMP */
 263         FPE_FLTUND,     /* 30 - UFL | IMP */
 264         FPE_FLTINV,     /* 31 - INV | UFL | IMP */
 265         FPE_FLTUND,     /* 32 - DNML | UFL | IMP */
 266         FPE_FLTINV,     /* 33 - INV | DNML | UFL | IMP */
 267         FPE_FLTDIV,     /* 34 - DZ | UFL | IMP */
 268         FPE_FLTINV,     /* 35 - INV | DZ | UFL | IMP */
 269         FPE_FLTDIV,     /* 36 - DNML | DZ | UFL | IMP */
 270         FPE_FLTINV,     /* 37 - INV | DNML | DZ | UFL | IMP */
 271         FPE_FLTOVF,     /* 38 - OFL | UFL | IMP */
 272         FPE_FLTINV,     /* 39 - INV | OFL | UFL | IMP */
 273         FPE_FLTUND,     /* 3A - DNML | OFL | UFL | IMP */
 274         FPE_FLTINV,     /* 3B - INV | DNML | OFL | UFL | IMP */
 275         FPE_FLTDIV,     /* 3C - DZ | OFL | UFL | IMP */
 276         FPE_FLTINV,     /* 3D - INV | DZ | OFL | UFL | IMP */
 277         FPE_FLTDIV,     /* 3E - DNML | DZ | OFL | UFL | IMP */
 278         FPE_FLTINV,     /* 3F - INV | DNML | DZ | OFL | UFL | IMP */
 279         FPE_FLTSUB,     /* 40 - STK */
 280         FPE_FLTSUB,     /* 41 - INV | STK */
 281         FPE_FLTUND,     /* 42 - DNML | STK */
 282         FPE_FLTSUB,     /* 43 - INV | DNML | STK */
 283         FPE_FLTDIV,     /* 44 - DZ | STK */
 284         FPE_FLTSUB,     /* 45 - INV | DZ | STK */
 285         FPE_FLTDIV,     /* 46 - DNML | DZ | STK */
 286         FPE_FLTSUB,     /* 47 - INV | DNML | DZ | STK */
 287         FPE_FLTOVF,     /* 48 - OFL | STK */
 288         FPE_FLTSUB,     /* 49 - INV | OFL | STK */
 289         FPE_FLTUND,     /* 4A - DNML | OFL | STK */
 290         FPE_FLTSUB,     /* 4B - INV | DNML | OFL | STK */
 291         FPE_FLTDIV,     /* 4C - DZ | OFL | STK */
 292         FPE_FLTSUB,     /* 4D - INV | DZ | OFL | STK */
 293         FPE_FLTDIV,     /* 4E - DNML | DZ | OFL | STK */
 294         FPE_FLTSUB,     /* 4F - INV | DNML | DZ | OFL | STK */
 295         FPE_FLTUND,     /* 50 - UFL | STK */
 296         FPE_FLTSUB,     /* 51 - INV | UFL | STK */
 297         FPE_FLTUND,     /* 52 - DNML | UFL | STK */
 298         FPE_FLTSUB,     /* 53 - INV | DNML | UFL | STK */
 299         FPE_FLTDIV,     /* 54 - DZ | UFL | STK */
 300         FPE_FLTSUB,     /* 55 - INV | DZ | UFL | STK */
 301         FPE_FLTDIV,     /* 56 - DNML | DZ | UFL | STK */
 302         FPE_FLTSUB,     /* 57 - INV | DNML | DZ | UFL | STK */
 303         FPE_FLTOVF,     /* 58 - OFL | UFL | STK */
 304         FPE_FLTSUB,     /* 59 - INV | OFL | UFL | STK */
 305         FPE_FLTUND,     /* 5A - DNML | OFL | UFL | STK */
 306         FPE_FLTSUB,     /* 5B - INV | DNML | OFL | UFL | STK */
 307         FPE_FLTDIV,     /* 5C - DZ | OFL | UFL | STK */
 308         FPE_FLTSUB,     /* 5D - INV | DZ | OFL | UFL | STK */
 309         FPE_FLTDIV,     /* 5E - DNML | DZ | OFL | UFL | STK */
 310         FPE_FLTSUB,     /* 5F - INV | DNML | DZ | OFL | UFL | STK */
 311         FPE_FLTRES,     /* 60 - IMP | STK */
 312         FPE_FLTSUB,     /* 61 - INV | IMP | STK */
 313         FPE_FLTUND,     /* 62 - DNML | IMP | STK */
 314         FPE_FLTSUB,     /* 63 - INV | DNML | IMP | STK */
 315         FPE_FLTDIV,     /* 64 - DZ | IMP | STK */
 316         FPE_FLTSUB,     /* 65 - INV | DZ | IMP | STK */
 317         FPE_FLTDIV,     /* 66 - DNML | DZ | IMP | STK */
 318         FPE_FLTSUB,     /* 67 - INV | DNML | DZ | IMP | STK */
 319         FPE_FLTOVF,     /* 68 - OFL | IMP | STK */
 320         FPE_FLTSUB,     /* 69 - INV | OFL | IMP | STK */
 321         FPE_FLTUND,     /* 6A - DNML | OFL | IMP | STK */
 322         FPE_FLTSUB,     /* 6B - INV | DNML | OFL | IMP | STK */
 323         FPE_FLTDIV,     /* 6C - DZ | OFL | IMP | STK */
 324         FPE_FLTSUB,     /* 6D - INV | DZ | OFL | IMP | STK */
 325         FPE_FLTDIV,     /* 6E - DNML | DZ | OFL | IMP | STK */
 326         FPE_FLTSUB,     /* 6F - INV | DNML | DZ | OFL | IMP | STK */
 327         FPE_FLTUND,     /* 70 - UFL | IMP | STK */
 328         FPE_FLTSUB,     /* 71 - INV | UFL | IMP | STK */
 329         FPE_FLTUND,     /* 72 - DNML | UFL | IMP | STK */
 330         FPE_FLTSUB,     /* 73 - INV | DNML | UFL | IMP | STK */
 331         FPE_FLTDIV,     /* 74 - DZ | UFL | IMP | STK */
 332         FPE_FLTSUB,     /* 75 - INV | DZ | UFL | IMP | STK */
 333         FPE_FLTDIV,     /* 76 - DNML | DZ | UFL | IMP | STK */
 334         FPE_FLTSUB,     /* 77 - INV | DNML | DZ | UFL | IMP | STK */
 335         FPE_FLTOVF,     /* 78 - OFL | UFL | IMP | STK */
 336         FPE_FLTSUB,     /* 79 - INV | OFL | UFL | IMP | STK */
 337         FPE_FLTUND,     /* 7A - DNML | OFL | UFL | IMP | STK */
 338         FPE_FLTSUB,     /* 7B - INV | DNML | OFL | UFL | IMP | STK */
 339         FPE_FLTDIV,     /* 7C - DZ | OFL | UFL | IMP | STK */
 340         FPE_FLTSUB,     /* 7D - INV | DZ | OFL | UFL | IMP | STK */
 341         FPE_FLTDIV,     /* 7E - DNML | DZ | OFL | UFL | IMP | STK */
 342         FPE_FLTSUB,     /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */
 343 };
 344 #endif
 345
 346 #if 0
 347
 348 /*
 349  * Preserve the FP status word, clear FP exceptions, then generate a SIGFPE.
 350  *
 351  * Clearing exceptions is necessary mainly to avoid IRQ13 bugs.  We now
 352  * depend on longjmp() restoring a usable state.  Restoring the state
 353  * or examining it might fail if we didn't clear exceptions.
 354  *
 355  * The error code chosen will be one of the FPE_... macros. It will be
 356  * sent as the second argument to old BSD-style signal handlers and as
 357  * "siginfo_t->si_code" (second argument) to SA_SIGINFO signal handlers.
 358  *
 359  * XXX the FP state is not preserved across signal handlers.  So signal
 360  * handlers cannot afford to do FP unless they preserve the state or
 361  * longjmp() out.  Both preserving the state and longjmp()ing may be
 362  * destroyed by IRQ13 bugs.  Clearing FP exceptions is not an acceptable
 363  * solution for signals other than SIGFPE.
 364  *
 365  * The MP lock is not held on entry (see i386/i386/exception.s) and
 366  * should not be held on exit.  Interrupts are enabled.  We must enter
 367  * a critical section to stabilize the FP system and prevent an interrupt
 368  * or preemption from changing the FP state out from under us.
 369  */
 370 void
 371 npx_intr(void *dummy)
 372 {
 373         int code;
 374         u_short control;
 375         struct intrframe *frame;
 376         u_long *exstat;
 377
 378         crit_enter();
 379
 380         /*
 381          * This exception can only occur with CR0_TS clear, otherwise we
 382          * would get a DNA exception.  However, since interrupts were
 383          * enabled a preemption could have sneaked in and used the FP system
 384          * before we entered our critical section.  If that occured, the
 385          * TS bit will be set and npxthread will be NULL.
 386          */
 387         panic("npx_intr: not coded");
 388         /* XXX FP STATE FLAG MUST BE PART OF CONTEXT SUPPLIED BY REAL KERNEL */
 389 #if 0
 390         if (rcr0() & CR0_TS) {
 391                 KASSERT(mdcpu->gd_npxthread == NULL, ("gd_npxthread was %p with TS set!", mdcpu->gd_npxthread));
 392                 npxdna();
 393                 crit_exit();
 394                 return;
 395         }
 396 #endif
 397         if (mdcpu->gd_npxthread == NULL) {
 398                 get_mplock();
 399                 kprintf("npxintr: npxthread = %p, curthread = %p\n",
 400                        mdcpu->gd_npxthread, curthread);
 401                 panic("npxintr from nowhere");
 402         }
 403         if (mdcpu->gd_npxthread != curthread) {
 404                 get_mplock();
 405                 kprintf("npxintr: npxthread = %p, curthread = %p\n",
 406                        mdcpu->gd_npxthread, curthread);
 407                 panic("npxintr from non-current process");
 408         }
 409
 410         exstat = GET_FPU_EXSW_PTR(curthread);
 411         outb(0xf0, 0);
 412         fnstsw(exstat);
 413         fnstcw(&control);
 414         fnclex();
 415
 416         get_mplock();
 417
 418         /*
 419          * Pass exception to process.
 420          */
 421         frame = (struct intrframe *)&dummy;     /* XXX */
 422         if ((ISPL(frame->if_cs) == SEL_UPL) /*||(frame->if_eflags&PSL_VM)*/) {
 423                 /*
 424                  * Interrupt is essentially a trap, so we can afford to call
 425                  * the SIGFPE handler (if any) as soon as the interrupt
 426                  * returns.
 427                  *
 428                  * XXX little or nothing is gained from this, and plenty is
 429                  * lost - the interrupt frame has to contain the trap frame
 430                  * (this is otherwise only necessary for the rescheduling trap
 431                  * in doreti, and the frame for that could easily be set up
 432                  * just before it is used).
 433                  */
 434                 curthread->td_lwp->lwp_md.md_regs = INTR_TO_TRAPFRAME(frame);
 435                 /*
 436                  * Encode the appropriate code for detailed information on
 437                  * this exception.
 438                  */
 439                 code =
 440                     fpetable[(*exstat & ~control & 0x3f) | (*exstat & 0x40)];
 441                 trapsignal(curthread->td_lwp, SIGFPE, code);
 442         } else {
 443                 /*
 444                  * Nested interrupt.  These losers occur when:
 445                  *      o an IRQ13 is bogusly generated at a bogus time, e.g.:
 446                  *              o immediately after an fnsave or frstor of an
 447                  *                error state.
 448                  *              o a couple of 386 instructions after
 449                  *                "fstpl _memvar" causes a stack overflow.
 450                  *        These are especially nasty when combined with a
 451                  *        trace trap.
 452                  *      o an IRQ13 occurs at the same time as another higher-
 453                  *        priority interrupt.
 454                  *
 455                  * Treat them like a true async interrupt.
 456                  */
 457                 lwpsignal(curproc, curthread->td_lwp, SIGFPE);
 458         }
 459         rel_mplock();
 460         crit_exit();
 461 }
 462
 463 #endif
 464
 465 /*
 466  * Implement the device not available (DNA) exception.  gd_npxthread had
 467  * better be NULL.  Restore the current thread's FP state and set gd_npxthread
 468  * to curthread.
 469  *
 470  * Interrupts are enabled and preemption can occur.  Enter a critical
 471  * section to stabilize the FP state.
 472  */
 473 int
 474 npxdna(struct trapframe *frame)
 475 {
 476         thread_t td = curthread;
 477         u_long *exstat;
 478         int didinit = 0;
 479
 480         if (mdcpu->gd_npxthread != NULL) {
 481                 kprintf("npxdna: npxthread = %p, curthread = %p\n",
 482                        mdcpu->gd_npxthread, td);
 483                 panic("npxdna");
 484         }
 485
 486         /*
 487          * Setup the initial saved state if the thread has never before
 488          * used the FP unit.  This also occurs when a thread pushes a
 489          * signal handler and uses FP in the handler.
 490          */
 491         if ((curthread->td_flags & TDF_USINGFP) == 0) {
 492                 curthread->td_flags |= TDF_USINGFP;
 493                 npxinit(__INITIAL_NPXCW__);
 494                 didinit = 1;
 495         }
 496
 497         /*
 498          * The setting of gd_npxthread and the call to fpurstor() must not
 499          * be preempted by an interrupt thread or we will take an npxdna
 500          * trap and potentially save our current fpstate (which is garbage)
 501          * and then restore the garbage rather then the originally saved
 502          * fpstate.
 503          */
 504         crit_enter();
 505         /*stop_emulating();*/
 506         /*
 507          * Record new context early in case frstor causes an IRQ13.
 508          */
 509         mdcpu->gd_npxthread = td;
 510         exstat = GET_FPU_EXSW_PTR(td);
 511         *exstat = 0;
 512         /*
 513          * The following frstor may cause an IRQ13 when the state being
 514          * restored has a pending error.  The error will appear to have been
 515          * triggered by the current (npx) user instruction even when that
 516          * instruction is a no-wait instruction that should not trigger an
 517          * error (e.g., fnclex).  On at least one 486 system all of the
 518          * no-wait instructions are broken the same as frstor, so our
 519          * treatment does not amplify the breakage.  On at least one
 520          * 386/Cyrix 387 system, fnclex works correctly while frstor and
 521          * fnsave are broken, so our treatment breaks fnclex if it is the
 522          * first FPU instruction after a context switch.
 523          */
 524         if ((td->td_savefpu->sv_xmm.sv_env.en_mxcsr & ~0xFFBF) && cpu_fxsr) {
 525                 krateprintf(&badfprate,
 526                             "FXRSTR: illegal FP MXCSR %08x didinit = %d\n",
 527                             td->td_savefpu->sv_xmm.sv_env.en_mxcsr, didinit);
 528                 td->td_savefpu->sv_xmm.sv_env.en_mxcsr &= 0xFFBF;
 529                 lwpsignal(curproc, curthread->td_lwp, SIGFPE);
 530         }
 531         fpurstor(curthread->td_savefpu);
 532         crit_exit();
 533
 534         return (1);
 535 }
 536
 537 /*
 538  * Wrapper for the fnsave instruction to handle h/w bugs.  If there is an error
 539  * pending, then fnsave generates a bogus IRQ13 on some systems.  Force
 540  * any IRQ13 to be handled immediately, and then ignore it.  This routine is
 541  * often called at splhigh so it must not use many system services.  In
 542  * particular, it's much easier to install a special handler than to
 543  * guarantee that it's safe to use npxintr() and its supporting code.
 544  *
 545  * WARNING!  This call is made during a switch and the MP lock will be
 546  * setup for the new target thread rather then the current thread, so we
 547  * cannot do anything here that depends on the *_mplock() functions as
 548  * we may trip over their assertions.
 549  *
 550  * WARNING!  When using fxsave we MUST fninit after saving the FP state.  The
 551  * kernel will always assume that the FP state is 'safe' (will not cause
 552  * exceptions) for mmx/xmm use if npxthread is NULL.  The kernel must still
 553  * setup a custom save area before actually using the FP unit, but it will
 554  * not bother calling fninit.  This greatly improves kernel performance when
 555  * it wishes to use the FP unit.
 556  */
 557 void
 558 npxsave(union savefpu *addr)
 559 {
 560         crit_enter();
 561         /*stop_emulating();*/
 562         fpusave(addr);
 563         mdcpu->gd_npxthread = NULL;
 564         fninit();
 565         /*start_emulating();*/
 566         crit_exit();
 567 }
 568
 569 static void
 570 fpusave(union savefpu *addr)
 571 {
 572         if (cpu_fxsr)
 573                 fxsave(addr);
 574         else
 575                 fnsave(addr);
 576 }
 577
 578 /*
 579  * Save the FP state to the mcontext structure.
 580  *
 581  * WARNING: If you want to try to npxsave() directly to mctx->mc_fpregs,
 582  * then it MUST be 16-byte aligned.  Currently this is not guarenteed.
 583  */
 584 void
 585 npxpush(mcontext_t *mctx)
 586 {
 587         thread_t td = curthread;
 588
 589         if (td->td_flags & TDF_USINGFP) {
 590                 if (mdcpu->gd_npxthread == td) {
 591                         /*
 592                          * XXX Note: This is a bit inefficient if the signal
 593                          * handler uses floating point, extra faults will
 594                          * occur.
 595                          */
 596                         mctx->mc_ownedfp = _MC_FPOWNED_FPU;
 597                         npxsave(td->td_savefpu);
 598                 } else {
 599                         mctx->mc_ownedfp = _MC_FPOWNED_PCB;
 600                 }
 601                 bcopy(td->td_savefpu, mctx->mc_fpregs, sizeof(mctx->mc_fpregs));
 602                 td->td_flags &= ~TDF_USINGFP;
 603                 mctx->mc_fpformat =
 604 #ifndef CPU_DISABLE_SSE
 605                         (cpu_fxsr) ? _MC_FPFMT_XMM :
 606 #endif
 607                         _MC_FPFMT_387;
 608         } else {
 609                 mctx->mc_ownedfp = _MC_FPOWNED_NONE;
 610                 mctx->mc_fpformat = _MC_FPFMT_NODEV;
 611         }
 612 }
 613
 614 /*
 615  * Restore the FP state from the mcontext structure.
 616  */
 617 void
 618 npxpop(mcontext_t *mctx)
 619 {
 620         thread_t td = curthread;
 621
 622         switch(mctx->mc_ownedfp) {
 623         case _MC_FPOWNED_NONE:
 624                 /*
 625                  * If the signal handler used the FP unit but the interrupted
 626                  * code did not, release the FP unit.  Clear TDF_USINGFP will
 627                  * force the FP unit to reinit so the interrupted code sees
 628                  * a clean slate.
 629                  */
 630                 if (td->td_flags & TDF_USINGFP) {
 631                         if (td == mdcpu->gd_npxthread)
 632                                 npxsave(td->td_savefpu);
 633                         td->td_flags &= ~TDF_USINGFP;
 634                 }
 635                 break;
 636         case _MC_FPOWNED_FPU:
 637         case _MC_FPOWNED_PCB:
 638                 /*
 639                  * Clear ownership of the FP unit and restore our saved state.
 640                  *
 641                  * NOTE: The signal handler may have set-up some FP state and
 642                  * enabled the FP unit, so we have to restore no matter what.
 643                  *
 644                  * XXX: This is bit inefficient, if the code being returned
 645                  * to is actively using the FP this results in multiple
 646                  * kernel faults.
 647                  *
 648                  * WARNING: The saved state was exposed to userland and may
 649                  * have to be sanitized to avoid a GP fault in the kernel.
 650                  */
 651                 if (td == mdcpu->gd_npxthread)
 652                         npxsave(td->td_savefpu);
 653                 bcopy(mctx->mc_fpregs, td->td_savefpu, sizeof(*td->td_savefpu));
 654                 if ((td->td_savefpu->sv_xmm.sv_env.en_mxcsr & ~0xFFBF) &&
 655                     cpu_fxsr) {
 656                         krateprintf(&badfprate,
 657                                     "pid %d (%s) signal return from user: "
 658                                     "illegal FP MXCSR %08x\n",
 659                                     td->td_proc->p_pid,
 660                                     td->td_proc->p_comm,
 661                                     td->td_savefpu->sv_xmm.sv_env.en_mxcsr);
 662                         td->td_savefpu->sv_xmm.sv_env.en_mxcsr &= 0xFFBF;
 663                 }
 664                 td->td_flags |= TDF_USINGFP;
 665                 break;
 666         }
 667 }
 668
 669
 670 #ifndef CPU_DISABLE_SSE
 671 /*
 672  * On AuthenticAMD processors, the fxrstor instruction does not restore
 673  * the x87's stored last instruction pointer, last data pointer, and last
 674  * opcode values, except in the rare case in which the exception summary
 675  * (ES) bit in the x87 status word is set to 1.
 676  *
 677  * In order to avoid leaking this information across processes, we clean
 678  * these values by performing a dummy load before executing fxrstor().
 679  */
 680 static  double  dummy_variable = 0.0;
 681 static void
 682 fpu_clean_state(void)
 683 {
 684         u_short status;
 685
 686         /*
 687          * Clear the ES bit in the x87 status word if it is currently
 688          * set, in order to avoid causing a fault in the upcoming load.
 689          */
 690         fnstsw(&status);
 691         if (status & 0x80)
 692                 fnclex();
 693
 694         /*
 695          * Load the dummy variable into the x87 stack.  This mangles
 696          * the x87 stack, but we don't care since we're about to call
 697          * fxrstor() anyway.
 698          */
 699         __asm __volatile("ffree %%st(7); fld %0" : : "m" (dummy_variable));
 700 }
 701 #endif /* CPU_DISABLE_SSE */
 702
 703 static void
 704 fpurstor(union savefpu *addr)
 705 {
 706 #ifndef CPU_DISABLE_SSE
 707         if (cpu_fxsr) {
 708                 fpu_clean_state();
 709                 fxrstor(addr);
 710         } else {
 711                 frstor(addr);
 712         }
 713 #else
 714         frstor(addr);
 715 #endif
 716 }
 717