sys/platform/pc64/x86_64/npx.c

   1 /*
   2  * Copyright (c) 1990 William Jolitz.
   3  * Copyright (c) 1991 The Regents of the University of California.
   4  * Copyright (c) 2006 The DragonFly Project.
   5  * Copyright (c) 2006 Matthew Dillon.
   6  * All rights reserved.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  *
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in
  16  *    the documentation and/or other materials provided with the
  17  *    distribution.
  18  * 3. Neither the name of The DragonFly Project nor the names of its
  19  *    contributors may be used to endorse or promote products derived
  20  *    from this software without specific, prior written permission.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  23  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  24  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  25  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
  26  * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  27  * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
  28  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  29  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  30  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  31  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  32  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  33  * SUCH DAMAGE.
  34  *
  35  * from: @(#)npx.c      7.2 (Berkeley) 5/12/91
  36  * $FreeBSD: src/sys/i386/isa/npx.c,v 1.80.2.3 2001/10/20 19:04:38 tegge Exp $
  37  */
  38
  39 #include "opt_debug_npx.h"
  40
  41 #include <sys/param.h>
  42 #include <sys/systm.h>
  43 #include <sys/bus.h>
  44 #include <sys/kernel.h>
  45 #include <sys/malloc.h>
  46 #include <sys/module.h>
  47 #include <sys/sysctl.h>
  48 #include <sys/proc.h>
  49 #include <sys/rman.h>
  50 #ifdef NPX_DEBUG
  51 #include <sys/syslog.h>
  52 #endif
  53 #include <sys/signalvar.h>
  54
  55 #include <sys/thread2.h>
  56 #include <sys/mplock2.h>
  57
  58 #ifndef SMP
  59 #include <machine/asmacros.h>
  60 #endif
  61 #include <machine/cputypes.h>
  62 #include <machine/frame.h>
  63 #include <machine/md_var.h>
  64 #include <machine/pcb.h>
  65 #include <machine/psl.h>
  66 #ifndef SMP
  67 #include <machine/clock.h>
  68 #endif
  69 #include <machine/specialreg.h>
  70 #include <machine/segments.h>
  71 #include <machine/globaldata.h>
  72
  73 #define fldcw(addr)             __asm("fldcw %0" : : "m" (*(addr)))
  74 #define fnclex()                __asm("fnclex")
  75 #define fninit()                __asm("fninit")
  76 #define fnop()                  __asm("fnop")
  77 #define fnsave(addr)            __asm __volatile("fnsave %0" : "=m" (*(addr)))
  78 #define fnstcw(addr)            __asm __volatile("fnstcw %0" : "=m" (*(addr)))
  79 #define fnstsw(addr)            __asm __volatile("fnstsw %0" : "=m" (*(addr)))
  80 #define frstor(addr)            __asm("frstor %0" : : "m" (*(addr)))
  81 #ifndef CPU_DISABLE_SSE
  82 #define fxrstor(addr)           __asm("fxrstor %0" : : "m" (*(addr)))
  83 #define fxsave(addr)            __asm __volatile("fxsave %0" : "=m" (*(addr)))
  84 #endif
  85 #define start_emulating()       __asm("smsw %%ax; orb %0,%%al; lmsw %%ax" \
  86                                       : : "n" (CR0_TS) : "ax")
  87 #define stop_emulating()        __asm("clts")
  88
  89 #ifndef CPU_DISABLE_SSE
  90 #define GET_FPU_EXSW_PTR(td) \
  91         (cpu_fxsr ? \
  92                 &(td)->td_savefpu->sv_xmm.sv_ex_sw : \
  93                 &(td)->td_savefpu->sv_87.sv_ex_sw)
  94 #else /* CPU_DISABLE_SSE */
  95 #define GET_FPU_EXSW_PTR(td) \
  96         (&(td)->td_savefpu->sv_87.sv_ex_sw)
  97 #endif /* CPU_DISABLE_SSE */
  98
  99 typedef u_char bool_t;
 100 #ifndef CPU_DISABLE_SSE
 101 static  void    fpu_clean_state(void);
 102 #endif
 103
 104 static struct krate badfprate = { 1 };
 105
 106 static  void    fpusave         (union savefpu *);
 107 static  void    fpurstor        (union savefpu *);
 108
 109 /*
 110  * Initialize the floating point unit.
 111  */
 112 void
 113 npxinit(u_short control)
 114 {
 115         static union savefpu dummy __aligned(16);
 116
 117         /*
 118          * fninit has the same h/w bugs as fnsave.  Use the detoxified
 119          * fnsave to throw away any junk in the fpu.  npxsave() initializes
 120          * the fpu and sets npxthread = NULL as important side effects.
 121          */
 122         npxsave(&dummy);
 123         crit_enter();
 124         stop_emulating();
 125         fldcw(&control);
 126         fpusave(curthread->td_savefpu);
 127         mdcpu->gd_npxthread = NULL;
 128         start_emulating();
 129         crit_exit();
 130 }
 131
 132 /*
 133  * Free coprocessor (if we have it).
 134  */
 135 void
 136 npxexit(void)
 137 {
 138         if (curthread == mdcpu->gd_npxthread)
 139                 npxsave(curthread->td_savefpu);
 140 }
 141
 142 #if 0
 143 /*
 144  * The following mechanism is used to ensure that the FPE_... value
 145  * that is passed as a trapcode to the signal handler of the user
 146  * process does not have more than one bit set.
 147  *
 148  * Multiple bits may be set if the user process modifies the control
 149  * word while a status word bit is already set.  While this is a sign
 150  * of bad coding, we have no choise than to narrow them down to one
 151  * bit, since we must not send a trapcode that is not exactly one of
 152  * the FPE_ macros.
 153  *
 154  * The mechanism has a static table with 127 entries.  Each combination
 155  * of the 7 FPU status word exception bits directly translates to a
 156  * position in this table, where a single FPE_... value is stored.
 157  * This FPE_... value stored there is considered the "most important"
 158  * of the exception bits and will be sent as the signal code.  The
 159  * precedence of the bits is based upon Intel Document "Numerical
 160  * Applications", Chapter "Special Computational Situations".
 161  *
 162  * The macro to choose one of these values does these steps: 1) Throw
 163  * away status word bits that cannot be masked.  2) Throw away the bits
 164  * currently masked in the control word, assuming the user isn't
 165  * interested in them anymore.  3) Reinsert status word bit 7 (stack
 166  * fault) if it is set, which cannot be masked but must be presered.
 167  * 4) Use the remaining bits to point into the trapcode table.
 168  *
 169  * The 6 maskable bits in order of their preference, as stated in the
 170  * above referenced Intel manual:
 171  * 1  Invalid operation (FP_X_INV)
 172  * 1a   Stack underflow
 173  * 1b   Stack overflow
 174  * 1c   Operand of unsupported format
 175  * 1d   SNaN operand.
 176  * 2  QNaN operand (not an exception, irrelavant here)
 177  * 3  Any other invalid-operation not mentioned above or zero divide
 178  *      (FP_X_INV, FP_X_DZ)
 179  * 4  Denormal operand (FP_X_DNML)
 180  * 5  Numeric over/underflow (FP_X_OFL, FP_X_UFL)
 181  * 6  Inexact result (FP_X_IMP)
 182  */
 183 static char fpetable[128] = {
 184         0,
 185         FPE_FLTINV,     /*  1 - INV */
 186         FPE_FLTUND,     /*  2 - DNML */
 187         FPE_FLTINV,     /*  3 - INV | DNML */
 188         FPE_FLTDIV,     /*  4 - DZ */
 189         FPE_FLTINV,     /*  5 - INV | DZ */
 190         FPE_FLTDIV,     /*  6 - DNML | DZ */
 191         FPE_FLTINV,     /*  7 - INV | DNML | DZ */
 192         FPE_FLTOVF,     /*  8 - OFL */
 193         FPE_FLTINV,     /*  9 - INV | OFL */
 194         FPE_FLTUND,     /*  A - DNML | OFL */
 195         FPE_FLTINV,     /*  B - INV | DNML | OFL */
 196         FPE_FLTDIV,     /*  C - DZ | OFL */
 197         FPE_FLTINV,     /*  D - INV | DZ | OFL */
 198         FPE_FLTDIV,     /*  E - DNML | DZ | OFL */
 199         FPE_FLTINV,     /*  F - INV | DNML | DZ | OFL */
 200         FPE_FLTUND,     /* 10 - UFL */
 201         FPE_FLTINV,     /* 11 - INV | UFL */
 202         FPE_FLTUND,     /* 12 - DNML | UFL */
 203         FPE_FLTINV,     /* 13 - INV | DNML | UFL */
 204         FPE_FLTDIV,     /* 14 - DZ | UFL */
 205         FPE_FLTINV,     /* 15 - INV | DZ | UFL */
 206         FPE_FLTDIV,     /* 16 - DNML | DZ | UFL */
 207         FPE_FLTINV,     /* 17 - INV | DNML | DZ | UFL */
 208         FPE_FLTOVF,     /* 18 - OFL | UFL */
 209         FPE_FLTINV,     /* 19 - INV | OFL | UFL */
 210         FPE_FLTUND,     /* 1A - DNML | OFL | UFL */
 211         FPE_FLTINV,     /* 1B - INV | DNML | OFL | UFL */
 212         FPE_FLTDIV,     /* 1C - DZ | OFL | UFL */
 213         FPE_FLTINV,     /* 1D - INV | DZ | OFL | UFL */
 214         FPE_FLTDIV,     /* 1E - DNML | DZ | OFL | UFL */
 215         FPE_FLTINV,     /* 1F - INV | DNML | DZ | OFL | UFL */
 216         FPE_FLTRES,     /* 20 - IMP */
 217         FPE_FLTINV,     /* 21 - INV | IMP */
 218         FPE_FLTUND,     /* 22 - DNML | IMP */
 219         FPE_FLTINV,     /* 23 - INV | DNML | IMP */
 220         FPE_FLTDIV,     /* 24 - DZ | IMP */
 221         FPE_FLTINV,     /* 25 - INV | DZ | IMP */
 222         FPE_FLTDIV,     /* 26 - DNML | DZ | IMP */
 223         FPE_FLTINV,     /* 27 - INV | DNML | DZ | IMP */
 224         FPE_FLTOVF,     /* 28 - OFL | IMP */
 225         FPE_FLTINV,     /* 29 - INV | OFL | IMP */
 226         FPE_FLTUND,     /* 2A - DNML | OFL | IMP */
 227         FPE_FLTINV,     /* 2B - INV | DNML | OFL | IMP */
 228         FPE_FLTDIV,     /* 2C - DZ | OFL | IMP */
 229         FPE_FLTINV,     /* 2D - INV | DZ | OFL | IMP */
 230         FPE_FLTDIV,     /* 2E - DNML | DZ | OFL | IMP */
 231         FPE_FLTINV,     /* 2F - INV | DNML | DZ | OFL | IMP */
 232         FPE_FLTUND,     /* 30 - UFL | IMP */
 233         FPE_FLTINV,     /* 31 - INV | UFL | IMP */
 234         FPE_FLTUND,     /* 32 - DNML | UFL | IMP */
 235         FPE_FLTINV,     /* 33 - INV | DNML | UFL | IMP */
 236         FPE_FLTDIV,     /* 34 - DZ | UFL | IMP */
 237         FPE_FLTINV,     /* 35 - INV | DZ | UFL | IMP */
 238         FPE_FLTDIV,     /* 36 - DNML | DZ | UFL | IMP */
 239         FPE_FLTINV,     /* 37 - INV | DNML | DZ | UFL | IMP */
 240         FPE_FLTOVF,     /* 38 - OFL | UFL | IMP */
 241         FPE_FLTINV,     /* 39 - INV | OFL | UFL | IMP */
 242         FPE_FLTUND,     /* 3A - DNML | OFL | UFL | IMP */
 243         FPE_FLTINV,     /* 3B - INV | DNML | OFL | UFL | IMP */
 244         FPE_FLTDIV,     /* 3C - DZ | OFL | UFL | IMP */
 245         FPE_FLTINV,     /* 3D - INV | DZ | OFL | UFL | IMP */
 246         FPE_FLTDIV,     /* 3E - DNML | DZ | OFL | UFL | IMP */
 247         FPE_FLTINV,     /* 3F - INV | DNML | DZ | OFL | UFL | IMP */
 248         FPE_FLTSUB,     /* 40 - STK */
 249         FPE_FLTSUB,     /* 41 - INV | STK */
 250         FPE_FLTUND,     /* 42 - DNML | STK */
 251         FPE_FLTSUB,     /* 43 - INV | DNML | STK */
 252         FPE_FLTDIV,     /* 44 - DZ | STK */
 253         FPE_FLTSUB,     /* 45 - INV | DZ | STK */
 254         FPE_FLTDIV,     /* 46 - DNML | DZ | STK */
 255         FPE_FLTSUB,     /* 47 - INV | DNML | DZ | STK */
 256         FPE_FLTOVF,     /* 48 - OFL | STK */
 257         FPE_FLTSUB,     /* 49 - INV | OFL | STK */
 258         FPE_FLTUND,     /* 4A - DNML | OFL | STK */
 259         FPE_FLTSUB,     /* 4B - INV | DNML | OFL | STK */
 260         FPE_FLTDIV,     /* 4C - DZ | OFL | STK */
 261         FPE_FLTSUB,     /* 4D - INV | DZ | OFL | STK */
 262         FPE_FLTDIV,     /* 4E - DNML | DZ | OFL | STK */
 263         FPE_FLTSUB,     /* 4F - INV | DNML | DZ | OFL | STK */
 264         FPE_FLTUND,     /* 50 - UFL | STK */
 265         FPE_FLTSUB,     /* 51 - INV | UFL | STK */
 266         FPE_FLTUND,     /* 52 - DNML | UFL | STK */
 267         FPE_FLTSUB,     /* 53 - INV | DNML | UFL | STK */
 268         FPE_FLTDIV,     /* 54 - DZ | UFL | STK */
 269         FPE_FLTSUB,     /* 55 - INV | DZ | UFL | STK */
 270         FPE_FLTDIV,     /* 56 - DNML | DZ | UFL | STK */
 271         FPE_FLTSUB,     /* 57 - INV | DNML | DZ | UFL | STK */
 272         FPE_FLTOVF,     /* 58 - OFL | UFL | STK */
 273         FPE_FLTSUB,     /* 59 - INV | OFL | UFL | STK */
 274         FPE_FLTUND,     /* 5A - DNML | OFL | UFL | STK */
 275         FPE_FLTSUB,     /* 5B - INV | DNML | OFL | UFL | STK */
 276         FPE_FLTDIV,     /* 5C - DZ | OFL | UFL | STK */
 277         FPE_FLTSUB,     /* 5D - INV | DZ | OFL | UFL | STK */
 278         FPE_FLTDIV,     /* 5E - DNML | DZ | OFL | UFL | STK */
 279         FPE_FLTSUB,     /* 5F - INV | DNML | DZ | OFL | UFL | STK */
 280         FPE_FLTRES,     /* 60 - IMP | STK */
 281         FPE_FLTSUB,     /* 61 - INV | IMP | STK */
 282         FPE_FLTUND,     /* 62 - DNML | IMP | STK */
 283         FPE_FLTSUB,     /* 63 - INV | DNML | IMP | STK */
 284         FPE_FLTDIV,     /* 64 - DZ | IMP | STK */
 285         FPE_FLTSUB,     /* 65 - INV | DZ | IMP | STK */
 286         FPE_FLTDIV,     /* 66 - DNML | DZ | IMP | STK */
 287         FPE_FLTSUB,     /* 67 - INV | DNML | DZ | IMP | STK */
 288         FPE_FLTOVF,     /* 68 - OFL | IMP | STK */
 289         FPE_FLTSUB,     /* 69 - INV | OFL | IMP | STK */
 290         FPE_FLTUND,     /* 6A - DNML | OFL | IMP | STK */
 291         FPE_FLTSUB,     /* 6B - INV | DNML | OFL | IMP | STK */
 292         FPE_FLTDIV,     /* 6C - DZ | OFL | IMP | STK */
 293         FPE_FLTSUB,     /* 6D - INV | DZ | OFL | IMP | STK */
 294         FPE_FLTDIV,     /* 6E - DNML | DZ | OFL | IMP | STK */
 295         FPE_FLTSUB,     /* 6F - INV | DNML | DZ | OFL | IMP | STK */
 296         FPE_FLTUND,     /* 70 - UFL | IMP | STK */
 297         FPE_FLTSUB,     /* 71 - INV | UFL | IMP | STK */
 298         FPE_FLTUND,     /* 72 - DNML | UFL | IMP | STK */
 299         FPE_FLTSUB,     /* 73 - INV | DNML | UFL | IMP | STK */
 300         FPE_FLTDIV,     /* 74 - DZ | UFL | IMP | STK */
 301         FPE_FLTSUB,     /* 75 - INV | DZ | UFL | IMP | STK */
 302         FPE_FLTDIV,     /* 76 - DNML | DZ | UFL | IMP | STK */
 303         FPE_FLTSUB,     /* 77 - INV | DNML | DZ | UFL | IMP | STK */
 304         FPE_FLTOVF,     /* 78 - OFL | UFL | IMP | STK */
 305         FPE_FLTSUB,     /* 79 - INV | OFL | UFL | IMP | STK */
 306         FPE_FLTUND,     /* 7A - DNML | OFL | UFL | IMP | STK */
 307         FPE_FLTSUB,     /* 7B - INV | DNML | OFL | UFL | IMP | STK */
 308         FPE_FLTDIV,     /* 7C - DZ | OFL | UFL | IMP | STK */
 309         FPE_FLTSUB,     /* 7D - INV | DZ | OFL | UFL | IMP | STK */
 310         FPE_FLTDIV,     /* 7E - DNML | DZ | OFL | UFL | IMP | STK */
 311         FPE_FLTSUB,     /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */
 312 };
 313
 314 #endif
 315
 316 #if 0
 317
 318 /*
 319  * Preserve the FP status word, clear FP exceptions, then generate a SIGFPE.
 320  *
 321  * Clearing exceptions is necessary mainly to avoid IRQ13 bugs.  We now
 322  * depend on longjmp() restoring a usable state.  Restoring the state
 323  * or examining it might fail if we didn't clear exceptions.
 324  *
 325  * The error code chosen will be one of the FPE_... macros. It will be
 326  * sent as the second argument to old BSD-style signal handlers and as
 327  * "siginfo_t->si_code" (second argument) to SA_SIGINFO signal handlers.
 328  *
 329  * XXX the FP state is not preserved across signal handlers.  So signal
 330  * handlers cannot afford to do FP unless they preserve the state or
 331  * longjmp() out.  Both preserving the state and longjmp()ing may be
 332  * destroyed by IRQ13 bugs.  Clearing FP exceptions is not an acceptable
 333  * solution for signals other than SIGFPE.
 334  *
 335  * The MP lock is not held on entry (see i386/i386/exception.s) and
 336  * should not be held on exit.  Interrupts are enabled.  We must enter
 337  * a critical section to stabilize the FP system and prevent an interrupt
 338  * or preemption from changing the FP state out from under us.
 339  */
 340 void
 341 npx_intr(void *dummy)
 342 {
 343         int code;
 344         u_short control;
 345         struct intrframe *frame;
 346         u_long *exstat;
 347
 348         crit_enter();
 349
 350         /*
 351          * This exception can only occur with CR0_TS clear, otherwise we
 352          * would get a DNA exception.  However, since interrupts were
 353          * enabled a preemption could have sneaked in and used the FP system
 354          * before we entered our critical section.  If that occured, the
 355          * TS bit will be set and npxthread will be NULL.
 356          */
 357         panic("npx_intr: not coded");
 358         /* XXX FP STATE FLAG MUST BE PART OF CONTEXT SUPPLIED BY REAL KERNEL */
 359 #if 0
 360         if (rcr0() & CR0_TS) {
 361                 KASSERT(mdcpu->gd_npxthread == NULL, ("gd_npxthread was %p with TS set!", mdcpu->gd_npxthread));
 362                 npxdna();
 363                 crit_exit();
 364                 return;
 365         }
 366 #endif
 367         if (mdcpu->gd_npxthread == NULL) {
 368                 get_mplock();
 369                 kprintf("npxintr: npxthread = %p, curthread = %p\n",
 370                        mdcpu->gd_npxthread, curthread);
 371                 panic("npxintr from nowhere");
 372         }
 373         if (mdcpu->gd_npxthread != curthread) {
 374                 get_mplock();
 375                 kprintf("npxintr: npxthread = %p, curthread = %p\n",
 376                        mdcpu->gd_npxthread, curthread);
 377                 panic("npxintr from non-current process");
 378         }
 379
 380         exstat = GET_FPU_EXSW_PTR(curthread);
 381         outb(0xf0, 0);
 382         fnstsw(exstat);
 383         fnstcw(&control);
 384         fnclex();
 385
 386         get_mplock();
 387
 388         /*
 389          * Pass exception to process.
 390          */
 391         frame = (struct intrframe *)&dummy;     /* XXX */
 392         if ((ISPL(frame->if_cs) == SEL_UPL) /*||(frame->if_eflags&PSL_VM)*/) {
 393                 /*
 394                  * Interrupt is essentially a trap, so we can afford to call
 395                  * the SIGFPE handler (if any) as soon as the interrupt
 396                  * returns.
 397                  *
 398                  * XXX little or nothing is gained from this, and plenty is
 399                  * lost - the interrupt frame has to contain the trap frame
 400                  * (this is otherwise only necessary for the rescheduling trap
 401                  * in doreti, and the frame for that could easily be set up
 402                  * just before it is used).
 403                  */
 404                 curthread->td_lwp->lwp_md.md_regs = INTR_TO_TRAPFRAME(frame);
 405                 /*
 406                  * Encode the appropriate code for detailed information on
 407                  * this exception.
 408                  */
 409                 code =
 410                     fpetable[(*exstat & ~control & 0x3f) | (*exstat & 0x40)];
 411                 trapsignal(curthread->td_lwp, SIGFPE, code);
 412         } else {
 413                 /*
 414                  * Nested interrupt.  These losers occur when:
 415                  *      o an IRQ13 is bogusly generated at a bogus time, e.g.:
 416                  *              o immediately after an fnsave or frstor of an
 417                  *                error state.
 418                  *              o a couple of 386 instructions after
 419                  *                "fstpl _memvar" causes a stack overflow.
 420                  *        These are especially nasty when combined with a
 421                  *        trace trap.
 422                  *      o an IRQ13 occurs at the same time as another higher-
 423                  *        priority interrupt.
 424                  *
 425                  * Treat them like a true async interrupt.
 426                  */
 427                 lwpsignal(curproc, curthread->td_lwp, SIGFPE);
 428         }
 429         rel_mplock();
 430         crit_exit();
 431 }
 432
 433 #endif
 434
 435 /*
 436  * Implement the device not available (DNA) exception.  gd_npxthread had
 437  * better be NULL.  Restore the current thread's FP state and set gd_npxthread
 438  * to curthread.
 439  *
 440  * Interrupts are enabled and preemption can occur.  Enter a critical
 441  * section to stabilize the FP state.
 442  */
 443 int
 444 npxdna(void)
 445 {
 446         thread_t td = curthread;
 447         u_long *exstat;
 448         int didinit = 0;
 449
 450         if (mdcpu->gd_npxthread != NULL) {
 451                 kprintf("npxdna: npxthread = %p, curthread = %p\n",
 452                        mdcpu->gd_npxthread, curthread);
 453                 panic("npxdna");
 454         }
 455
 456         /*
 457          * Setup the initial saved state if the thread has never before
 458          * used the FP unit.  This also occurs when a thread pushes a
 459          * signal handler and uses FP in the handler.
 460          */
 461         if ((td->td_flags & (TDF_USINGFP | TDF_KERNELFP)) == 0) {
 462                 td->td_flags |= TDF_USINGFP;
 463                 npxinit(__INITIAL_NPXCW__);
 464                 didinit = 1;
 465         }
 466
 467         /*
 468          * The setting of gd_npxthread and the call to fpurstor() must not
 469          * be preempted by an interrupt thread or we will take an npxdna
 470          * trap and potentially save our current fpstate (which is garbage)
 471          * and then restore the garbage rather then the originally saved
 472          * fpstate.
 473          */
 474         crit_enter();
 475         stop_emulating();
 476         /*
 477          * Record new context early in case frstor causes an IRQ13.
 478          */
 479         mdcpu->gd_npxthread = td;
 480         exstat = GET_FPU_EXSW_PTR(td);
 481         *exstat = 0;
 482         /*
 483          * The following frstor may cause an IRQ13 when the state being
 484          * restored has a pending error.  The error will appear to have been
 485          * triggered by the current (npx) user instruction even when that
 486          * instruction is a no-wait instruction that should not trigger an
 487          * error (e.g., fnclex).  On at least one 486 system all of the
 488          * no-wait instructions are broken the same as frstor, so our
 489          * treatment does not amplify the breakage.  On at least one
 490          * 386/Cyrix 387 system, fnclex works correctly while frstor and
 491          * fnsave are broken, so our treatment breaks fnclex if it is the
 492          * first FPU instruction after a context switch.
 493          */
 494         if ((td->td_savefpu->sv_xmm.sv_env.en_mxcsr & ~0xFFBF)
 495 #ifndef CPU_DISABLE_SSE
 496             && cpu_fxsr
 497 #endif
 498         ) {
 499                 krateprintf(&badfprate,
 500                             "FXRSTR: illegal FP MXCSR %08x didinit = %d\n",
 501                             td->td_savefpu->sv_xmm.sv_env.en_mxcsr, didinit);
 502                 td->td_savefpu->sv_xmm.sv_env.en_mxcsr &= 0xFFBF;
 503                 lwpsignal(curproc, curthread->td_lwp, SIGFPE);
 504         }
 505         fpurstor(td->td_savefpu);
 506         crit_exit();
 507
 508         return (1);
 509 }
 510
 511 /*
 512  * Wrapper for the fnsave instruction to handle h/w bugs.  If there is an error
 513  * pending, then fnsave generates a bogus IRQ13 on some systems.  Force
 514  * any IRQ13 to be handled immediately, and then ignore it.  This routine is
 515  * often called at splhigh so it must not use many system services.  In
 516  * particular, it's much easier to install a special handler than to
 517  * guarantee that it's safe to use npxintr() and its supporting code.
 518  *
 519  * WARNING!  This call is made during a switch and the MP lock will be
 520  * setup for the new target thread rather then the current thread, so we
 521  * cannot do anything here that depends on the *_mplock() functions as
 522  * we may trip over their assertions.
 523  *
 524  * WARNING!  When using fxsave we MUST fninit after saving the FP state.  The
 525  * kernel will always assume that the FP state is 'safe' (will not cause
 526  * exceptions) for mmx/xmm use if npxthread is NULL.  The kernel must still
 527  * setup a custom save area before actually using the FP unit, but it will
 528  * not bother calling fninit.  This greatly improves kernel performance when
 529  * it wishes to use the FP unit.
 530  */
 531 void
 532 npxsave(union savefpu *addr)
 533 {
 534         crit_enter();
 535         stop_emulating();
 536         fpusave(addr);
 537         mdcpu->gd_npxthread = NULL;
 538         fninit();
 539         start_emulating();
 540         crit_exit();
 541 }
 542
 543 static void
 544 fpusave(union savefpu *addr)
 545 {
 546 #ifndef CPU_DISABLE_SSE
 547         if (cpu_fxsr)
 548                 fxsave(addr);
 549         else
 550 #endif
 551                 fnsave(addr);
 552 }
 553
 554 /*
 555  * Save the FP state to the mcontext structure.
 556  *
 557  * WARNING: If you want to try to npxsave() directly to mctx->mc_fpregs,
 558  * then it MUST be 16-byte aligned.  Currently this is not guarenteed.
 559  */
 560 void
 561 npxpush(mcontext_t *mctx)
 562 {
 563         thread_t td = curthread;
 564
 565         KKASSERT((td->td_flags & TDF_KERNELFP) == 0);
 566
 567         if (td->td_flags & TDF_USINGFP) {
 568                 if (mdcpu->gd_npxthread == td) {
 569                         /*
 570                          * XXX Note: This is a bit inefficient if the signal
 571                          * handler uses floating point, extra faults will
 572                          * occur.
 573                          */
 574                         mctx->mc_ownedfp = _MC_FPOWNED_FPU;
 575                         npxsave(td->td_savefpu);
 576                 } else {
 577                         mctx->mc_ownedfp = _MC_FPOWNED_PCB;
 578                 }
 579                 bcopy(td->td_savefpu, mctx->mc_fpregs, sizeof(mctx->mc_fpregs));
 580                 td->td_flags &= ~TDF_USINGFP;
 581                 mctx->mc_fpformat =
 582 #ifndef CPU_DISABLE_SSE
 583                         (cpu_fxsr) ? _MC_FPFMT_XMM :
 584 #endif
 585                         _MC_FPFMT_387;
 586         } else {
 587                 mctx->mc_ownedfp = _MC_FPOWNED_NONE;
 588                 mctx->mc_fpformat = _MC_FPFMT_NODEV;
 589         }
 590 }
 591
 592 /*
 593  * Restore the FP state from the mcontext structure.
 594  */
 595 void
 596 npxpop(mcontext_t *mctx)
 597 {
 598         thread_t td = curthread;
 599
 600         switch(mctx->mc_ownedfp) {
 601         case _MC_FPOWNED_NONE:
 602                 /*
 603                  * If the signal handler used the FP unit but the interrupted
 604                  * code did not, release the FP unit.  Clear TDF_USINGFP will
 605                  * force the FP unit to reinit so the interrupted code sees
 606                  * a clean slate.
 607                  */
 608                 if (td->td_flags & TDF_USINGFP) {
 609                         if (td == mdcpu->gd_npxthread)
 610                                 npxsave(td->td_savefpu);
 611                         td->td_flags &= ~TDF_USINGFP;
 612                 }
 613                 break;
 614         case _MC_FPOWNED_FPU:
 615         case _MC_FPOWNED_PCB:
 616                 /*
 617                  * Clear ownership of the FP unit and restore our saved state.
 618                  *
 619                  * NOTE: The signal handler may have set-up some FP state and
 620                  * enabled the FP unit, so we have to restore no matter what.
 621                  *
 622                  * XXX: This is bit inefficient, if the code being returned
 623                  * to is actively using the FP this results in multiple
 624                  * kernel faults.
 625                  *
 626                  * WARNING: The saved state was exposed to userland and may
 627                  * have to be sanitized to avoid a GP fault in the kernel.
 628                  */
 629                 if (td == mdcpu->gd_npxthread)
 630                         npxsave(td->td_savefpu);
 631                 bcopy(mctx->mc_fpregs, td->td_savefpu, sizeof(*td->td_savefpu));
 632                 if ((td->td_savefpu->sv_xmm.sv_env.en_mxcsr & ~0xFFBF)
 633 #ifndef CPU_DISABLE_SSE
 634                     && cpu_fxsr
 635 #endif
 636                 ) {
 637                         krateprintf(&badfprate,
 638                                     "pid %d (%s) signal return from user: "
 639                                     "illegal FP MXCSR %08x\n",
 640                                     td->td_proc->p_pid,
 641                                     td->td_proc->p_comm,
 642                                     td->td_savefpu->sv_xmm.sv_env.en_mxcsr);
 643                 }
 644                 td->td_flags |= TDF_USINGFP;
 645                 break;
 646         }
 647 }
 648
 649
 650 #ifndef CPU_DISABLE_SSE
 651 /*
 652  * On AuthenticAMD processors, the fxrstor instruction does not restore
 653  * the x87's stored last instruction pointer, last data pointer, and last
 654  * opcode values, except in the rare case in which the exception summary
 655  * (ES) bit in the x87 status word is set to 1.
 656  *
 657  * In order to avoid leaking this information across processes, we clean
 658  * these values by performing a dummy load before executing fxrstor().
 659  */
 660 static  double  dummy_variable = 0.0;
 661 static void
 662 fpu_clean_state(void)
 663 {
 664         u_short status;
 665
 666         /*
 667          * Clear the ES bit in the x87 status word if it is currently
 668          * set, in order to avoid causing a fault in the upcoming load.
 669          */
 670         fnstsw(&status);
 671         if (status & 0x80)
 672                 fnclex();
 673
 674         /*
 675          * Load the dummy variable into the x87 stack.  This mangles
 676          * the x87 stack, but we don't care since we're about to call
 677          * fxrstor() anyway.
 678          */
 679         __asm __volatile("ffree %%st(7); fld %0" : : "m" (dummy_variable));
 680 }
 681 #endif /* CPU_DISABLE_SSE */
 682
 683 static void
 684 fpurstor(union savefpu *addr)
 685 {
 686 #ifndef CPU_DISABLE_SSE
 687         if (cpu_fxsr) {
 688                 fpu_clean_state();
 689                 fxrstor(addr);
 690         } else {
 691                 frstor(addr);
 692         }
 693 #else
 694         frstor(addr);
 695 #endif
 696 }
 697