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kernel - Move mplock to machine-independent C
[dragonfly.git] / sys / dev / disk / nata / ata-chipset.c
blobe775db6e2154f9b894714a6dbd37403bfc8c6c97
1 /*-
2 * Copyright (c) 1998 - 2006 Søren Schmidt <sos@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * $FreeBSD: src/sys/dev/ata/ata-chipset.c,v 1.196 2007/04/08 19:18:51 sos Exp $
27 * $DragonFly: src/sys/dev/disk/nata/ata-chipset.c,v 1.15 2008/07/12 16:38:10 mneumann Exp $
28 */
29
30 #include "opt_ata.h"
31
32 #include <sys/param.h>
33 #include <sys/bus.h>
34 #include <sys/bus_dma.h>
35 #include <sys/bus_resource.h>
36 #include <sys/callout.h>
37 #include <sys/endian.h>
38 #include <sys/libkern.h>
39 #include <sys/lock.h> /* for {get,rel}_mplock() */
40 #include <sys/malloc.h>
41 #include <sys/nata.h>
42 #include <sys/queue.h>
43 #include <sys/rman.h>
44 #include <sys/spinlock.h>
45 #include <sys/systm.h>
46 #include <sys/taskqueue.h>
47
48 #include <sys/spinlock2.h>
49 #include <sys/mplock2.h>
50
51 #include <machine/bus_dma.h>
52
53 #include <bus/pci/pcireg.h>
54 #include <bus/pci/pcivar.h>
55
56 #include "ata-all.h"
57 #include "ata-pci.h"
58 #include "ata_if.h"
59
60 /* local prototypes */
61 /* ata-chipset.c */
62 static int ata_generic_chipinit(device_t dev);
63 static void ata_generic_intr(void *data);
64 static void ata_generic_setmode(device_t dev, int mode);
65 static void ata_sata_phy_check_events(device_t dev);
66 static void ata_sata_phy_event(void *context, int dummy);
67 static int ata_sata_phy_reset(device_t dev);
68 static int ata_sata_connect(struct ata_channel *ch);
69 static void ata_sata_setmode(device_t dev, int mode);
70 static int ata_request2fis_h2d(struct ata_request *request, u_int8_t *fis);
71 static int ata_ahci_chipinit(device_t dev);
72 static int ata_ahci_allocate(device_t dev);
73 static int ata_ahci_status(device_t dev);
74 static int ata_ahci_begin_transaction(struct ata_request *request);
75 static int ata_ahci_end_transaction(struct ata_request *request);
76 static void ata_ahci_reset(device_t dev);
77 static void ata_ahci_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
78 static void ata_ahci_dmainit(device_t dev);
79 static int ata_ahci_setup_fis(struct ata_ahci_cmd_tab *ctp, struct ata_request *request);
80 static int ata_acard_chipinit(device_t dev);
81 static int ata_acard_allocate(device_t dev);
82 static int ata_acard_status(device_t dev);
83 static void ata_acard_850_setmode(device_t dev, int mode);
84 static void ata_acard_86X_setmode(device_t dev, int mode);
85 static int ata_ali_chipinit(device_t dev);
86 static int ata_ali_allocate(device_t dev);
87 static int ata_ali_sata_allocate(device_t dev);
88 static void ata_ali_reset(device_t dev);
89 static void ata_ali_setmode(device_t dev, int mode);
90 static int ata_amd_chipinit(device_t dev);
91 static int ata_ati_chipinit(device_t dev);
92 static void ata_ati_setmode(device_t dev, int mode);
93 static int ata_cyrix_chipinit(device_t dev);
94 static void ata_cyrix_setmode(device_t dev, int mode);
95 static int ata_cypress_chipinit(device_t dev);
96 static void ata_cypress_setmode(device_t dev, int mode);
97 static int ata_highpoint_chipinit(device_t dev);
98 static int ata_highpoint_allocate(device_t dev);
99 static void ata_highpoint_setmode(device_t dev, int mode);
100 static int ata_highpoint_check_80pin(device_t dev, int mode);
101 static int ata_intel_chipinit(device_t dev);
102 static int ata_intel_allocate(device_t dev);
103 static void ata_intel_reset(device_t dev);
104 static void ata_intel_old_setmode(device_t dev, int mode);
105 static void ata_intel_new_setmode(device_t dev, int mode);
106 static void ata_intel_sata_setmode(device_t dev, int mode);
107 static int ata_intel_31244_allocate(device_t dev);
108 static int ata_intel_31244_status(device_t dev);
109 static int ata_intel_31244_command(struct ata_request *request);
110 static void ata_intel_31244_reset(device_t dev);
111 static int ata_ite_chipinit(device_t dev);
112 static void ata_ite_setmode(device_t dev, int mode);
113 static int ata_jmicron_chipinit(device_t dev);
114 static int ata_jmicron_allocate(device_t dev);
115 static void ata_jmicron_reset(device_t dev);
116 static void ata_jmicron_dmainit(device_t dev);
117 static void ata_jmicron_setmode(device_t dev, int mode);
118 static int ata_marvell_pata_chipinit(device_t dev);
119 static int ata_marvell_pata_allocate(device_t dev);
120 static void ata_marvell_pata_setmode(device_t dev, int mode);
121 static int ata_marvell_edma_chipinit(device_t dev);
122 static int ata_marvell_edma_allocate(device_t dev);
123 static int ata_marvell_edma_status(device_t dev);
124 static int ata_marvell_edma_begin_transaction(struct ata_request *request);
125 static int ata_marvell_edma_end_transaction(struct ata_request *request);
126 static void ata_marvell_edma_reset(device_t dev);
127 static void ata_marvell_edma_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
128 static void ata_marvell_edma_dmainit(device_t dev);
129 static int ata_national_chipinit(device_t dev);
130 static void ata_national_setmode(device_t dev, int mode);
131 static int ata_netcell_chipinit(device_t dev);
132 static int ata_netcell_allocate(device_t dev);
133 static int ata_nvidia_chipinit(device_t dev);
134 static int ata_nvidia_allocate(device_t dev);
135 static int ata_nvidia_status(device_t dev);
136 static void ata_nvidia_reset(device_t dev);
137 static int ata_promise_chipinit(device_t dev);
138 static int ata_promise_allocate(device_t dev);
139 static int ata_promise_status(device_t dev);
140 static int ata_promise_dmastart(device_t dev);
141 static int ata_promise_dmastop(device_t dev);
142 static void ata_promise_dmareset(device_t dev);
143 static void ata_promise_dmainit(device_t dev);
144 static void ata_promise_setmode(device_t dev, int mode);
145 static int ata_promise_tx2_allocate(device_t dev);
146 static int ata_promise_tx2_status(device_t dev);
147 static int ata_promise_mio_allocate(device_t dev);
148 static void ata_promise_mio_intr(void *data);
149 static int ata_promise_mio_status(device_t dev);
150 static int ata_promise_mio_command(struct ata_request *request);
151 static void ata_promise_mio_reset(device_t dev);
152 static void ata_promise_mio_dmainit(device_t dev);
153 static void ata_promise_mio_setmode(device_t dev, int mode);
154 static void ata_promise_sx4_intr(void *data);
155 static int ata_promise_sx4_command(struct ata_request *request);
156 static int ata_promise_apkt(u_int8_t *bytep, struct ata_request *request);
157 static void ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt);
158 static void ata_promise_next_hpkt(struct ata_pci_controller *ctlr);
159 static int ata_serverworks_chipinit(device_t dev);
160 static int ata_serverworks_allocate(device_t dev);
161 static void ata_serverworks_setmode(device_t dev, int mode);
162 static int ata_sii_chipinit(device_t dev);
163 static int ata_cmd_allocate(device_t dev);
164 static int ata_cmd_status(device_t dev);
165 static void ata_cmd_setmode(device_t dev, int mode);
166 static int ata_sii_allocate(device_t dev);
167 static int ata_sii_status(device_t dev);
168 static void ata_sii_reset(device_t dev);
169 static void ata_sii_setmode(device_t dev, int mode);
170 static int ata_siiprb_allocate(device_t dev);
171 static int ata_siiprb_status(device_t dev);
172 static int ata_siiprb_begin_transaction(struct ata_request *request);
173 static int ata_siiprb_end_transaction(struct ata_request *request);
174 static void ata_siiprb_reset(device_t dev);
175 static void ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
176 static void ata_siiprb_dmainit(device_t dev);
177 static int ata_sis_chipinit(device_t dev);
178 static int ata_sis_allocate(device_t dev);
179 static void ata_sis_reset(device_t dev);
180 static void ata_sis_setmode(device_t dev, int mode);
181 static int ata_via_chipinit(device_t dev);
182 static int ata_via_allocate(device_t dev);
183 static void ata_via_reset(device_t dev);
184 static void ata_via_setmode(device_t dev, int mode);
185 static void ata_via_southbridge_fixup(device_t dev);
186 static void ata_via_family_setmode(device_t dev, int mode);
187 static struct ata_chip_id *ata_match_chip(device_t dev, struct ata_chip_id *index);
188 static struct ata_chip_id *ata_find_chip(device_t dev, struct ata_chip_id *index, int slot);
189 static int ata_setup_interrupt(device_t dev);
190 static int ata_serialize(device_t dev, int flags);
191 static void ata_print_cable(device_t dev, u_int8_t *who);
192 static int ata_atapi(device_t dev);
193 static int ata_check_80pin(device_t dev, int mode);
194 static int ata_mode2idx(int mode);
195
196
197 /*
198 * generic ATA support functions
199 */
200 int
201 ata_generic_ident(device_t dev)
202 {
203 struct ata_pci_controller *ctlr = device_get_softc(dev);
204 char buffer[64];
205
206 ksnprintf(buffer, sizeof(buffer),
207 "%s ATA controller", ata_pcivendor2str(dev));
208 device_set_desc_copy(dev, buffer);
209 ctlr->chipinit = ata_generic_chipinit;
210 return 0;
211 }
212
213 static int
214 ata_generic_chipinit(device_t dev)
215 {
216 struct ata_pci_controller *ctlr = device_get_softc(dev);
217
218 if (ata_setup_interrupt(dev))
219 return ENXIO;
220 ctlr->setmode = ata_generic_setmode;
221 return 0;
222 }
223
224 static void
225 ata_generic_intr(void *data)
226 {
227 struct ata_pci_controller *ctlr = data;
228 struct ata_channel *ch;
229 int unit;
230
231 for (unit = 0; unit < ctlr->channels; unit++) {
232 if ((ch = ctlr->interrupt[unit].argument))
233 ctlr->interrupt[unit].function(ch);
234 }
235 }
236
237 static void
238 ata_generic_setmode(device_t dev, int mode)
239 {
240 struct ata_device *atadev = device_get_softc(dev);
241
242 mode = ata_limit_mode(dev, mode, ATA_UDMA2);
243 mode = ata_check_80pin(dev, mode);
244 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
245 atadev->mode = mode;
246 }
247
248
249 /*
250 * SATA support functions
251 */
252 static void
253 ata_sata_phy_check_events(device_t dev)
254 {
255 struct ata_channel *ch = device_get_softc(dev);
256 u_int32_t error = ATA_IDX_INL(ch, ATA_SERROR);
257
258 /* clear error bits/interrupt */
259 ATA_IDX_OUTL(ch, ATA_SERROR, error);
260
261 /* do we have any events flagged ? */
262 if (error) {
263 struct ata_connect_task *tp;
264 u_int32_t status = ATA_IDX_INL(ch, ATA_SSTATUS);
265
266 /* if we have a connection event deal with it */
267 if ((error & ATA_SE_PHY_CHANGED) &&
268 (tp = (struct ata_connect_task *)
269 kmalloc(sizeof(struct ata_connect_task),
270 M_ATA, M_INTWAIT | M_ZERO))) {
271
272 if (((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN1) ||
273 ((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN2)) {
274 if (bootverbose)
275 device_printf(ch->dev, "CONNECT requested\n");
276 tp->action = ATA_C_ATTACH;
277 }
278 else {
279 if (bootverbose)
280 device_printf(ch->dev, "DISCONNECT requested\n");
281 tp->action = ATA_C_DETACH;
282 }
283 tp->dev = ch->dev;
284 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp);
285 taskqueue_enqueue(taskqueue_thread[mycpuid], &tp->task);
286 }
287 }
288 }
289
290 static void
291 ata_sata_phy_event(void *context, int dummy)
292 {
293 struct ata_connect_task *tp = (struct ata_connect_task *)context;
294 struct ata_channel *ch = device_get_softc(tp->dev);
295 device_t *children;
296 int nchildren, i;
297
298 get_mplock();
299 if (tp->action == ATA_C_ATTACH) {
300 if (bootverbose)
301 device_printf(tp->dev, "CONNECTED\n");
302 ATA_RESET(tp->dev);
303 ata_identify(tp->dev);
304 }
305 if (tp->action == ATA_C_DETACH) {
306 if (!device_get_children(tp->dev, &children, &nchildren)) {
307 for (i = 0; i < nchildren; i++)
308 if (children[i])
309 device_delete_child(tp->dev, children[i]);
310 kfree(children, M_TEMP);
311 }
312 spin_lock_wr(&ch->state_mtx);
313 ch->state = ATA_IDLE;
314 spin_unlock_wr(&ch->state_mtx);
315 if (bootverbose)
316 device_printf(tp->dev, "DISCONNECTED\n");
317 }
318 rel_mplock();
319 kfree(tp, M_ATA);
320 }
321
322 static int
323 ata_sata_phy_reset(device_t dev)
324 {
325 struct ata_channel *ch = device_get_softc(dev);
326 int loop, retry;
327
328 if ((ATA_IDX_INL(ch, ATA_SCONTROL) & ATA_SC_DET_MASK) == ATA_SC_DET_IDLE)
329 return ata_sata_connect(ch);
330
331 for (retry = 0; retry < 10; retry++) {
332 for (loop = 0; loop < 10; loop++) {
333 ATA_IDX_OUTL(ch, ATA_SCONTROL, ATA_SC_DET_RESET);
334 ata_udelay(100);
335 if ((ATA_IDX_INL(ch, ATA_SCONTROL) &
336 ATA_SC_DET_MASK) == ATA_SC_DET_RESET)
337 break;
338 }
339 ata_udelay(5000);
340 for (loop = 0; loop < 10; loop++) {
341 ATA_IDX_OUTL(ch, ATA_SCONTROL, ATA_SC_DET_IDLE |
342 ATA_SC_IPM_DIS_PARTIAL |
343 ATA_SC_IPM_DIS_SLUMBER);
344 ata_udelay(100);
345 if ((ATA_IDX_INL(ch, ATA_SCONTROL) & ATA_SC_DET_MASK) == 0)
346 return ata_sata_connect(ch);
347 }
348 }
349 return 0;
350 }
351
352 static int
353 ata_sata_connect(struct ata_channel *ch)
354 {
355 u_int32_t status;
356 int timeout;
357
358 /* wait up to 1 second for "connect well" */
359 for (timeout = 0; timeout < 100 ; timeout++) {
360 status = ATA_IDX_INL(ch, ATA_SSTATUS);
361 if ((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN1 ||
362 (status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN2)
363 break;
364 ata_udelay(10000);
365 }
366 if (timeout >= 100) {
367 if (bootverbose)
368 device_printf(ch->dev, "SATA connect status=%08x\n", status);
369 return 0;
370 }
371
372 if (bootverbose)
373 device_printf(ch->dev, "SATA connect time=%dms\n", timeout * 10);
374
375 /* clear SATA error register */
376 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
377
378 return 1;
379 }
380
381 static void
382 ata_sata_setmode(device_t dev, int mode)
383 {
384 struct ata_device *atadev = device_get_softc(dev);
385
386 /*
387 * if we detect that the device isn't a real SATA device we limit
388 * the transfer mode to UDMA5/ATA100.
389 * this works around the problems some devices has with the
390 * Marvell 88SX8030 SATA->PATA converters and UDMA6/ATA133.
391 */
392 if (atadev->param.satacapabilities != 0x0000 &&
393 atadev->param.satacapabilities != 0xffff) {
394 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
395
396 /* on some drives we need to set the transfer mode */
397 ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0,
398 ata_limit_mode(dev, mode, ATA_UDMA6));
399
400 /* query SATA STATUS for the speed */
401 if (ch->r_io[ATA_SSTATUS].res &&
402 ((ATA_IDX_INL(ch, ATA_SSTATUS) & ATA_SS_CONWELL_MASK) ==
403 ATA_SS_CONWELL_GEN2))
404 atadev->mode = ATA_SA300;
405 else
406 atadev->mode = ATA_SA150;
407 }
408 else {
409 mode = ata_limit_mode(dev, mode, ATA_UDMA5);
410 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
411 atadev->mode = mode;
412 }
413 }
414
415 static int
416 ata_request2fis_h2d(struct ata_request *request, u_int8_t *fis)
417 {
418 struct ata_device *atadev = device_get_softc(request->dev);
419
420 if (request->flags & ATA_R_ATAPI) {
421 fis[0] = 0x27; /* host to device */
422 fis[1] = 0x80; /* command FIS (note PM goes here) */
423 fis[2] = ATA_PACKET_CMD;
424 if (request->flags & (ATA_R_READ | ATA_R_WRITE))
425 fis[3] = ATA_F_DMA;
426 else {
427 fis[5] = request->transfersize;
428 fis[6] = request->transfersize >> 8;
429 }
430 fis[7] = ATA_D_LBA | atadev->unit;
431 fis[15] = ATA_A_4BIT;
432 return 20;
433 }
434 else {
435 ata_modify_if_48bit(request);
436 fis[0] = 0x27; /* host to device */
437 fis[1] = 0x80; /* command FIS (note PM goes here) */
438 fis[2] = request->u.ata.command;
439 fis[3] = request->u.ata.feature;
440 fis[4] = request->u.ata.lba;
441 fis[5] = request->u.ata.lba >> 8;
442 fis[6] = request->u.ata.lba >> 16;
443 fis[7] = ATA_D_LBA | atadev->unit;
444 if (!(atadev->flags & ATA_D_48BIT_ACTIVE))
445 fis[7] |= (request->u.ata.lba >> 24 & 0x0f);
446 fis[8] = request->u.ata.lba >> 24;
447 fis[9] = request->u.ata.lba >> 32;
448 fis[10] = request->u.ata.lba >> 40;
449 fis[11] = request->u.ata.feature >> 8;
450 fis[12] = request->u.ata.count;
451 fis[13] = request->u.ata.count >> 8;
452 fis[15] = ATA_A_4BIT;
453 return 20;
454 }
455 return 0;
456 }
457
458 /*
459 * AHCI v1.x compliant SATA chipset support functions
460 */
461 int
462 ata_ahci_ident(device_t dev)
463 {
464 struct ata_pci_controller *ctlr = device_get_softc(dev);
465 static struct ata_chip_id id = {0, 0, 0, 0x00, ATA_SA300, "AHCI"};
466 char buffer[64];
467
468 if (pci_read_config(dev, PCIR_PROGIF, 1) != PCIP_STORAGE_SATA_AHCI_1_0)
469 return ENXIO;
470
471 if (bootverbose)
472 ksnprintf(buffer, sizeof(buffer), "%s (ID=%08x) AHCI controller",
473 ata_pcivendor2str(dev), pci_get_devid(dev));
474 else
475 ksnprintf(buffer, sizeof(buffer), "%s AHCI controller",
476 ata_pcivendor2str(dev));
477 device_set_desc_copy(dev, buffer);
478 ctlr->chip = &id;
479 ctlr->chipinit = ata_ahci_chipinit;
480 return 0;
481 }
482
483
484 /*
485 * AHCI v1.x compliant SATA chipset support functions
486 */
487 int
488 ata_ahci_chipinit(device_t dev)
489 {
490 struct ata_pci_controller *ctlr = device_get_softc(dev);
491 u_int32_t version;
492 int unit;
493
494 /* if we have a memory BAR(5) we are likely on an AHCI part */
495 ctlr->r_type2 = SYS_RES_MEMORY;
496 ctlr->r_rid2 = PCIR_BAR(5);
497 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
498 &ctlr->r_rid2, RF_ACTIVE)))
499 return ENXIO;
500
501 /* setup interrupt delivery if not done allready by a vendor driver */
502 if (!ctlr->r_irq) {
503 if (ata_setup_interrupt(dev))
504 return ENXIO;
505 }
506 else
507 device_printf(dev, "AHCI called from vendor specific driver\n");
508
509 /* enable AHCI mode */
510 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, ATA_AHCI_GHC_AE);
511
512 /* reset AHCI controller */
513 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, ATA_AHCI_GHC_HR);
514 DELAY(1000000);
515 if (ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) & ATA_AHCI_GHC_HR) {
516 bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, ctlr->r_res2);
517 device_printf(dev, "AHCI controller reset failure\n");
518 return ENXIO;
519 }
520
521 /* reenable AHCI mode */
522 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, ATA_AHCI_GHC_AE);
523
524 /* get the number of HW channels */
525 ctlr->channels =
526 MAX(flsl(ATA_INL(ctlr->r_res2, ATA_AHCI_PI)),
527 (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_NPMASK) + 1);
528
529 /* disable interrupt sources and clear interrupts */
530 for (unit = 0; unit < ctlr->channels; unit++) {
531 int offset = unit << 7;
532 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IE + offset, 0);
533 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset, -1);
534 }
535 ATA_OUTL(ctlr->r_res2, ATA_AHCI_IS, ATA_INL(ctlr->r_res2, ATA_AHCI_IS));
536
537 /* enable AHCI interrupts */
538 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC,
539 ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) | ATA_AHCI_GHC_IE);
540
541 ctlr->reset = ata_ahci_reset;
542 ctlr->dmainit = ata_ahci_dmainit;
543 ctlr->allocate = ata_ahci_allocate;
544 ctlr->setmode = ata_sata_setmode;
545
546 /* enable PCI interrupt */
547 pci_write_config(dev, PCIR_COMMAND,
548 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
549
550 /* announce we support the HW */
551 version = ATA_INL(ctlr->r_res2, ATA_AHCI_VS);
552 device_printf(dev,
553 "AHCI Version %x%x.%x%x controller with %d ports detected\n",
554 (version >> 24) & 0xff, (version >> 16) & 0xff,
555 (version >> 8) & 0xff, version & 0xff,
556 (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_NPMASK) + 1);
557 return 0;
558 }
559
560 static int
561 ata_ahci_allocate(device_t dev)
562 {
563 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
564 struct ata_channel *ch = device_get_softc(dev);
565 u_int64_t work;
566 int offset = ch->unit << 7;
567
568 /* set the SATA resources */
569 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
570 ch->r_io[ATA_SSTATUS].offset = ATA_AHCI_P_SSTS + offset;
571 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
572 ch->r_io[ATA_SERROR].offset = ATA_AHCI_P_SERR + offset;
573 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
574 ch->r_io[ATA_SCONTROL].offset = ATA_AHCI_P_SCTL + offset;
575 ch->r_io[ATA_SACTIVE].res = ctlr->r_res2;
576 ch->r_io[ATA_SACTIVE].offset = ATA_AHCI_P_SACT + offset;
577
578 ch->hw.status = ata_ahci_status;
579 ch->hw.begin_transaction = ata_ahci_begin_transaction;
580 ch->hw.end_transaction = ata_ahci_end_transaction;
581 ch->hw.command = NULL; /* not used here */
582
583 /* setup work areas */
584 work = ch->dma->work_bus + ATA_AHCI_CL_OFFSET;
585 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CLB + offset, work & 0xffffffff);
586 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CLBU + offset, work >> 32);
587
588 work = ch->dma->work_bus + ATA_AHCI_FB_OFFSET;
589 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FB + offset, work & 0xffffffff);
590 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FBU + offset, work >> 32);
591
592 /* enable wanted port interrupts */
593 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IE + offset,
594 (ATA_AHCI_P_IX_CPD | ATA_AHCI_P_IX_TFE | ATA_AHCI_P_IX_HBF |
595 ATA_AHCI_P_IX_HBD | ATA_AHCI_P_IX_IF | ATA_AHCI_P_IX_OF |
596 ATA_AHCI_P_IX_PRC | ATA_AHCI_P_IX_PC | ATA_AHCI_P_IX_DP |
597 ATA_AHCI_P_IX_UF | ATA_AHCI_P_IX_SDB | ATA_AHCI_P_IX_DS |
598 ATA_AHCI_P_IX_PS | ATA_AHCI_P_IX_DHR));
599
600 /* start operations on this channel */
601 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
602 (ATA_AHCI_P_CMD_ACTIVE | ATA_AHCI_P_CMD_FRE |
603 ATA_AHCI_P_CMD_POD | ATA_AHCI_P_CMD_SUD | ATA_AHCI_P_CMD_ST));
604 return 0;
605 }
606
607 static int
608 ata_ahci_status(device_t dev)
609 {
610 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
611 struct ata_channel *ch = device_get_softc(dev);
612 u_int32_t action = ATA_INL(ctlr->r_res2, ATA_AHCI_IS);
613 int offset = ch->unit << 7;
614 int tag = 0;
615
616 if (action & (1 << ch->unit)) {
617 u_int32_t istatus = ATA_INL(ctlr->r_res2, ATA_AHCI_P_IS + offset);
618 u_int32_t cstatus = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CI + offset);
619
620 /* clear interrupt(s) */
621 ATA_OUTL(ctlr->r_res2, ATA_AHCI_IS, action & (1 << ch->unit));
622 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset, istatus);
623
624 /* do we have any PHY events ? */
625 /* XXX SOS check istatus phy bits */
626 ata_sata_phy_check_events(dev);
627
628 /* do we have a potentially hanging engine to take care of? */
629 if ((istatus & 0x78400050) && (cstatus & (1 << tag))) {
630
631 u_int32_t cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
632 int timeout = 0;
633
634 /* kill off all activity on this channel */
635 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
636 cmd & ~(ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST));
637
638 /* XXX SOS this is not entirely wrong */
639 do {
640 DELAY(1000);
641 if (timeout++ > 500) {
642 device_printf(dev, "stopping AHCI engine failed\n");
643 break;
644 }
645 } while (ATA_INL(ctlr->r_res2,
646 ATA_AHCI_P_CMD + offset) & ATA_AHCI_P_CMD_CR);
647
648 /* start operations on this channel */
649 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
650 cmd | (ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST));
651
652 return 1;
653 }
654 else
655 return (!(cstatus & (1 << tag)));
656 }
657 return 0;
658 }
659
660 /* must be called with ATA channel locked and state_mtx held */
661 static int
662 ata_ahci_begin_transaction(struct ata_request *request)
663 {
664 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
665 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
666 struct ata_ahci_cmd_tab *ctp;
667 struct ata_ahci_cmd_list *clp;
668 int offset = ch->unit << 7;
669 int tag = 0, entries = 0;
670 int fis_size;
671
672 /* get a piece of the workspace for this request */
673 ctp = (struct ata_ahci_cmd_tab *)
674 (ch->dma->work + ATA_AHCI_CT_OFFSET + (ATA_AHCI_CT_SIZE * tag));
675
676 /* setup the FIS for this request */
677 if (!(fis_size = ata_ahci_setup_fis(ctp, request))) {
678 device_printf(request->dev, "setting up SATA FIS failed\n");
679 request->result = EIO;
680 return ATA_OP_FINISHED;
681 }
682
683 /* if request moves data setup and load SG list */
684 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) {
685 if (ch->dma->load(ch->dev, request->data, request->bytecount,
686 request->flags & ATA_R_READ,
687 ctp->prd_tab, &entries)) {
688 device_printf(request->dev, "setting up DMA failed\n");
689 request->result = EIO;
690 return ATA_OP_FINISHED;
691 }
692 }
693
694 /* setup the command list entry */
695 clp = (struct ata_ahci_cmd_list *)
696 (ch->dma->work + ATA_AHCI_CL_OFFSET + (ATA_AHCI_CL_SIZE * tag));
697
698 clp->prd_length = entries;
699 clp->cmd_flags = (request->flags & ATA_R_WRITE ? (1<<6) : 0) |
700 (request->flags & ATA_R_ATAPI ? ((1<<5) | (1<<7)) : 0) |
701 (fis_size / sizeof(u_int32_t));
702 clp->bytecount = 0;
703 clp->cmd_table_phys = htole64(ch->dma->work_bus + ATA_AHCI_CT_OFFSET +
704 (ATA_AHCI_CT_SIZE * tag));
705
706 /* clear eventual ACTIVE bit */
707 ATA_IDX_OUTL(ch, ATA_SACTIVE, ATA_IDX_INL(ch, ATA_SACTIVE) & (1 << tag));
708
709 /* set command type bit */
710 if (request->flags & ATA_R_ATAPI)
711 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
712 ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) |
713 ATA_AHCI_P_CMD_ATAPI);
714 else
715 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
716 ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) &
717 ~ATA_AHCI_P_CMD_ATAPI);
718
719 /* issue command to controller */
720 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CI + offset, (1 << tag));
721
722 if (!(request->flags & ATA_R_ATAPI)) {
723 /* device reset doesn't interrupt */
724 if (request->u.ata.command == ATA_DEVICE_RESET) {
725 u_int32_t tf_data;
726 int timeout = 1000000;
727
728 do {
729 DELAY(10);
730 tf_data = ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + (ch->unit<<7));
731 } while ((tf_data & ATA_S_BUSY) && timeout--);
732 if (bootverbose)
733 device_printf(ch->dev, "device_reset timeout=%dus\n",
734 (1000000-timeout)*10);
735 request->status = tf_data;
736 if (request->status & ATA_S_ERROR)
737 request->error = tf_data >> 8;
738 return ATA_OP_FINISHED;
739 }
740 }
741
742 /* start the timeout */
743 callout_reset(&request->callout, request->timeout * hz,
744 (timeout_t*)ata_timeout, request);
745 return ATA_OP_CONTINUES;
746 }
747
748 /* must be called with ATA channel locked and state_mtx held */
749 static int
750 ata_ahci_end_transaction(struct ata_request *request)
751 {
752 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
753 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
754 struct ata_ahci_cmd_list *clp;
755 u_int32_t tf_data;
756 int offset = ch->unit << 7;
757 int tag = 0;
758
759 /* kill the timeout */
760 callout_stop(&request->callout);
761
762 /* get status */
763 tf_data = ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + offset);
764 request->status = tf_data;
765
766 /* if error status get details */
767 if (request->status & ATA_S_ERROR)
768 request->error = tf_data >> 8;
769
770 /* record how much data we actually moved */
771 clp = (struct ata_ahci_cmd_list *)
772 (ch->dma->work + ATA_AHCI_CL_OFFSET + (ATA_AHCI_CL_SIZE * tag));
773 request->donecount = clp->bytecount;
774
775 /* release SG list etc */
776 ch->dma->unload(ch->dev);
777
778 return ATA_OP_FINISHED;
779 }
780
781 static void
782 ata_ahci_reset(device_t dev)
783 {
784 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
785 struct ata_channel *ch = device_get_softc(dev);
786 u_int32_t cmd, signature;
787 int offset = ch->unit << 7;
788 int timeout;
789
790 if (!(ATA_INL(ctlr->r_res2, ATA_AHCI_PI) & (1 << ch->unit))) {
791 device_printf(dev, "port not implemented\n");
792 return;
793 }
794 ch->devices = 0;
795
796 /* kill off all activity on this channel */
797 cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
798 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
799 cmd & ~(ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST));
800
801 /* XXX SOS this is not entirely wrong */
802 timeout = 0;
803 do {
804 DELAY(1000);
805 if (timeout++ > 500) {
806 device_printf(dev, "stopping AHCI engine failed\n");
807 break;
808 }
809 }
810 while (ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) & ATA_AHCI_P_CMD_CR);
811
812 /* issue Command List Override if supported */
813 if (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_CLO) {
814 cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
815 cmd |= ATA_AHCI_P_CMD_CLO;
816 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, cmd);
817 timeout = 0;
818 do {
819 DELAY(1000);
820 if (timeout++ > 500) {
821 device_printf(dev, "executing CLO failed\n");
822 break;
823 }
824 }
825 while (ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD+offset)&ATA_AHCI_P_CMD_CLO);
826 }
827
828 /* reset PHY and decide what is present */
829 if (ata_sata_phy_reset(dev)) {
830
831 /* clear any interrupts pending on this channel */
832 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset,
833 ATA_INL(ctlr->r_res2, ATA_AHCI_P_IS + offset));
834
835 /* clear SATA error register */
836 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
837
838 /* start operations on this channel */
839 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
840 (ATA_AHCI_P_CMD_ACTIVE | ATA_AHCI_P_CMD_FRE |
841 ATA_AHCI_P_CMD_POD | ATA_AHCI_P_CMD_SUD | ATA_AHCI_P_CMD_ST));
842
843 signature = ATA_INL(ctlr->r_res2, ATA_AHCI_P_SIG + offset);
844 switch (signature) {
845 case 0x00000101:
846 ch->devices = ATA_ATA_MASTER;
847 break;
848 case 0x96690101:
849 ch->devices = ATA_PORTMULTIPLIER;
850 device_printf(ch->dev, "Portmultipliers not supported yet\n");
851 ch->devices = 0;
852 break;
853 case 0xeb140101:
854 ch->devices = ATA_ATAPI_MASTER;
855 break;
856 default: /* SOS XXX */
857 if (bootverbose)
858 device_printf(ch->dev, "No signature, assuming disk device\n");
859 ch->devices = ATA_ATA_MASTER;
860 }
861 }
862 if (bootverbose)
863 device_printf(dev, "ahci_reset devices=0x%b\n", ch->devices,
864 "\20\4ATAPI_SLAVE\3ATAPI_MASTER\2ATA_SLAVE\1ATA_MASTER");
865 }
866
867 static void
868 ata_ahci_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
869 {
870 struct ata_dmasetprd_args *args = xsc;
871 struct ata_ahci_dma_prd *prd = args->dmatab;
872 int i;
873
874 if (!(args->error = error)) {
875 for (i = 0; i < nsegs; i++) {
876 prd[i].dba = htole64(segs[i].ds_addr);
877 prd[i].dbc = htole32((segs[i].ds_len - 1) & ATA_AHCI_PRD_MASK);
878 }
879 }
880 args->nsegs = nsegs;
881 }
882
883 static void
884 ata_ahci_dmainit(device_t dev)
885 {
886 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
887 struct ata_channel *ch = device_get_softc(dev);
888
889 ata_dmainit(dev);
890 if (ch->dma) {
891 /* note start and stop are not used here */
892 ch->dma->setprd = ata_ahci_dmasetprd;
893 ch->dma->max_iosize = 8192 * DEV_BSIZE;
894 if (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_64BIT)
895 ch->dma->max_address = BUS_SPACE_MAXADDR;
896 }
897 }
898
899 static int
900 ata_ahci_setup_fis(struct ata_ahci_cmd_tab *ctp, struct ata_request *request)
901 {
902 bzero(ctp->cfis, 64);
903 if (request->flags & ATA_R_ATAPI) {
904 bzero(ctp->acmd, 32);
905 bcopy(request->u.atapi.ccb, ctp->acmd, 16);
906 }
907 return ata_request2fis_h2d(request, &ctp->cfis[0]);
908 }
909
910 /*
911 * Acard chipset support functions
912 */
913 int
914 ata_acard_ident(device_t dev)
915 {
916 struct ata_pci_controller *ctlr = device_get_softc(dev);
917 struct ata_chip_id *idx;
918 static struct ata_chip_id ids[] =
919 {{ ATA_ATP850R, 0, ATPOLD, 0x00, ATA_UDMA2, "ATP850" },
920 { ATA_ATP860A, 0, 0, 0x00, ATA_UDMA4, "ATP860A" },
921 { ATA_ATP860R, 0, 0, 0x00, ATA_UDMA4, "ATP860R" },
922 { ATA_ATP865A, 0, 0, 0x00, ATA_UDMA6, "ATP865A" },
923 { ATA_ATP865R, 0, 0, 0x00, ATA_UDMA6, "ATP865R" },
924 { 0, 0, 0, 0, 0, 0}};
925 char buffer[64];
926
927 if (!(idx = ata_match_chip(dev, ids)))
928 return ENXIO;
929
930 ksprintf(buffer, "Acard %s %s controller",
931 idx->text, ata_mode2str(idx->max_dma));
932 device_set_desc_copy(dev, buffer);
933 ctlr->chip = idx;
934 ctlr->chipinit = ata_acard_chipinit;
935 return 0;
936 }
937
938 static int
939 ata_acard_chipinit(device_t dev)
940 {
941 struct ata_pci_controller *ctlr = device_get_softc(dev);
942
943 if (ata_setup_interrupt(dev))
944 return ENXIO;
945
946 ctlr->allocate = ata_acard_allocate;
947 if (ctlr->chip->cfg1 == ATPOLD) {
948 ctlr->setmode = ata_acard_850_setmode;
949 ctlr->locking = ata_serialize;
950 }
951 else
952 ctlr->setmode = ata_acard_86X_setmode;
953 return 0;
954 }
955
956 static int
957 ata_acard_allocate(device_t dev)
958 {
959 struct ata_channel *ch = device_get_softc(dev);
960
961 /* setup the usual register normal pci style */
962 if (ata_pci_allocate(dev))
963 return ENXIO;
964
965 ch->hw.status = ata_acard_status;
966 return 0;
967 }
968
969 static int
970 ata_acard_status(device_t dev)
971 {
972 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
973 struct ata_channel *ch = device_get_softc(dev);
974
975 if (ctlr->chip->cfg1 == ATPOLD &&
976 ATA_LOCKING(ch->dev, ATA_LF_WHICH) != ch->unit)
977 return 0;
978 if (ch->dma && (ch->dma->flags & ATA_DMA_ACTIVE)) {
979 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
980
981 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
982 ATA_BMSTAT_INTERRUPT)
983 return 0;
984 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
985 DELAY(1);
986 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
987 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
988 DELAY(1);
989 }
990 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) {
991 DELAY(100);
992 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY)
993 return 0;
994 }
995 return 1;
996 }
997
998 static void
999 ata_acard_850_setmode(device_t dev, int mode)
1000 {
1001 device_t gparent = GRANDPARENT(dev);
1002 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1003 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1004 struct ata_device *atadev = device_get_softc(dev);
1005 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1006 int error;
1007
1008 mode = ata_limit_mode(dev, mode,
1009 ata_atapi(dev) ? ATA_PIO_MAX : ctlr->chip->max_dma);
1010
1011 /* XXX SOS missing WDMA0+1 + PIO modes */
1012 if (mode >= ATA_WDMA2) {
1013 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1014 if (bootverbose)
1015 device_printf(dev, "%ssetting %s on %s chip\n",
1016 (error) ? "FAILURE " : "",
1017 ata_mode2str(mode), ctlr->chip->text);
1018 if (!error) {
1019 u_int8_t reg54 = pci_read_config(gparent, 0x54, 1);
1020
1021 reg54 &= ~(0x03 << (devno << 1));
1022 if (mode >= ATA_UDMA0)
1023 reg54 |= (((mode & ATA_MODE_MASK) + 1) << (devno << 1));
1024 pci_write_config(gparent, 0x54, reg54, 1);
1025 pci_write_config(gparent, 0x4a, 0xa6, 1);
1026 pci_write_config(gparent, 0x40 + (devno << 1), 0x0301, 2);
1027 atadev->mode = mode;
1028 return;
1029 }
1030 }
1031 /* we could set PIO mode timings, but we assume the BIOS did that */
1032 }
1033
1034 static void
1035 ata_acard_86X_setmode(device_t dev, int mode)
1036 {
1037 device_t gparent = GRANDPARENT(dev);
1038 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1039 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1040 struct ata_device *atadev = device_get_softc(dev);
1041 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1042 int error;
1043
1044
1045 mode = ata_limit_mode(dev, mode,
1046 ata_atapi(dev) ? ATA_PIO_MAX : ctlr->chip->max_dma);
1047
1048 mode = ata_check_80pin(dev, mode);
1049
1050 /* XXX SOS missing WDMA0+1 + PIO modes */
1051 if (mode >= ATA_WDMA2) {
1052 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1053 if (bootverbose)
1054 device_printf(dev, "%ssetting %s on %s chip\n",
1055 (error) ? "FAILURE " : "",
1056 ata_mode2str(mode), ctlr->chip->text);
1057 if (!error) {
1058 u_int16_t reg44 = pci_read_config(gparent, 0x44, 2);
1059
1060 reg44 &= ~(0x000f << (devno << 2));
1061 if (mode >= ATA_UDMA0)
1062 reg44 |= (((mode & ATA_MODE_MASK) + 1) << (devno << 2));
1063 pci_write_config(gparent, 0x44, reg44, 2);
1064 pci_write_config(gparent, 0x4a, 0xa6, 1);
1065 pci_write_config(gparent, 0x40 + devno, 0x31, 1);
1066 atadev->mode = mode;
1067 return;
1068 }
1069 }
1070 /* we could set PIO mode timings, but we assume the BIOS did that */
1071 }
1072
1073
1074 /*
1075 * Acer Labs Inc (ALI) chipset support functions
1076 */
1077 int
1078 ata_ali_ident(device_t dev)
1079 {
1080 struct ata_pci_controller *ctlr = device_get_softc(dev);
1081 struct ata_chip_id *idx;
1082 static struct ata_chip_id ids[] =
1083 {{ ATA_ALI_5289, 0x00, 2, ALISATA, ATA_SA150, "M5289" },
1084 { ATA_ALI_5288, 0x00, 4, ALISATA, ATA_SA300, "M5288" },
1085 { ATA_ALI_5287, 0x00, 4, ALISATA, ATA_SA150, "M5287" },
1086 { ATA_ALI_5281, 0x00, 2, ALISATA, ATA_SA150, "M5281" },
1087 { ATA_ALI_5229, 0xc5, 0, ALINEW, ATA_UDMA6, "M5229" },
1088 { ATA_ALI_5229, 0xc4, 0, ALINEW, ATA_UDMA5, "M5229" },
1089 { ATA_ALI_5229, 0xc2, 0, ALINEW, ATA_UDMA4, "M5229" },
1090 { ATA_ALI_5229, 0x20, 0, ALIOLD, ATA_UDMA2, "M5229" },
1091 { ATA_ALI_5229, 0x00, 0, ALIOLD, ATA_WDMA2, "M5229" },
1092 { 0, 0, 0, 0, 0, 0}};
1093 char buffer[64];
1094
1095 if (!(idx = ata_match_chip(dev, ids)))
1096 return ENXIO;
1097
1098 ksprintf(buffer, "AcerLabs %s %s controller",
1099 idx->text, ata_mode2str(idx->max_dma));
1100 device_set_desc_copy(dev, buffer);
1101 ctlr->chip = idx;
1102 ctlr->chipinit = ata_ali_chipinit;
1103 return 0;
1104 }
1105
1106 static int
1107 ata_ali_chipinit(device_t dev)
1108 {
1109 struct ata_pci_controller *ctlr = device_get_softc(dev);
1110
1111 if (ata_setup_interrupt(dev))
1112 return ENXIO;
1113
1114 switch (ctlr->chip->cfg2) {
1115 case ALISATA:
1116 ctlr->channels = ctlr->chip->cfg1;
1117 ctlr->allocate = ata_ali_sata_allocate;
1118 ctlr->setmode = ata_sata_setmode;
1119
1120 /* AHCI mode is correctly supported only on the ALi 5288. */
1121 if ((ctlr->chip->chipid == ATA_ALI_5288) &&
1122 (ata_ahci_chipinit(dev) != ENXIO))
1123 return 0;
1124
1125 /* enable PCI interrupt */
1126 pci_write_config(dev, PCIR_COMMAND,
1127 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
1128 break;
1129
1130 case ALINEW:
1131 /* use device interrupt as byte count end */
1132 pci_write_config(dev, 0x4a, pci_read_config(dev, 0x4a, 1) | 0x20, 1);
1133
1134 /* enable cable detection and UDMA support on newer chips */
1135 pci_write_config(dev, 0x4b, pci_read_config(dev, 0x4b, 1) | 0x09, 1);
1136
1137 /* enable ATAPI UDMA mode */
1138 pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) | 0x01, 1);
1139
1140 /* only chips with revision > 0xc4 can do 48bit DMA */
1141 if (ctlr->chip->chiprev <= 0xc4)
1142 device_printf(dev,
1143 "using PIO transfers above 137GB as workaround for "
1144 "48bit DMA access bug, expect reduced performance\n");
1145 ctlr->allocate = ata_ali_allocate;
1146 ctlr->reset = ata_ali_reset;
1147 ctlr->setmode = ata_ali_setmode;
1148 break;
1149
1150 case ALIOLD:
1151 /* deactivate the ATAPI FIFO and enable ATAPI UDMA */
1152 pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) | 0x03, 1);
1153 ctlr->setmode = ata_ali_setmode;
1154 break;
1155 }
1156 return 0;
1157 }
1158
1159 static int
1160 ata_ali_allocate(device_t dev)
1161 {
1162 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
1163 struct ata_channel *ch = device_get_softc(dev);
1164
1165 /* setup the usual register normal pci style */
1166 if (ata_pci_allocate(dev))
1167 return ENXIO;
1168
1169 /* older chips can't do 48bit DMA transfers */
1170 if (ctlr->chip->chiprev <= 0xc4)
1171 ch->flags |= ATA_NO_48BIT_DMA;
1172
1173 return 0;
1174 }
1175
1176 static int
1177 ata_ali_sata_allocate(device_t dev)
1178 {
1179 device_t parent = device_get_parent(dev);
1180 struct ata_pci_controller *ctlr = device_get_softc(parent);
1181 struct ata_channel *ch = device_get_softc(dev);
1182 struct resource *io = NULL, *ctlio = NULL;
1183 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2);
1184 int i, rid;
1185
1186 rid = PCIR_BAR(0) + (unit01 ? 8 : 0);
1187 io = bus_alloc_resource_any(parent, SYS_RES_IOPORT, &rid, RF_ACTIVE);
1188 if (!io)
1189 return ENXIO;
1190
1191 rid = PCIR_BAR(1) + (unit01 ? 8 : 0);
1192 ctlio = bus_alloc_resource_any(parent, SYS_RES_IOPORT, &rid, RF_ACTIVE);
1193 if (!ctlio) {
1194 bus_release_resource(dev, SYS_RES_IOPORT, ATA_IOADDR_RID, io);
1195 return ENXIO;
1196 }
1197
1198 for (i = ATA_DATA; i <= ATA_COMMAND; i ++) {
1199 ch->r_io[i].res = io;
1200 ch->r_io[i].offset = i + (unit10 ? 8 : 0);
1201 }
1202 ch->r_io[ATA_CONTROL].res = ctlio;
1203 ch->r_io[ATA_CONTROL].offset = 2 + (unit10 ? 4 : 0);
1204 ch->r_io[ATA_IDX_ADDR].res = io;
1205 ata_default_registers(dev);
1206 if (ctlr->r_res1) {
1207 for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) {
1208 ch->r_io[i].res = ctlr->r_res1;
1209 ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE);
1210 }
1211 }
1212 ch->flags |= ATA_NO_SLAVE;
1213
1214 /* XXX SOS PHY handling awkward in ALI chip not supported yet */
1215 ata_pci_hw(dev);
1216 return 0;
1217 }
1218
1219 static void
1220 ata_ali_reset(device_t dev)
1221 {
1222 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
1223 struct ata_channel *ch = device_get_softc(dev);
1224 device_t *children;
1225 int nchildren, i;
1226
1227 ata_generic_reset(dev);
1228
1229 /*
1230 * workaround for datacorruption bug found on at least SUN Blade-100
1231 * find the ISA function on the southbridge and disable then enable
1232 * the ATA channel tristate buffer
1233 */
1234 if (ctlr->chip->chiprev == 0xc3 || ctlr->chip->chiprev == 0xc2) {
1235 if (!device_get_children(GRANDPARENT(dev), &children, &nchildren)) {
1236 for (i = 0; i < nchildren; i++) {
1237 if (pci_get_devid(children[i]) == ATA_ALI_1533) {
1238 pci_write_config(children[i], 0x58,
1239 pci_read_config(children[i], 0x58, 1) &
1240 ~(0x04 << ch->unit), 1);
1241 pci_write_config(children[i], 0x58,
1242 pci_read_config(children[i], 0x58, 1) |
1243 (0x04 << ch->unit), 1);
1244 break;
1245 }
1246 }
1247 kfree(children, M_TEMP);
1248 }
1249 }
1250 }
1251
1252 static void
1253 ata_ali_setmode(device_t dev, int mode)
1254 {
1255 device_t gparent = GRANDPARENT(dev);
1256 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1257 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1258 struct ata_device *atadev = device_get_softc(dev);
1259 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1260 int error;
1261
1262 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
1263
1264 if (ctlr->chip->cfg2 & ALINEW) {
1265 if (mode > ATA_UDMA2 &&
1266 pci_read_config(gparent, 0x4a, 1) & (1 << ch->unit)) {
1267 ata_print_cable(dev, "controller");
1268 mode = ATA_UDMA2;
1269 }
1270 }
1271 else
1272 mode = ata_check_80pin(dev, mode);
1273
1274 if (ctlr->chip->cfg2 & ALIOLD) {
1275 /* doesn't support ATAPI DMA on write */
1276 ch->flags |= ATA_ATAPI_DMA_RO;
1277 if (ch->devices & ATA_ATAPI_MASTER && ch->devices & ATA_ATAPI_SLAVE) {
1278 /* doesn't support ATAPI DMA on two ATAPI devices */
1279 device_printf(dev, "two atapi devices on this channel, no DMA\n");
1280 mode = ata_limit_mode(dev, mode, ATA_PIO_MAX);
1281 }
1282 }
1283
1284 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1285
1286 if (bootverbose)
1287 device_printf(dev, "%ssetting %s on %s chip\n",
1288 (error) ? "FAILURE " : "",
1289 ata_mode2str(mode), ctlr->chip->text);
1290 if (!error) {
1291 if (mode >= ATA_UDMA0) {
1292 u_int8_t udma[] = {0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x0f, 0x0d};
1293 u_int32_t word54 = pci_read_config(gparent, 0x54, 4);
1294
1295 word54 &= ~(0x000f000f << (devno << 2));
1296 word54 |= (((udma[mode&ATA_MODE_MASK]<<16)|0x05)<<(devno<<2));
1297 pci_write_config(gparent, 0x54, word54, 4);
1298 pci_write_config(gparent, 0x58 + (ch->unit << 2),
1299 0x00310001, 4);
1300 }
1301 else {
1302 u_int32_t piotimings[] =
1303 { 0x006d0003, 0x00580002, 0x00440001, 0x00330001,
1304 0x00310001, 0x00440001, 0x00330001, 0x00310001};
1305
1306 pci_write_config(gparent, 0x54, pci_read_config(gparent, 0x54, 4) &
1307 ~(0x0008000f << (devno << 2)), 4);
1308 pci_write_config(gparent, 0x58 + (ch->unit << 2),
1309 piotimings[ata_mode2idx(mode)], 4);
1310 }
1311 atadev->mode = mode;
1312 }
1313 }
1314
1315
1316 /*
1317 * American Micro Devices (AMD) chipset support functions
1318 */
1319 int
1320 ata_amd_ident(device_t dev)
1321 {
1322 struct ata_pci_controller *ctlr = device_get_softc(dev);
1323 struct ata_chip_id *idx;
1324 static struct ata_chip_id ids[] =
1325 {{ ATA_AMD756, 0x00, AMDNVIDIA, 0x00, ATA_UDMA4, "756" },
1326 { ATA_AMD766, 0x00, AMDNVIDIA, AMDCABLE|AMDBUG, ATA_UDMA5, "766" },
1327 { ATA_AMD768, 0x00, AMDNVIDIA, AMDCABLE, ATA_UDMA5, "768" },
1328 { ATA_AMD8111, 0x00, AMDNVIDIA, AMDCABLE, ATA_UDMA6, "8111" },
1329 { 0, 0, 0, 0, 0, 0}};
1330 char buffer[64];
1331
1332 if (!(idx = ata_match_chip(dev, ids)))
1333 return ENXIO;
1334
1335 ksprintf(buffer, "AMD %s %s controller",
1336 idx->text, ata_mode2str(idx->max_dma));
1337 device_set_desc_copy(dev, buffer);
1338 ctlr->chip = idx;
1339 ctlr->chipinit = ata_amd_chipinit;
1340 return 0;
1341 }
1342
1343 static int
1344 ata_amd_chipinit(device_t dev)
1345 {
1346 struct ata_pci_controller *ctlr = device_get_softc(dev);
1347
1348 if (ata_setup_interrupt(dev))
1349 return ENXIO;
1350
1351 /* disable/set prefetch, postwrite */
1352 if (ctlr->chip->cfg2 & AMDBUG)
1353 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) & 0x0f, 1);
1354 else
1355 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) | 0xf0, 1);
1356
1357 ctlr->setmode = ata_via_family_setmode;
1358 return 0;
1359 }
1360
1361
1362 /*
1363 * ATI chipset support functions
1364 */
1365 int
1366 ata_ati_ident(device_t dev)
1367 {
1368 struct ata_pci_controller *ctlr = device_get_softc(dev);
1369 struct ata_chip_id *idx;
1370 static struct ata_chip_id ids[] =
1371 {{ ATA_ATI_IXP200, 0x00, 0, 0, ATA_UDMA5, "IXP200" },
1372 { ATA_ATI_IXP300, 0x00, 0, 0, ATA_UDMA6, "IXP300" },
1373 { ATA_ATI_IXP400, 0x00, 0, 0, ATA_UDMA6, "IXP400" },
1374 { ATA_ATI_SB600, 0x00, 0, 0, ATA_UDMA6, "SB600" },
1375 { ATA_ATI_IXP300_S1, 0x00, SIIMEMIO, 0, ATA_SA150, "IXP300" },
1376 { ATA_ATI_IXP400_S1, 0x00, SIIMEMIO, 0, ATA_SA150, "IXP400" },
1377 { ATA_ATI_IXP400_S2, 0x00, SIIMEMIO, 0, ATA_SA150, "IXP400" },
1378 { ATA_ATI_SB600_S1, 0x00, ATIAHCI, 0, ATA_SA300, "SB600" },
1379 { ATA_ATI_SB600_S2, 0x00, ATIAHCI, 0, ATA_SA300, "SB600" },
1380 { 0, 0, 0, 0, 0, 0}};
1381 char buffer[64];
1382
1383 if (!(idx = ata_match_chip(dev, ids)))
1384 return ENXIO;
1385
1386 ksprintf(buffer, "ATI %s %s controller",
1387 idx->text, ata_mode2str(idx->max_dma));
1388 device_set_desc_copy(dev, buffer);
1389 ctlr->chip = idx;
1390
1391 /*
1392 * The ATI SATA controllers are actually a SiI 3112 controller, except
1393 * for the SB600.
1394 */
1395 if (ctlr->chip->cfg1 & SIIMEMIO)
1396 ctlr->chipinit = ata_sii_chipinit;
1397 else
1398 ctlr->chipinit = ata_ati_chipinit;
1399 return 0;
1400 }
1401
1402 static int
1403 ata_ati_chipinit(device_t dev)
1404 {
1405 struct ata_pci_controller *ctlr = device_get_softc(dev);
1406
1407 if (ata_setup_interrupt(dev))
1408 return ENXIO;
1409
1410 /* The SB600 needs special treatment. */
1411 if (ctlr->chip->cfg1 & ATIAHCI) {
1412 /* Check if the chip is configured as an AHCI part. */
1413 if ((pci_get_subclass(dev) == PCIS_STORAGE_SATA) &&
1414 (pci_read_config(dev, PCIR_PROGIF, 1) == PCIP_STORAGE_SATA_AHCI_1_0)) {
1415 if (ata_ahci_chipinit(dev) != ENXIO)
1416 return 0;
1417 }
1418 }
1419
1420 ctlr->setmode = ata_ati_setmode;
1421 return 0;
1422 }
1423
1424 static void
1425 ata_ati_setmode(device_t dev, int mode)
1426 {
1427 device_t gparent = GRANDPARENT(dev);
1428 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1429 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1430 struct ata_device *atadev = device_get_softc(dev);
1431 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1432 int offset = (devno ^ 0x01) << 3;
1433 int error;
1434 u_int8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20, 0x34, 0x22, 0x20,
1435 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
1436 u_int8_t dmatimings[] = { 0x77, 0x21, 0x20 };
1437
1438 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
1439
1440 mode = ata_check_80pin(dev, mode);
1441
1442 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1443
1444 if (bootverbose)
1445 device_printf(dev, "%ssetting %s on %s chip\n",
1446 (error) ? "FAILURE " : "",
1447 ata_mode2str(mode), ctlr->chip->text);
1448 if (!error) {
1449 if (mode >= ATA_UDMA0) {
1450 pci_write_config(gparent, 0x56,
1451 (pci_read_config(gparent, 0x56, 2) &
1452 ~(0xf << (devno << 2))) |
1453 ((mode & ATA_MODE_MASK) << (devno << 2)), 2);
1454 pci_write_config(gparent, 0x54,
1455 pci_read_config(gparent, 0x54, 1) |
1456 (0x01 << devno), 1);
1457 pci_write_config(gparent, 0x44,
1458 (pci_read_config(gparent, 0x44, 4) &
1459 ~(0xff << offset)) |
1460 (dmatimings[2] << offset), 4);
1461 }
1462 else if (mode >= ATA_WDMA0) {
1463 pci_write_config(gparent, 0x54,
1464 pci_read_config(gparent, 0x54, 1) &
1465 ~(0x01 << devno), 1);
1466 pci_write_config(gparent, 0x44,
1467 (pci_read_config(gparent, 0x44, 4) &
1468 ~(0xff << offset)) |
1469 (dmatimings[mode & ATA_MODE_MASK] << offset), 4);
1470 }
1471 else
1472 pci_write_config(gparent, 0x54,
1473 pci_read_config(gparent, 0x54, 1) &
1474 ~(0x01 << devno), 1);
1475
1476 pci_write_config(gparent, 0x4a,
1477 (pci_read_config(gparent, 0x4a, 2) &
1478 ~(0xf << (devno << 2))) |
1479 (((mode - ATA_PIO0) & ATA_MODE_MASK) << (devno<<2)),2);
1480 pci_write_config(gparent, 0x40,
1481 (pci_read_config(gparent, 0x40, 4) &
1482 ~(0xff << offset)) |
1483 (piotimings[ata_mode2idx(mode)] << offset), 4);
1484 atadev->mode = mode;
1485 }
1486 }
1487
1488 /*
1489 * Cyrix chipset support functions
1490 */
1491 int
1492 ata_cyrix_ident(device_t dev)
1493 {
1494 struct ata_pci_controller *ctlr = device_get_softc(dev);
1495
1496 if (pci_get_devid(dev) == ATA_CYRIX_5530) {
1497 device_set_desc(dev, "Cyrix 5530 ATA33 controller");
1498 ctlr->chipinit = ata_cyrix_chipinit;
1499 return 0;
1500 }
1501 return ENXIO;
1502 }
1503
1504 static int
1505 ata_cyrix_chipinit(device_t dev)
1506 {
1507 struct ata_pci_controller *ctlr = device_get_softc(dev);
1508
1509 if (ata_setup_interrupt(dev))
1510 return ENXIO;
1511
1512 if (ctlr->r_res1)
1513 ctlr->setmode = ata_cyrix_setmode;
1514 else
1515 ctlr->setmode = ata_generic_setmode;
1516 return 0;
1517 }
1518
1519 static void
1520 ata_cyrix_setmode(device_t dev, int mode)
1521 {
1522 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1523 struct ata_device *atadev = device_get_softc(dev);
1524 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1525 u_int32_t piotiming[] =
1526 { 0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010 };
1527 u_int32_t dmatiming[] = { 0x00077771, 0x00012121, 0x00002020 };
1528 u_int32_t udmatiming[] = { 0x00921250, 0x00911140, 0x00911030 };
1529 int error;
1530
1531 ch->dma->alignment = 16;
1532 ch->dma->max_iosize = 126 * DEV_BSIZE;
1533
1534 mode = ata_limit_mode(dev, mode, ATA_UDMA2);
1535
1536 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1537
1538 if (bootverbose)
1539 device_printf(dev, "%ssetting %s on Cyrix chip\n",
1540 (error) ? "FAILURE " : "", ata_mode2str(mode));
1541 if (!error) {
1542 if (mode >= ATA_UDMA0) {
1543 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res,
1544 0x24 + (devno << 3), udmatiming[mode & ATA_MODE_MASK]);
1545 }
1546 else if (mode >= ATA_WDMA0) {
1547 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res,
1548 0x24 + (devno << 3), dmatiming[mode & ATA_MODE_MASK]);
1549 }
1550 else {
1551 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res,
1552 0x20 + (devno << 3), piotiming[mode & ATA_MODE_MASK]);
1553 }
1554 atadev->mode = mode;
1555 }
1556 }
1557
1558
1559 /*
1560 * Cypress chipset support functions
1561 */
1562 int
1563 ata_cypress_ident(device_t dev)
1564 {
1565 struct ata_pci_controller *ctlr = device_get_softc(dev);
1566
1567 /*
1568 * the Cypress chip is a mess, it contains two ATA functions, but
1569 * both channels are visible on the first one.
1570 * simply ignore the second function for now, as the right
1571 * solution (ignoring the second channel on the first function)
1572 * doesn't work with the crappy ATA interrupt setup on the alpha.
1573 */
1574 if (pci_get_devid(dev) == ATA_CYPRESS_82C693 &&
1575 pci_get_function(dev) == 1 &&
1576 pci_get_subclass(dev) == PCIS_STORAGE_IDE) {
1577 device_set_desc(dev, "Cypress 82C693 ATA controller");
1578 ctlr->chipinit = ata_cypress_chipinit;
1579 return 0;
1580 }
1581 return ENXIO;
1582 }
1583
1584 static int
1585 ata_cypress_chipinit(device_t dev)
1586 {
1587 struct ata_pci_controller *ctlr = device_get_softc(dev);
1588
1589 if (ata_setup_interrupt(dev))
1590 return ENXIO;
1591
1592 ctlr->setmode = ata_cypress_setmode;
1593 return 0;
1594 }
1595
1596 static void
1597 ata_cypress_setmode(device_t dev, int mode)
1598 {
1599 device_t gparent = GRANDPARENT(dev);
1600 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1601 struct ata_device *atadev = device_get_softc(dev);
1602 int error;
1603
1604 mode = ata_limit_mode(dev, mode, ATA_WDMA2);
1605
1606 /* XXX SOS missing WDMA0+1 + PIO modes */
1607 if (mode == ATA_WDMA2) {
1608 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1609 if (bootverbose)
1610 device_printf(dev, "%ssetting WDMA2 on Cypress chip\n",
1611 error ? "FAILURE " : "");
1612 if (!error) {
1613 pci_write_config(gparent, ch->unit ? 0x4e : 0x4c, 0x2020, 2);
1614 atadev->mode = mode;
1615 return;
1616 }
1617 }
1618 /* we could set PIO mode timings, but we assume the BIOS did that */
1619 }
1620
1621
1622 /*
1623 * HighPoint chipset support functions
1624 */
1625 int
1626 ata_highpoint_ident(device_t dev)
1627 {
1628 struct ata_pci_controller *ctlr = device_get_softc(dev);
1629 struct ata_chip_id *idx;
1630 static struct ata_chip_id ids[] =
1631 {{ ATA_HPT374, 0x07, HPT374, 0x00, ATA_UDMA6, "HPT374" },
1632 { ATA_HPT372, 0x02, HPT372, 0x00, ATA_UDMA6, "HPT372N" },
1633 { ATA_HPT372, 0x01, HPT372, 0x00, ATA_UDMA6, "HPT372" },
1634 { ATA_HPT371, 0x01, HPT372, 0x00, ATA_UDMA6, "HPT371" },
1635 { ATA_HPT366, 0x05, HPT372, 0x00, ATA_UDMA6, "HPT372" },
1636 { ATA_HPT366, 0x03, HPT370, 0x00, ATA_UDMA5, "HPT370" },
1637 { ATA_HPT366, 0x02, HPT366, 0x00, ATA_UDMA4, "HPT368" },
1638 { ATA_HPT366, 0x00, HPT366, HPTOLD, ATA_UDMA4, "HPT366" },
1639 { ATA_HPT302, 0x01, HPT372, 0x00, ATA_UDMA6, "HPT302" },
1640 { 0, 0, 0, 0, 0, 0}};
1641 char buffer[64];
1642
1643 if (!(idx = ata_match_chip(dev, ids)))
1644 return ENXIO;
1645
1646 strcpy(buffer, "HighPoint ");
1647 strcat(buffer, idx->text);
1648 if (idx->cfg1 == HPT374) {
1649 if (pci_get_function(dev) == 0)
1650 strcat(buffer, " (channel 0+1)");
1651 if (pci_get_function(dev) == 1)
1652 strcat(buffer, " (channel 2+3)");
1653 }
1654 ksprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma));
1655 device_set_desc_copy(dev, buffer);
1656 ctlr->chip = idx;
1657 ctlr->chipinit = ata_highpoint_chipinit;
1658 return 0;
1659 }
1660
1661 static int
1662 ata_highpoint_chipinit(device_t dev)
1663 {
1664 struct ata_pci_controller *ctlr = device_get_softc(dev);
1665
1666 if (ata_setup_interrupt(dev))
1667 return ENXIO;
1668
1669 if (ctlr->chip->cfg2 == HPTOLD) {
1670 /* disable interrupt prediction */
1671 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x80), 1);
1672 }
1673 else {
1674 /* disable interrupt prediction */
1675 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x03), 1);
1676 pci_write_config(dev, 0x55, (pci_read_config(dev, 0x55, 1) & ~0x03), 1);
1677
1678 /* enable interrupts */
1679 pci_write_config(dev, 0x5a, (pci_read_config(dev, 0x5a, 1) & ~0x10), 1);
1680
1681 /* set clocks etc */
1682 if (ctlr->chip->cfg1 < HPT372)
1683 pci_write_config(dev, 0x5b, 0x22, 1);
1684 else
1685 pci_write_config(dev, 0x5b,
1686 (pci_read_config(dev, 0x5b, 1) & 0x01) | 0x20, 1);
1687 }
1688 ctlr->allocate = ata_highpoint_allocate;
1689 ctlr->setmode = ata_highpoint_setmode;
1690 return 0;
1691 }
1692
1693 static int
1694 ata_highpoint_allocate(device_t dev)
1695 {
1696 struct ata_channel *ch = device_get_softc(dev);
1697
1698 /* setup the usual register normal pci style */
1699 if (ata_pci_allocate(dev))
1700 return ENXIO;
1701
1702 ch->flags |= ATA_ALWAYS_DMASTAT;
1703 return 0;
1704 }
1705
1706 static void
1707 ata_highpoint_setmode(device_t dev, int mode)
1708 {
1709 device_t gparent = GRANDPARENT(dev);
1710 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1711 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1712 struct ata_device *atadev = device_get_softc(dev);
1713 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1714 int error;
1715 u_int32_t timings33[][4] = {
1716 /* HPT366 HPT370 HPT372 HPT374 mode */
1717 { 0x40d0a7aa, 0x06914e57, 0x0d029d5e, 0x0ac1f48a }, /* PIO 0 */
1718 { 0x40d0a7a3, 0x06914e43, 0x0d029d26, 0x0ac1f465 }, /* PIO 1 */
1719 { 0x40d0a753, 0x06514e33, 0x0c829ca6, 0x0a81f454 }, /* PIO 2 */
1720 { 0x40c8a742, 0x06514e22, 0x0c829c84, 0x0a81f443 }, /* PIO 3 */
1721 { 0x40c8a731, 0x06514e21, 0x0c829c62, 0x0a81f442 }, /* PIO 4 */
1722 { 0x20c8a797, 0x26514e97, 0x2c82922e, 0x228082ea }, /* MWDMA 0 */
1723 { 0x20c8a732, 0x26514e33, 0x2c829266, 0x22808254 }, /* MWDMA 1 */
1724 { 0x20c8a731, 0x26514e21, 0x2c829262, 0x22808242 }, /* MWDMA 2 */
1725 { 0x10c8a731, 0x16514e31, 0x1c829c62, 0x121882ea }, /* UDMA 0 */
1726 { 0x10cba731, 0x164d4e31, 0x1c9a9c62, 0x12148254 }, /* UDMA 1 */
1727 { 0x10caa731, 0x16494e31, 0x1c929c62, 0x120c8242 }, /* UDMA 2 */
1728 { 0x10cfa731, 0x166d4e31, 0x1c8e9c62, 0x128c8242 }, /* UDMA 3 */
1729 { 0x10c9a731, 0x16454e31, 0x1c8a9c62, 0x12ac8242 }, /* UDMA 4 */
1730 { 0, 0x16454e31, 0x1c8a9c62, 0x12848242 }, /* UDMA 5 */
1731 { 0, 0, 0x1c869c62, 0x12808242 } /* UDMA 6 */
1732 };
1733
1734 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
1735
1736 if (ctlr->chip->cfg1 == HPT366 && ata_atapi(dev))
1737 mode = ata_limit_mode(dev, mode, ATA_PIO_MAX);
1738
1739 mode = ata_highpoint_check_80pin(dev, mode);
1740
1741 /*
1742 * most if not all HPT chips cant really handle that the device is
1743 * running at ATA_UDMA6/ATA133 speed, so we cheat at set the device to
1744 * a max of ATA_UDMA5/ATA100 to guard against suboptimal performance
1745 */
1746 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0,
1747 ata_limit_mode(dev, mode, ATA_UDMA5));
1748 if (bootverbose)
1749 device_printf(dev, "%ssetting %s on HighPoint chip\n",
1750 (error) ? "FAILURE " : "", ata_mode2str(mode));
1751 if (!error)
1752 pci_write_config(gparent, 0x40 + (devno << 2),
1753 timings33[ata_mode2idx(mode)][ctlr->chip->cfg1], 4);
1754 atadev->mode = mode;
1755 }
1756
1757 static int
1758 ata_highpoint_check_80pin(device_t dev, int mode)
1759 {
1760 device_t gparent = GRANDPARENT(dev);
1761 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1762 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1763 u_int8_t reg, val, res;
1764
1765 if (ctlr->chip->cfg1 == HPT374 && pci_get_function(gparent) == 1) {
1766 reg = ch->unit ? 0x57 : 0x53;
1767 val = pci_read_config(gparent, reg, 1);
1768 pci_write_config(gparent, reg, val | 0x80, 1);
1769 }
1770 else {
1771 reg = 0x5b;
1772 val = pci_read_config(gparent, reg, 1);
1773 pci_write_config(gparent, reg, val & 0xfe, 1);
1774 }
1775 res = pci_read_config(gparent, 0x5a, 1) & (ch->unit ? 0x1:0x2);
1776 pci_write_config(gparent, reg, val, 1);
1777
1778 if (mode > ATA_UDMA2 && res) {
1779 ata_print_cable(dev, "controller");
1780 mode = ATA_UDMA2;
1781 }
1782 return mode;
1783 }
1784
1785
1786 /*
1787 * Intel chipset support functions
1788 */
1789 int
1790 ata_intel_ident(device_t dev)
1791 {
1792 struct ata_pci_controller *ctlr = device_get_softc(dev);
1793 struct ata_chip_id *idx;
1794 static struct ata_chip_id ids[] =
1795 {{ ATA_I82371FB, 0, 0, 0x00, ATA_WDMA2, "PIIX" },
1796 { ATA_I82371SB, 0, 0, 0x00, ATA_WDMA2, "PIIX3" },
1797 { ATA_I82371AB, 0, 0, 0x00, ATA_UDMA2, "PIIX4" },
1798 { ATA_I82443MX, 0, 0, 0x00, ATA_UDMA2, "PIIX4" },
1799 { ATA_I82451NX, 0, 0, 0x00, ATA_UDMA2, "PIIX4" },
1800 { ATA_I82801AB, 0, 0, 0x00, ATA_UDMA2, "ICH0" },
1801 { ATA_I82801AA, 0, 0, 0x00, ATA_UDMA4, "ICH" },
1802 { ATA_I82372FB, 0, 0, 0x00, ATA_UDMA4, "ICH" },
1803 { ATA_I82801BA, 0, 0, 0x00, ATA_UDMA5, "ICH2" },
1804 { ATA_I82801BA_1, 0, 0, 0x00, ATA_UDMA5, "ICH2" },
1805 { ATA_I82801CA, 0, 0, 0x00, ATA_UDMA5, "ICH3" },
1806 { ATA_I82801CA_1, 0, 0, 0x00, ATA_UDMA5, "ICH3" },
1807 { ATA_I82801DB, 0, 0, 0x00, ATA_UDMA5, "ICH4" },
1808 { ATA_I82801DB_1, 0, 0, 0x00, ATA_UDMA5, "ICH4" },
1809 { ATA_I82801EB, 0, 0, 0x00, ATA_UDMA5, "ICH5" },
1810 { ATA_I82801EB_S1, 0, 0, 0x00, ATA_SA150, "ICH5" },
1811 { ATA_I82801EB_R1, 0, 0, 0x00, ATA_SA150, "ICH5" },
1812 { ATA_I6300ESB, 0, 0, 0x00, ATA_UDMA5, "6300ESB" },
1813 { ATA_I6300ESB_S1, 0, 0, 0x00, ATA_SA150, "6300ESB" },
1814 { ATA_I6300ESB_R1, 0, 0, 0x00, ATA_SA150, "6300ESB" },
1815 { ATA_I82801FB, 0, 0, 0x00, ATA_UDMA5, "ICH6" },
1816 { ATA_I82801FB_S1, 0, AHCI, 0x00, ATA_SA150, "ICH6" },
1817 { ATA_I82801FB_R1, 0, AHCI, 0x00, ATA_SA150, "ICH6" },
1818 { ATA_I82801FBM, 0, AHCI, 0x00, ATA_SA150, "ICH6M" },
1819 { ATA_I82801GB, 0, 0, 0x00, ATA_UDMA5, "ICH7" },
1820 { ATA_I82801GB_S1, 0, AHCI, 0x00, ATA_SA300, "ICH7" },
1821 { ATA_I82801GB_R1, 0, AHCI, 0x00, ATA_SA300, "ICH7" },
1822 { ATA_I82801GB_AH, 0, AHCI, 0x00, ATA_SA300, "ICH7" },
1823 { ATA_I82801GBM_S1, 0, AHCI, 0x00, ATA_SA300, "ICH7M" },
1824 { ATA_I82801GBM_R1, 0, AHCI, 0x00, ATA_SA300, "ICH7M" },
1825 { ATA_I82801GBM_AH, 0, AHCI, 0x00, ATA_SA300, "ICH7M" },
1826 { ATA_I63XXESB2, 0, 0, 0x00, ATA_UDMA5, "63XXESB2" },
1827 { ATA_I63XXESB2_S1, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" },
1828 { ATA_I63XXESB2_S2, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" },
1829 { ATA_I63XXESB2_R1, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" },
1830 { ATA_I63XXESB2_R2, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" },
1831 { ATA_I82801HB_S1, 0, AHCI, 0x00, ATA_SA300, "ICH8" },
1832 { ATA_I82801HB_S2, 0, AHCI, 0x00, ATA_SA300, "ICH8" },
1833 { ATA_I82801HB_R1, 0, AHCI, 0x00, ATA_SA300, "ICH8" },
1834 { ATA_I82801HB_AH4, 0, AHCI, 0x00, ATA_SA300, "ICH8" },
1835 { ATA_I82801HB_AH6, 0, AHCI, 0x00, ATA_SA300, "ICH8" },
1836 { ATA_I82801HBM_S1, 0, 0, 0x00, ATA_SA300, "ICH8M" },
1837 { ATA_I82801HBM_S2, 0, AHCI, 0x00, ATA_SA300, "ICH8M" },
1838 { ATA_I82801HBM_S3, 0, AHCI, 0x00, ATA_SA300, "ICH8M" },
1839 { ATA_I82801IB_S1, 0, AHCI, 0x00, ATA_SA300, "ICH9" },
1840 { ATA_I82801IB_S2, 0, AHCI, 0x00, ATA_SA300, "ICH9" },
1841 { ATA_I82801IB_AH2, 0, AHCI, 0x00, ATA_SA300, "ICH9" },
1842 { ATA_I82801IB_AH4, 0, AHCI, 0x00, ATA_SA300, "ICH9" },
1843 { ATA_I82801IB_AH6, 0, AHCI, 0x00, ATA_SA300, "ICH9" },
1844 { ATA_I31244, 0, 0, 0x00, ATA_SA150, "31244" },
1845 { 0, 0, 0, 0, 0, 0}};
1846 char buffer[64];
1847
1848 if (!(idx = ata_match_chip(dev, ids)))
1849 return ENXIO;
1850
1851 ksprintf(buffer, "Intel %s %s controller",
1852 idx->text, ata_mode2str(idx->max_dma));
1853 device_set_desc_copy(dev, buffer);
1854 ctlr->chip = idx;
1855 ctlr->chipinit = ata_intel_chipinit;
1856 return 0;
1857 }
1858
1859 static int
1860 ata_intel_chipinit(device_t dev)
1861 {
1862 struct ata_pci_controller *ctlr = device_get_softc(dev);
1863
1864 if (ata_setup_interrupt(dev))
1865 return ENXIO;
1866
1867 /* good old PIIX needs special treatment (not implemented) */
1868 if (ctlr->chip->chipid == ATA_I82371FB) {
1869 ctlr->setmode = ata_intel_old_setmode;
1870 }
1871
1872 /* the intel 31244 needs special care if in DPA mode */
1873 else if (ctlr->chip->chipid == ATA_I31244) {
1874 if (pci_get_subclass(dev) != PCIS_STORAGE_IDE) {
1875 ctlr->r_type2 = SYS_RES_MEMORY;
1876 ctlr->r_rid2 = PCIR_BAR(0);
1877 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
1878 &ctlr->r_rid2,
1879 RF_ACTIVE)))
1880 return ENXIO;
1881 ctlr->channels = 4;
1882 ctlr->allocate = ata_intel_31244_allocate;
1883 ctlr->reset = ata_intel_31244_reset;
1884 }
1885 ctlr->setmode = ata_sata_setmode;
1886 }
1887
1888 /* non SATA intel chips goes here */
1889 else if (ctlr->chip->max_dma < ATA_SA150) {
1890 ctlr->allocate = ata_intel_allocate;
1891 ctlr->setmode = ata_intel_new_setmode;
1892 }
1893
1894 /* SATA parts can be either compat or AHCI */
1895 else {
1896 /* force all ports active "the legacy way" */
1897 pci_write_config(dev, 0x92, pci_read_config(dev, 0x92, 2) | 0x0f,2);
1898
1899 ctlr->allocate = ata_intel_allocate;
1900 ctlr->reset = ata_intel_reset;
1901
1902 /*
1903 * if we have AHCI capability and BAR(5) as a memory resource
1904 * and AHCI or RAID mode enabled in BIOS we go for AHCI mode
1905 */
1906 if ((ctlr->chip->cfg1 == AHCI) &&
1907 (pci_read_config(dev, 0x90, 1) & 0xc0) &&
1908 (ata_ahci_chipinit(dev) != ENXIO))
1909 return 0;
1910
1911 /* if BAR(5) is IO it should point to SATA interface registers */
1912 ctlr->r_type2 = SYS_RES_IOPORT;
1913 ctlr->r_rid2 = PCIR_BAR(5);
1914 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
1915 &ctlr->r_rid2, RF_ACTIVE)))
1916 ctlr->setmode = ata_intel_sata_setmode;
1917 else
1918 ctlr->setmode = ata_sata_setmode;
1919
1920 /* enable PCI interrupt */
1921 pci_write_config(dev, PCIR_COMMAND,
1922 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
1923 }
1924 return 0;
1925 }
1926
1927 static int
1928 ata_intel_allocate(device_t dev)
1929 {
1930 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
1931 struct ata_channel *ch = device_get_softc(dev);
1932
1933 /* setup the usual register normal pci style */
1934 if (ata_pci_allocate(dev))
1935 return ENXIO;
1936
1937 /* if r_res2 is valid it points to SATA interface registers */
1938 if (ctlr->r_res2) {
1939 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2;
1940 ch->r_io[ATA_IDX_ADDR].offset = 0x00;
1941 ch->r_io[ATA_IDX_DATA].res = ctlr->r_res2;
1942 ch->r_io[ATA_IDX_DATA].offset = 0x04;
1943 }
1944
1945 ch->flags |= ATA_ALWAYS_DMASTAT;
1946 return 0;
1947 }
1948
1949 static void
1950 ata_intel_reset(device_t dev)
1951 {
1952 device_t parent = device_get_parent(dev);
1953 struct ata_pci_controller *ctlr = device_get_softc(parent);
1954 struct ata_channel *ch = device_get_softc(dev);
1955 int mask, timeout;
1956
1957 /* ICH6 & ICH7 in compat mode has 4 SATA ports as master/slave on 2 ch's */
1958 if (ctlr->chip->cfg1) {
1959 mask = (0x0005 << ch->unit);
1960 }
1961 else {
1962 /* ICH5 in compat mode has SATA ports as master/slave on 1 channel */
1963 if (pci_read_config(parent, 0x90, 1) & 0x04)
1964 mask = 0x0003;
1965 else {
1966 mask = (0x0001 << ch->unit);
1967 /* XXX SOS should be in intel_allocate if we grow it */
1968 ch->flags |= ATA_NO_SLAVE;
1969 }
1970 }
1971 pci_write_config(parent, 0x92, pci_read_config(parent, 0x92, 2) & ~mask, 2);
1972 DELAY(10);
1973 pci_write_config(parent, 0x92, pci_read_config(parent, 0x92, 2) | mask, 2);
1974
1975 /* wait up to 1 sec for "connect well" */
1976 for (timeout = 0; timeout < 100 ; timeout++) {
1977 if (((pci_read_config(parent, 0x92, 2) & (mask << 4)) == (mask << 4)) &&
1978 (ATA_IDX_INB(ch, ATA_STATUS) != 0xff))
1979 break;
1980 ata_udelay(10000);
1981 }
1982 ata_generic_reset(dev);
1983 }
1984
1985 static void
1986 ata_intel_old_setmode(device_t dev, int mode)
1987 {
1988 /* NOT YET */
1989 }
1990
1991 static void
1992 ata_intel_new_setmode(device_t dev, int mode)
1993 {
1994 device_t gparent = GRANDPARENT(dev);
1995 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1996 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1997 struct ata_device *atadev = device_get_softc(dev);
1998 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1999 u_int32_t reg40 = pci_read_config(gparent, 0x40, 4);
2000 u_int8_t reg44 = pci_read_config(gparent, 0x44, 1);
2001 u_int8_t reg48 = pci_read_config(gparent, 0x48, 1);
2002 u_int16_t reg4a = pci_read_config(gparent, 0x4a, 2);
2003 u_int16_t reg54 = pci_read_config(gparent, 0x54, 2);
2004 u_int32_t mask40 = 0, new40 = 0;
2005 u_int8_t mask44 = 0, new44 = 0;
2006 int error;
2007 u_int8_t timings[] = { 0x00, 0x00, 0x10, 0x21, 0x23, 0x10, 0x21, 0x23,
2008 0x23, 0x23, 0x23, 0x23, 0x23, 0x23, 0x23 };
2009 /* PIO0 PIO1 PIO2 PIO3 PIO4 WDMA0 WDMA1 WDMA2 */
2010 /* UDMA0 UDMA1 UDMA2 UDMA3 UDMA4 UDMA5 UDMA6 */
2011
2012 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
2013
2014 if ( mode > ATA_UDMA2 && !(reg54 & (0x10 << devno))) {
2015 ata_print_cable(dev, "controller");
2016 mode = ATA_UDMA2;
2017 }
2018
2019 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
2020
2021 if (bootverbose)
2022 device_printf(dev, "%ssetting %s on %s chip\n",
2023 (error) ? "FAILURE " : "",
2024 ata_mode2str(mode), ctlr->chip->text);
2025 if (error)
2026 return;
2027
2028 /*
2029 * reg48: 1 bit per (primary drive 0, primary drive 1, secondary
2030 * drive 0, secondary drive 1)
2031 *
2032 * 0 Disable Ultra DMA mode
2033 * 1 Enable Ultra DMA mode
2034 *
2035 * reg4a: 4 bits per (primary drive 0, primary drive 1, secondary
2036 * drive 0, secondary drive 1).
2037 * 0000 UDMA mode 0
2038 * 0001 UDMA mode 1, 3, 5
2039 * 0010 UDMA mode 2, 4, reserved
2040 * 0011 reserved
2041 * (top two bits for each drive reserved)
2042 */
2043 #if 0
2044 device_printf(dev,
2045 "regs before 40=%08x 44=%02x 48=%02x 4a=%04x 54=%04x\n",
2046 reg40, reg44, reg48 ,reg4a, reg54);
2047 #endif
2048 reg48 &= ~(0x0001 << devno);
2049 reg4a &= ~(0x3 << (devno << 2));
2050 if (mode >= ATA_UDMA0) {
2051 reg48 |= 0x0001 << devno;
2052 if (mode > ATA_UDMA0)
2053 reg4a |= (1 + !(mode & 0x01)) << (devno << 2);
2054 }
2055 pci_write_config(gparent, 0x48, reg48, 2);
2056 pci_write_config(gparent, 0x4a, reg4a, 2);
2057
2058 /*
2059 * reg54:
2060 *
2061 * 32:20 reserved
2062 * 19:18 Secondary ATA signal mode
2063 * 17:16 Primary ATA signal mode
2064 * 00 = Normal (enabled)
2065 * 01 = Tri-state (disabled)
2066 * 10 = Drive Low (disabled)
2067 * 11 = Reserved
2068 *
2069 * 15 Secondary drive 1 - Base Clock
2070 * 14 Secondary drive 0 - Base Clock
2071 * 13 Primary drive 1 - Base Clock
2072 * 12 Primary drive 0 - Base Clock
2073 * 0 = Select 33 MHz clock
2074 * 1 = Select 100 Mhz clock
2075 *
2076 * 11 Reserved
2077 * 10 Vendor specific (set by BIOS?)
2078 * 09:08 Reserved
2079 *
2080 * 07 Secondary drive 1 - Cable Type
2081 * 06 Secondary drive 0 - Cable Type
2082 * 05 Primary drive 1 - Cable Type
2083 * 04 Primary drive 0 - Cable Type
2084 * 0 = 40 Conductor
2085 * 1 = 80 Conductor (or high speed cable)
2086 *
2087 * 03 Secondary drive 1 - Select 33/66 clock
2088 * 02 Secondary drive 0 - Select 33/66 clock
2089 * 01 Primary drive 1 - Select 33/66 clock
2090 * 00 Primary drive 0 - Select 33/66 clock
2091 * 0 = Select 33 MHz
2092 * 1 = Select 66 MHz
2093 *
2094 * It is unclear what this should be set to when operating
2095 * in 100MHz mode.
2096 *
2097 * NOTE: UDMA2 = 33 MHz
2098 * UDMA3 = 40 MHz (?) - unsupported
2099 * UDMA4 = 66 MHz
2100 * UDMA5 = 100 MHz
2101 * UDMA6 = 133 Mhz
2102 */
2103 reg54 |= 0x0400; /* set vendor specific bit */
2104 reg54 &= ~((0x1 << devno) | (0x1000 << devno));
2105
2106 if (mode >= ATA_UDMA5)
2107 reg54 |= (0x1000 << devno);
2108 else if (mode >= ATA_UDMA3) /* XXX should this be ATA_UDMA3 or 4? */
2109 reg54 |= (0x1 << devno);
2110
2111 pci_write_config(gparent, 0x54, reg54, 2);
2112
2113 /*
2114 * Reg40 (32 bits... well, actually two 16 bit registers)
2115 *
2116 * Primary channel bits 15:00, Secondary channel bits 31:00. Note
2117 * that slave timings are handled in register 44.
2118 *
2119 * 15 ATA Decode Enable (R/W) 1 = enable decoding of I/O ranges
2120 *
2121 * 14 Slave ATA Timing Register Enable (R/W)
2122 *
2123 * 13:12 IORDY Sample Mode
2124 * 00 PIO-0
2125 * 01 PIO-2, SW-2
2126 * 10 PIO-3, PIO-4, MW-1, MW-2
2127 * 11 Reserved
2128 *
2129 * 11:10 Reserved
2130 *
2131 * 09:08 Recovery Mode
2132 * 00 PIO-0, PIO-2, SW-2
2133 * 01 PIO-3, MW-1
2134 * 10 Reserved
2135 * 11 PIO-4, MW-2
2136 *
2137 * 07:04 Secondary Device Control Bits
2138 * 03:00 Primary Device Control Bits
2139 *
2140 * bit 3 DMA Timing Enable
2141 *
2142 * bit 2 Indicate Presence of ATA(1) or ATAPI(0) device
2143 *
2144 * bit 1 Enable IORDY sample point capability for PIO
2145 * xfers. Always enabled for PIO4 and PIO3, enabled
2146 * for PIO2 if indicated by the device, and otherwise
2147 * probably should be 0.
2148 *
2149 * bit 0 Fast Drive Timing Enable. Enables faster then PIO-0
2150 * timing modes.
2151 */
2152
2153 /*
2154 * Modify reg40 according to the table
2155 */
2156 if (atadev->unit == ATA_MASTER) {
2157 mask40 = 0x3300;
2158 new40 = timings[ata_mode2idx(mode)] << 8;
2159 }
2160 else {
2161 mask44 = 0x0f;
2162 new44 = ((timings[ata_mode2idx(mode)] & 0x30) >> 2) |
2163 (timings[ata_mode2idx(mode)] & 0x03);
2164 }
2165
2166 /*
2167 * Slave ATA timing register enable
2168 */
2169 mask40 |= 0x4000;
2170 new40 |= 0x4000;
2171
2172 /*
2173 * Device control bits 3:0 for master, 7:4 for slave.
2174 *
2175 * bit3 DMA Timing enable.
2176 * bit2 Indicate presence of ATA(1) or ATAPI(0) device, set accordingly
2177 * bit1 Enable IORDY sample point capability for PIO xfers. Always
2178 * enabled for PIO4 and PIO3, enabled for PIO2 if indicated by
2179 * the device, and otherwise should be 0.
2180 * bit0 Fast Drive Timing Enable. Enable faster then PIO-0 timing modes.
2181 *
2182 * Set to: 0 x 1 1
2183 */
2184
2185 if (atadev->unit == ATA_MASTER) {
2186 mask40 |= 0x0F;
2187 new40 |= 0x03;
2188 if (!ata_atapi(dev))
2189 new40 |= 0x04;
2190 } else {
2191 mask40 |= 0xF0;
2192 new40 |= 0x30;
2193 if (!ata_atapi(dev))
2194 new40 |= 0x40;
2195 }
2196 /*
2197 reg40 &= ~0x00ff00ff;
2198 reg40 |= 0x40774077;
2199 */
2200
2201 /*
2202 * Primary or Secondary controller
2203 */
2204 if (ch->unit) {
2205 mask40 <<= 16;
2206 new40 <<= 16;
2207 mask44 <<= 4;
2208 new44 <<= 4;
2209 }
2210 pci_write_config(gparent, 0x40, (reg40 & ~mask40) | new40, 4);
2211 pci_write_config(gparent, 0x44, (reg44 & ~mask44) | new44, 1);
2212
2213 #if 0
2214 reg40 = pci_read_config(gparent, 0x40, 4);
2215 reg44 = pci_read_config(gparent, 0x44, 1);
2216 reg48 = pci_read_config(gparent, 0x48, 1);
2217 reg4a = pci_read_config(gparent, 0x4a, 2);
2218 reg54 = pci_read_config(gparent, 0x54, 2);
2219 device_printf(dev,
2220 "regs after 40=%08x 44=%02x 48=%02x 4a=%04x 54=%04x\n",
2221 reg40, reg44, reg48 ,reg4a, reg54);
2222 #endif
2223
2224 atadev->mode = mode;
2225 }
2226
2227 static void
2228 ata_intel_sata_setmode(device_t dev, int mode)
2229 {
2230 struct ata_device *atadev = device_get_softc(dev);
2231
2232 if (atadev->param.satacapabilities != 0x0000 &&
2233 atadev->param.satacapabilities != 0xffff) {
2234
2235 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
2236 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
2237
2238 /* on some drives we need to set the transfer mode */
2239 ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0,
2240 ata_limit_mode(dev, mode, ATA_UDMA6));
2241
2242 /* set ATA_SSTATUS register offset */
2243 ATA_IDX_OUTL(ch, ATA_IDX_ADDR, devno * 0x100);
2244
2245 /* query SATA STATUS for the speed */
2246 if ((ATA_IDX_INL(ch, ATA_IDX_DATA) & ATA_SS_CONWELL_MASK) ==
2247 ATA_SS_CONWELL_GEN2)
2248 atadev->mode = ATA_SA300;
2249 else
2250 atadev->mode = ATA_SA150;
2251 }
2252 else {
2253 mode = ata_limit_mode(dev, mode, ATA_UDMA5);
2254 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
2255 atadev->mode = mode;
2256 }
2257 }
2258
2259 static int
2260 ata_intel_31244_allocate(device_t dev)
2261 {
2262 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2263 struct ata_channel *ch = device_get_softc(dev);
2264 int i;
2265 int ch_offset;
2266
2267 ch_offset = 0x200 + ch->unit * 0x200;
2268
2269 for (i = ATA_DATA; i < ATA_MAX_RES; i++)
2270 ch->r_io[i].res = ctlr->r_res2;
2271
2272 /* setup ATA registers */
2273 ch->r_io[ATA_DATA].offset = ch_offset + 0x00;
2274 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x06;
2275 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08;
2276 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c;
2277 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10;
2278 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14;
2279 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18;
2280 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1d;
2281 ch->r_io[ATA_ERROR].offset = ch_offset + 0x04;
2282 ch->r_io[ATA_STATUS].offset = ch_offset + 0x1c;
2283 ch->r_io[ATA_ALTSTAT].offset = ch_offset + 0x28;
2284 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x29;
2285
2286 /* setup DMA registers */
2287 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x100;
2288 ch->r_io[ATA_SERROR].offset = ch_offset + 0x104;
2289 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x108;
2290
2291 /* setup SATA registers */
2292 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x70;
2293 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x72;
2294 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x74;
2295
2296 ch->flags |= ATA_NO_SLAVE;
2297 ata_pci_hw(dev);
2298 ch->hw.status = ata_intel_31244_status;
2299 ch->hw.command = ata_intel_31244_command;
2300
2301 /* enable PHY state change interrupt */
2302 ATA_OUTL(ctlr->r_res2, 0x4,
2303 ATA_INL(ctlr->r_res2, 0x04) | (0x01 << (ch->unit << 3)));
2304 return 0;
2305 }
2306
2307 static int
2308 ata_intel_31244_status(device_t dev)
2309 {
2310 /* do we have any PHY events ? */
2311 ata_sata_phy_check_events(dev);
2312
2313 /* any drive action to take care of ? */
2314 return ata_pci_status(dev);
2315 }
2316
2317 static int
2318 ata_intel_31244_command(struct ata_request *request)
2319 {
2320 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
2321 struct ata_device *atadev = device_get_softc(request->dev);
2322 u_int64_t lba;
2323
2324 if (!(atadev->flags & ATA_D_48BIT_ACTIVE))
2325 return (ata_generic_command(request));
2326
2327 lba = request->u.ata.lba;
2328 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | atadev->unit);
2329 /* enable interrupt */
2330 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT);
2331 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature);
2332 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count);
2333 ATA_IDX_OUTW(ch, ATA_SECTOR, ((lba >> 16) & 0xff00) | (lba & 0x00ff));
2334 ATA_IDX_OUTW(ch, ATA_CYL_LSB, ((lba >> 24) & 0xff00) |
2335 ((lba >> 8) & 0x00ff));
2336 ATA_IDX_OUTW(ch, ATA_CYL_MSB, ((lba >> 32) & 0xff00) |
2337 ((lba >> 16) & 0x00ff));
2338
2339 /* issue command to controller */
2340 ATA_IDX_OUTB(ch, ATA_COMMAND, request->u.ata.command);
2341
2342 return 0;
2343 }
2344
2345 static void
2346 ata_intel_31244_reset(device_t dev)
2347 {
2348 if (ata_sata_phy_reset(dev))
2349 ata_generic_reset(dev);
2350 }
2351
2352
2353 /*
2354 * Integrated Technology Express Inc. (ITE) chipset support functions
2355 */
2356 int
2357 ata_ite_ident(device_t dev)
2358 {
2359 struct ata_pci_controller *ctlr = device_get_softc(dev);
2360 struct ata_chip_id *idx;
2361 static struct ata_chip_id ids[] =
2362 {{ ATA_IT8212F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8212F" },
2363 { ATA_IT8211F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8211F" },
2364 { 0, 0, 0, 0, 0, 0}};
2365 char buffer[64];
2366
2367 if (!(idx = ata_match_chip(dev, ids)))
2368 return ENXIO;
2369
2370 ksprintf(buffer, "ITE %s %s controller",
2371 idx->text, ata_mode2str(idx->max_dma));
2372 device_set_desc_copy(dev, buffer);
2373 ctlr->chip = idx;
2374 ctlr->chipinit = ata_ite_chipinit;
2375 return 0;
2376 }
2377
2378 static int
2379 ata_ite_chipinit(device_t dev)
2380 {
2381 struct ata_pci_controller *ctlr = device_get_softc(dev);
2382
2383 if (ata_setup_interrupt(dev))
2384 return ENXIO;
2385
2386 ctlr->setmode = ata_ite_setmode;
2387
2388 /* set PCI mode and 66Mhz reference clock */
2389 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) & ~0x83, 1);
2390
2391 /* set default active & recover timings */
2392 pci_write_config(dev, 0x54, 0x31, 1);
2393 pci_write_config(dev, 0x56, 0x31, 1);
2394 return 0;
2395 }
2396
2397 static void
2398 ata_ite_setmode(device_t dev, int mode)
2399 {
2400 device_t gparent = GRANDPARENT(dev);
2401 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
2402 struct ata_device *atadev = device_get_softc(dev);
2403 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
2404 int error;
2405
2406 /* correct the mode for what the HW supports */
2407 mode = ata_limit_mode(dev, mode, ATA_UDMA6);
2408
2409 /* check the CBLID bits for 80 conductor cable detection */
2410 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x40, 2) &
2411 (ch->unit ? (1<<3) : (1<<2)))) {
2412 ata_print_cable(dev, "controller");
2413 mode = ATA_UDMA2;
2414 }
2415
2416 /* set the wanted mode on the device */
2417 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
2418
2419 if (bootverbose)
2420 device_printf(dev, "%s setting %s on ITE8212F chip\n",
2421 (error) ? "failed" : "success", ata_mode2str(mode));
2422
2423 /* if the device accepted the mode change, setup the HW accordingly */
2424 if (!error) {
2425 if (mode >= ATA_UDMA0) {
2426 u_int8_t udmatiming[] =
2427 { 0x44, 0x42, 0x31, 0x21, 0x11, 0xa2, 0x91 };
2428
2429 /* enable UDMA mode */
2430 pci_write_config(gparent, 0x50,
2431 pci_read_config(gparent, 0x50, 1) &
2432 ~(1 << (devno + 3)), 1);
2433
2434 /* set UDMA timing */
2435 pci_write_config(gparent,
2436 0x56 + (ch->unit << 2) + ATA_DEV(atadev->unit),
2437 udmatiming[mode & ATA_MODE_MASK], 1);
2438 }
2439 else {
2440 u_int8_t chtiming[] =
2441 { 0xaa, 0xa3, 0xa1, 0x33, 0x31, 0x88, 0x32, 0x31 };
2442
2443 /* disable UDMA mode */
2444 pci_write_config(gparent, 0x50,
2445 pci_read_config(gparent, 0x50, 1) |
2446 (1 << (devno + 3)), 1);
2447
2448 /* set active and recover timing (shared between master & slave) */
2449 if (pci_read_config(gparent, 0x54 + (ch->unit << 2), 1) <
2450 chtiming[ata_mode2idx(mode)])
2451 pci_write_config(gparent, 0x54 + (ch->unit << 2),
2452 chtiming[ata_mode2idx(mode)], 1);
2453 }
2454 atadev->mode = mode;
2455 }
2456 }
2457
2458
2459 /*
2460 * JMicron chipset support functions
2461 */
2462 int
2463 ata_jmicron_ident(device_t dev)
2464 {
2465 struct ata_pci_controller *ctlr = device_get_softc(dev);
2466 struct ata_chip_id *idx;
2467 static struct ata_chip_id ids[] =
2468 {{ ATA_JMB360, 0, 1, 0, ATA_SA300, "JMB360" },
2469 { ATA_JMB361, 0, 1, 1, ATA_SA300, "JMB361" },
2470 { ATA_JMB363, 0, 2, 1, ATA_SA300, "JMB363" },
2471 { ATA_JMB365, 0, 1, 2, ATA_SA300, "JMB365" },
2472 { ATA_JMB366, 0, 2, 2, ATA_SA300, "JMB366" },
2473 { ATA_JMB368, 0, 0, 1, ATA_UDMA6, "JMB368" },
2474 { 0, 0, 0, 0, 0, 0}};
2475 char buffer[64];
2476
2477 if (!(idx = ata_match_chip(dev, ids)))
2478 return ENXIO;
2479
2480 if ((pci_read_config(dev, 0xdf, 1) & 0x40) &&
2481 (pci_get_function(dev) == (pci_read_config(dev, 0x40, 1) & 0x02 >> 1)))
2482 ksnprintf(buffer, sizeof(buffer), "JMicron %s %s controller",
2483 idx->text, ata_mode2str(ATA_UDMA6));
2484 else
2485 ksnprintf(buffer, sizeof(buffer), "JMicron %s %s controller",
2486 idx->text, ata_mode2str(idx->max_dma));
2487 device_set_desc_copy(dev, buffer);
2488 ctlr->chip = idx;
2489 ctlr->chipinit = ata_jmicron_chipinit;
2490 return 0;
2491 }
2492
2493 static int
2494 ata_jmicron_chipinit(device_t dev)
2495 {
2496 struct ata_pci_controller *ctlr = device_get_softc(dev);
2497 int error;
2498
2499 if (ata_setup_interrupt(dev))
2500 return ENXIO;
2501
2502 /* do we have multiple PCI functions ? */
2503 if (pci_read_config(dev, 0xdf, 1) & 0x40) {
2504 /* are we on the AHCI part ? */
2505 if (ata_ahci_chipinit(dev) != ENXIO)
2506 return 0;
2507
2508 /* otherwise we are on the PATA part */
2509 ctlr->allocate = ata_pci_allocate;
2510 ctlr->reset = ata_generic_reset;
2511 ctlr->dmainit = ata_pci_dmainit;
2512 ctlr->setmode = ata_jmicron_setmode;
2513 ctlr->channels = ctlr->chip->cfg2;
2514 }
2515 else {
2516 /* set controller configuration to a combined setup we support */
2517 pci_write_config(dev, 0x40, 0x80c0a131, 4);
2518 pci_write_config(dev, 0x80, 0x01200000, 4);
2519
2520 if ((error = ata_ahci_chipinit(dev)))
2521 return error;
2522
2523 ctlr->allocate = ata_jmicron_allocate;
2524 ctlr->reset = ata_jmicron_reset;
2525 ctlr->dmainit = ata_jmicron_dmainit;
2526 ctlr->setmode = ata_jmicron_setmode;
2527
2528 /* set the number of HW channels */
2529 ctlr->channels = ctlr->chip->cfg1 + ctlr->chip->cfg2;
2530 }
2531 return 0;
2532 }
2533
2534 static int
2535 ata_jmicron_allocate(device_t dev)
2536 {
2537 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2538 struct ata_channel *ch = device_get_softc(dev);
2539 int error;
2540
2541 if (ch->unit >= ctlr->chip->cfg1) {
2542 ch->unit -= ctlr->chip->cfg1;
2543 error = ata_pci_allocate(dev);
2544 ch->unit += ctlr->chip->cfg1;
2545 }
2546 else
2547 error = ata_ahci_allocate(dev);
2548 return error;
2549 }
2550
2551 static void
2552 ata_jmicron_reset(device_t dev)
2553 {
2554 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2555 struct ata_channel *ch = device_get_softc(dev);
2556
2557 if (ch->unit >= ctlr->chip->cfg1)
2558 ata_generic_reset(dev);
2559 else
2560 ata_ahci_reset(dev);
2561 }
2562
2563 static void
2564 ata_jmicron_dmainit(device_t dev)
2565 {
2566 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2567 struct ata_channel *ch = device_get_softc(dev);
2568
2569 if (ch->unit >= ctlr->chip->cfg1)
2570 ata_pci_dmainit(dev);
2571 else
2572 ata_ahci_dmainit(dev);
2573 }
2574
2575 static void
2576 ata_jmicron_setmode(device_t dev, int mode)
2577 {
2578 struct ata_pci_controller *ctlr = device_get_softc(GRANDPARENT(dev));
2579 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
2580
2581 if (pci_read_config(dev, 0xdf, 1) & 0x40 || ch->unit >= ctlr->chip->cfg1) {
2582 struct ata_device *atadev = device_get_softc(dev);
2583
2584 /* check for 80pin cable present */
2585 if (pci_read_config(dev, 0x40, 1) & 0x08)
2586 mode = ata_limit_mode(dev, mode, ATA_UDMA2);
2587 else
2588 mode = ata_limit_mode(dev, mode, ATA_UDMA6);
2589
2590 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
2591 atadev->mode = mode;
2592 }
2593 else
2594 ata_sata_setmode(dev, mode);
2595 }
2596
2597
2598 /*
2599 * Marvell chipset support functions
2600 */
2601 #define ATA_MV_HOST_BASE(ch) \
2602 ((ch->unit & 3) * 0x0100) + (ch->unit > 3 ? 0x30000 : 0x20000)
2603 #define ATA_MV_EDMA_BASE(ch) \
2604 ((ch->unit & 3) * 0x2000) + (ch->unit > 3 ? 0x30000 : 0x20000)
2605
2606 struct ata_marvell_response {
2607 u_int16_t tag;
2608 u_int8_t edma_status;
2609 u_int8_t dev_status;
2610 u_int32_t timestamp;
2611 };
2612
2613 struct ata_marvell_dma_prdentry {
2614 u_int32_t addrlo;
2615 u_int32_t count;
2616 u_int32_t addrhi;
2617 u_int32_t reserved;
2618 };
2619
2620 int
2621 ata_marvell_ident(device_t dev)
2622 {
2623 struct ata_pci_controller *ctlr = device_get_softc(dev);
2624 struct ata_chip_id *idx;
2625 static struct ata_chip_id ids[] =
2626 {{ ATA_M88SX5040, 0, 4, MV50XX, ATA_SA150, "88SX5040" },
2627 { ATA_M88SX5041, 0, 4, MV50XX, ATA_SA150, "88SX5041" },
2628 { ATA_M88SX5080, 0, 8, MV50XX, ATA_SA150, "88SX5080" },
2629 { ATA_M88SX5081, 0, 8, MV50XX, ATA_SA150, "88SX5081" },
2630 { ATA_M88SX6041, 0, 4, MV60XX, ATA_SA300, "88SX6041" },
2631 { ATA_M88SX6081, 0, 8, MV60XX, ATA_SA300, "88SX6081" },
2632 { ATA_M88SX6101, 0, 1, MV61XX, ATA_UDMA6, "88SX6101" },
2633 { ATA_M88SX6145, 0, 2, MV61XX, ATA_UDMA6, "88SX6145" },
2634 { 0, 0, 0, 0, 0, 0}};
2635 char buffer[64];
2636
2637 if (!(idx = ata_match_chip(dev, ids)))
2638 return ENXIO;
2639
2640 ksprintf(buffer, "Marvell %s %s controller",
2641 idx->text, ata_mode2str(idx->max_dma));
2642 device_set_desc_copy(dev, buffer);
2643 ctlr->chip = idx;
2644 switch (ctlr->chip->cfg2) {
2645 case MV50XX:
2646 case MV60XX:
2647 ctlr->chipinit = ata_marvell_edma_chipinit;
2648 break;
2649 case MV61XX:
2650 ctlr->chipinit = ata_marvell_pata_chipinit;
2651 break;
2652 }
2653 return 0;
2654 }
2655
2656 static int
2657 ata_marvell_pata_chipinit(device_t dev)
2658 {
2659 struct ata_pci_controller *ctlr = device_get_softc(dev);
2660
2661 if (ata_setup_interrupt(dev))
2662 return ENXIO;
2663
2664 ctlr->allocate = ata_marvell_pata_allocate;
2665 ctlr->setmode = ata_marvell_pata_setmode;
2666 ctlr->channels = ctlr->chip->cfg1;
2667 return 0;
2668 }
2669
2670 static int
2671 ata_marvell_pata_allocate(device_t dev)
2672 {
2673 struct ata_channel *ch = device_get_softc(dev);
2674
2675 /* setup the usual register normal pci style */
2676 if (ata_pci_allocate(dev))
2677 return ENXIO;
2678
2679 /* dont use 32 bit PIO transfers */
2680 ch->flags |= ATA_USE_16BIT;
2681
2682 return 0;
2683 }
2684
2685 static void
2686 ata_marvell_pata_setmode(device_t dev, int mode)
2687 {
2688 device_t gparent = GRANDPARENT(dev);
2689 struct ata_pci_controller *ctlr = device_get_softc(gparent);
2690 struct ata_device *atadev = device_get_softc(dev);
2691
2692 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
2693 mode = ata_check_80pin(dev, mode);
2694 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
2695 atadev->mode = mode;
2696 }
2697
2698 static int
2699 ata_marvell_edma_chipinit(device_t dev)
2700 {
2701 struct ata_pci_controller *ctlr = device_get_softc(dev);
2702
2703 if (ata_setup_interrupt(dev))
2704 return ENXIO;
2705
2706 ctlr->r_type1 = SYS_RES_MEMORY;
2707 ctlr->r_rid1 = PCIR_BAR(0);
2708 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1,
2709 &ctlr->r_rid1, RF_ACTIVE)))
2710 return ENXIO;
2711
2712 /* mask all host controller interrupts */
2713 ATA_OUTL(ctlr->r_res1, 0x01d64, 0x00000000);
2714
2715 /* mask all PCI interrupts */
2716 ATA_OUTL(ctlr->r_res1, 0x01d5c, 0x00000000);
2717
2718 ctlr->allocate = ata_marvell_edma_allocate;
2719 ctlr->reset = ata_marvell_edma_reset;
2720 ctlr->dmainit = ata_marvell_edma_dmainit;
2721 ctlr->setmode = ata_sata_setmode;
2722 ctlr->channels = ctlr->chip->cfg1;
2723
2724 /* clear host controller interrupts */
2725 ATA_OUTL(ctlr->r_res1, 0x20014, 0x00000000);
2726 if (ctlr->chip->cfg1 > 4)
2727 ATA_OUTL(ctlr->r_res1, 0x30014, 0x00000000);
2728
2729 /* clear PCI interrupts */
2730 ATA_OUTL(ctlr->r_res1, 0x01d58, 0x00000000);
2731
2732 /* unmask PCI interrupts we want */
2733 ATA_OUTL(ctlr->r_res1, 0x01d5c, 0x007fffff);
2734
2735 /* unmask host controller interrupts we want */
2736 ATA_OUTL(ctlr->r_res1, 0x01d64, 0x000000ff/*HC0*/ | 0x0001fe00/*HC1*/ |
2737 /*(1<<19) | (1<<20) | (1<<21) |*/(1<<22) | (1<<24) | (0x7f << 25));
2738
2739 /* enable PCI interrupt */
2740 pci_write_config(dev, PCIR_COMMAND,
2741 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
2742 return 0;
2743 }
2744
2745 static int
2746 ata_marvell_edma_allocate(device_t dev)
2747 {
2748 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2749 struct ata_channel *ch = device_get_softc(dev);
2750 u_int64_t work = ch->dma->work_bus;
2751 int i;
2752
2753 /* clear work area */
2754 bzero(ch->dma->work, 1024+256);
2755
2756 /* set legacy ATA resources */
2757 for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
2758 ch->r_io[i].res = ctlr->r_res1;
2759 ch->r_io[i].offset = 0x02100 + (i << 2) + ATA_MV_EDMA_BASE(ch);
2760 }
2761 ch->r_io[ATA_CONTROL].res = ctlr->r_res1;
2762 ch->r_io[ATA_CONTROL].offset = 0x02120 + ATA_MV_EDMA_BASE(ch);
2763 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res1;
2764 ata_default_registers(dev);
2765
2766 /* set SATA resources */
2767 switch (ctlr->chip->cfg2) {
2768 case MV50XX:
2769 ch->r_io[ATA_SSTATUS].res = ctlr->r_res1;
2770 ch->r_io[ATA_SSTATUS].offset = 0x00100 + ATA_MV_HOST_BASE(ch);
2771 ch->r_io[ATA_SERROR].res = ctlr->r_res1;
2772 ch->r_io[ATA_SERROR].offset = 0x00104 + ATA_MV_HOST_BASE(ch);
2773 ch->r_io[ATA_SCONTROL].res = ctlr->r_res1;
2774 ch->r_io[ATA_SCONTROL].offset = 0x00108 + ATA_MV_HOST_BASE(ch);
2775 break;
2776 case MV60XX:
2777 ch->r_io[ATA_SSTATUS].res = ctlr->r_res1;
2778 ch->r_io[ATA_SSTATUS].offset = 0x02300 + ATA_MV_EDMA_BASE(ch);
2779 ch->r_io[ATA_SERROR].res = ctlr->r_res1;
2780 ch->r_io[ATA_SERROR].offset = 0x02304 + ATA_MV_EDMA_BASE(ch);
2781 ch->r_io[ATA_SCONTROL].res = ctlr->r_res1;
2782 ch->r_io[ATA_SCONTROL].offset = 0x02308 + ATA_MV_EDMA_BASE(ch);
2783 ch->r_io[ATA_SACTIVE].res = ctlr->r_res1;
2784 ch->r_io[ATA_SACTIVE].offset = 0x02350 + ATA_MV_EDMA_BASE(ch);
2785 break;
2786 }
2787
2788 ch->flags |= ATA_NO_SLAVE;
2789 ch->flags |= ATA_USE_16BIT; /* XXX SOS needed ? */
2790 ata_generic_hw(dev);
2791 ch->hw.begin_transaction = ata_marvell_edma_begin_transaction;
2792 ch->hw.end_transaction = ata_marvell_edma_end_transaction;
2793 ch->hw.status = ata_marvell_edma_status;
2794
2795 /* disable the EDMA machinery */
2796 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002);
2797 DELAY(100000); /* SOS should poll for disabled */
2798
2799 /* set configuration to non-queued 128b read transfers stop on error */
2800 ATA_OUTL(ctlr->r_res1, 0x02000 + ATA_MV_EDMA_BASE(ch), (1<<11) | (1<<13));
2801
2802 /* request queue base high */
2803 ATA_OUTL(ctlr->r_res1, 0x02010 + ATA_MV_EDMA_BASE(ch), work >> 32);
2804
2805 /* request queue in ptr */
2806 ATA_OUTL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch), work & 0xffffffff);
2807
2808 /* request queue out ptr */
2809 ATA_OUTL(ctlr->r_res1, 0x02018 + ATA_MV_EDMA_BASE(ch), 0x0);
2810
2811 /* response queue base high */
2812 work += 1024;
2813 ATA_OUTL(ctlr->r_res1, 0x0201c + ATA_MV_EDMA_BASE(ch), work >> 32);
2814
2815 /* response queue in ptr */
2816 ATA_OUTL(ctlr->r_res1, 0x02020 + ATA_MV_EDMA_BASE(ch), 0x0);
2817
2818 /* response queue out ptr */
2819 ATA_OUTL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch), work & 0xffffffff);
2820
2821 /* clear SATA error register */
2822 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
2823
2824 /* clear any outstanding error interrupts */
2825 ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0);
2826
2827 /* unmask all error interrupts */
2828 ATA_OUTL(ctlr->r_res1, 0x0200c + ATA_MV_EDMA_BASE(ch), ~0x0);
2829
2830 /* enable EDMA machinery */
2831 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001);
2832 return 0;
2833 }
2834
2835 static int
2836 ata_marvell_edma_status(device_t dev)
2837 {
2838 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2839 struct ata_channel *ch = device_get_softc(dev);
2840 u_int32_t cause = ATA_INL(ctlr->r_res1, 0x01d60);
2841 int shift = (ch->unit << 1) + (ch->unit > 3);
2842
2843 if (cause & (1 << shift)) {
2844
2845 /* clear interrupt(s) */
2846 ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0);
2847
2848 /* do we have any PHY events ? */
2849 ata_sata_phy_check_events(dev);
2850 }
2851
2852 /* do we have any device action ? */
2853 return (cause & (2 << shift));
2854 }
2855
2856 /* must be called with ATA channel locked and state_mtx held */
2857 static int
2858 ata_marvell_edma_begin_transaction(struct ata_request *request)
2859 {
2860 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
2861 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
2862 u_int32_t req_in;
2863 u_int8_t *bytep;
2864 u_int16_t *wordp;
2865 u_int32_t *quadp;
2866 int i, tag = 0x07;
2867 int dummy, error, slot;
2868
2869 /* only DMA R/W goes through the EMDA machine */
2870 if (request->u.ata.command != ATA_READ_DMA &&
2871 request->u.ata.command != ATA_WRITE_DMA) {
2872
2873 /* disable the EDMA machinery */
2874 if (ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)
2875 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002);
2876 return ata_begin_transaction(request);
2877 }
2878
2879 /* check for 48 bit access and convert if needed */
2880 ata_modify_if_48bit(request);
2881
2882 /* check sanity, setup SG list and DMA engine */
2883 if ((error = ch->dma->load(ch->dev, request->data, request->bytecount,
2884 request->flags & ATA_R_READ, ch->dma->sg,
2885 &dummy))) {
2886 device_printf(request->dev, "setting up DMA failed\n");
2887 request->result = error;
2888 return ATA_OP_FINISHED;
2889 }
2890
2891 /* get next free request queue slot */
2892 req_in = ATA_INL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch));
2893 slot = (((req_in & ~0xfffffc00) >> 5) + 0) & 0x1f;
2894 bytep = (u_int8_t *)(ch->dma->work);
2895 bytep += (slot << 5);
2896 wordp = (u_int16_t *)bytep;
2897 quadp = (u_int32_t *)bytep;
2898
2899 /* fill in this request */
2900 quadp[0] = (long)ch->dma->sg_bus & 0xffffffff;
2901 quadp[1] = (u_int64_t)ch->dma->sg_bus >> 32;
2902 wordp[4] = (request->flags & ATA_R_READ ? 0x01 : 0x00) | (tag<<1);
2903
2904 i = 10;
2905 bytep[i++] = (request->u.ata.count >> 8) & 0xff;
2906 bytep[i++] = 0x10 | ATA_COUNT;
2907 bytep[i++] = request->u.ata.count & 0xff;
2908 bytep[i++] = 0x10 | ATA_COUNT;
2909
2910 bytep[i++] = (request->u.ata.lba >> 24) & 0xff;
2911 bytep[i++] = 0x10 | ATA_SECTOR;
2912 bytep[i++] = request->u.ata.lba & 0xff;
2913 bytep[i++] = 0x10 | ATA_SECTOR;
2914
2915 bytep[i++] = (request->u.ata.lba >> 32) & 0xff;
2916 bytep[i++] = 0x10 | ATA_CYL_LSB;
2917 bytep[i++] = (request->u.ata.lba >> 8) & 0xff;
2918 bytep[i++] = 0x10 | ATA_CYL_LSB;
2919
2920 bytep[i++] = (request->u.ata.lba >> 40) & 0xff;
2921 bytep[i++] = 0x10 | ATA_CYL_MSB;
2922 bytep[i++] = (request->u.ata.lba >> 16) & 0xff;
2923 bytep[i++] = 0x10 | ATA_CYL_MSB;
2924
2925 bytep[i++] = ATA_D_LBA | ATA_D_IBM | ((request->u.ata.lba >> 24) & 0xf);
2926 bytep[i++] = 0x10 | ATA_DRIVE;
2927
2928 bytep[i++] = request->u.ata.command;
2929 bytep[i++] = 0x90 | ATA_COMMAND;
2930
2931 /* enable EDMA machinery if needed */
2932 if (!(ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)) {
2933 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001);
2934 while (!(ATA_INL(ctlr->r_res1,
2935 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001))
2936 DELAY(10);
2937 }
2938
2939 /* tell EDMA it has a new request */
2940 slot = (((req_in & ~0xfffffc00) >> 5) + 1) & 0x1f;
2941 req_in &= 0xfffffc00;
2942 req_in += (slot << 5);
2943 ATA_OUTL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch), req_in);
2944
2945 return ATA_OP_CONTINUES;
2946 }
2947
2948 /* must be called with ATA channel locked and state_mtx held */
2949 static int
2950 ata_marvell_edma_end_transaction(struct ata_request *request)
2951 {
2952 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
2953 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
2954 int offset = (ch->unit > 3 ? 0x30014 : 0x20014);
2955 u_int32_t icr = ATA_INL(ctlr->r_res1, offset);
2956 int res;
2957
2958 /* EDMA interrupt */
2959 if ((icr & (0x0001 << (ch->unit & 3)))) {
2960 struct ata_marvell_response *response;
2961 u_int32_t rsp_in, rsp_out;
2962 int slot;
2963
2964 /* stop timeout */
2965 callout_stop(&request->callout);
2966
2967 /* get response ptr's */
2968 rsp_in = ATA_INL(ctlr->r_res1, 0x02020 + ATA_MV_EDMA_BASE(ch));
2969 rsp_out = ATA_INL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch));
2970 slot = (((rsp_in & ~0xffffff00) >> 3)) & 0x1f;
2971 rsp_out &= 0xffffff00;
2972 rsp_out += (slot << 3);
2973 response = (struct ata_marvell_response *)
2974 (ch->dma->work + 1024 + (slot << 3));
2975
2976 /* record status for this request */
2977 request->status = response->dev_status;
2978 request->error = 0;
2979
2980 /* ack response */
2981 ATA_OUTL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch), rsp_out);
2982
2983 /* update progress */
2984 if (!(request->status & ATA_S_ERROR) &&
2985 !(request->flags & ATA_R_TIMEOUT))
2986 request->donecount = request->bytecount;
2987
2988 /* unload SG list */
2989 ch->dma->unload(ch->dev);
2990
2991 res = ATA_OP_FINISHED;
2992 }
2993
2994 /* legacy ATA interrupt */
2995 else {
2996 res = ata_end_transaction(request);
2997 }
2998
2999 /* ack interrupt */
3000 ATA_OUTL(ctlr->r_res1, offset, ~(icr & (0x0101 << (ch->unit & 3))));
3001 return res;
3002 }
3003
3004 static void
3005 ata_marvell_edma_reset(device_t dev)
3006 {
3007 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3008 struct ata_channel *ch = device_get_softc(dev);
3009
3010 /* disable the EDMA machinery */
3011 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002);
3012 while ((ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001))
3013 DELAY(10);
3014
3015 /* clear SATA error register */
3016 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
3017
3018 /* clear any outstanding error interrupts */
3019 ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0);
3020
3021 /* unmask all error interrupts */
3022 ATA_OUTL(ctlr->r_res1, 0x0200c + ATA_MV_EDMA_BASE(ch), ~0x0);
3023
3024 /* enable channel and test for devices */
3025 if (ata_sata_phy_reset(dev))
3026 ata_generic_reset(dev);
3027
3028 /* enable EDMA machinery */
3029 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001);
3030 }
3031
3032 static void
3033 ata_marvell_edma_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs,
3034 int error)
3035 {
3036 struct ata_dmasetprd_args *args = xsc;
3037 struct ata_marvell_dma_prdentry *prd = args->dmatab;
3038 int i;
3039
3040 if ((args->error = error))
3041 return;
3042
3043 for (i = 0; i < nsegs; i++) {
3044 prd[i].addrlo = htole32(segs[i].ds_addr);
3045 prd[i].count = htole32(segs[i].ds_len);
3046 prd[i].addrhi = htole32((u_int64_t)segs[i].ds_addr >> 32);
3047 }
3048 prd[i - 1].count |= htole32(ATA_DMA_EOT);
3049 }
3050
3051 static void
3052 ata_marvell_edma_dmainit(device_t dev)
3053 {
3054 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3055 struct ata_channel *ch = device_get_softc(dev);
3056
3057 ata_dmainit(dev);
3058 if (ch->dma) {
3059 /* note start and stop are not used here */
3060 ch->dma->setprd = ata_marvell_edma_dmasetprd;
3061
3062 if (ATA_INL(ctlr->r_res1, 0x00d00) & 0x00000004)
3063 ch->dma->max_address = BUS_SPACE_MAXADDR;
3064
3065 /* chip does not reliably do 64K DMA transfers */
3066 ch->dma->max_iosize = 126 * DEV_BSIZE;
3067 }
3068 }
3069
3070
3071 /*
3072 * National chipset support functions
3073 */
3074 int
3075 ata_national_ident(device_t dev)
3076 {
3077 struct ata_pci_controller *ctlr = device_get_softc(dev);
3078
3079 /* this chip is a clone of the Cyrix chip, bugs and all */
3080 if (pci_get_devid(dev) == ATA_SC1100) {
3081 device_set_desc(dev, "National Geode SC1100 ATA33 controller");
3082 ctlr->chipinit = ata_national_chipinit;
3083 return 0;
3084 }
3085 return ENXIO;
3086 }
3087
3088 static int
3089 ata_national_chipinit(device_t dev)
3090 {
3091 struct ata_pci_controller *ctlr = device_get_softc(dev);
3092
3093 if (ata_setup_interrupt(dev))
3094 return ENXIO;
3095
3096 ctlr->setmode = ata_national_setmode;
3097 return 0;
3098 }
3099
3100 static void
3101 ata_national_setmode(device_t dev, int mode)
3102 {
3103 device_t gparent = GRANDPARENT(dev);
3104 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
3105 struct ata_device *atadev = device_get_softc(dev);
3106 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
3107 u_int32_t piotiming[] =
3108 { 0x9172d132, 0x21717121, 0x00803020, 0x20102010, 0x00100010,
3109 0x00803020, 0x20102010, 0x00100010,
3110 0x00100010, 0x00100010, 0x00100010 };
3111 u_int32_t dmatiming[] = { 0x80077771, 0x80012121, 0x80002020 };
3112 u_int32_t udmatiming[] = { 0x80921250, 0x80911140, 0x80911030 };
3113 int error;
3114
3115 ch->dma->alignment = 16;
3116 ch->dma->max_iosize = 126 * DEV_BSIZE;
3117
3118 mode = ata_limit_mode(dev, mode, ATA_UDMA2);
3119
3120 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
3121
3122 if (bootverbose)
3123 device_printf(dev, "%s setting %s on National chip\n",
3124 (error) ? "failed" : "success", ata_mode2str(mode));
3125 if (!error) {
3126 if (mode >= ATA_UDMA0) {
3127 pci_write_config(gparent, 0x44 + (devno << 3),
3128 udmatiming[mode & ATA_MODE_MASK], 4);
3129 }
3130 else if (mode >= ATA_WDMA0) {
3131 pci_write_config(gparent, 0x44 + (devno << 3),
3132 dmatiming[mode & ATA_MODE_MASK], 4);
3133 }
3134 else {
3135 pci_write_config(gparent, 0x44 + (devno << 3),
3136 pci_read_config(gparent, 0x44 + (devno << 3), 4) |
3137 0x80000000, 4);
3138 }
3139 pci_write_config(gparent, 0x40 + (devno << 3),
3140 piotiming[ata_mode2idx(mode)], 4);
3141 atadev->mode = mode;
3142 }
3143 }
3144
3145 /*
3146 * NetCell chipset support functions
3147 */
3148 int
3149 ata_netcell_ident(device_t dev)
3150 {
3151 struct ata_pci_controller *ctlr = device_get_softc(dev);
3152
3153 if (pci_get_devid(dev) == ATA_NETCELL_SR) {
3154 device_set_desc(dev, "Netcell SyncRAID SR3000/5000 RAID Controller");
3155 ctlr->chipinit = ata_netcell_chipinit;
3156 return 0;
3157 }
3158 return ENXIO;
3159 }
3160
3161 static int
3162 ata_netcell_chipinit(device_t dev)
3163 {
3164 struct ata_pci_controller *ctlr = device_get_softc(dev);
3165
3166 if (ata_generic_chipinit(dev))
3167 return ENXIO;
3168
3169 ctlr->allocate = ata_netcell_allocate;
3170 return 0;
3171 }
3172
3173 static int
3174 ata_netcell_allocate(device_t dev)
3175 {
3176 struct ata_channel *ch = device_get_softc(dev);
3177
3178 /* setup the usual register normal pci style */
3179 if (ata_pci_allocate(dev))
3180 return ENXIO;
3181
3182 /* the NetCell only supports 16 bit PIO transfers */
3183 ch->flags |= ATA_USE_16BIT;
3184
3185 return 0;
3186 }
3187
3188
3189 /*
3190 * nVidia chipset support functions
3191 */
3192 int
3193 ata_nvidia_ident(device_t dev)
3194 {
3195 struct ata_pci_controller *ctlr = device_get_softc(dev);
3196 struct ata_chip_id *idx;
3197 static struct ata_chip_id ids[] =
3198 {{ ATA_NFORCE1, 0, AMDNVIDIA, NVIDIA, ATA_UDMA5, "nForce" },
3199 { ATA_NFORCE2, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce2" },
3200 { ATA_NFORCE2_PRO, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce2 Pro" },
3201 { ATA_NFORCE2_PRO_S1, 0, 0, 0, ATA_SA150, "nForce2 Pro" },
3202 { ATA_NFORCE3, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce3" },
3203 { ATA_NFORCE3_PRO, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce3 Pro" },
3204 { ATA_NFORCE3_PRO_S1, 0, 0, 0, ATA_SA150, "nForce3 Pro" },
3205 { ATA_NFORCE3_PRO_S2, 0, 0, 0, ATA_SA150, "nForce3 Pro" },
3206 { ATA_NFORCE_MCP04, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP" },
3207 { ATA_NFORCE_MCP04_S1, 0, 0, NV4, ATA_SA150, "nForce MCP" },
3208 { ATA_NFORCE_MCP04_S2, 0, 0, NV4, ATA_SA150, "nForce MCP" },
3209 { ATA_NFORCE_CK804, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce CK804" },
3210 { ATA_NFORCE_CK804_S1, 0, 0, NV4, ATA_SA300, "nForce CK804" },
3211 { ATA_NFORCE_CK804_S2, 0, 0, NV4, ATA_SA300, "nForce CK804" },
3212 { ATA_NFORCE_MCP51, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP51" },
3213 { ATA_NFORCE_MCP51_S1, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP51" },
3214 { ATA_NFORCE_MCP51_S2, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP51" },
3215 { ATA_NFORCE_MCP55, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP55" },
3216 { ATA_NFORCE_MCP55_S1, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP55" },
3217 { ATA_NFORCE_MCP55_S2, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP55" },
3218 { ATA_NFORCE_MCP61, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP61" },
3219 { ATA_NFORCE_MCP61_S1, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP61" },
3220 { ATA_NFORCE_MCP61_S2, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP61" },
3221 { ATA_NFORCE_MCP61_S3, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP61" },
3222 { ATA_NFORCE_MCP65, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP65" },
3223 { ATA_NFORCE_MCP67, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP67" },
3224 { ATA_NFORCE_MCP67_S2, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP67" },
3225 { ATA_NFORCE_MCP73, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP73" },
3226 { ATA_NFORCE_MCP77, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP77" },
3227 { 0, 0, 0, 0, 0, 0}} ;
3228 char buffer[64] ;
3229
3230 if (!(idx = ata_match_chip(dev, ids)))
3231 return ENXIO;
3232
3233 ksprintf(buffer, "nVidia %s %s controller",
3234 idx->text, ata_mode2str(idx->max_dma));
3235 device_set_desc_copy(dev, buffer);
3236 ctlr->chip = idx;
3237 ctlr->chipinit = ata_nvidia_chipinit;
3238 return 0;
3239 }
3240
3241 static int
3242 ata_nvidia_chipinit(device_t dev)
3243 {
3244 struct ata_pci_controller *ctlr = device_get_softc(dev);
3245
3246 if (ata_setup_interrupt(dev))
3247 return ENXIO;
3248
3249 if (ctlr->chip->max_dma >= ATA_SA150) {
3250 if (pci_read_config(dev, PCIR_BAR(5), 1) & 1)
3251 ctlr->r_type2 = SYS_RES_IOPORT;
3252 else
3253 ctlr->r_type2 = SYS_RES_MEMORY;
3254 ctlr->r_rid2 = PCIR_BAR(5);
3255 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
3256 &ctlr->r_rid2, RF_ACTIVE))) {
3257 int offset = ctlr->chip->cfg2 & NV4 ? 0x0440 : 0x0010;
3258
3259 ctlr->allocate = ata_nvidia_allocate;
3260 ctlr->reset = ata_nvidia_reset;
3261
3262 /* enable control access */
3263 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) | 0x04,1);
3264
3265 if (ctlr->chip->cfg2 & NVQ) {
3266 /* clear interrupt status */
3267 ATA_OUTL(ctlr->r_res2, offset, 0x00ff00ff);
3268
3269 /* enable device and PHY state change interrupts */
3270 ATA_OUTL(ctlr->r_res2, offset + 4, 0x000d000d);
3271
3272 /* disable NCQ support */
3273 ATA_OUTL(ctlr->r_res2, 0x0400,
3274 ATA_INL(ctlr->r_res2, 0x0400) & 0xfffffff9);
3275 }
3276 else {
3277 /* clear interrupt status */
3278 ATA_OUTB(ctlr->r_res2, offset, 0xff);
3279
3280 /* enable device and PHY state change interrupts */
3281 ATA_OUTB(ctlr->r_res2, offset + 1, 0xdd);
3282 }
3283
3284 /* enable PCI interrupt */
3285 pci_write_config(dev, PCIR_COMMAND,
3286 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400,2);
3287
3288 }
3289 ctlr->setmode = ata_sata_setmode;
3290 }
3291 else {
3292 /* disable prefetch, postwrite */
3293 pci_write_config(dev, 0x51, pci_read_config(dev, 0x51, 1) & 0x0f, 1);
3294 ctlr->setmode = ata_via_family_setmode;
3295 }
3296 return 0;
3297 }
3298
3299 static int
3300 ata_nvidia_allocate(device_t dev)
3301 {
3302 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3303 struct ata_channel *ch = device_get_softc(dev);
3304
3305 /* setup the usual register normal pci style */
3306 if (ata_pci_allocate(dev))
3307 return ENXIO;
3308
3309 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
3310 ch->r_io[ATA_SSTATUS].offset = (ch->unit << 6);
3311 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
3312 ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << 6);
3313 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
3314 ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << 6);
3315
3316 ch->hw.status = ata_nvidia_status;
3317 ch->flags |= ATA_NO_SLAVE;
3318
3319 return 0;
3320 }
3321
3322 static int
3323 ata_nvidia_status(device_t dev)
3324 {
3325 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3326 struct ata_channel *ch = device_get_softc(dev);
3327 int offset = ctlr->chip->cfg2 & NV4 ? 0x0440 : 0x0010;
3328 int shift = ch->unit << (ctlr->chip->cfg2 & NVQ ? 4 : 2);
3329 u_int32_t istatus;
3330
3331 /* get interrupt status */
3332 if (ctlr->chip->cfg2 & NVQ)
3333 istatus = ATA_INL(ctlr->r_res2, offset);
3334 else
3335 istatus = ATA_INB(ctlr->r_res2, offset);
3336
3337 /* do we have any PHY events ? */
3338 if (istatus & (0x0c << shift))
3339 ata_sata_phy_check_events(dev);
3340
3341 /* clear interrupt(s) */
3342 if (ctlr->chip->cfg2 & NVQ)
3343 ATA_OUTL(ctlr->r_res2, offset, (0x0f << shift) | 0x00f000f0);
3344 else
3345 ATA_OUTB(ctlr->r_res2, offset, (0x0f << shift));
3346
3347 /* do we have any device action ? */
3348 return (istatus & (0x01 << shift));
3349 }
3350
3351 static void
3352 ata_nvidia_reset(device_t dev)
3353 {
3354 if (ata_sata_phy_reset(dev))
3355 ata_generic_reset(dev);
3356 }
3357
3358
3359 /*
3360 * Promise chipset support functions
3361 */
3362 #define ATA_PDC_APKT_OFFSET 0x00000010
3363 #define ATA_PDC_HPKT_OFFSET 0x00000040
3364 #define ATA_PDC_ASG_OFFSET 0x00000080
3365 #define ATA_PDC_LSG_OFFSET 0x000000c0
3366 #define ATA_PDC_HSG_OFFSET 0x00000100
3367 #define ATA_PDC_CHN_OFFSET 0x00000400
3368 #define ATA_PDC_BUF_BASE 0x00400000
3369 #define ATA_PDC_BUF_OFFSET 0x00100000
3370 #define ATA_PDC_MAX_HPKT 8
3371 #define ATA_PDC_WRITE_REG 0x00
3372 #define ATA_PDC_WRITE_CTL 0x0e
3373 #define ATA_PDC_WRITE_END 0x08
3374 #define ATA_PDC_WAIT_NBUSY 0x10
3375 #define ATA_PDC_WAIT_READY 0x18
3376 #define ATA_PDC_1B 0x20
3377 #define ATA_PDC_2B 0x40
3378
3379 struct host_packet {
3380 u_int32_t addr;
3381 TAILQ_ENTRY(host_packet) chain;
3382 };
3383
3384 struct ata_promise_sx4 {
3385 struct spinlock mtx;
3386 TAILQ_HEAD(, host_packet) queue;
3387 int busy;
3388 };
3389
3390 int
3391 ata_promise_ident(device_t dev)
3392 {
3393 struct ata_pci_controller *ctlr = device_get_softc(dev);
3394 struct ata_chip_id *idx;
3395 static struct ata_chip_id ids[] =
3396 {{ ATA_PDC20246, 0, PROLD, 0x00, ATA_UDMA2, "PDC20246" },
3397 { ATA_PDC20262, 0, PRNEW, 0x00, ATA_UDMA4, "PDC20262" },
3398 { ATA_PDC20263, 0, PRNEW, 0x00, ATA_UDMA4, "PDC20263" },
3399 { ATA_PDC20265, 0, PRNEW, 0x00, ATA_UDMA5, "PDC20265" },
3400 { ATA_PDC20267, 0, PRNEW, 0x00, ATA_UDMA5, "PDC20267" },
3401 { ATA_PDC20268, 0, PRTX, PRTX4, ATA_UDMA5, "PDC20268" },
3402 { ATA_PDC20269, 0, PRTX, 0x00, ATA_UDMA6, "PDC20269" },
3403 { ATA_PDC20270, 0, PRTX, PRTX4, ATA_UDMA5, "PDC20270" },
3404 { ATA_PDC20271, 0, PRTX, 0x00, ATA_UDMA6, "PDC20271" },
3405 { ATA_PDC20275, 0, PRTX, 0x00, ATA_UDMA6, "PDC20275" },
3406 { ATA_PDC20276, 0, PRTX, PRSX6K, ATA_UDMA6, "PDC20276" },
3407 { ATA_PDC20277, 0, PRTX, 0x00, ATA_UDMA6, "PDC20277" },
3408 { ATA_PDC20318, 0, PRMIO, PRSATA, ATA_SA150, "PDC20318" },
3409 { ATA_PDC20319, 0, PRMIO, PRSATA, ATA_SA150, "PDC20319" },
3410 { ATA_PDC20371, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20371" },
3411 { ATA_PDC20375, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20375" },
3412 { ATA_PDC20376, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20376" },
3413 { ATA_PDC20377, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20377" },
3414 { ATA_PDC20378, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20378" },
3415 { ATA_PDC20379, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20379" },
3416 { ATA_PDC20571, 0, PRMIO, PRCMBO2, ATA_SA150, "PDC20571" },
3417 { ATA_PDC20575, 0, PRMIO, PRCMBO2, ATA_SA150, "PDC20575" },
3418 { ATA_PDC20579, 0, PRMIO, PRCMBO2, ATA_SA150, "PDC20579" },
3419 { ATA_PDC20771, 0, PRMIO, PRCMBO2, ATA_SA300, "PDC20771" },
3420 { ATA_PDC40775, 0, PRMIO, PRCMBO2, ATA_SA300, "PDC40775" },
3421 { ATA_PDC20617, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20617" },
3422 { ATA_PDC20618, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20618" },
3423 { ATA_PDC20619, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20619" },
3424 { ATA_PDC20620, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20620" },
3425 { ATA_PDC20621, 0, PRMIO, PRSX4X, ATA_UDMA5, "PDC20621" },
3426 { ATA_PDC20622, 0, PRMIO, PRSX4X, ATA_SA150, "PDC20622" },
3427 { ATA_PDC40518, 0, PRMIO, PRSATA2, ATA_SA150, "PDC40518" },
3428 { ATA_PDC40519, 0, PRMIO, PRSATA2, ATA_SA150, "PDC40519" },
3429 { ATA_PDC40718, 0, PRMIO, PRSATA2, ATA_SA300, "PDC40718" },
3430 { ATA_PDC40719, 0, PRMIO, PRSATA2, ATA_SA300, "PDC40719" },
3431 { ATA_PDC40779, 0, PRMIO, PRSATA2, ATA_SA300, "PDC40779" },
3432 { 0, 0, 0, 0, 0, 0}};
3433 char buffer[64];
3434 uintptr_t devid = 0;
3435
3436 if (!(idx = ata_match_chip(dev, ids)))
3437 return ENXIO;
3438
3439 /* if we are on a SuperTrak SX6000 dont attach */
3440 if ((idx->cfg2 & PRSX6K) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE &&
3441 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)),
3442 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) &&
3443 devid == ATA_I960RM)
3444 return ENXIO;
3445
3446 strcpy(buffer, "Promise ");
3447 strcat(buffer, idx->text);
3448
3449 /* if we are on a FastTrak TX4, adjust the interrupt resource */
3450 if ((idx->cfg2 & PRTX4) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE &&
3451 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)),
3452 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) &&
3453 ((devid == ATA_DEC_21150) || (devid == ATA_DEC_21150_1))) {
3454 static long start = 0, end = 0;
3455
3456 if (pci_get_slot(dev) == 1) {
3457 bus_get_resource(dev, SYS_RES_IRQ, 0, &start, &end);
3458 strcat(buffer, " (channel 0+1)");
3459 }
3460 else if (pci_get_slot(dev) == 2 && start && end) {
3461 bus_set_resource(dev, SYS_RES_IRQ, 0, start, end);
3462 strcat(buffer, " (channel 2+3)");
3463 }
3464 else {
3465 start = end = 0;
3466 }
3467 }
3468 ksprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma));
3469 device_set_desc_copy(dev, buffer);
3470 ctlr->chip = idx;
3471 ctlr->chipinit = ata_promise_chipinit;
3472 return 0;
3473 }
3474
3475 static int
3476 ata_promise_chipinit(device_t dev)
3477 {
3478 struct ata_pci_controller *ctlr = device_get_softc(dev);
3479 int fake_reg, stat_reg;
3480
3481 if (ata_setup_interrupt(dev))
3482 return ENXIO;
3483
3484 switch (ctlr->chip->cfg1) {
3485 case PRNEW:
3486 /* setup clocks */
3487 ATA_OUTB(ctlr->r_res1, 0x11, ATA_INB(ctlr->r_res1, 0x11) | 0x0a);
3488
3489 ctlr->dmainit = ata_promise_dmainit;
3490 /* FALLTHROUGH */
3491
3492 case PROLD:
3493 /* enable burst mode */
3494 ATA_OUTB(ctlr->r_res1, 0x1f, ATA_INB(ctlr->r_res1, 0x1f) | 0x01);
3495 ctlr->allocate = ata_promise_allocate;
3496 ctlr->setmode = ata_promise_setmode;
3497 return 0;
3498
3499 case PRTX:
3500 ctlr->allocate = ata_promise_tx2_allocate;
3501 ctlr->setmode = ata_promise_setmode;
3502 return 0;
3503
3504 case PRMIO:
3505 ctlr->r_type1 = SYS_RES_MEMORY;
3506 ctlr->r_rid1 = PCIR_BAR(4);
3507 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1,
3508 &ctlr->r_rid1, RF_ACTIVE)))
3509 goto failnfree;
3510
3511 ctlr->r_type2 = SYS_RES_MEMORY;
3512 ctlr->r_rid2 = PCIR_BAR(3);
3513 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
3514 &ctlr->r_rid2, RF_ACTIVE)))
3515 goto failnfree;
3516
3517 if (ctlr->chip->cfg2 == PRSX4X) {
3518 struct ata_promise_sx4 *hpkt;
3519 u_int32_t dimm = ATA_INL(ctlr->r_res2, 0x000c0080);
3520
3521 if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) ||
3522 bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
3523 ata_promise_sx4_intr, ctlr, &ctlr->handle, NULL)) {
3524 device_printf(dev, "unable to setup interrupt\n");
3525 goto failnfree;
3526 }
3527
3528 /* print info about cache memory */
3529 device_printf(dev, "DIMM size %dMB @ 0x%08x%s\n",
3530 (((dimm >> 16) & 0xff)-((dimm >> 24) & 0xff)+1) << 4,
3531 ((dimm >> 24) & 0xff),
3532 ATA_INL(ctlr->r_res2, 0x000c0088) & (1<<16) ?
3533 " ECC enabled" : "" );
3534
3535 /* adjust cache memory parameters */
3536 ATA_OUTL(ctlr->r_res2, 0x000c000c,
3537 (ATA_INL(ctlr->r_res2, 0x000c000c) & 0xffff0000));
3538
3539 /* setup host packet controls */
3540 hpkt = kmalloc(sizeof(struct ata_promise_sx4),
3541 M_TEMP, M_INTWAIT | M_ZERO);
3542 spin_init(&hpkt->mtx);
3543 TAILQ_INIT(&hpkt->queue);
3544 hpkt->busy = 0;
3545 device_set_ivars(dev, hpkt);
3546 ctlr->allocate = ata_promise_mio_allocate;
3547 ctlr->reset = ata_promise_mio_reset;
3548 ctlr->dmainit = ata_promise_mio_dmainit;
3549 ctlr->setmode = ata_promise_setmode;
3550 ctlr->channels = 4;
3551 return 0;
3552 }
3553
3554 /* mio type controllers need an interrupt intercept */
3555 if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) ||
3556 bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
3557 ata_promise_mio_intr, ctlr, &ctlr->handle, NULL)) {
3558 device_printf(dev, "unable to setup interrupt\n");
3559 goto failnfree;
3560 }
3561
3562 switch (ctlr->chip->cfg2) {
3563 case PRPATA:
3564 ctlr->channels = ((ATA_INL(ctlr->r_res2, 0x48) & 0x01) > 0) +
3565 ((ATA_INL(ctlr->r_res2, 0x48) & 0x02) > 0) + 2;
3566 goto sata150;
3567 case PRCMBO:
3568 ctlr->channels = 3;
3569 goto sata150;
3570 case PRSATA:
3571 ctlr->channels = 4;
3572 sata150:
3573 fake_reg = 0x60;
3574 stat_reg = 0x6c;
3575 break;
3576
3577 case PRCMBO2:
3578 ctlr->channels = 3;
3579 goto sataii;
3580 case PRSATA2:
3581 default:
3582 ctlr->channels = 4;
3583 sataii:
3584 fake_reg = 0x54;
3585 stat_reg = 0x60;
3586 break;
3587 }
3588
3589 /* prime fake interrupt register */
3590 ATA_OUTL(ctlr->r_res2, fake_reg, 0xffffffff);
3591
3592 /* clear SATA status */
3593 ATA_OUTL(ctlr->r_res2, stat_reg, 0x000000ff);
3594
3595 ctlr->allocate = ata_promise_mio_allocate;
3596 ctlr->reset = ata_promise_mio_reset;
3597 ctlr->dmainit = ata_promise_mio_dmainit;
3598 ctlr->setmode = ata_promise_mio_setmode;
3599
3600 return 0;
3601 }
3602
3603 failnfree:
3604 if (ctlr->r_res2)
3605 bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, ctlr->r_res2);
3606 if (ctlr->r_res1)
3607 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1, ctlr->r_res1);
3608 return ENXIO;
3609 }
3610
3611 static int
3612 ata_promise_allocate(device_t dev)
3613 {
3614 struct ata_channel *ch = device_get_softc(dev);
3615
3616 if (ata_pci_allocate(dev))
3617 return ENXIO;
3618
3619 ch->hw.status = ata_promise_status;
3620 return 0;
3621 }
3622
3623 static int
3624 ata_promise_status(device_t dev)
3625 {
3626 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3627 struct ata_channel *ch = device_get_softc(dev);
3628
3629 if (ATA_INL(ctlr->r_res1, 0x1c) & (ch->unit ? 0x00004000 : 0x00000400)) {
3630 return ata_pci_status(dev);
3631 }
3632 return 0;
3633 }
3634
3635 static int
3636 ata_promise_dmastart(device_t dev)
3637 {
3638 struct ata_pci_controller *ctlr = device_get_softc(GRANDPARENT(dev));
3639 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
3640 struct ata_device *atadev = device_get_softc(dev);
3641
3642 if (atadev->flags & ATA_D_48BIT_ACTIVE) {
3643 ATA_OUTB(ctlr->r_res1, 0x11,
3644 ATA_INB(ctlr->r_res1, 0x11) | (ch->unit ? 0x08 : 0x02));
3645 ATA_OUTL(ctlr->r_res1, ch->unit ? 0x24 : 0x20,
3646 ((ch->dma->flags & ATA_DMA_READ) ? 0x05000000 : 0x06000000) |
3647 (ch->dma->cur_iosize >> 1));
3648 }
3649 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, (ATA_IDX_INB(ch, ATA_BMSTAT_PORT) |
3650 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR)));
3651 ATA_IDX_OUTL(ch, ATA_BMDTP_PORT, ch->dma->sg_bus);
3652 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
3653 ((ch->dma->flags & ATA_DMA_READ) ? ATA_BMCMD_WRITE_READ : 0) |
3654 ATA_BMCMD_START_STOP);
3655 ch->flags |= ATA_DMA_ACTIVE;
3656 return 0;
3657 }
3658
3659 static int
3660 ata_promise_dmastop(device_t dev)
3661 {
3662 struct ata_pci_controller *ctlr = device_get_softc(GRANDPARENT(dev));
3663 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
3664 struct ata_device *atadev = device_get_softc(dev);
3665 int error;
3666
3667 if (atadev->flags & ATA_D_48BIT_ACTIVE) {
3668 ATA_OUTB(ctlr->r_res1, 0x11,
3669 ATA_INB(ctlr->r_res1, 0x11) & ~(ch->unit ? 0x08 : 0x02));
3670 ATA_OUTL(ctlr->r_res1, ch->unit ? 0x24 : 0x20, 0);
3671 }
3672 error = ATA_IDX_INB(ch, ATA_BMSTAT_PORT);
3673 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
3674 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
3675 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR);
3676 ch->flags &= ~ATA_DMA_ACTIVE;
3677 return error;
3678 }
3679
3680 static void
3681 ata_promise_dmareset(device_t dev)
3682 {
3683 struct ata_channel *ch = device_get_softc(dev);
3684
3685 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
3686 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
3687 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR);
3688 ch->flags &= ~ATA_DMA_ACTIVE;
3689 }
3690
3691 static void
3692 ata_promise_dmainit(device_t dev)
3693 {
3694 struct ata_channel *ch = device_get_softc(dev);
3695
3696 ata_dmainit(dev);
3697 if (ch->dma) {
3698 ch->dma->start = ata_promise_dmastart;
3699 ch->dma->stop = ata_promise_dmastop;
3700 ch->dma->reset = ata_promise_dmareset;
3701 }
3702 }
3703
3704 static void
3705 ata_promise_setmode(device_t dev, int mode)
3706 {
3707 device_t gparent = GRANDPARENT(dev);
3708 struct ata_pci_controller *ctlr = device_get_softc(gparent);
3709 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
3710 struct ata_device *atadev = device_get_softc(dev);
3711 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
3712 int error;
3713 u_int32_t timings[][2] = {
3714 /* PROLD PRNEW mode */
3715 { 0x004ff329, 0x004fff2f }, /* PIO 0 */
3716 { 0x004fec25, 0x004ff82a }, /* PIO 1 */
3717 { 0x004fe823, 0x004ff026 }, /* PIO 2 */
3718 { 0x004fe622, 0x004fec24 }, /* PIO 3 */
3719 { 0x004fe421, 0x004fe822 }, /* PIO 4 */
3720 { 0x004567f3, 0x004acef6 }, /* MWDMA 0 */
3721 { 0x004467f3, 0x0048cef6 }, /* MWDMA 1 */
3722 { 0x004367f3, 0x0046cef6 }, /* MWDMA 2 */
3723 { 0x004367f3, 0x0046cef6 }, /* UDMA 0 */
3724 { 0x004247f3, 0x00448ef6 }, /* UDMA 1 */
3725 { 0x004127f3, 0x00436ef6 }, /* UDMA 2 */
3726 { 0, 0x00424ef6 }, /* UDMA 3 */
3727 { 0, 0x004127f3 }, /* UDMA 4 */
3728 { 0, 0x004127f3 } /* UDMA 5 */
3729 };
3730
3731 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
3732
3733 switch (ctlr->chip->cfg1) {
3734 case PROLD:
3735 case PRNEW:
3736 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x50, 2) &
3737 (ch->unit ? 1 << 11 : 1 << 10))) {
3738 ata_print_cable(dev, "controller");
3739 mode = ATA_UDMA2;
3740 }
3741 if (ata_atapi(dev) && mode > ATA_PIO_MAX)
3742 mode = ata_limit_mode(dev, mode, ATA_PIO_MAX);
3743 break;
3744
3745 case PRTX:
3746 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b);
3747 if (mode > ATA_UDMA2 &&
3748 ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x04) {
3749 ata_print_cable(dev, "controller");
3750 mode = ATA_UDMA2;
3751 }
3752 break;
3753
3754 case PRMIO:
3755 if (mode > ATA_UDMA2 &&
3756 (ATA_INL(ctlr->r_res2,
3757 (ctlr->chip->cfg2 & PRSX4X ? 0x000c0260 : 0x0260) +
3758 (ch->unit << 7)) & 0x01000000)) {
3759 ata_print_cable(dev, "controller");
3760 mode = ATA_UDMA2;
3761 }
3762 break;
3763 }
3764
3765 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
3766
3767 if (bootverbose)
3768 device_printf(dev, "%ssetting %s on %s chip\n",
3769 (error) ? "FAILURE " : "",
3770 ata_mode2str(mode), ctlr->chip->text);
3771 if (!error) {
3772 if (ctlr->chip->cfg1 < PRTX)
3773 pci_write_config(gparent, 0x60 + (devno << 2),
3774 timings[ata_mode2idx(mode)][ctlr->chip->cfg1], 4);
3775 atadev->mode = mode;
3776 }
3777 return;
3778 }
3779
3780 static int
3781 ata_promise_tx2_allocate(device_t dev)
3782 {
3783 struct ata_channel *ch = device_get_softc(dev);
3784
3785 if (ata_pci_allocate(dev))
3786 return ENXIO;
3787
3788 ch->hw.status = ata_promise_tx2_status;
3789 return 0;
3790 }
3791
3792 static int
3793 ata_promise_tx2_status(device_t dev)
3794 {
3795 struct ata_channel *ch = device_get_softc(dev);
3796
3797 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b);
3798 if (ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x20) {
3799 return ata_pci_status(dev);
3800 }
3801 return 0;
3802 }
3803
3804 static int
3805 ata_promise_mio_allocate(device_t dev)
3806 {
3807 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3808 struct ata_channel *ch = device_get_softc(dev);
3809 int offset = (ctlr->chip->cfg2 & PRSX4X) ? 0x000c0000 : 0;
3810 int i;
3811
3812 for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
3813 ch->r_io[i].res = ctlr->r_res2;
3814 ch->r_io[i].offset = offset + 0x0200 + (i << 2) + (ch->unit << 7);
3815 }
3816 ch->r_io[ATA_CONTROL].res = ctlr->r_res2;
3817 ch->r_io[ATA_CONTROL].offset = offset + 0x0238 + (ch->unit << 7);
3818 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2;
3819 ata_default_registers(dev);
3820 if ((ctlr->chip->cfg2 & (PRSATA | PRSATA2)) ||
3821 ((ctlr->chip->cfg2 & (PRCMBO | PRCMBO2)) && ch->unit < 2)) {
3822 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
3823 ch->r_io[ATA_SSTATUS].offset = 0x400 + (ch->unit << 8);
3824 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
3825 ch->r_io[ATA_SERROR].offset = 0x404 + (ch->unit << 8);
3826 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
3827 ch->r_io[ATA_SCONTROL].offset = 0x408 + (ch->unit << 8);
3828 ch->flags |= ATA_NO_SLAVE;
3829 }
3830 ch->flags |= ATA_USE_16BIT;
3831
3832 ata_generic_hw(dev);
3833 if (ctlr->chip->cfg2 & PRSX4X) {
3834 ch->hw.command = ata_promise_sx4_command;
3835 }
3836 else {
3837 ch->hw.command = ata_promise_mio_command;
3838 ch->hw.status = ata_promise_mio_status;
3839 }
3840 return 0;
3841 }
3842
3843 static void
3844 ata_promise_mio_intr(void *data)
3845 {
3846 struct ata_pci_controller *ctlr = data;
3847 struct ata_channel *ch;
3848 u_int32_t vector;
3849 int unit, fake_reg;
3850
3851 switch (ctlr->chip->cfg2) {
3852 case PRPATA:
3853 case PRCMBO:
3854 case PRSATA:
3855 fake_reg = 0x60;
3856 break;
3857 case PRCMBO2:
3858 case PRSATA2:
3859 default:
3860 fake_reg = 0x54;
3861 break;
3862 }
3863
3864 /*
3865 * since reading interrupt status register on early "mio" chips
3866 * clears the status bits we cannot read it for each channel later on
3867 * in the generic interrupt routine.
3868 * store the bits in an unused register in the chip so we can read
3869 * it from there safely to get around this "feature".
3870 */
3871 vector = ATA_INL(ctlr->r_res2, 0x040);
3872 ATA_OUTL(ctlr->r_res2, 0x040, vector);
3873 ATA_OUTL(ctlr->r_res2, fake_reg, vector);
3874
3875 for (unit = 0; unit < ctlr->channels; unit++) {
3876 if ((ch = ctlr->interrupt[unit].argument))
3877 ctlr->interrupt[unit].function(ch);
3878 }
3879
3880 ATA_OUTL(ctlr->r_res2, fake_reg, 0xffffffff);
3881 }
3882
3883 static int
3884 ata_promise_mio_status(device_t dev)
3885 {
3886 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3887 struct ata_channel *ch = device_get_softc(dev);
3888 struct ata_connect_task *tp;
3889 u_int32_t fake_reg, stat_reg, vector, status;
3890
3891 switch (ctlr->chip->cfg2) {
3892 case PRPATA:
3893 case PRCMBO:
3894 case PRSATA:
3895 fake_reg = 0x60;
3896 stat_reg = 0x6c;
3897 break;
3898 case PRCMBO2:
3899 case PRSATA2:
3900 default:
3901 fake_reg = 0x54;
3902 stat_reg = 0x60;
3903 break;
3904 }
3905
3906 /* read and acknowledge interrupt */
3907 vector = ATA_INL(ctlr->r_res2, fake_reg);
3908
3909 /* read and clear interface status */
3910 status = ATA_INL(ctlr->r_res2, stat_reg);
3911 ATA_OUTL(ctlr->r_res2, stat_reg, status & (0x00000011 << ch->unit));
3912
3913 /* check for and handle disconnect events */
3914 if ((status & (0x00000001 << ch->unit)) &&
3915 (tp = (struct ata_connect_task *)
3916 kmalloc(sizeof(struct ata_connect_task),
3917 M_ATA, M_INTWAIT | M_ZERO))) {
3918
3919 if (bootverbose)
3920 device_printf(ch->dev, "DISCONNECT requested\n");
3921 tp->action = ATA_C_DETACH;
3922 tp->dev = ch->dev;
3923 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp);
3924 taskqueue_enqueue(taskqueue_thread[mycpuid], &tp->task);
3925 }
3926
3927 /* check for and handle connect events */
3928 if ((status & (0x00000010 << ch->unit)) &&
3929 (tp = (struct ata_connect_task *)
3930 kmalloc(sizeof(struct ata_connect_task),
3931 M_ATA, M_INTWAIT | M_ZERO))) {
3932
3933 if (bootverbose)
3934 device_printf(ch->dev, "CONNECT requested\n");
3935 tp->action = ATA_C_ATTACH;
3936 tp->dev = ch->dev;
3937 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp);
3938 taskqueue_enqueue(taskqueue_thread[mycpuid], &tp->task);
3939 }
3940
3941 /* do we have any device action ? */
3942 return (vector & (1 << (ch->unit + 1)));
3943 }
3944
3945 static int
3946 ata_promise_mio_command(struct ata_request *request)
3947 {
3948 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
3949 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
3950 u_int32_t *wordp = (u_int32_t *)ch->dma->work;
3951
3952 ATA_OUTL(ctlr->r_res2, (ch->unit + 1) << 2, 0x00000001);
3953
3954 /* XXX SOS add ATAPI commands support later */
3955 switch (request->u.ata.command) {
3956 default:
3957 return ata_generic_command(request);
3958
3959 case ATA_READ_DMA:
3960 case ATA_READ_DMA48:
3961 wordp[0] = htole32(0x04 | ((ch->unit + 1) << 16) | (0x00 << 24));
3962 break;
3963
3964 case ATA_WRITE_DMA:
3965 case ATA_WRITE_DMA48:
3966 wordp[0] = htole32(0x00 | ((ch->unit + 1) << 16) | (0x00 << 24));
3967 break;
3968 }
3969 wordp[1] = htole32(ch->dma->sg_bus);
3970 wordp[2] = 0;
3971 ata_promise_apkt((u_int8_t*)wordp, request);
3972
3973 ATA_OUTL(ctlr->r_res2, 0x0240 + (ch->unit << 7), ch->dma->work_bus);
3974 return 0;
3975 }
3976
3977 static void
3978 ata_promise_mio_reset(device_t dev)
3979 {
3980 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3981 struct ata_channel *ch = device_get_softc(dev);
3982 struct ata_promise_sx4 *hpktp;
3983
3984 switch (ctlr->chip->cfg2) {
3985 case PRSX4X:
3986
3987 /* softreset channel ATA module */
3988 hpktp = device_get_ivars(ctlr->dev);
3989 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7), ch->unit + 1);
3990 ata_udelay(1000);
3991 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7),
3992 (ATA_INL(ctlr->r_res2, 0xc0260 + (ch->unit << 7)) &
3993 ~0x00003f9f) | (ch->unit + 1));
3994
3995 /* softreset HOST module */ /* XXX SOS what about other outstandings */
3996 spin_lock_wr(&hpktp->mtx);
3997 ATA_OUTL(ctlr->r_res2, 0xc012c,
3998 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f) | (1 << 11));
3999 DELAY(10);
4000 ATA_OUTL(ctlr->r_res2, 0xc012c,
4001 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f));
4002 hpktp->busy = 0;
4003 spin_unlock_wr(&hpktp->mtx);
4004 ata_generic_reset(dev);
4005 break;
4006
4007 case PRPATA:
4008 case PRCMBO:
4009 case PRSATA:
4010 if ((ctlr->chip->cfg2 == PRSATA) ||
4011 ((ctlr->chip->cfg2 == PRCMBO) && (ch->unit < 2))) {
4012
4013 /* mask plug/unplug intr */
4014 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00110000 << ch->unit));
4015 }
4016
4017 /* softreset channels ATA module */
4018 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11));
4019 ata_udelay(10000);
4020 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7),
4021 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) &
4022 ~0x00003f9f) | (ch->unit + 1));
4023
4024 if ((ctlr->chip->cfg2 == PRSATA) ||
4025 ((ctlr->chip->cfg2 == PRCMBO) && (ch->unit < 2))) {
4026
4027 if (ata_sata_phy_reset(dev))
4028 ata_generic_reset(dev);
4029
4030 /* reset and enable plug/unplug intr */
4031 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00000011 << ch->unit));
4032 }
4033 else
4034 ata_generic_reset(dev);
4035 break;
4036
4037 case PRCMBO2:
4038 case PRSATA2:
4039 if ((ctlr->chip->cfg2 == PRSATA2) ||
4040 ((ctlr->chip->cfg2 == PRCMBO2) && (ch->unit < 2))) {
4041 /* set portmultiplier port */
4042 ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x0f);
4043
4044 /* mask plug/unplug intr */
4045 ATA_OUTL(ctlr->r_res2, 0x060, (0x00110000 << ch->unit));
4046 }
4047
4048 /* softreset channels ATA module */
4049 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11));
4050 ata_udelay(10000);
4051 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7),
4052 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) &
4053 ~0x00003f9f) | (ch->unit + 1));
4054
4055 if ((ctlr->chip->cfg2 == PRSATA2) ||
4056 ((ctlr->chip->cfg2 == PRCMBO2) && (ch->unit < 2))) {
4057
4058 /* set PHY mode to "improved" */
4059 ATA_OUTL(ctlr->r_res2, 0x414 + (ch->unit << 8),
4060 (ATA_INL(ctlr->r_res2, 0x414 + (ch->unit << 8)) &
4061 ~0x00000003) | 0x00000001);
4062
4063 if (ata_sata_phy_reset(dev))
4064 ata_generic_reset(dev);
4065
4066 /* reset and enable plug/unplug intr */
4067 ATA_OUTL(ctlr->r_res2, 0x060, (0x00000011 << ch->unit));
4068
4069 /* set portmultiplier port */
4070 ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x00);
4071 }
4072 else
4073 ata_generic_reset(dev);
4074 break;
4075
4076 }
4077 }
4078
4079 static void
4080 ata_promise_mio_dmainit(device_t dev)
4081 {
4082 /* note start and stop are not used here */
4083 ata_dmainit(dev);
4084 }
4085
4086 static void
4087 ata_promise_mio_setmode(device_t dev, int mode)
4088 {
4089 device_t gparent = GRANDPARENT(dev);
4090 struct ata_pci_controller *ctlr = device_get_softc(gparent);
4091 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
4092
4093 if ( (ctlr->chip->cfg2 == PRSATA) ||
4094 ((ctlr->chip->cfg2 == PRCMBO) && (ch->unit < 2)) ||
4095 (ctlr->chip->cfg2 == PRSATA2) ||
4096 ((ctlr->chip->cfg2 == PRCMBO2) && (ch->unit < 2)))
4097 ata_sata_setmode(dev, mode);
4098 else
4099 ata_promise_setmode(dev, mode);
4100 }
4101
4102 static void
4103 ata_promise_sx4_intr(void *data)
4104 {
4105 struct ata_pci_controller *ctlr = data;
4106 struct ata_channel *ch;
4107 u_int32_t vector = ATA_INL(ctlr->r_res2, 0x000c0480);
4108 int unit;
4109
4110 for (unit = 0; unit < ctlr->channels; unit++) {
4111 if (vector & (1 << (unit + 1)))
4112 if ((ch = ctlr->interrupt[unit].argument))
4113 ctlr->interrupt[unit].function(ch);
4114 if (vector & (1 << (unit + 5)))
4115 if ((ch = ctlr->interrupt[unit].argument))
4116 ata_promise_queue_hpkt(ctlr,
4117 htole32((ch->unit * ATA_PDC_CHN_OFFSET) +
4118 ATA_PDC_HPKT_OFFSET));
4119 if (vector & (1 << (unit + 9))) {
4120 ata_promise_next_hpkt(ctlr);
4121 if ((ch = ctlr->interrupt[unit].argument))
4122 ctlr->interrupt[unit].function(ch);
4123 }
4124 if (vector & (1 << (unit + 13))) {
4125 ata_promise_next_hpkt(ctlr);
4126 if ((ch = ctlr->interrupt[unit].argument))
4127 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7),
4128 htole32((ch->unit * ATA_PDC_CHN_OFFSET) +
4129 ATA_PDC_APKT_OFFSET));
4130 }
4131 }
4132 }
4133
4134 static int
4135 ata_promise_sx4_command(struct ata_request *request)
4136 {
4137 device_t gparent = GRANDPARENT(request->dev);
4138 struct ata_pci_controller *ctlr = device_get_softc(gparent);
4139 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
4140 struct ata_dma_prdentry *prd = ch->dma->sg;
4141 caddr_t window = rman_get_virtual(ctlr->r_res1);
4142 u_int32_t *wordp;
4143 int i, idx, length = 0;
4144
4145 /* XXX SOS add ATAPI commands support later */
4146 switch (request->u.ata.command) {
4147
4148 default:
4149 return -1;
4150
4151 case ATA_ATA_IDENTIFY:
4152 case ATA_READ:
4153 case ATA_READ48:
4154 case ATA_READ_MUL:
4155 case ATA_READ_MUL48:
4156 case ATA_WRITE:
4157 case ATA_WRITE48:
4158 case ATA_WRITE_MUL:
4159 case ATA_WRITE_MUL48:
4160 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001);
4161 return ata_generic_command(request);
4162
4163 case ATA_SETFEATURES:
4164 case ATA_FLUSHCACHE:
4165 case ATA_FLUSHCACHE48:
4166 case ATA_SLEEP:
4167 case ATA_SET_MULTI:
4168 wordp = (u_int32_t *)
4169 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET);
4170 wordp[0] = htole32(0x08 | ((ch->unit + 1)<<16) | (0x00 << 24));
4171 wordp[1] = 0;
4172 wordp[2] = 0;
4173 ata_promise_apkt((u_int8_t *)wordp, request);
4174 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001);
4175 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001);
4176 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7),
4177 htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_APKT_OFFSET));
4178 return 0;
4179
4180 case ATA_READ_DMA:
4181 case ATA_READ_DMA48:
4182 case ATA_WRITE_DMA:
4183 case ATA_WRITE_DMA48:
4184 wordp = (u_int32_t *)
4185 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HSG_OFFSET);
4186 i = idx = 0;
4187 do {
4188 wordp[idx++] = prd[i].addr;
4189 wordp[idx++] = prd[i].count;
4190 length += (prd[i].count & ~ATA_DMA_EOT);
4191 } while (!(prd[i++].count & ATA_DMA_EOT));
4192
4193 wordp = (u_int32_t *)
4194 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_LSG_OFFSET);
4195 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE);
4196 wordp[1] = htole32(request->bytecount | ATA_DMA_EOT);
4197
4198 wordp = (u_int32_t *)
4199 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_ASG_OFFSET);
4200 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE);
4201 wordp[1] = htole32(request->bytecount | ATA_DMA_EOT);
4202
4203 wordp = (u_int32_t *)
4204 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET);
4205 if (request->flags & ATA_R_READ)
4206 wordp[0] = htole32(0x14 | ((ch->unit+9)<<16) | ((ch->unit+5)<<24));
4207 if (request->flags & ATA_R_WRITE)
4208 wordp[0] = htole32(0x00 | ((ch->unit+13)<<16) | (0x00<<24));
4209 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_HSG_OFFSET);
4210 wordp[2] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_LSG_OFFSET);
4211 wordp[3] = 0;
4212
4213 wordp = (u_int32_t *)
4214 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET);
4215 if (request->flags & ATA_R_READ)
4216 wordp[0] = htole32(0x04 | ((ch->unit+5)<<16) | (0x00<<24));
4217 if (request->flags & ATA_R_WRITE)
4218 wordp[0] = htole32(0x10 | ((ch->unit+1)<<16) | ((ch->unit+13)<<24));
4219 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_ASG_OFFSET);
4220 wordp[2] = 0;
4221 ata_promise_apkt((u_int8_t *)wordp, request);
4222 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001);
4223
4224 if (request->flags & ATA_R_READ) {
4225 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+5)<<2), 0x00000001);
4226 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+9)<<2), 0x00000001);
4227 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7),
4228 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET));
4229 }
4230 if (request->flags & ATA_R_WRITE) {
4231 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+1)<<2), 0x00000001);
4232 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+13)<<2), 0x00000001);
4233 ata_promise_queue_hpkt(ctlr,
4234 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET));
4235 }
4236 return 0;
4237 }
4238 }
4239
4240 static int
4241 ata_promise_apkt(u_int8_t *bytep, struct ata_request *request)
4242 {
4243 struct ata_device *atadev = device_get_softc(request->dev);
4244 int i = 12;
4245
4246 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_PDC_WAIT_NBUSY|ATA_DRIVE;
4247 bytep[i++] = ATA_D_IBM | ATA_D_LBA | atadev->unit;
4248 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_CTL;
4249 bytep[i++] = ATA_A_4BIT;
4250
4251 if (atadev->flags & ATA_D_48BIT_ACTIVE) {
4252 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_FEATURE;
4253 bytep[i++] = request->u.ata.feature >> 8;
4254 bytep[i++] = request->u.ata.feature;
4255 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_COUNT;
4256 bytep[i++] = request->u.ata.count >> 8;
4257 bytep[i++] = request->u.ata.count;
4258 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_SECTOR;
4259 bytep[i++] = request->u.ata.lba >> 24;
4260 bytep[i++] = request->u.ata.lba;
4261 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_LSB;
4262 bytep[i++] = request->u.ata.lba >> 32;
4263 bytep[i++] = request->u.ata.lba >> 8;
4264 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_MSB;
4265 bytep[i++] = request->u.ata.lba >> 40;
4266 bytep[i++] = request->u.ata.lba >> 16;
4267 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE;
4268 bytep[i++] = ATA_D_LBA | atadev->unit;
4269 }
4270 else {
4271 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_FEATURE;
4272 bytep[i++] = request->u.ata.feature;
4273 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_COUNT;
4274 bytep[i++] = request->u.ata.count;
4275 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_SECTOR;
4276 bytep[i++] = request->u.ata.lba;
4277 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_LSB;
4278 bytep[i++] = request->u.ata.lba >> 8;
4279 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_MSB;
4280 bytep[i++] = request->u.ata.lba >> 16;
4281 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE;
4282 bytep[i++] = (atadev->flags & ATA_D_USE_CHS ? 0 : ATA_D_LBA) |
4283 ATA_D_IBM | atadev->unit | ((request->u.ata.lba >> 24)&0xf);
4284 }
4285 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_END | ATA_COMMAND;
4286 bytep[i++] = request->u.ata.command;
4287 return i;
4288 }
4289
4290 static void
4291 ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt)
4292 {
4293 struct ata_promise_sx4 *hpktp = device_get_ivars(ctlr->dev);
4294
4295 spin_lock_wr(&hpktp->mtx);
4296 if (hpktp->busy) {
4297 struct host_packet *hp =
4298 kmalloc(sizeof(struct host_packet), M_TEMP, M_INTWAIT | M_ZERO);
4299 hp->addr = hpkt;
4300 TAILQ_INSERT_TAIL(&hpktp->queue, hp, chain);
4301 }
4302 else {
4303 hpktp->busy = 1;
4304 ATA_OUTL(ctlr->r_res2, 0x000c0100, hpkt);
4305 }
4306 spin_unlock_wr(&hpktp->mtx);
4307 }
4308
4309 static void
4310 ata_promise_next_hpkt(struct ata_pci_controller *ctlr)
4311 {
4312 struct ata_promise_sx4 *hpktp = device_get_ivars(ctlr->dev);
4313 struct host_packet *hp;
4314
4315 spin_lock_wr(&hpktp->mtx);
4316 if ((hp = TAILQ_FIRST(&hpktp->queue))) {
4317 TAILQ_REMOVE(&hpktp->queue, hp, chain);
4318 ATA_OUTL(ctlr->r_res2, 0x000c0100, hp->addr);
4319 kfree(hp, M_TEMP);
4320 }
4321 else
4322 hpktp->busy = 0;
4323 spin_unlock_wr(&hpktp->mtx);
4324 }
4325
4326
4327 /*
4328 * ServerWorks chipset support functions
4329 */
4330 int
4331 ata_serverworks_ident(device_t dev)
4332 {
4333 struct ata_pci_controller *ctlr = device_get_softc(dev);
4334 struct ata_chip_id *idx;
4335 static struct ata_chip_id ids[] =
4336 {{ ATA_ROSB4, 0x00, SWKS33, 0, ATA_UDMA2, "ROSB4" },
4337 { ATA_CSB5, 0x92, SWKS100, 0, ATA_UDMA5, "CSB5" },
4338 { ATA_CSB5, 0x00, SWKS66, 0, ATA_UDMA4, "CSB5" },
4339 { ATA_CSB6, 0x00, SWKS100, 0, ATA_UDMA5, "CSB6" },
4340 { ATA_CSB6_1, 0x00, SWKS66, 0, ATA_UDMA4, "CSB6" },
4341 { ATA_HT1000, 0x00, SWKS100, 0, ATA_UDMA5, "HT1000" },
4342 { ATA_HT1000_S1, 0x00, SWKS100, 4, ATA_SA150, "HT1000" },
4343 { ATA_HT1000_S2, 0x00, SWKSMIO, 4, ATA_SA150, "HT1000" },
4344 { ATA_K2, 0x00, SWKSMIO, 4, ATA_SA150, "K2" },
4345 { ATA_FRODO4, 0x00, SWKSMIO, 4, ATA_SA150, "Frodo4" },
4346 { ATA_FRODO8, 0x00, SWKSMIO, 8, ATA_SA150, "Frodo8" },
4347 { 0, 0, 0, 0, 0, 0}};
4348 char buffer[64];
4349
4350 if (!(idx = ata_match_chip(dev, ids)))
4351 return ENXIO;
4352
4353 ksprintf(buffer, "ServerWorks %s %s controller",
4354 idx->text, ata_mode2str(idx->max_dma));
4355 device_set_desc_copy(dev, buffer);
4356 ctlr->chip = idx;
4357 ctlr->chipinit = ata_serverworks_chipinit;
4358 return 0;
4359 }
4360
4361 static int
4362 ata_serverworks_chipinit(device_t dev)
4363 {
4364 struct ata_pci_controller *ctlr = device_get_softc(dev);
4365
4366 if (ata_setup_interrupt(dev))
4367 return ENXIO;
4368
4369 if (ctlr->chip->cfg1 == SWKSMIO) {
4370 ctlr->r_type2 = SYS_RES_MEMORY;
4371 ctlr->r_rid2 = PCIR_BAR(5);
4372 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
4373 &ctlr->r_rid2, RF_ACTIVE)))
4374 return ENXIO;
4375
4376 ctlr->channels = ctlr->chip->cfg2;
4377 ctlr->allocate = ata_serverworks_allocate;
4378 ctlr->setmode = ata_sata_setmode;
4379 return 0;
4380 }
4381 else if (ctlr->chip->cfg1 == SWKS33) {
4382 device_t *children;
4383 int nchildren, i;
4384
4385 /* locate the ISA part in the southbridge and enable UDMA33 */
4386 if (!device_get_children(device_get_parent(dev), &children,&nchildren)){
4387 for (i = 0; i < nchildren; i++) {
4388 if (pci_get_devid(children[i]) == ATA_ROSB4_ISA) {
4389 pci_write_config(children[i], 0x64,
4390 (pci_read_config(children[i], 0x64, 4) &
4391 ~0x00002000) | 0x00004000, 4);
4392 break;
4393 }
4394 }
4395 kfree(children, M_TEMP);
4396 }
4397 }
4398 else {
4399 pci_write_config(dev, 0x5a,
4400 (pci_read_config(dev, 0x5a, 1) & ~0x40) |
4401 (ctlr->chip->cfg1 == SWKS100) ? 0x03 : 0x02, 1);
4402 }
4403 ctlr->setmode = ata_serverworks_setmode;
4404 return 0;
4405 }
4406
4407 static int
4408 ata_serverworks_allocate(device_t dev)
4409 {
4410 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4411 struct ata_channel *ch = device_get_softc(dev);
4412 int ch_offset;
4413 int i;
4414
4415 ch_offset = ch->unit * 0x100;
4416
4417 for (i = ATA_DATA; i < ATA_MAX_RES; i++)
4418 ch->r_io[i].res = ctlr->r_res2;
4419
4420 /* setup ATA registers */
4421 ch->r_io[ATA_DATA].offset = ch_offset + 0x00;
4422 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x04;
4423 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08;
4424 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c;
4425 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10;
4426 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14;
4427 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18;
4428 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1c;
4429 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x20;
4430 ata_default_registers(dev);
4431
4432 /* setup DMA registers */
4433 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x30;
4434 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x32;
4435 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x34;
4436
4437 /* setup SATA registers */
4438 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x40;
4439 ch->r_io[ATA_SERROR].offset = ch_offset + 0x44;
4440 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x48;
4441
4442 ch->flags |= ATA_NO_SLAVE;
4443 ata_pci_hw(dev);
4444
4445 /* chip does not reliably do 64K DMA transfers */
4446 if (ch->dma)
4447 ch->dma->max_iosize = 126 * DEV_BSIZE;
4448
4449 return 0;
4450 }
4451
4452 static void
4453 ata_serverworks_setmode(device_t dev, int mode)
4454 {
4455 device_t gparent = GRANDPARENT(dev);
4456 struct ata_pci_controller *ctlr = device_get_softc(gparent);
4457 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
4458 struct ata_device *atadev = device_get_softc(dev);
4459 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
4460 int offset = (devno ^ 0x01) << 3;
4461 int error;
4462 u_int8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20, 0x34, 0x22, 0x20,
4463 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
4464 u_int8_t dmatimings[] = { 0x77, 0x21, 0x20 };
4465
4466 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
4467
4468 mode = ata_check_80pin(dev, mode);
4469
4470 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
4471
4472 if (bootverbose)
4473 device_printf(dev, "%ssetting %s on %s chip\n",
4474 (error) ? "FAILURE " : "",
4475 ata_mode2str(mode), ctlr->chip->text);
4476 if (!error) {
4477 if (mode >= ATA_UDMA0) {
4478 pci_write_config(gparent, 0x56,
4479 (pci_read_config(gparent, 0x56, 2) &
4480 ~(0xf << (devno << 2))) |
4481 ((mode & ATA_MODE_MASK) << (devno << 2)), 2);
4482 pci_write_config(gparent, 0x54,
4483 pci_read_config(gparent, 0x54, 1) |
4484 (0x01 << devno), 1);
4485 pci_write_config(gparent, 0x44,
4486 (pci_read_config(gparent, 0x44, 4) &
4487 ~(0xff << offset)) |
4488 (dmatimings[2] << offset), 4);
4489 }
4490 else if (mode >= ATA_WDMA0) {
4491 pci_write_config(gparent, 0x54,
4492 pci_read_config(gparent, 0x54, 1) &
4493 ~(0x01 << devno), 1);
4494 pci_write_config(gparent, 0x44,
4495 (pci_read_config(gparent, 0x44, 4) &
4496 ~(0xff << offset)) |
4497 (dmatimings[mode & ATA_MODE_MASK] << offset), 4);
4498 }
4499 else
4500 pci_write_config(gparent, 0x54,
4501 pci_read_config(gparent, 0x54, 1) &
4502 ~(0x01 << devno), 1);
4503
4504 pci_write_config(gparent, 0x40,
4505 (pci_read_config(gparent, 0x40, 4) &
4506 ~(0xff << offset)) |
4507 (piotimings[ata_mode2idx(mode)] << offset), 4);
4508 atadev->mode = mode;
4509 }
4510 }
4511
4512
4513 /*
4514 * Silicon Image Inc. (SiI) (former CMD) chipset support functions
4515 */
4516 int
4517 ata_sii_ident(device_t dev)
4518 {
4519 struct ata_pci_controller *ctlr = device_get_softc(dev);
4520 struct ata_chip_id *idx;
4521 static struct ata_chip_id ids[] =
4522 {{ ATA_SII3114, 0x00, SIIMEMIO, SII4CH, ATA_SA150, "SiI 3114" },
4523 { ATA_SII3512, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3512" },
4524 { ATA_SII3112, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3112" },
4525 { ATA_SII3112_1, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3112" },
4526 { ATA_SII3512, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3512" },
4527 { ATA_SII3112, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3112" },
4528 { ATA_SII3112_1, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3112" },
4529 { ATA_SII3124, 0x00, SIIPRBIO, SII4CH, ATA_SA300, "SiI 3124" },
4530 { ATA_SII3132, 0x00, SIIPRBIO, 0, ATA_SA300, "SiI 3132" },
4531 { ATA_SII0680, 0x00, SIIMEMIO, SIISETCLK, ATA_UDMA6, "SiI 0680" },
4532 { ATA_CMD649, 0x00, 0, SIIINTR, ATA_UDMA5, "CMD 649" },
4533 { ATA_CMD648, 0x00, 0, SIIINTR, ATA_UDMA4, "CMD 648" },
4534 { ATA_CMD646, 0x07, 0, 0, ATA_UDMA2, "CMD 646U2" },
4535 { ATA_CMD646, 0x00, 0, 0, ATA_WDMA2, "CMD 646" },
4536 { 0, 0, 0, 0, 0, 0}};
4537 char buffer[64];
4538
4539 if (!(idx = ata_match_chip(dev, ids)))
4540 return ENXIO;
4541
4542 ksprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
4543 device_set_desc_copy(dev, buffer);
4544 ctlr->chip = idx;
4545 ctlr->chipinit = ata_sii_chipinit;
4546 return 0;
4547 }
4548
4549 static int
4550 ata_sii_chipinit(device_t dev)
4551 {
4552 struct ata_pci_controller *ctlr = device_get_softc(dev);
4553
4554 if (ata_setup_interrupt(dev))
4555 return ENXIO;
4556
4557 switch (ctlr->chip->cfg1) {
4558 case SIIPRBIO:
4559 ctlr->r_type1 = SYS_RES_MEMORY;
4560 ctlr->r_rid1 = PCIR_BAR(0);
4561 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1,
4562 &ctlr->r_rid1, RF_ACTIVE)))
4563 return ENXIO;
4564
4565 ctlr->r_rid2 = PCIR_BAR(2);
4566 ctlr->r_type2 = SYS_RES_MEMORY;
4567 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
4568 &ctlr->r_rid2, RF_ACTIVE))){
4569 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1,ctlr->r_res1);
4570 return ENXIO;
4571 }
4572 ctlr->allocate = ata_siiprb_allocate;
4573 ctlr->reset = ata_siiprb_reset;
4574 ctlr->dmainit = ata_siiprb_dmainit;
4575 ctlr->setmode = ata_sata_setmode;
4576 ctlr->channels = (ctlr->chip->cfg2 == SII4CH) ? 4 : 2;
4577
4578 /* reset controller */
4579 ATA_OUTL(ctlr->r_res1, 0x0040, 0x80000000);
4580 DELAY(10000);
4581 ATA_OUTL(ctlr->r_res1, 0x0040, 0x0000000f);
4582
4583 /* enable PCI interrupt */
4584 pci_write_config(dev, PCIR_COMMAND,
4585 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
4586 break;
4587
4588 case SIIMEMIO:
4589 ctlr->r_type2 = SYS_RES_MEMORY;
4590 ctlr->r_rid2 = PCIR_BAR(5);
4591 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
4592 &ctlr->r_rid2, RF_ACTIVE)))
4593 return ENXIO;
4594
4595 if (ctlr->chip->cfg2 & SIISETCLK) {
4596 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
4597 pci_write_config(dev, 0x8a,
4598 (pci_read_config(dev, 0x8a, 1) & 0xcf)|0x10,1);
4599 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
4600 device_printf(dev, "%s could not set ATA133 clock\n",
4601 ctlr->chip->text);
4602 }
4603
4604 /* if we have 4 channels enable the second set */
4605 if (ctlr->chip->cfg2 & SII4CH) {
4606 ATA_OUTL(ctlr->r_res2, 0x0200, 0x00000002);
4607 ctlr->channels = 4;
4608 }
4609
4610 /* dont block interrupts from any channel */
4611 pci_write_config(dev, 0x48,
4612 (pci_read_config(dev, 0x48, 4) & ~0x03c00000), 4);
4613
4614 /* enable PCI interrupt as BIOS might not */
4615 pci_write_config(dev, 0x8a, (pci_read_config(dev, 0x8a, 1) & 0x3f), 1);
4616
4617 ctlr->allocate = ata_sii_allocate;
4618 if (ctlr->chip->max_dma >= ATA_SA150) {
4619 ctlr->reset = ata_sii_reset;
4620 ctlr->setmode = ata_sata_setmode;
4621 }
4622 else
4623 ctlr->setmode = ata_sii_setmode;
4624 break;
4625
4626 default:
4627 if ((pci_read_config(dev, 0x51, 1) & 0x08) != 0x08) {
4628 device_printf(dev, "HW has secondary channel disabled\n");
4629 ctlr->channels = 1;
4630 }
4631
4632 /* enable interrupt as BIOS might not */
4633 pci_write_config(dev, 0x71, 0x01, 1);
4634
4635 ctlr->allocate = ata_cmd_allocate;
4636 ctlr->setmode = ata_cmd_setmode;
4637 break;
4638 }
4639 return 0;
4640 }
4641
4642 static int
4643 ata_cmd_allocate(device_t dev)
4644 {
4645 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4646 struct ata_channel *ch = device_get_softc(dev);
4647
4648 /* setup the usual register normal pci style */
4649 if (ata_pci_allocate(dev))
4650 return ENXIO;
4651
4652 if (ctlr->chip->cfg2 & SIIINTR)
4653 ch->hw.status = ata_cmd_status;
4654
4655 return 0;
4656 }
4657
4658 static int
4659 ata_cmd_status(device_t dev)
4660 {
4661 struct ata_channel *ch = device_get_softc(dev);
4662 u_int8_t reg71;
4663
4664 if (((reg71 = pci_read_config(device_get_parent(ch->dev), 0x71, 1)) &
4665 (ch->unit ? 0x08 : 0x04))) {
4666 pci_write_config(device_get_parent(ch->dev), 0x71,
4667 reg71 & ~(ch->unit ? 0x04 : 0x08), 1);
4668 return ata_pci_status(dev);
4669 }
4670 return 0;
4671 }
4672
4673 static void
4674 ata_cmd_setmode(device_t dev, int mode)
4675 {
4676 device_t gparent = GRANDPARENT(dev);
4677 struct ata_pci_controller *ctlr = device_get_softc(gparent);
4678 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
4679 struct ata_device *atadev = device_get_softc(dev);
4680 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
4681 int error;
4682
4683 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
4684
4685 mode = ata_check_80pin(dev, mode);
4686
4687 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
4688
4689 if (bootverbose)
4690 device_printf(dev, "%ssetting %s on %s chip\n",
4691 (error) ? "FAILURE " : "",
4692 ata_mode2str(mode), ctlr->chip->text);
4693 if (!error) {
4694 int treg = 0x54 + ((devno < 3) ? (devno << 1) : 7);
4695 int ureg = ch->unit ? 0x7b : 0x73;
4696
4697 if (mode >= ATA_UDMA0) {
4698 int udmatimings[][2] = { { 0x31, 0xc2 }, { 0x21, 0x82 },
4699 { 0x11, 0x42 }, { 0x25, 0x8a },
4700 { 0x15, 0x4a }, { 0x05, 0x0a } };
4701
4702 u_int8_t umode = pci_read_config(gparent, ureg, 1);
4703
4704 umode &= ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca);
4705 umode |= udmatimings[mode & ATA_MODE_MASK][ATA_DEV(atadev->unit)];
4706 pci_write_config(gparent, ureg, umode, 1);
4707 }
4708 else if (mode >= ATA_WDMA0) {
4709 int dmatimings[] = { 0x87, 0x32, 0x3f };
4710
4711 pci_write_config(gparent, treg, dmatimings[mode & ATA_MODE_MASK],1);
4712 pci_write_config(gparent, ureg,
4713 pci_read_config(gparent, ureg, 1) &
4714 ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1);
4715 }
4716 else {
4717 int piotimings[] = { 0xa9, 0x57, 0x44, 0x32, 0x3f };
4718 pci_write_config(gparent, treg,
4719 piotimings[(mode & ATA_MODE_MASK) - ATA_PIO0], 1);
4720 pci_write_config(gparent, ureg,
4721 pci_read_config(gparent, ureg, 1) &
4722 ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1);
4723 }
4724 atadev->mode = mode;
4725 }
4726 }
4727
4728 static int
4729 ata_sii_allocate(device_t dev)
4730 {
4731 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4732 struct ata_channel *ch = device_get_softc(dev);
4733 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2);
4734 int i;
4735
4736 for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
4737 ch->r_io[i].res = ctlr->r_res2;
4738 ch->r_io[i].offset = 0x80 + i + (unit01 << 6) + (unit10 << 8);
4739 }
4740 ch->r_io[ATA_CONTROL].res = ctlr->r_res2;
4741 ch->r_io[ATA_CONTROL].offset = 0x8a + (unit01 << 6) + (unit10 << 8);
4742 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2;
4743 ata_default_registers(dev);
4744
4745 ch->r_io[ATA_BMCMD_PORT].res = ctlr->r_res2;
4746 ch->r_io[ATA_BMCMD_PORT].offset = 0x00 + (unit01 << 3) + (unit10 << 8);
4747 ch->r_io[ATA_BMSTAT_PORT].res = ctlr->r_res2;
4748 ch->r_io[ATA_BMSTAT_PORT].offset = 0x02 + (unit01 << 3) + (unit10 << 8);
4749 ch->r_io[ATA_BMDTP_PORT].res = ctlr->r_res2;
4750 ch->r_io[ATA_BMDTP_PORT].offset = 0x04 + (unit01 << 3) + (unit10 << 8);
4751
4752 if (ctlr->chip->max_dma >= ATA_SA150) {
4753 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
4754 ch->r_io[ATA_SSTATUS].offset = 0x104 + (unit01 << 7) + (unit10 << 8);
4755 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
4756 ch->r_io[ATA_SERROR].offset = 0x108 + (unit01 << 7) + (unit10 << 8);
4757 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
4758 ch->r_io[ATA_SCONTROL].offset = 0x100 + (unit01 << 7) + (unit10 << 8);
4759 ch->flags |= ATA_NO_SLAVE;
4760
4761 /* enable PHY state change interrupt */
4762 ATA_OUTL(ctlr->r_res2, 0x148 + (unit01 << 7) + (unit10 << 8),(1 << 16));
4763 }
4764
4765 if ((ctlr->chip->cfg2 & SIIBUG) && ch->dma) {
4766 /* work around errata in early chips */
4767 ch->dma->boundary = 16 * DEV_BSIZE;
4768 ch->dma->segsize = 15 * DEV_BSIZE;
4769 }
4770
4771 ata_pci_hw(dev);
4772 ch->hw.status = ata_sii_status;
4773 return 0;
4774 }
4775
4776 static int
4777 ata_sii_status(device_t dev)
4778 {
4779 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4780 struct ata_channel *ch = device_get_softc(dev);
4781 int offset0 = ((ch->unit & 1) << 3) + ((ch->unit & 2) << 8);
4782 int offset1 = ((ch->unit & 1) << 6) + ((ch->unit & 2) << 8);
4783
4784 /* do we have any PHY events ? */
4785 if (ctlr->chip->max_dma >= ATA_SA150 &&
4786 (ATA_INL(ctlr->r_res2, 0x10 + offset0) & 0x00000010))
4787 ata_sata_phy_check_events(dev);
4788
4789 if (ATA_INL(ctlr->r_res2, 0xa0 + offset1) & 0x00000800)
4790 return ata_pci_status(dev);
4791 else
4792 return 0;
4793 }
4794
4795 static void
4796 ata_sii_reset(device_t dev)
4797 {
4798 if (ata_sata_phy_reset(dev))
4799 ata_generic_reset(dev);
4800 }
4801
4802 static void
4803 ata_sii_setmode(device_t dev, int mode)
4804 {
4805 device_t gparent = GRANDPARENT(dev);
4806 struct ata_pci_controller *ctlr = device_get_softc(gparent);
4807 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
4808 struct ata_device *atadev = device_get_softc(dev);
4809 int rego = (ch->unit << 4) + (ATA_DEV(atadev->unit) << 1);
4810 int mreg = ch->unit ? 0x84 : 0x80;
4811 int mask = 0x03 << (ATA_DEV(atadev->unit) << 2);
4812 int mval = pci_read_config(gparent, mreg, 1) & ~mask;
4813 int error;
4814
4815 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
4816
4817 if (ctlr->chip->cfg2 & SIISETCLK) {
4818 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x79, 1) &
4819 (ch->unit ? 0x02 : 0x01))) {
4820 ata_print_cable(dev, "controller");
4821 mode = ATA_UDMA2;
4822 }
4823 }
4824 else
4825 mode = ata_check_80pin(dev, mode);
4826
4827 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
4828
4829 if (bootverbose)
4830 device_printf(dev, "%ssetting %s on %s chip\n",
4831 (error) ? "FAILURE " : "",
4832 ata_mode2str(mode), ctlr->chip->text);
4833 if (error)
4834 return;
4835
4836 if (mode >= ATA_UDMA0) {
4837 u_int8_t udmatimings[] = { 0xf, 0xb, 0x7, 0x5, 0x3, 0x2, 0x1 };
4838 u_int8_t ureg = 0xac + rego;
4839
4840 pci_write_config(gparent, mreg,
4841 mval | (0x03 << (ATA_DEV(atadev->unit) << 2)), 1);
4842 pci_write_config(gparent, ureg,
4843 (pci_read_config(gparent, ureg, 1) & ~0x3f) |
4844 udmatimings[mode & ATA_MODE_MASK], 1);
4845
4846 }
4847 else if (mode >= ATA_WDMA0) {
4848 u_int8_t dreg = 0xa8 + rego;
4849 u_int16_t dmatimings[] = { 0x2208, 0x10c2, 0x10c1 };
4850
4851 pci_write_config(gparent, mreg,
4852 mval | (0x02 << (ATA_DEV(atadev->unit) << 2)), 1);
4853 pci_write_config(gparent, dreg, dmatimings[mode & ATA_MODE_MASK], 2);
4854
4855 }
4856 else {
4857 u_int8_t preg = 0xa4 + rego;
4858 u_int16_t piotimings[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
4859
4860 pci_write_config(gparent, mreg,
4861 mval | (0x01 << (ATA_DEV(atadev->unit) << 2)), 1);
4862 pci_write_config(gparent, preg, piotimings[mode & ATA_MODE_MASK], 2);
4863 }
4864 atadev->mode = mode;
4865 }
4866
4867 struct ata_siiprb_dma_prdentry {
4868 u_int64_t addr;
4869 u_int32_t count;
4870 u_int32_t control;
4871 } __packed;
4872
4873 struct ata_siiprb_ata_command {
4874 u_int32_t reserved0;
4875 struct ata_siiprb_dma_prdentry prd[126];
4876 } __packed;
4877
4878 struct ata_siiprb_atapi_command {
4879 u_int8_t cdb[16];
4880 struct ata_siiprb_dma_prdentry prd[125];
4881 } __packed;
4882
4883 struct ata_siiprb_command {
4884 u_int16_t control;
4885 u_int16_t protocol_override;
4886 u_int32_t transfer_count;
4887 u_int8_t fis[20];
4888 union {
4889 struct ata_siiprb_ata_command ata;
4890 struct ata_siiprb_atapi_command atapi;
4891 } u;
4892 } __packed;
4893
4894 static int
4895 ata_siiprb_allocate(device_t dev)
4896 {
4897 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4898 struct ata_channel *ch = device_get_softc(dev);
4899 int offset = ch->unit * 0x2000;
4900
4901 /* set the SATA resources */
4902 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
4903 ch->r_io[ATA_SSTATUS].offset = 0x1f04 + offset;
4904 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
4905 ch->r_io[ATA_SERROR].offset = 0x1f08 + offset;
4906 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
4907 ch->r_io[ATA_SCONTROL].offset = 0x1f00 + offset;
4908 ch->r_io[ATA_SACTIVE].res = ctlr->r_res2;
4909 ch->r_io[ATA_SACTIVE].offset = 0x1f0c + offset;
4910
4911 ch->hw.begin_transaction = ata_siiprb_begin_transaction;
4912 ch->hw.end_transaction = ata_siiprb_end_transaction;
4913 ch->hw.status = ata_siiprb_status;
4914 ch->hw.command = NULL; /* not used here */
4915 return 0;
4916 }
4917
4918 static int
4919 ata_siiprb_status(device_t dev)
4920 {
4921 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4922 struct ata_channel *ch = device_get_softc(dev);
4923 int offset = ch->unit * 0x2000;
4924
4925 if ((ATA_INL(ctlr->r_res1, 0x0044) & (1 << ch->unit))) {
4926 u_int32_t istatus = ATA_INL(ctlr->r_res2, 0x1008 + offset);
4927
4928 /* do we have any PHY events ? */
4929 ata_sata_phy_check_events(dev);
4930
4931 /* clear interrupt(s) */
4932 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, istatus);
4933
4934 /* do we have any device action ? */
4935 return (istatus & 0x00000001);
4936 }
4937 return 0;
4938 }
4939
4940 static int
4941 ata_siiprb_begin_transaction(struct ata_request *request)
4942 {
4943 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
4944 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
4945 struct ata_siiprb_command *prb;
4946 int offset = ch->unit * 0x2000;
4947 u_int64_t prb_bus;
4948 int tag = 0, dummy;
4949
4950 /* check for 48 bit access and convert if needed */
4951 ata_modify_if_48bit(request);
4952
4953 /* get a piece of the workspace for this request */
4954 prb = (struct ata_siiprb_command *)
4955 (ch->dma->work + (sizeof(struct ata_siiprb_command) * tag));
4956
4957 /* set basic prd options ata/atapi etc etc */
4958 bzero(prb, sizeof(struct ata_siiprb_command));
4959
4960 /* setup the FIS for this request */
4961 if (!ata_request2fis_h2d(request, &prb->fis[0])) {
4962 device_printf(request->dev, "setting up SATA FIS failed\n");
4963 request->result = EIO;
4964 return ATA_OP_FINISHED;
4965 }
4966
4967 /* if request moves data setup and load SG list */
4968 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) {
4969 struct ata_siiprb_dma_prdentry *prd;
4970
4971 if (request->flags & ATA_R_ATAPI)
4972 prd = &prb->u.atapi.prd[0];
4973 else
4974 prd = &prb->u.ata.prd[0];
4975 if (ch->dma->load(ch->dev, request->data, request->bytecount,
4976 request->flags & ATA_R_READ, prd, &dummy)) {
4977 device_printf(request->dev, "setting up DMA failed\n");
4978 request->result = EIO;
4979 return ATA_OP_FINISHED;
4980 }
4981 }
4982
4983 /* activate the prb */
4984 prb_bus = ch->dma->work_bus + (sizeof(struct ata_siiprb_command) * tag);
4985 ATA_OUTL(ctlr->r_res2,
4986 0x1c00 + offset + (tag * sizeof(u_int64_t)), prb_bus);
4987 ATA_OUTL(ctlr->r_res2,
4988 0x1c04 + offset + (tag * sizeof(u_int64_t)), prb_bus>>32);
4989
4990 /* start the timeout */
4991 callout_reset(&request->callout, request->timeout * hz,
4992 (timeout_t*)ata_timeout, request);
4993 return ATA_OP_CONTINUES;
4994 }
4995
4996 static int
4997 ata_siiprb_end_transaction(struct ata_request *request)
4998 {
4999 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
5000 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
5001 struct ata_siiprb_command *prb;
5002 int offset = ch->unit * 0x2000;
5003 int error, tag = 0;
5004
5005 /* kill the timeout */
5006 callout_stop(&request->callout);
5007
5008 prb = (struct ata_siiprb_command *)
5009 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + (tag << 7) + offset);
5010
5011 /* if error status get details */
5012 request->status = prb->fis[2];
5013 if (request->status & ATA_S_ERROR)
5014 request->error = prb->fis[3];
5015
5016 /* update progress */
5017 if (!(request->status & ATA_S_ERROR) && !(request->flags & ATA_R_TIMEOUT)) {
5018 if (request->flags & ATA_R_READ)
5019 request->donecount = prb->transfer_count;
5020 else
5021 request->donecount = request->bytecount;
5022 }
5023
5024 /* any controller errors flagged ? */
5025 if ((error = ATA_INL(ctlr->r_res2, 0x1024 + offset))) {
5026 kprintf("ata_siiprb_end_transaction %s error=%08x\n",
5027 ata_cmd2str(request), error);
5028 }
5029
5030 /* release SG list etc */
5031 ch->dma->unload(ch->dev);
5032
5033 return ATA_OP_FINISHED;
5034 }
5035
5036 static void
5037 ata_siiprb_reset(device_t dev)
5038 {
5039 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
5040 struct ata_channel *ch = device_get_softc(dev);
5041 int offset = ch->unit * 0x2000;
5042 struct ata_siiprb_command *prb;
5043 u_int64_t prb_bus;
5044 u_int32_t status, signature;
5045 int timeout, tag = 0;
5046
5047 /* reset channel HW */
5048 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000001);
5049 DELAY(1000);
5050 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000001);
5051 DELAY(10000);
5052
5053 /* poll for channel ready */
5054 for (timeout = 0; timeout < 1000; timeout++) {
5055 if ((status = ATA_INL(ctlr->r_res2, 0x1000 + offset)) & 0x00040000)
5056 break;
5057 DELAY(1000);
5058 }
5059 if (timeout >= 1000) {
5060 device_printf(ch->dev, "channel HW reset timeout reset failure\n");
5061 ch->devices = 0;
5062 goto finish;
5063 }
5064 if (bootverbose)
5065 device_printf(ch->dev, "channel HW reset time=%dms\n", timeout * 1);
5066
5067 /* reset phy */
5068 if (!ata_sata_phy_reset(dev)) {
5069 if (bootverbose)
5070 device_printf(ch->dev, "phy reset found no device\n");
5071 ch->devices = 0;
5072 goto finish;
5073 }
5074
5075 /* get a piece of the workspace for a soft reset request */
5076 prb = (struct ata_siiprb_command *)
5077 (ch->dma->work + (sizeof(struct ata_siiprb_command) * tag));
5078 bzero(prb, sizeof(struct ata_siiprb_command));
5079 prb->control = htole16(0x0080);
5080
5081 /* activate the soft reset prb */
5082 prb_bus = ch->dma->work_bus + (sizeof(struct ata_siiprb_command) * tag);
5083 ATA_OUTL(ctlr->r_res2,
5084 0x1c00 + offset + (tag * sizeof(u_int64_t)), prb_bus);
5085 ATA_OUTL(ctlr->r_res2,
5086 0x1c04 + offset + (tag * sizeof(u_int64_t)), prb_bus>>32);
5087
5088 /* poll for channel ready */
5089 for (timeout = 0; timeout < 1000; timeout++) {
5090 DELAY(1000);
5091 if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00010000)
5092 break;
5093 }
5094 if (timeout >= 1000) {
5095 device_printf(ch->dev, "reset timeout - no device found\n");
5096 ch->devices = 0;
5097 goto finish;
5098 }
5099 if (bootverbose)
5100 device_printf(ch->dev, "soft reset exec time=%dms status=%08x\n",
5101 timeout, status);
5102
5103 /* find out whats there */
5104 prb = (struct ata_siiprb_command *)
5105 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + (tag << 7) + offset);
5106 signature =
5107 prb->fis[12]|(prb->fis[4]<<8)|(prb->fis[5]<<16)|(prb->fis[6]<<24);
5108 if (bootverbose)
5109 device_printf(ch->dev, "signature=%08x\n", signature);
5110 switch (signature) {
5111 case 0xeb140101:
5112 ch->devices = ATA_ATAPI_MASTER;
5113 device_printf(ch->dev, "SATA ATAPI devices not supported yet\n");
5114 ch->devices = 0;
5115 break;
5116 case 0x96690101:
5117 ch->devices = ATA_PORTMULTIPLIER;
5118 device_printf(ch->dev, "Portmultipliers not supported yet\n");
5119 ch->devices = 0;
5120 break;
5121 case 0x00000101:
5122 ch->devices = ATA_ATA_MASTER;
5123 break;
5124 default:
5125 ch->devices = 0;
5126 }
5127
5128 finish:
5129 /* clear interrupt(s) */
5130 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x000008ff);
5131
5132 /* require explicit interrupt ack */
5133 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000008);
5134
5135 /* 64bit mode */
5136 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000400);
5137
5138 /* enable interrupts wanted */
5139 ATA_OUTL(ctlr->r_res2, 0x1010 + offset, 0x000000ff);
5140 }
5141
5142 static void
5143 ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
5144 {
5145 struct ata_dmasetprd_args *args = xsc;
5146 struct ata_siiprb_dma_prdentry *prd = args->dmatab;
5147 int i;
5148
5149 if ((args->error = error))
5150 return;
5151
5152 for (i = 0; i < nsegs; i++) {
5153 prd[i].addr = htole64(segs[i].ds_addr);
5154 prd[i].count = htole32(segs[i].ds_len);
5155 }
5156 prd[i - 1].control = htole32(ATA_DMA_EOT);
5157 }
5158
5159 static void
5160 ata_siiprb_dmainit(device_t dev)
5161 {
5162 struct ata_channel *ch = device_get_softc(dev);
5163
5164 ata_dmainit(dev);
5165 if (ch->dma) {
5166 /* note start and stop are not used here */
5167 ch->dma->setprd = ata_siiprb_dmasetprd;
5168 ch->dma->max_address = BUS_SPACE_MAXADDR;
5169 }
5170 }
5171
5172
5173 /*
5174 * Silicon Integrated Systems Corp. (SiS) chipset support functions
5175 */
5176 int
5177 ata_sis_ident(device_t dev)
5178 {
5179 struct ata_pci_controller *ctlr = device_get_softc(dev);
5180 struct ata_chip_id *idx;
5181 static struct ata_chip_id ids[] =
5182 {{ ATA_SIS182, 0x00, SISSATA, 0, ATA_SA150, "182" }, /* south */
5183 { ATA_SIS181, 0x00, SISSATA, 0, ATA_SA150, "181" }, /* south */
5184 { ATA_SIS180, 0x00, SISSATA, 0, ATA_SA150, "180" }, /* south */
5185 { ATA_SIS965, 0x00, SIS133NEW, 0, ATA_UDMA6, "965" }, /* south */
5186 { ATA_SIS964, 0x00, SIS133NEW, 0, ATA_UDMA6, "964" }, /* south */
5187 { ATA_SIS963, 0x00, SIS133NEW, 0, ATA_UDMA6, "963" }, /* south */
5188 { ATA_SIS962, 0x00, SIS133NEW, 0, ATA_UDMA6, "962" }, /* south */
5189
5190 { ATA_SIS745, 0x00, SIS100NEW, 0, ATA_UDMA5, "745" }, /* 1chip */
5191 { ATA_SIS735, 0x00, SIS100NEW, 0, ATA_UDMA5, "735" }, /* 1chip */
5192 { ATA_SIS733, 0x00, SIS100NEW, 0, ATA_UDMA5, "733" }, /* 1chip */
5193 { ATA_SIS730, 0x00, SIS100OLD, 0, ATA_UDMA5, "730" }, /* 1chip */
5194
5195 { ATA_SIS635, 0x00, SIS100NEW, 0, ATA_UDMA5, "635" }, /* 1chip */
5196 { ATA_SIS633, 0x00, SIS100NEW, 0, ATA_UDMA5, "633" }, /* unknown */
5197 { ATA_SIS630, 0x30, SIS100OLD, 0, ATA_UDMA5, "630S"}, /* 1chip */
5198 { ATA_SIS630, 0x00, SIS66, 0, ATA_UDMA4, "630" }, /* 1chip */
5199 { ATA_SIS620, 0x00, SIS66, 0, ATA_UDMA4, "620" }, /* 1chip */
5200
5201 { ATA_SIS550, 0x00, SIS66, 0, ATA_UDMA5, "550" },
5202 { ATA_SIS540, 0x00, SIS66, 0, ATA_UDMA4, "540" },
5203 { ATA_SIS530, 0x00, SIS66, 0, ATA_UDMA4, "530" },
5204
5205 { ATA_SIS5513, 0xc2, SIS33, 1, ATA_UDMA2, "5513" },
5206 { ATA_SIS5513, 0x00, SIS33, 1, ATA_WDMA2, "5513" },
5207 { 0, 0, 0, 0, 0, 0 }};
5208 char buffer[64];
5209 int found = 0;
5210
5211 if (!(idx = ata_find_chip(dev, ids, -pci_get_slot(dev))))
5212 return ENXIO;
5213
5214 if (idx->cfg2 && !found) {
5215 u_int8_t reg57 = pci_read_config(dev, 0x57, 1);
5216
5217 pci_write_config(dev, 0x57, (reg57 & 0x7f), 1);
5218 if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == ATA_SIS5518) {
5219 found = 1;
5220 idx->cfg1 = SIS133NEW;
5221 idx->max_dma = ATA_UDMA6;
5222 ksprintf(buffer, "SiS 962/963 %s controller",
5223 ata_mode2str(idx->max_dma));
5224 }
5225 pci_write_config(dev, 0x57, reg57, 1);
5226 }
5227 if (idx->cfg2 && !found) {
5228 u_int8_t reg4a = pci_read_config(dev, 0x4a, 1);
5229
5230 pci_write_config(dev, 0x4a, (reg4a | 0x10), 1);
5231 if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == ATA_SIS5517) {
5232 struct ata_chip_id id[] =
5233 {{ ATA_SISSOUTH, 0x10, 0, 0, 0, "" }, { 0, 0, 0, 0, 0, 0 }};
5234
5235 found = 1;
5236 if (ata_find_chip(dev, id, pci_get_slot(dev))) {
5237 idx->cfg1 = SIS133OLD;
5238 idx->max_dma = ATA_UDMA6;
5239 }
5240 else {
5241 idx->cfg1 = SIS100NEW;
5242 idx->max_dma = ATA_UDMA5;
5243 }
5244 ksprintf(buffer, "SiS 961 %s controller",ata_mode2str(idx->max_dma));
5245 }
5246 pci_write_config(dev, 0x4a, reg4a, 1);
5247 }
5248 if (!found)
5249 ksprintf(buffer,"SiS %s %s controller",
5250 idx->text, ata_mode2str(idx->max_dma));
5251
5252 device_set_desc_copy(dev, buffer);
5253 ctlr->chip = idx;
5254 ctlr->chipinit = ata_sis_chipinit;
5255 return 0;
5256 }
5257
5258 static int
5259 ata_sis_chipinit(device_t dev)
5260 {
5261 struct ata_pci_controller *ctlr = device_get_softc(dev);
5262
5263 if (ata_setup_interrupt(dev))
5264 return ENXIO;
5265
5266 switch (ctlr->chip->cfg1) {
5267 case SIS33:
5268 break;
5269 case SIS66:
5270 case SIS100OLD:
5271 pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 1) & ~0x04, 1);
5272 break;
5273 case SIS100NEW:
5274 case SIS133OLD:
5275 pci_write_config(dev, 0x49, pci_read_config(dev, 0x49, 1) & ~0x01, 1);
5276 break;
5277 case SIS133NEW:
5278 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 2) | 0x0008, 2);
5279 pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 2) | 0x0008, 2);
5280 break;
5281 case SISSATA:
5282 ctlr->r_type2 = SYS_RES_IOPORT;
5283 ctlr->r_rid2 = PCIR_BAR(5);
5284 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
5285 &ctlr->r_rid2, RF_ACTIVE))) {
5286 ctlr->allocate = ata_sis_allocate;
5287 ctlr->reset = ata_sis_reset;
5288
5289 /* enable PCI interrupt */
5290 pci_write_config(dev, PCIR_COMMAND,
5291 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400,2);
5292 }
5293 ctlr->setmode = ata_sata_setmode;
5294 return 0;
5295 default:
5296 return ENXIO;
5297 }
5298 ctlr->setmode = ata_sis_setmode;
5299 return 0;
5300 }
5301
5302 static int
5303 ata_sis_allocate(device_t dev)
5304 {
5305 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
5306 struct ata_channel *ch = device_get_softc(dev);
5307 int offset = ch->unit << ((ctlr->chip->chipid == ATA_SIS182) ? 5 : 6);
5308
5309 /* setup the usual register normal pci style */
5310 if (ata_pci_allocate(dev))
5311 return ENXIO;
5312
5313 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
5314 ch->r_io[ATA_SSTATUS].offset = 0x00 + offset;
5315 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
5316 ch->r_io[ATA_SERROR].offset = 0x04 + offset;
5317 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
5318 ch->r_io[ATA_SCONTROL].offset = 0x08 + offset;
5319 ch->flags |= ATA_NO_SLAVE;
5320
5321 /* XXX SOS PHY hotplug handling missing in SiS chip ?? */
5322 /* XXX SOS unknown how to enable PHY state change interrupt */
5323 return 0;
5324 }
5325
5326 static void
5327 ata_sis_reset(device_t dev)
5328 {
5329 if (ata_sata_phy_reset(dev))
5330 ata_generic_reset(dev);
5331 }
5332
5333 static void
5334 ata_sis_setmode(device_t dev, int mode)
5335 {
5336 device_t gparent = GRANDPARENT(dev);
5337 struct ata_pci_controller *ctlr = device_get_softc(gparent);
5338 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
5339 struct ata_device *atadev = device_get_softc(dev);
5340 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
5341 int error;
5342
5343 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
5344
5345 if (ctlr->chip->cfg1 == SIS133NEW) {
5346 if (mode > ATA_UDMA2 &&
5347 pci_read_config(gparent, ch->unit ? 0x52 : 0x50,2) & 0x8000) {
5348 ata_print_cable(dev, "controller");
5349 mode = ATA_UDMA2;
5350 }
5351 }
5352 else {
5353 if (mode > ATA_UDMA2 &&
5354 pci_read_config(gparent, 0x48, 1)&(ch->unit ? 0x20 : 0x10)) {
5355 ata_print_cable(dev, "controller");
5356 mode = ATA_UDMA2;
5357 }
5358 }
5359
5360 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
5361
5362 if (bootverbose)
5363 device_printf(dev, "%ssetting %s on %s chip\n",
5364 (error) ? "FAILURE " : "",
5365 ata_mode2str(mode), ctlr->chip->text);
5366 if (!error) {
5367 switch (ctlr->chip->cfg1) {
5368 case SIS133NEW: {
5369 u_int32_t timings[] =
5370 { 0x28269008, 0x0c266008, 0x04263008, 0x0c0a3008, 0x05093008,
5371 0x22196008, 0x0c0a3008, 0x05093008, 0x050939fc, 0x050936ac,
5372 0x0509347c, 0x0509325c, 0x0509323c, 0x0509322c, 0x0509321c};
5373 u_int32_t reg;
5374
5375 reg = (pci_read_config(gparent, 0x57, 1)&0x40?0x70:0x40)+(devno<<2);
5376 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 4);
5377 break;
5378 }
5379 case SIS133OLD: {
5380 u_int16_t timings[] =
5381 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033, 0x0031,
5382 0x8f31, 0x8a31, 0x8731, 0x8531, 0x8331, 0x8231, 0x8131 };
5383
5384 u_int16_t reg = 0x40 + (devno << 1);
5385
5386 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2);
5387 break;
5388 }
5389 case SIS100NEW: {
5390 u_int16_t timings[] =
5391 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033,
5392 0x0031, 0x8b31, 0x8731, 0x8531, 0x8431, 0x8231, 0x8131 };
5393 u_int16_t reg = 0x40 + (devno << 1);
5394
5395 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2);
5396 break;
5397 }
5398 case SIS100OLD:
5399 case SIS66:
5400 case SIS33: {
5401 u_int16_t timings[] =
5402 { 0x0c0b, 0x0607, 0x0404, 0x0303, 0x0301, 0x0404, 0x0303,
5403 0x0301, 0xf301, 0xd301, 0xb301, 0xa301, 0x9301, 0x8301 };
5404 u_int16_t reg = 0x40 + (devno << 1);
5405
5406 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2);
5407 break;
5408 }
5409 }
5410 atadev->mode = mode;
5411 }
5412 }
5413
5414
5415 /* VIA Technologies Inc. chipset support functions */
5416 int
5417 ata_via_ident(device_t dev)
5418 {
5419 struct ata_pci_controller *ctlr = device_get_softc(dev);
5420 struct ata_chip_id *idx;
5421 static struct ata_chip_id ids[] =
5422 {{ ATA_VIA82C586, 0x02, VIA33, 0x00, ATA_UDMA2, "82C586B" },
5423 { ATA_VIA82C586, 0x00, VIA33, 0x00, ATA_WDMA2, "82C586" },
5424 { ATA_VIA82C596, 0x12, VIA66, VIACLK, ATA_UDMA4, "82C596B" },
5425 { ATA_VIA82C596, 0x00, VIA33, 0x00, ATA_UDMA2, "82C596" },
5426 { ATA_VIA82C686, 0x40, VIA100, VIABUG, ATA_UDMA5, "82C686B"},
5427 { ATA_VIA82C686, 0x10, VIA66, VIACLK, ATA_UDMA4, "82C686A" },
5428 { ATA_VIA82C686, 0x00, VIA33, 0x00, ATA_UDMA2, "82C686" },
5429 { ATA_VIA8231, 0x00, VIA100, VIABUG, ATA_UDMA5, "8231" },
5430 { ATA_VIA8233, 0x00, VIA100, 0x00, ATA_UDMA5, "8233" },
5431 { ATA_VIA8233C, 0x00, VIA100, 0x00, ATA_UDMA5, "8233C" },
5432 { ATA_VIA8233A, 0x00, VIA133, 0x00, ATA_UDMA6, "8233A" },
5433 { ATA_VIA8235, 0x00, VIA133, 0x00, ATA_UDMA6, "8235" },
5434 { ATA_VIA8237, 0x00, VIA133, 0x00, ATA_UDMA6, "8237" },
5435 { ATA_VIA8237A, 0x00, VIA133, 0x00, ATA_UDMA6, "8237A" },
5436 { ATA_VIA8251, 0x00, VIA133, 0x00, ATA_UDMA6, "8251" },
5437 { 0, 0, 0, 0, 0, 0 }};
5438 static struct ata_chip_id new_ids[] =
5439 {{ ATA_VIA6410, 0x00, 0, 0x00, ATA_UDMA6, "6410" },
5440 { ATA_VIA6420, 0x00, 7, 0x00, ATA_SA150, "6420" },
5441 { ATA_VIA6421, 0x00, 6, VIABAR, ATA_SA150, "6421" },
5442 { ATA_VIA8237A, 0x00, 7, 0x00, ATA_SA150, "8237A" },
5443 { ATA_VIA8237S, 0x00, 7, 0x00, ATA_SA150, "8237S" },
5444 { ATA_VIA8251, 0x00, 0, VIAAHCI, ATA_SA300, "8251" },
5445 { 0, 0, 0, 0, 0, 0 }};
5446 char buffer[64];
5447
5448 if (pci_get_devid(dev) == ATA_VIA82C571) {
5449 if (!(idx = ata_find_chip(dev, ids, -99)))
5450 return ENXIO;
5451 }
5452 else {
5453 if (!(idx = ata_match_chip(dev, new_ids)))
5454 return ENXIO;
5455 }
5456
5457 ksprintf(buffer, "VIA %s %s controller",
5458 idx->text, ata_mode2str(idx->max_dma));
5459 device_set_desc_copy(dev, buffer);
5460 ctlr->chip = idx;
5461 ctlr->chipinit = ata_via_chipinit;
5462 return 0;
5463 }
5464
5465 static int
5466 ata_via_chipinit(device_t dev)
5467 {
5468 struct ata_pci_controller *ctlr = device_get_softc(dev);
5469
5470 if (ata_setup_interrupt(dev))
5471 return ENXIO;
5472
5473 if (ctlr->chip->max_dma >= ATA_SA150) {
5474 /* do we have AHCI capability ? */
5475 if ((ctlr->chip->cfg2 == VIAAHCI) && ata_ahci_chipinit(dev) != ENXIO)
5476 return 0;
5477
5478 ctlr->r_type2 = SYS_RES_IOPORT;
5479 ctlr->r_rid2 = PCIR_BAR(5);
5480 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
5481 &ctlr->r_rid2, RF_ACTIVE))) {
5482 ctlr->allocate = ata_via_allocate;
5483 ctlr->reset = ata_via_reset;
5484
5485 /* enable PCI interrupt */
5486 pci_write_config(dev, PCIR_COMMAND,
5487 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400,2);
5488 }
5489
5490 if (ctlr->chip->cfg2 & VIABAR) {
5491 ctlr->channels = 3;
5492 ctlr->setmode = ata_via_setmode;
5493 }
5494 else
5495 ctlr->setmode = ata_sata_setmode;
5496 return 0;
5497 }
5498
5499 /* prepare for ATA-66 on the 82C686a and 82C596b */
5500 if (ctlr->chip->cfg2 & VIACLK)
5501 pci_write_config(dev, 0x50, 0x030b030b, 4);
5502
5503 /* the southbridge might need the data corruption fix */
5504 if (ctlr->chip->cfg2 & VIABUG)
5505 ata_via_southbridge_fixup(dev);
5506
5507 /* set fifo configuration half'n'half */
5508 pci_write_config(dev, 0x43,
5509 (pci_read_config(dev, 0x43, 1) & 0x90) | 0x2a, 1);
5510
5511 /* set status register read retry */
5512 pci_write_config(dev, 0x44, pci_read_config(dev, 0x44, 1) | 0x08, 1);
5513
5514 /* set DMA read & end-of-sector fifo flush */
5515 pci_write_config(dev, 0x46,
5516 (pci_read_config(dev, 0x46, 1) & 0x0c) | 0xf0, 1);
5517
5518 /* set sector size */
5519 pci_write_config(dev, 0x60, DEV_BSIZE, 2);
5520 pci_write_config(dev, 0x68, DEV_BSIZE, 2);
5521
5522 ctlr->setmode = ata_via_family_setmode;
5523 return 0;
5524 }
5525
5526 static int
5527 ata_via_allocate(device_t dev)
5528 {
5529 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
5530 struct ata_channel *ch = device_get_softc(dev);
5531
5532 /* newer SATA chips has resources in one BAR for each channel */
5533 if (ctlr->chip->cfg2 & VIABAR) {
5534 struct resource *r_io;
5535 int i, rid;
5536
5537 rid = PCIR_BAR(ch->unit);
5538 if (!(r_io = bus_alloc_resource_any(device_get_parent(dev),
5539 SYS_RES_IOPORT,
5540 &rid, RF_ACTIVE)))
5541 return ENXIO;
5542
5543 for (i = ATA_DATA; i <= ATA_COMMAND; i ++) {
5544 ch->r_io[i].res = r_io;
5545 ch->r_io[i].offset = i;
5546 }
5547 ch->r_io[ATA_CONTROL].res = r_io;
5548 ch->r_io[ATA_CONTROL].offset = 2 + ATA_IOSIZE;
5549 ch->r_io[ATA_IDX_ADDR].res = r_io;
5550 ata_default_registers(dev);
5551 for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) {
5552 ch->r_io[i].res = ctlr->r_res1;
5553 ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE);
5554 }
5555 ata_pci_hw(dev);
5556 if (ch->unit >= 2)
5557 return 0;
5558 }
5559 else {
5560 /* setup the usual register normal pci style */
5561 if (ata_pci_allocate(dev))
5562 return ENXIO;
5563 }
5564
5565 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
5566 ch->r_io[ATA_SSTATUS].offset = (ch->unit << ctlr->chip->cfg1);
5567 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
5568 ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << ctlr->chip->cfg1);
5569 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
5570 ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << ctlr->chip->cfg1);
5571 ch->flags |= ATA_NO_SLAVE;
5572
5573 /* XXX SOS PHY hotplug handling missing in VIA chip ?? */
5574 /* XXX SOS unknown how to enable PHY state change interrupt */
5575 return 0;
5576 }
5577
5578 static void
5579 ata_via_reset(device_t dev)
5580 {
5581 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
5582 struct ata_channel *ch = device_get_softc(dev);
5583
5584 if ((ctlr->chip->cfg2 & VIABAR) && (ch->unit > 1))
5585 ata_generic_reset(dev);
5586 else
5587 if (ata_sata_phy_reset(dev))
5588 ata_generic_reset(dev);
5589 }
5590
5591 static void
5592 ata_via_setmode(device_t dev, int mode)
5593 {
5594 device_t gparent = GRANDPARENT(dev);
5595 struct ata_pci_controller *ctlr = device_get_softc(gparent);
5596 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
5597 struct ata_device *atadev = device_get_softc(dev);
5598 int error;
5599
5600 if ((ctlr->chip->cfg2 & VIABAR) && (ch->unit > 1)) {
5601 u_int8_t pio_timings[] = { 0xa8, 0x65, 0x65, 0x32, 0x20,
5602 0x65, 0x32, 0x20,
5603 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
5604 u_int8_t dma_timings[] = { 0xee, 0xe8, 0xe6, 0xe4, 0xe2, 0xe1, 0xe0 };
5605
5606 mode = ata_check_80pin(dev, ata_limit_mode(dev, mode, ATA_UDMA6));
5607 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
5608 if (bootverbose)
5609 device_printf(dev, "%ssetting %s on %s chip\n",
5610 (error) ? "FAILURE " : "", ata_mode2str(mode),
5611 ctlr->chip->text);
5612 if (!error) {
5613 pci_write_config(gparent, 0xab, pio_timings[ata_mode2idx(mode)], 1);
5614 if (mode >= ATA_UDMA0)
5615 pci_write_config(gparent, 0xb3,
5616 dma_timings[mode & ATA_MODE_MASK], 1);
5617 atadev->mode = mode;
5618 }
5619 }
5620 else
5621 ata_sata_setmode(dev, mode);
5622 }
5623
5624 static void
5625 ata_via_southbridge_fixup(device_t dev)
5626 {
5627 device_t *children;
5628 int nchildren, i;
5629
5630 if (device_get_children(device_get_parent(dev), &children, &nchildren))
5631 return;
5632
5633 for (i = 0; i < nchildren; i++) {
5634 if (pci_get_devid(children[i]) == ATA_VIA8363 ||
5635 pci_get_devid(children[i]) == ATA_VIA8371 ||
5636 pci_get_devid(children[i]) == ATA_VIA8662 ||
5637 pci_get_devid(children[i]) == ATA_VIA8361) {
5638 u_int8_t reg76 = pci_read_config(children[i], 0x76, 1);
5639
5640 if ((reg76 & 0xf0) != 0xd0) {
5641 device_printf(dev,
5642 "Correcting VIA config for southbridge data corruption bug\n");
5643 pci_write_config(children[i], 0x75, 0x80, 1);
5644 pci_write_config(children[i], 0x76, (reg76 & 0x0f) | 0xd0, 1);
5645 }
5646 break;
5647 }
5648 }
5649 kfree(children, M_TEMP);
5650 }
5651
5652
5653 /* common code for VIA, AMD & nVidia */
5654 static void
5655 ata_via_family_setmode(device_t dev, int mode)
5656 {
5657 device_t gparent = GRANDPARENT(dev);
5658 struct ata_pci_controller *ctlr = device_get_softc(gparent);
5659 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
5660 struct ata_device *atadev = device_get_softc(dev);
5661 u_int8_t timings[] = { 0xa8, 0x65, 0x42, 0x22, 0x20, 0x42, 0x22, 0x20,
5662 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
5663 int modes[][7] = {
5664 { 0xc2, 0xc1, 0xc0, 0x00, 0x00, 0x00, 0x00 }, /* VIA ATA33 */
5665 { 0xee, 0xec, 0xea, 0xe9, 0xe8, 0x00, 0x00 }, /* VIA ATA66 */
5666 { 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0, 0x00 }, /* VIA ATA100 */
5667 { 0xf7, 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0 }, /* VIA ATA133 */
5668 { 0xc2, 0xc1, 0xc0, 0xc4, 0xc5, 0xc6, 0xc7 }}; /* AMD/nVIDIA */
5669 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
5670 int reg = 0x53 - devno;
5671 int error;
5672
5673 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
5674
5675 if (ctlr->chip->cfg2 & AMDCABLE) {
5676 if (mode > ATA_UDMA2 &&
5677 !(pci_read_config(gparent, 0x42, 1) & (1 << devno))) {
5678 ata_print_cable(dev, "controller");
5679 mode = ATA_UDMA2;
5680 }
5681 }
5682 else
5683 mode = ata_check_80pin(dev, mode);
5684
5685 if (ctlr->chip->cfg2 & NVIDIA)
5686 reg += 0x10;
5687
5688 if (ctlr->chip->cfg1 != VIA133)
5689 pci_write_config(gparent, reg - 0x08, timings[ata_mode2idx(mode)], 1);
5690
5691 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
5692
5693 if (bootverbose)
5694 device_printf(dev, "%ssetting %s on %s chip\n",
5695 (error) ? "FAILURE " : "", ata_mode2str(mode),
5696 ctlr->chip->text);
5697 if (!error) {
5698 if (mode >= ATA_UDMA0)
5699 pci_write_config(gparent, reg,
5700 modes[ctlr->chip->cfg1][mode & ATA_MODE_MASK], 1);
5701 else
5702 pci_write_config(gparent, reg, 0x8b, 1);
5703 atadev->mode = mode;
5704 }
5705 }
5706
5707
5708 /* misc functions */
5709 static struct ata_chip_id *
5710 ata_match_chip(device_t dev, struct ata_chip_id *index)
5711 {
5712 while (index->chipid != 0) {
5713 if (pci_get_devid(dev) == index->chipid &&
5714 pci_get_revid(dev) >= index->chiprev)
5715 return index;
5716 index++;
5717 }
5718 return NULL;
5719 }
5720
5721 static struct ata_chip_id *
5722 ata_find_chip(device_t dev, struct ata_chip_id *index, int slot)
5723 {
5724 device_t *children;
5725 int nchildren, i;
5726
5727 if (device_get_children(device_get_parent(dev), &children, &nchildren))
5728 return 0;
5729
5730 while (index->chipid != 0) {
5731 for (i = 0; i < nchildren; i++) {
5732 if (((slot >= 0 && pci_get_slot(children[i]) == slot) ||
5733 (slot < 0 && pci_get_slot(children[i]) <= -slot)) &&
5734 pci_get_devid(children[i]) == index->chipid &&
5735 pci_get_revid(children[i]) >= index->chiprev) {
5736 kfree(children, M_TEMP);
5737 return index;
5738 }
5739 }
5740 index++;
5741 }
5742 kfree(children, M_TEMP);
5743 return NULL;
5744 }
5745
5746 static int
5747 ata_setup_interrupt(device_t dev)
5748 {
5749 struct ata_pci_controller *ctlr = device_get_softc(dev);
5750 int rid = ATA_IRQ_RID;
5751
5752 if (!ctlr->legacy) {
5753 if (!(ctlr->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
5754 RF_SHAREABLE | RF_ACTIVE))) {
5755 device_printf(dev, "unable to map interrupt\n");
5756 return ENXIO;
5757 }
5758 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
5759 ata_generic_intr, ctlr, &ctlr->handle, NULL))) {
5760 device_printf(dev, "unable to setup interrupt\n");
5761 return ENXIO;
5762 }
5763 }
5764 return 0;
5765 }
5766
5767 struct ata_serialize {
5768 struct spinlock locked_mtx;
5769 int locked_ch;
5770 int restart_ch;
5771 };
5772
5773 static int
5774 ata_serialize(device_t dev, int flags)
5775 {
5776 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
5777 struct ata_channel *ch = device_get_softc(dev);
5778 struct ata_serialize *serial;
5779 static int inited = 0;
5780 int res;
5781
5782 if (!inited) {
5783 serial = kmalloc(sizeof(struct ata_serialize),
5784 M_TEMP, M_INTWAIT | M_ZERO);
5785 spin_init(&serial->locked_mtx);
5786 serial->locked_ch = -1;
5787 serial->restart_ch = -1;
5788 device_set_ivars(ctlr->dev, serial);
5789 inited = 1;
5790 }
5791 else
5792 serial = device_get_ivars(ctlr->dev);
5793
5794 spin_lock_wr(&serial->locked_mtx);
5795 switch (flags) {
5796 case ATA_LF_LOCK:
5797 if (serial->locked_ch == -1)
5798 serial->locked_ch = ch->unit;
5799 if (serial->locked_ch != ch->unit)
5800 serial->restart_ch = ch->unit;
5801 break;
5802
5803 case ATA_LF_UNLOCK:
5804 if (serial->locked_ch == ch->unit) {
5805 serial->locked_ch = -1;
5806 if (serial->restart_ch != -1) {
5807 if ((ch = ctlr->interrupt[serial->restart_ch].argument)) {
5808 serial->restart_ch = -1;
5809 spin_unlock_wr(&serial->locked_mtx);
5810 ata_start(ch->dev);
5811 return -1;
5812 }
5813 }
5814 }
5815 break;
5816
5817 case ATA_LF_WHICH:
5818 break;
5819 }
5820 res = serial->locked_ch;
5821 spin_unlock_wr(&serial->locked_mtx);
5822 return res;
5823 }
5824
5825 static void
5826 ata_print_cable(device_t dev, u_int8_t *who)
5827 {
5828 device_printf(dev,
5829 "DMA limited to UDMA33, %s found non-ATA66 cable\n", who);
5830 }
5831
5832 static int
5833 ata_atapi(device_t dev)
5834 {
5835 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
5836 struct ata_device *atadev = device_get_softc(dev);
5837
5838 return ((atadev->unit == ATA_MASTER && ch->devices & ATA_ATAPI_MASTER) ||
5839 (atadev->unit == ATA_SLAVE && ch->devices & ATA_ATAPI_SLAVE));
5840 }
5841
5842 static int
5843 ata_check_80pin(device_t dev, int mode)
5844 {
5845 struct ata_device *atadev = device_get_softc(dev);
5846
5847 if (mode > ATA_UDMA2 && !(atadev->param.hwres & ATA_CABLE_ID)) {
5848 ata_print_cable(dev, "device");
5849 mode = ATA_UDMA2;
5850 }
5851 return mode;
5852 }
5853
5854 static int
5855 ata_mode2idx(int mode)
5856 {
5857 if ((mode & ATA_DMA_MASK) == ATA_UDMA0)
5858 return (mode & ATA_MODE_MASK) + 8;
5859 if ((mode & ATA_DMA_MASK) == ATA_WDMA0)
5860 return (mode & ATA_MODE_MASK) + 5;
5861 return (mode & ATA_MODE_MASK) - ATA_PIO0;
5862 }
DragonFly BSD