2 * Copyright © 2010 Daniel Vetter
3 * Copyright © 2011-2014 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include <linux/seq_file.h>
28 #include <drm/i915_drm.h>
30 #include "i915_vgpu.h"
31 #include "i915_trace.h"
32 #include "intel_drv.h"
34 #include <linux/bitmap.h>
35 #include <linux/highmem.h>
38 * DOC: Global GTT views
40 * Background and previous state
42 * Historically objects could exists (be bound) in global GTT space only as
43 * singular instances with a view representing all of the object's backing pages
44 * in a linear fashion. This view will be called a normal view.
46 * To support multiple views of the same object, where the number of mapped
47 * pages is not equal to the backing store, or where the layout of the pages
48 * is not linear, concept of a GGTT view was added.
50 * One example of an alternative view is a stereo display driven by a single
51 * image. In this case we would have a framebuffer looking like this
57 * Above would represent a normal GGTT view as normally mapped for GPU or CPU
58 * rendering. In contrast, fed to the display engine would be an alternative
59 * view which could look something like this:
64 * In this example both the size and layout of pages in the alternative view is
65 * different from the normal view.
67 * Implementation and usage
69 * GGTT views are implemented using VMAs and are distinguished via enum
70 * i915_ggtt_view_type and struct i915_ggtt_view.
72 * A new flavour of core GEM functions which work with GGTT bound objects were
73 * added with the _ggtt_ infix, and sometimes with _view postfix to avoid
74 * renaming in large amounts of code. They take the struct i915_ggtt_view
75 * parameter encapsulating all metadata required to implement a view.
77 * As a helper for callers which are only interested in the normal view,
78 * globally const i915_ggtt_view_normal singleton instance exists. All old core
79 * GEM API functions, the ones not taking the view parameter, are operating on,
80 * or with the normal GGTT view.
82 * Code wanting to add or use a new GGTT view needs to:
84 * 1. Add a new enum with a suitable name.
85 * 2. Extend the metadata in the i915_ggtt_view structure if required.
86 * 3. Add support to i915_get_vma_pages().
88 * New views are required to build a scatter-gather table from within the
89 * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and
90 * exists for the lifetime of an VMA.
92 * Core API is designed to have copy semantics which means that passed in
93 * struct i915_ggtt_view does not need to be persistent (left around after
94 * calling the core API functions).
99 i915_get_ggtt_vma_pages(struct i915_vma
*vma
);
101 const struct i915_ggtt_view i915_ggtt_view_normal
;
102 const struct i915_ggtt_view i915_ggtt_view_rotated
= {
103 .type
= I915_GGTT_VIEW_ROTATED
106 static int sanitize_enable_ppgtt(struct drm_device
*dev
, int enable_ppgtt
)
108 bool has_aliasing_ppgtt
;
111 has_aliasing_ppgtt
= INTEL_INFO(dev
)->gen
>= 6;
112 has_full_ppgtt
= INTEL_INFO(dev
)->gen
>= 7;
114 if (intel_vgpu_active(dev
))
115 has_full_ppgtt
= false; /* emulation is too hard */
118 * We don't allow disabling PPGTT for gen9+ as it's a requirement for
119 * execlists, the sole mechanism available to submit work.
121 if (INTEL_INFO(dev
)->gen
< 9 &&
122 (enable_ppgtt
== 0 || !has_aliasing_ppgtt
))
125 if (enable_ppgtt
== 1)
128 if (enable_ppgtt
== 2 && has_full_ppgtt
)
131 #ifdef CONFIG_INTEL_IOMMU
132 /* Disable ppgtt on SNB if VT-d is on. */
133 if (INTEL_INFO(dev
)->gen
== 6 && intel_iommu_gfx_mapped
) {
134 DRM_INFO("Disabling PPGTT because VT-d is on\n");
139 /* Early VLV doesn't have this */
140 if (IS_VALLEYVIEW(dev
) && !IS_CHERRYVIEW(dev
) &&
141 dev
->pdev
->revision
< 0xb) {
142 DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
146 if (INTEL_INFO(dev
)->gen
>= 8 && i915
.enable_execlists
)
149 return has_aliasing_ppgtt
? 1 : 0;
152 static int ppgtt_bind_vma(struct i915_vma
*vma
,
153 enum i915_cache_level cache_level
,
158 /* Currently applicable only to VLV */
160 pte_flags
|= PTE_READ_ONLY
;
162 vma
->vm
->insert_entries(vma
->vm
, vma
->obj
->pages
, vma
->node
.start
,
163 cache_level
, pte_flags
);
168 static void ppgtt_unbind_vma(struct i915_vma
*vma
)
170 vma
->vm
->clear_range(vma
->vm
,
176 static gen8_pte_t
gen8_pte_encode(dma_addr_t addr
,
177 enum i915_cache_level level
,
180 gen8_pte_t pte
= valid
? _PAGE_PRESENT
| _PAGE_RW
: 0;
184 case I915_CACHE_NONE
:
185 pte
|= PPAT_UNCACHED_INDEX
;
188 pte
|= PPAT_DISPLAY_ELLC_INDEX
;
191 pte
|= PPAT_CACHED_INDEX
;
198 static gen8_pde_t
gen8_pde_encode(const dma_addr_t addr
,
199 const enum i915_cache_level level
)
201 gen8_pde_t pde
= _PAGE_PRESENT
| _PAGE_RW
;
203 if (level
!= I915_CACHE_NONE
)
204 pde
|= PPAT_CACHED_PDE_INDEX
;
206 pde
|= PPAT_UNCACHED_INDEX
;
210 static gen6_pte_t
snb_pte_encode(dma_addr_t addr
,
211 enum i915_cache_level level
,
212 bool valid
, u32 unused
)
214 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
215 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
218 case I915_CACHE_L3_LLC
:
220 pte
|= GEN6_PTE_CACHE_LLC
;
222 case I915_CACHE_NONE
:
223 pte
|= GEN6_PTE_UNCACHED
;
232 static gen6_pte_t
ivb_pte_encode(dma_addr_t addr
,
233 enum i915_cache_level level
,
234 bool valid
, u32 unused
)
236 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
237 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
240 case I915_CACHE_L3_LLC
:
241 pte
|= GEN7_PTE_CACHE_L3_LLC
;
244 pte
|= GEN6_PTE_CACHE_LLC
;
246 case I915_CACHE_NONE
:
247 pte
|= GEN6_PTE_UNCACHED
;
256 static gen6_pte_t
byt_pte_encode(dma_addr_t addr
,
257 enum i915_cache_level level
,
258 bool valid
, u32 flags
)
260 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
261 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
263 if (!(flags
& PTE_READ_ONLY
))
264 pte
|= BYT_PTE_WRITEABLE
;
266 if (level
!= I915_CACHE_NONE
)
267 pte
|= BYT_PTE_SNOOPED_BY_CPU_CACHES
;
272 static gen6_pte_t
hsw_pte_encode(dma_addr_t addr
,
273 enum i915_cache_level level
,
274 bool valid
, u32 unused
)
276 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
277 pte
|= HSW_PTE_ADDR_ENCODE(addr
);
279 if (level
!= I915_CACHE_NONE
)
280 pte
|= HSW_WB_LLC_AGE3
;
285 static gen6_pte_t
iris_pte_encode(dma_addr_t addr
,
286 enum i915_cache_level level
,
287 bool valid
, u32 unused
)
289 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
290 pte
|= HSW_PTE_ADDR_ENCODE(addr
);
293 case I915_CACHE_NONE
:
296 pte
|= HSW_WT_ELLC_LLC_AGE3
;
299 pte
|= HSW_WB_ELLC_LLC_AGE3
;
306 static int __setup_page_dma(struct drm_device
*dev
,
307 struct i915_page_dma
*p
, gfp_t flags
)
309 struct device
*device
= dev
->pdev
->dev
;
311 p
->page
= alloc_page(flags
);
315 p
->daddr
= dma_map_page(device
,
316 p
->page
, 0, 4096, PCI_DMA_BIDIRECTIONAL
);
318 if (dma_mapping_error(device
, p
->daddr
)) {
319 __free_page(p
->page
);
326 static int setup_page_dma(struct drm_device
*dev
, struct i915_page_dma
*p
)
328 return __setup_page_dma(dev
, p
, GFP_KERNEL
);
331 static void cleanup_page_dma(struct drm_device
*dev
, struct i915_page_dma
*p
)
333 if (WARN_ON(!p
->page
))
336 dma_unmap_page(dev
->pdev
->dev
, p
->daddr
, 4096, PCI_DMA_BIDIRECTIONAL
);
337 __free_page(p
->page
);
338 memset(p
, 0, sizeof(*p
));
341 static void *kmap_page_dma(struct i915_page_dma
*p
)
343 return kmap_atomic(p
->page
);
346 /* We use the flushing unmap only with ppgtt structures:
347 * page directories, page tables and scratch pages.
349 static void kunmap_page_dma(struct drm_device
*dev
, void *vaddr
)
351 /* There are only few exceptions for gen >=6. chv and bxt.
352 * And we are not sure about the latter so play safe for now.
354 if (IS_CHERRYVIEW(dev
) || IS_BROXTON(dev
))
355 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
357 kunmap_atomic(vaddr
);
360 #define kmap_px(px) kmap_page_dma(px_base(px))
361 #define kunmap_px(ppgtt, vaddr) kunmap_page_dma((ppgtt)->base.dev, (vaddr))
363 #define setup_px(dev, px) setup_page_dma((dev), px_base(px))
364 #define cleanup_px(dev, px) cleanup_page_dma((dev), px_base(px))
365 #define fill_px(dev, px, v) fill_page_dma((dev), px_base(px), (v))
366 #define fill32_px(dev, px, v) fill_page_dma_32((dev), px_base(px), (v))
368 static void fill_page_dma(struct drm_device
*dev
, struct i915_page_dma
*p
,
372 uint64_t * const vaddr
= kmap_page_dma(p
);
374 for (i
= 0; i
< 512; i
++)
377 kunmap_page_dma(dev
, vaddr
);
380 static void fill_page_dma_32(struct drm_device
*dev
, struct i915_page_dma
*p
,
381 const uint32_t val32
)
387 fill_page_dma(dev
, p
, v
);
390 static struct i915_page_scratch
*alloc_scratch_page(struct drm_device
*dev
)
392 struct i915_page_scratch
*sp
;
395 sp
= kzalloc(sizeof(*sp
), GFP_KERNEL
);
397 return ERR_PTR(-ENOMEM
);
399 ret
= __setup_page_dma(dev
, px_base(sp
), GFP_DMA32
| __GFP_ZERO
);
405 set_pages_uc(px_page(sp
), 1);
410 static void free_scratch_page(struct drm_device
*dev
,
411 struct i915_page_scratch
*sp
)
413 set_pages_wb(px_page(sp
), 1);
419 static struct i915_page_table
*alloc_pt(struct drm_device
*dev
)
421 struct i915_page_table
*pt
;
422 const size_t count
= INTEL_INFO(dev
)->gen
>= 8 ?
423 GEN8_PTES
: GEN6_PTES
;
426 pt
= kzalloc(sizeof(*pt
), GFP_KERNEL
);
428 return ERR_PTR(-ENOMEM
);
430 pt
->used_ptes
= kcalloc(BITS_TO_LONGS(count
), sizeof(*pt
->used_ptes
),
436 ret
= setup_px(dev
, pt
);
443 kfree(pt
->used_ptes
);
450 static void free_pt(struct drm_device
*dev
, struct i915_page_table
*pt
)
453 kfree(pt
->used_ptes
);
458 * alloc_pt_range() - Allocate a multiple page tables
459 * @pd: The page directory which will have at least @count entries
460 * available to point to the allocated page tables.
461 * @pde: First page directory entry for which we are allocating.
462 * @count: Number of pages to allocate.
465 * Allocates multiple page table pages and sets the appropriate entries in the
466 * page table structure within the page directory. Function cleans up after
467 * itself on any failures.
469 * Return: 0 if allocation succeeded.
471 static int alloc_pt_range(struct i915_page_directory
*pd
, uint16_t pde
, size_t count
,
472 struct drm_device
*dev
)
476 /* 512 is the max page tables per page_directory on any platform. */
477 if (WARN_ON(pde
+ count
> I915_PDES
))
480 for (i
= pde
; i
< pde
+ count
; i
++) {
481 struct i915_page_table
*pt
= alloc_pt(dev
);
487 WARN(pd
->page_table
[i
],
488 "Leaking page directory entry %d (%p)\n",
489 i
, pd
->page_table
[i
]);
490 pd
->page_table
[i
] = pt
;
497 free_pt(dev
, pd
->page_table
[i
]);
501 static void gen8_initialize_pt(struct i915_address_space
*vm
,
502 struct i915_page_table
*pt
)
504 gen8_pte_t scratch_pte
;
506 scratch_pte
= gen8_pte_encode(px_dma(vm
->scratch_page
),
507 I915_CACHE_LLC
, true);
509 fill_px(vm
->dev
, pt
, scratch_pte
);
512 static void gen6_initialize_pt(struct i915_address_space
*vm
,
513 struct i915_page_table
*pt
)
515 gen6_pte_t scratch_pte
;
517 WARN_ON(px_dma(vm
->scratch_page
) == 0);
519 scratch_pte
= vm
->pte_encode(px_dma(vm
->scratch_page
),
520 I915_CACHE_LLC
, true, 0);
522 fill32_px(vm
->dev
, pt
, scratch_pte
);
525 static struct i915_page_directory
*alloc_pd(struct drm_device
*dev
)
527 struct i915_page_directory
*pd
;
530 pd
= kzalloc(sizeof(*pd
), GFP_KERNEL
);
532 return ERR_PTR(-ENOMEM
);
534 pd
->used_pdes
= kcalloc(BITS_TO_LONGS(I915_PDES
),
535 sizeof(*pd
->used_pdes
), GFP_KERNEL
);
539 ret
= setup_px(dev
, pd
);
546 kfree(pd
->used_pdes
);
553 static void free_pd(struct drm_device
*dev
, struct i915_page_directory
*pd
)
557 kfree(pd
->used_pdes
);
562 static void gen8_initialize_pd(struct i915_address_space
*vm
,
563 struct i915_page_directory
*pd
)
565 gen8_pde_t scratch_pde
;
567 scratch_pde
= gen8_pde_encode(px_dma(vm
->scratch_pt
), I915_CACHE_LLC
);
569 fill_px(vm
->dev
, pd
, scratch_pde
);
572 /* Broadwell Page Directory Pointer Descriptors */
573 static int gen8_write_pdp(struct drm_i915_gem_request
*req
,
577 struct intel_engine_cs
*ring
= req
->ring
;
582 ret
= intel_ring_begin(req
, 6);
586 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
587 intel_ring_emit(ring
, GEN8_RING_PDP_UDW(ring
, entry
));
588 intel_ring_emit(ring
, upper_32_bits(addr
));
589 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
590 intel_ring_emit(ring
, GEN8_RING_PDP_LDW(ring
, entry
));
591 intel_ring_emit(ring
, lower_32_bits(addr
));
592 intel_ring_advance(ring
);
597 static int gen8_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
598 struct drm_i915_gem_request
*req
)
602 for (i
= GEN8_LEGACY_PDPES
- 1; i
>= 0; i
--) {
603 const dma_addr_t pd_daddr
= i915_page_dir_dma_addr(ppgtt
, i
);
605 ret
= gen8_write_pdp(req
, i
, pd_daddr
);
613 static void gen8_ppgtt_clear_range(struct i915_address_space
*vm
,
618 struct i915_hw_ppgtt
*ppgtt
=
619 container_of(vm
, struct i915_hw_ppgtt
, base
);
620 gen8_pte_t
*pt_vaddr
, scratch_pte
;
621 unsigned pdpe
= start
>> GEN8_PDPE_SHIFT
& GEN8_PDPE_MASK
;
622 unsigned pde
= start
>> GEN8_PDE_SHIFT
& GEN8_PDE_MASK
;
623 unsigned pte
= start
>> GEN8_PTE_SHIFT
& GEN8_PTE_MASK
;
624 unsigned num_entries
= length
>> PAGE_SHIFT
;
625 unsigned last_pte
, i
;
627 scratch_pte
= gen8_pte_encode(px_dma(ppgtt
->base
.scratch_page
),
628 I915_CACHE_LLC
, use_scratch
);
630 while (num_entries
) {
631 struct i915_page_directory
*pd
;
632 struct i915_page_table
*pt
;
634 if (WARN_ON(!ppgtt
->pdp
.page_directory
[pdpe
]))
637 pd
= ppgtt
->pdp
.page_directory
[pdpe
];
639 if (WARN_ON(!pd
->page_table
[pde
]))
642 pt
= pd
->page_table
[pde
];
644 if (WARN_ON(!px_page(pt
)))
647 last_pte
= pte
+ num_entries
;
648 if (last_pte
> GEN8_PTES
)
649 last_pte
= GEN8_PTES
;
651 pt_vaddr
= kmap_px(pt
);
653 for (i
= pte
; i
< last_pte
; i
++) {
654 pt_vaddr
[i
] = scratch_pte
;
658 kunmap_px(ppgtt
, pt
);
661 if (++pde
== I915_PDES
) {
668 static void gen8_ppgtt_insert_entries(struct i915_address_space
*vm
,
669 struct sg_table
*pages
,
671 enum i915_cache_level cache_level
, u32 unused
)
673 struct i915_hw_ppgtt
*ppgtt
=
674 container_of(vm
, struct i915_hw_ppgtt
, base
);
675 gen8_pte_t
*pt_vaddr
;
676 unsigned pdpe
= start
>> GEN8_PDPE_SHIFT
& GEN8_PDPE_MASK
;
677 unsigned pde
= start
>> GEN8_PDE_SHIFT
& GEN8_PDE_MASK
;
678 unsigned pte
= start
>> GEN8_PTE_SHIFT
& GEN8_PTE_MASK
;
679 struct sg_page_iter sg_iter
;
683 for_each_sg_page(pages
->sgl
, &sg_iter
, pages
->nents
, 0) {
684 if (WARN_ON(pdpe
>= GEN8_LEGACY_PDPES
))
687 if (pt_vaddr
== NULL
) {
688 struct i915_page_directory
*pd
= ppgtt
->pdp
.page_directory
[pdpe
];
689 struct i915_page_table
*pt
= pd
->page_table
[pde
];
691 pt_vaddr
= kmap_px(pt
);
695 gen8_pte_encode(sg_page_iter_dma_address(&sg_iter
),
697 if (++pte
== GEN8_PTES
) {
698 kunmap_px(ppgtt
, pt_vaddr
);
700 if (++pde
== I915_PDES
) {
709 kunmap_px(ppgtt
, pt_vaddr
);
712 static void gen8_free_page_tables(struct drm_device
*dev
,
713 struct i915_page_directory
*pd
)
720 for_each_set_bit(i
, pd
->used_pdes
, I915_PDES
) {
721 if (WARN_ON(!pd
->page_table
[i
]))
724 free_pt(dev
, pd
->page_table
[i
]);
725 pd
->page_table
[i
] = NULL
;
729 static int gen8_init_scratch(struct i915_address_space
*vm
)
731 struct drm_device
*dev
= vm
->dev
;
733 vm
->scratch_page
= alloc_scratch_page(dev
);
734 if (IS_ERR(vm
->scratch_page
))
735 return PTR_ERR(vm
->scratch_page
);
737 vm
->scratch_pt
= alloc_pt(dev
);
738 if (IS_ERR(vm
->scratch_pt
)) {
739 free_scratch_page(dev
, vm
->scratch_page
);
740 return PTR_ERR(vm
->scratch_pt
);
743 vm
->scratch_pd
= alloc_pd(dev
);
744 if (IS_ERR(vm
->scratch_pd
)) {
745 free_pt(dev
, vm
->scratch_pt
);
746 free_scratch_page(dev
, vm
->scratch_page
);
747 return PTR_ERR(vm
->scratch_pd
);
750 gen8_initialize_pt(vm
, vm
->scratch_pt
);
751 gen8_initialize_pd(vm
, vm
->scratch_pd
);
756 static void gen8_free_scratch(struct i915_address_space
*vm
)
758 struct drm_device
*dev
= vm
->dev
;
760 free_pd(dev
, vm
->scratch_pd
);
761 free_pt(dev
, vm
->scratch_pt
);
762 free_scratch_page(dev
, vm
->scratch_page
);
765 static void gen8_ppgtt_cleanup(struct i915_address_space
*vm
)
767 struct i915_hw_ppgtt
*ppgtt
=
768 container_of(vm
, struct i915_hw_ppgtt
, base
);
771 for_each_set_bit(i
, ppgtt
->pdp
.used_pdpes
, GEN8_LEGACY_PDPES
) {
772 if (WARN_ON(!ppgtt
->pdp
.page_directory
[i
]))
775 gen8_free_page_tables(ppgtt
->base
.dev
,
776 ppgtt
->pdp
.page_directory
[i
]);
777 free_pd(ppgtt
->base
.dev
, ppgtt
->pdp
.page_directory
[i
]);
780 gen8_free_scratch(vm
);
784 * gen8_ppgtt_alloc_pagetabs() - Allocate page tables for VA range.
785 * @ppgtt: Master ppgtt structure.
786 * @pd: Page directory for this address range.
787 * @start: Starting virtual address to begin allocations.
788 * @length Size of the allocations.
789 * @new_pts: Bitmap set by function with new allocations. Likely used by the
790 * caller to free on error.
792 * Allocate the required number of page tables. Extremely similar to
793 * gen8_ppgtt_alloc_page_directories(). The main difference is here we are limited by
794 * the page directory boundary (instead of the page directory pointer). That
795 * boundary is 1GB virtual. Therefore, unlike gen8_ppgtt_alloc_page_directories(), it is
796 * possible, and likely that the caller will need to use multiple calls of this
797 * function to achieve the appropriate allocation.
799 * Return: 0 if success; negative error code otherwise.
801 static int gen8_ppgtt_alloc_pagetabs(struct i915_hw_ppgtt
*ppgtt
,
802 struct i915_page_directory
*pd
,
805 unsigned long *new_pts
)
807 struct drm_device
*dev
= ppgtt
->base
.dev
;
808 struct i915_page_table
*pt
;
812 gen8_for_each_pde(pt
, pd
, start
, length
, temp
, pde
) {
813 /* Don't reallocate page tables */
815 /* Scratch is never allocated this way */
816 WARN_ON(pt
== ppgtt
->base
.scratch_pt
);
824 gen8_initialize_pt(&ppgtt
->base
, pt
);
825 pd
->page_table
[pde
] = pt
;
826 __set_bit(pde
, new_pts
);
832 for_each_set_bit(pde
, new_pts
, I915_PDES
)
833 free_pt(dev
, pd
->page_table
[pde
]);
839 * gen8_ppgtt_alloc_page_directories() - Allocate page directories for VA range.
840 * @ppgtt: Master ppgtt structure.
841 * @pdp: Page directory pointer for this address range.
842 * @start: Starting virtual address to begin allocations.
843 * @length Size of the allocations.
844 * @new_pds Bitmap set by function with new allocations. Likely used by the
845 * caller to free on error.
847 * Allocate the required number of page directories starting at the pde index of
848 * @start, and ending at the pde index @start + @length. This function will skip
849 * over already allocated page directories within the range, and only allocate
850 * new ones, setting the appropriate pointer within the pdp as well as the
851 * correct position in the bitmap @new_pds.
853 * The function will only allocate the pages within the range for a give page
854 * directory pointer. In other words, if @start + @length straddles a virtually
855 * addressed PDP boundary (512GB for 4k pages), there will be more allocations
856 * required by the caller, This is not currently possible, and the BUG in the
857 * code will prevent it.
859 * Return: 0 if success; negative error code otherwise.
861 static int gen8_ppgtt_alloc_page_directories(struct i915_hw_ppgtt
*ppgtt
,
862 struct i915_page_directory_pointer
*pdp
,
865 unsigned long *new_pds
)
867 struct drm_device
*dev
= ppgtt
->base
.dev
;
868 struct i915_page_directory
*pd
;
872 WARN_ON(!bitmap_empty(new_pds
, GEN8_LEGACY_PDPES
));
874 gen8_for_each_pdpe(pd
, pdp
, start
, length
, temp
, pdpe
) {
882 gen8_initialize_pd(&ppgtt
->base
, pd
);
883 pdp
->page_directory
[pdpe
] = pd
;
884 __set_bit(pdpe
, new_pds
);
890 for_each_set_bit(pdpe
, new_pds
, GEN8_LEGACY_PDPES
)
891 free_pd(dev
, pdp
->page_directory
[pdpe
]);
897 free_gen8_temp_bitmaps(unsigned long *new_pds
, unsigned long **new_pts
)
901 for (i
= 0; i
< GEN8_LEGACY_PDPES
; i
++)
907 /* Fills in the page directory bitmap, and the array of page tables bitmap. Both
908 * of these are based on the number of PDPEs in the system.
911 int __must_check
alloc_gen8_temp_bitmaps(unsigned long **new_pds
,
912 unsigned long ***new_pts
)
918 pds
= kcalloc(BITS_TO_LONGS(GEN8_LEGACY_PDPES
), sizeof(unsigned long), GFP_KERNEL
);
922 pts
= kcalloc(GEN8_LEGACY_PDPES
, sizeof(unsigned long *), GFP_KERNEL
);
928 for (i
= 0; i
< GEN8_LEGACY_PDPES
; i
++) {
929 pts
[i
] = kcalloc(BITS_TO_LONGS(I915_PDES
),
930 sizeof(unsigned long), GFP_KERNEL
);
941 free_gen8_temp_bitmaps(pds
, pts
);
945 /* PDE TLBs are a pain to invalidate on GEN8+. When we modify
946 * the page table structures, we mark them dirty so that
947 * context switching/execlist queuing code takes extra steps
948 * to ensure that tlbs are flushed.
950 static void mark_tlbs_dirty(struct i915_hw_ppgtt
*ppgtt
)
952 ppgtt
->pd_dirty_rings
= INTEL_INFO(ppgtt
->base
.dev
)->ring_mask
;
955 static int gen8_alloc_va_range(struct i915_address_space
*vm
,
959 struct i915_hw_ppgtt
*ppgtt
=
960 container_of(vm
, struct i915_hw_ppgtt
, base
);
961 unsigned long *new_page_dirs
, **new_page_tables
;
962 struct i915_page_directory
*pd
;
963 const uint64_t orig_start
= start
;
964 const uint64_t orig_length
= length
;
969 /* Wrap is never okay since we can only represent 48b, and we don't
970 * actually use the other side of the canonical address space.
972 if (WARN_ON(start
+ length
< start
))
975 if (WARN_ON(start
+ length
> ppgtt
->base
.total
))
978 ret
= alloc_gen8_temp_bitmaps(&new_page_dirs
, &new_page_tables
);
982 /* Do the allocations first so we can easily bail out */
983 ret
= gen8_ppgtt_alloc_page_directories(ppgtt
, &ppgtt
->pdp
, start
, length
,
986 free_gen8_temp_bitmaps(new_page_dirs
, new_page_tables
);
990 /* For every page directory referenced, allocate page tables */
991 gen8_for_each_pdpe(pd
, &ppgtt
->pdp
, start
, length
, temp
, pdpe
) {
992 ret
= gen8_ppgtt_alloc_pagetabs(ppgtt
, pd
, start
, length
,
993 new_page_tables
[pdpe
]);
999 length
= orig_length
;
1001 /* Allocations have completed successfully, so set the bitmaps, and do
1003 gen8_for_each_pdpe(pd
, &ppgtt
->pdp
, start
, length
, temp
, pdpe
) {
1004 gen8_pde_t
*const page_directory
= kmap_px(pd
);
1005 struct i915_page_table
*pt
;
1006 uint64_t pd_len
= gen8_clamp_pd(start
, length
);
1007 uint64_t pd_start
= start
;
1010 /* Every pd should be allocated, we just did that above. */
1013 gen8_for_each_pde(pt
, pd
, pd_start
, pd_len
, temp
, pde
) {
1014 /* Same reasoning as pd */
1017 WARN_ON(!gen8_pte_count(pd_start
, pd_len
));
1019 /* Set our used ptes within the page table */
1020 bitmap_set(pt
->used_ptes
,
1021 gen8_pte_index(pd_start
),
1022 gen8_pte_count(pd_start
, pd_len
));
1024 /* Our pde is now pointing to the pagetable, pt */
1025 __set_bit(pde
, pd
->used_pdes
);
1027 /* Map the PDE to the page table */
1028 page_directory
[pde
] = gen8_pde_encode(px_dma(pt
),
1031 /* NB: We haven't yet mapped ptes to pages. At this
1032 * point we're still relying on insert_entries() */
1035 kunmap_px(ppgtt
, page_directory
);
1037 __set_bit(pdpe
, ppgtt
->pdp
.used_pdpes
);
1040 free_gen8_temp_bitmaps(new_page_dirs
, new_page_tables
);
1041 mark_tlbs_dirty(ppgtt
);
1046 for_each_set_bit(temp
, new_page_tables
[pdpe
], I915_PDES
)
1047 free_pt(vm
->dev
, ppgtt
->pdp
.page_directory
[pdpe
]->page_table
[temp
]);
1050 for_each_set_bit(pdpe
, new_page_dirs
, GEN8_LEGACY_PDPES
)
1051 free_pd(vm
->dev
, ppgtt
->pdp
.page_directory
[pdpe
]);
1053 free_gen8_temp_bitmaps(new_page_dirs
, new_page_tables
);
1054 mark_tlbs_dirty(ppgtt
);
1059 * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
1060 * with a net effect resembling a 2-level page table in normal x86 terms. Each
1061 * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
1065 static int gen8_ppgtt_init(struct i915_hw_ppgtt
*ppgtt
)
1069 ret
= gen8_init_scratch(&ppgtt
->base
);
1073 ppgtt
->base
.start
= 0;
1074 #ifndef __DragonFly__
1075 ppgtt
->base
.total
= 1ULL << 32;
1076 if (IS_ENABLED(CONFIG_X86_32
))
1077 /* While we have a proliferation of size_t variables
1078 * we cannot represent the full ppgtt size on 32bit,
1079 * so limit it to the same size as the GGTT (currently
1083 ppgtt
->base
.total
= to_i915(ppgtt
->base
.dev
)->gtt
.base
.total
;
1084 ppgtt
->base
.cleanup
= gen8_ppgtt_cleanup
;
1085 ppgtt
->base
.allocate_va_range
= gen8_alloc_va_range
;
1086 ppgtt
->base
.insert_entries
= gen8_ppgtt_insert_entries
;
1087 ppgtt
->base
.clear_range
= gen8_ppgtt_clear_range
;
1088 ppgtt
->base
.unbind_vma
= ppgtt_unbind_vma
;
1089 ppgtt
->base
.bind_vma
= ppgtt_bind_vma
;
1091 ppgtt
->switch_mm
= gen8_mm_switch
;
1096 static int gen8_aliasing_ppgtt_init(struct i915_hw_ppgtt
*ppgtt
)
1098 struct drm_device
*dev
= ppgtt
->base
.dev
;
1099 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1100 uint64_t start
= 0, size
= dev_priv
->gtt
.base
.total
;
1103 ret
= gen8_ppgtt_init(ppgtt
);
1107 /* Aliasing PPGTT has to always work and be mapped because of the way we
1108 * use RESTORE_INHIBIT in the context switch. This will be fixed
1110 ret
= gen8_alloc_va_range(&ppgtt
->base
, start
, size
);
1112 free_pd(ppgtt
->base
.dev
, ppgtt
->base
.scratch_pd
);
1113 free_pt(ppgtt
->base
.dev
, ppgtt
->base
.scratch_pt
);
1117 ppgtt
->base
.allocate_va_range
= NULL
;
1118 ppgtt
->base
.clear_range(&ppgtt
->base
, 0, ppgtt
->base
.total
, true);
1123 static void gen6_dump_ppgtt(struct i915_hw_ppgtt
*ppgtt
, struct seq_file
*m
)
1125 struct i915_address_space
*vm
= &ppgtt
->base
;
1126 struct i915_page_table
*unused
;
1127 gen6_pte_t scratch_pte
;
1129 uint32_t pte
, pde
, temp
;
1130 uint32_t start
= ppgtt
->base
.start
, length
= ppgtt
->base
.total
;
1132 scratch_pte
= vm
->pte_encode(px_dma(vm
->scratch_page
),
1133 I915_CACHE_LLC
, true, 0);
1135 gen6_for_each_pde(unused
, &ppgtt
->pd
, start
, length
, temp
, pde
) {
1137 gen6_pte_t
*pt_vaddr
;
1138 const dma_addr_t pt_addr
= px_dma(ppgtt
->pd
.page_table
[pde
]);
1139 pd_entry
= readl(ppgtt
->pd_addr
+ pde
);
1140 expected
= (GEN6_PDE_ADDR_ENCODE(pt_addr
) | GEN6_PDE_VALID
);
1142 if (pd_entry
!= expected
)
1143 seq_printf(m
, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
1147 seq_printf(m
, "\tPDE: %x\n", pd_entry
);
1149 pt_vaddr
= kmap_px(ppgtt
->pd
.page_table
[pde
]);
1151 for (pte
= 0; pte
< GEN6_PTES
; pte
+=4) {
1153 (pde
* PAGE_SIZE
* GEN6_PTES
) +
1157 for (i
= 0; i
< 4; i
++)
1158 if (pt_vaddr
[pte
+ i
] != scratch_pte
)
1163 seq_printf(m
, "\t\t0x%lx [%03d,%04d]: =", va
, pde
, pte
);
1164 for (i
= 0; i
< 4; i
++) {
1165 if (pt_vaddr
[pte
+ i
] != scratch_pte
)
1166 seq_printf(m
, " %08x", pt_vaddr
[pte
+ i
]);
1168 seq_puts(m
, " SCRATCH ");
1172 kunmap_px(ppgtt
, pt_vaddr
);
1176 /* Write pde (index) from the page directory @pd to the page table @pt */
1177 static void gen6_write_pde(struct i915_page_directory
*pd
,
1178 const int pde
, struct i915_page_table
*pt
)
1180 /* Caller needs to make sure the write completes if necessary */
1181 struct i915_hw_ppgtt
*ppgtt
=
1182 container_of(pd
, struct i915_hw_ppgtt
, pd
);
1185 pd_entry
= GEN6_PDE_ADDR_ENCODE(px_dma(pt
));
1186 pd_entry
|= GEN6_PDE_VALID
;
1188 writel(pd_entry
, ppgtt
->pd_addr
+ pde
);
1191 /* Write all the page tables found in the ppgtt structure to incrementing page
1193 static void gen6_write_page_range(struct drm_i915_private
*dev_priv
,
1194 struct i915_page_directory
*pd
,
1195 uint32_t start
, uint32_t length
)
1197 struct i915_page_table
*pt
;
1200 gen6_for_each_pde(pt
, pd
, start
, length
, temp
, pde
)
1201 gen6_write_pde(pd
, pde
, pt
);
1203 /* Make sure write is complete before other code can use this page
1204 * table. Also require for WC mapped PTEs */
1205 readl(dev_priv
->gtt
.gsm
);
1208 static uint32_t get_pd_offset(struct i915_hw_ppgtt
*ppgtt
)
1210 BUG_ON(ppgtt
->pd
.base
.ggtt_offset
& 0x3f);
1212 return (ppgtt
->pd
.base
.ggtt_offset
/ 64) << 16;
1215 static int hsw_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
1216 struct drm_i915_gem_request
*req
)
1218 struct intel_engine_cs
*ring
= req
->ring
;
1221 /* NB: TLBs must be flushed and invalidated before a switch */
1222 ret
= ring
->flush(req
, I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
1226 ret
= intel_ring_begin(req
, 6);
1230 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(2));
1231 intel_ring_emit(ring
, RING_PP_DIR_DCLV(ring
));
1232 intel_ring_emit(ring
, PP_DIR_DCLV_2G
);
1233 intel_ring_emit(ring
, RING_PP_DIR_BASE(ring
));
1234 intel_ring_emit(ring
, get_pd_offset(ppgtt
));
1235 intel_ring_emit(ring
, MI_NOOP
);
1236 intel_ring_advance(ring
);
1241 static int vgpu_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
1242 struct drm_i915_gem_request
*req
)
1244 struct intel_engine_cs
*ring
= req
->ring
;
1245 struct drm_i915_private
*dev_priv
= to_i915(ppgtt
->base
.dev
);
1247 I915_WRITE(RING_PP_DIR_DCLV(ring
), PP_DIR_DCLV_2G
);
1248 I915_WRITE(RING_PP_DIR_BASE(ring
), get_pd_offset(ppgtt
));
1252 static int gen7_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
1253 struct drm_i915_gem_request
*req
)
1255 struct intel_engine_cs
*ring
= req
->ring
;
1258 /* NB: TLBs must be flushed and invalidated before a switch */
1259 ret
= ring
->flush(req
, I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
1263 ret
= intel_ring_begin(req
, 6);
1267 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(2));
1268 intel_ring_emit(ring
, RING_PP_DIR_DCLV(ring
));
1269 intel_ring_emit(ring
, PP_DIR_DCLV_2G
);
1270 intel_ring_emit(ring
, RING_PP_DIR_BASE(ring
));
1271 intel_ring_emit(ring
, get_pd_offset(ppgtt
));
1272 intel_ring_emit(ring
, MI_NOOP
);
1273 intel_ring_advance(ring
);
1275 /* XXX: RCS is the only one to auto invalidate the TLBs? */
1276 if (ring
->id
!= RCS
) {
1277 ret
= ring
->flush(req
, I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
1285 static int gen6_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
1286 struct drm_i915_gem_request
*req
)
1288 struct intel_engine_cs
*ring
= req
->ring
;
1289 struct drm_device
*dev
= ppgtt
->base
.dev
;
1290 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1293 I915_WRITE(RING_PP_DIR_DCLV(ring
), PP_DIR_DCLV_2G
);
1294 I915_WRITE(RING_PP_DIR_BASE(ring
), get_pd_offset(ppgtt
));
1296 POSTING_READ(RING_PP_DIR_DCLV(ring
));
1301 static void gen8_ppgtt_enable(struct drm_device
*dev
)
1303 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1304 struct intel_engine_cs
*ring
;
1307 for_each_ring(ring
, dev_priv
, j
) {
1308 I915_WRITE(RING_MODE_GEN7(ring
),
1309 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
1313 static void gen7_ppgtt_enable(struct drm_device
*dev
)
1315 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1316 struct intel_engine_cs
*ring
;
1317 uint32_t ecochk
, ecobits
;
1320 ecobits
= I915_READ(GAC_ECO_BITS
);
1321 I915_WRITE(GAC_ECO_BITS
, ecobits
| ECOBITS_PPGTT_CACHE64B
);
1323 ecochk
= I915_READ(GAM_ECOCHK
);
1324 if (IS_HASWELL(dev
)) {
1325 ecochk
|= ECOCHK_PPGTT_WB_HSW
;
1327 ecochk
|= ECOCHK_PPGTT_LLC_IVB
;
1328 ecochk
&= ~ECOCHK_PPGTT_GFDT_IVB
;
1330 I915_WRITE(GAM_ECOCHK
, ecochk
);
1332 for_each_ring(ring
, dev_priv
, i
) {
1333 /* GFX_MODE is per-ring on gen7+ */
1334 I915_WRITE(RING_MODE_GEN7(ring
),
1335 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
1339 static void gen6_ppgtt_enable(struct drm_device
*dev
)
1341 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1342 uint32_t ecochk
, gab_ctl
, ecobits
;
1344 ecobits
= I915_READ(GAC_ECO_BITS
);
1345 I915_WRITE(GAC_ECO_BITS
, ecobits
| ECOBITS_SNB_BIT
|
1346 ECOBITS_PPGTT_CACHE64B
);
1348 gab_ctl
= I915_READ(GAB_CTL
);
1349 I915_WRITE(GAB_CTL
, gab_ctl
| GAB_CTL_CONT_AFTER_PAGEFAULT
);
1351 ecochk
= I915_READ(GAM_ECOCHK
);
1352 I915_WRITE(GAM_ECOCHK
, ecochk
| ECOCHK_SNB_BIT
| ECOCHK_PPGTT_CACHE64B
);
1354 I915_WRITE(GFX_MODE
, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
1357 /* PPGTT support for Sandybdrige/Gen6 and later */
1358 static void gen6_ppgtt_clear_range(struct i915_address_space
*vm
,
1363 struct i915_hw_ppgtt
*ppgtt
=
1364 container_of(vm
, struct i915_hw_ppgtt
, base
);
1365 gen6_pte_t
*pt_vaddr
, scratch_pte
;
1366 unsigned first_entry
= start
>> PAGE_SHIFT
;
1367 unsigned num_entries
= length
>> PAGE_SHIFT
;
1368 unsigned act_pt
= first_entry
/ GEN6_PTES
;
1369 unsigned first_pte
= first_entry
% GEN6_PTES
;
1370 unsigned last_pte
, i
;
1372 scratch_pte
= vm
->pte_encode(px_dma(vm
->scratch_page
),
1373 I915_CACHE_LLC
, true, 0);
1375 while (num_entries
) {
1376 last_pte
= first_pte
+ num_entries
;
1377 if (last_pte
> GEN6_PTES
)
1378 last_pte
= GEN6_PTES
;
1380 pt_vaddr
= kmap_px(ppgtt
->pd
.page_table
[act_pt
]);
1382 for (i
= first_pte
; i
< last_pte
; i
++)
1383 pt_vaddr
[i
] = scratch_pte
;
1385 kunmap_px(ppgtt
, pt_vaddr
);
1387 num_entries
-= last_pte
- first_pte
;
1393 static void gen6_ppgtt_insert_entries(struct i915_address_space
*vm
,
1394 struct sg_table
*pages
,
1396 enum i915_cache_level cache_level
, u32 flags
)
1398 struct i915_hw_ppgtt
*ppgtt
=
1399 container_of(vm
, struct i915_hw_ppgtt
, base
);
1400 gen6_pte_t
*pt_vaddr
;
1401 unsigned first_entry
= start
>> PAGE_SHIFT
;
1402 unsigned act_pt
= first_entry
/ GEN6_PTES
;
1403 unsigned act_pte
= first_entry
% GEN6_PTES
;
1404 struct sg_page_iter sg_iter
;
1407 for_each_sg_page(pages
->sgl
, &sg_iter
, pages
->nents
, 0) {
1408 if (pt_vaddr
== NULL
)
1409 pt_vaddr
= kmap_px(ppgtt
->pd
.page_table
[act_pt
]);
1412 vm
->pte_encode(sg_page_iter_dma_address(&sg_iter
),
1413 cache_level
, true, flags
);
1415 if (++act_pte
== GEN6_PTES
) {
1416 kunmap_px(ppgtt
, pt_vaddr
);
1423 kunmap_px(ppgtt
, pt_vaddr
);
1426 static int gen6_alloc_va_range(struct i915_address_space
*vm
,
1427 uint64_t start_in
, uint64_t length_in
)
1429 DECLARE_BITMAP(new_page_tables
, I915_PDES
);
1430 struct drm_device
*dev
= vm
->dev
;
1431 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1432 struct i915_hw_ppgtt
*ppgtt
=
1433 container_of(vm
, struct i915_hw_ppgtt
, base
);
1434 struct i915_page_table
*pt
;
1435 uint32_t start
, length
, start_save
, length_save
;
1439 if (WARN_ON(start_in
+ length_in
> ppgtt
->base
.total
))
1442 start
= start_save
= start_in
;
1443 length
= length_save
= length_in
;
1445 bitmap_zero(new_page_tables
, I915_PDES
);
1447 /* The allocation is done in two stages so that we can bail out with
1448 * minimal amount of pain. The first stage finds new page tables that
1449 * need allocation. The second stage marks use ptes within the page
1452 gen6_for_each_pde(pt
, &ppgtt
->pd
, start
, length
, temp
, pde
) {
1453 if (pt
!= vm
->scratch_pt
) {
1454 // WARN_ON(bitmap_empty(pt->used_ptes, GEN6_PTES));
1458 /* We've already allocated a page table */
1459 WARN_ON(!bitmap_empty(pt
->used_ptes
, GEN6_PTES
));
1467 gen6_initialize_pt(vm
, pt
);
1469 ppgtt
->pd
.page_table
[pde
] = pt
;
1470 __set_bit(pde
, new_page_tables
);
1471 trace_i915_page_table_entry_alloc(vm
, pde
, start
, GEN6_PDE_SHIFT
);
1475 length
= length_save
;
1477 gen6_for_each_pde(pt
, &ppgtt
->pd
, start
, length
, temp
, pde
) {
1478 DECLARE_BITMAP(tmp_bitmap
, GEN6_PTES
);
1480 bitmap_zero(tmp_bitmap
, GEN6_PTES
);
1481 bitmap_set(tmp_bitmap
, gen6_pte_index(start
),
1482 gen6_pte_count(start
, length
));
1484 if (__test_and_clear_bit(pde
, new_page_tables
))
1485 gen6_write_pde(&ppgtt
->pd
, pde
, pt
);
1487 trace_i915_page_table_entry_map(vm
, pde
, pt
,
1488 gen6_pte_index(start
),
1489 gen6_pte_count(start
, length
),
1491 bitmap_or(pt
->used_ptes
, tmp_bitmap
, pt
->used_ptes
,
1495 WARN_ON(!bitmap_empty(new_page_tables
, I915_PDES
));
1497 /* Make sure write is complete before other code can use this page
1498 * table. Also require for WC mapped PTEs */
1499 readl(dev_priv
->gtt
.gsm
);
1501 mark_tlbs_dirty(ppgtt
);
1505 for_each_set_bit(pde
, new_page_tables
, I915_PDES
) {
1506 struct i915_page_table
*pt
= ppgtt
->pd
.page_table
[pde
];
1508 ppgtt
->pd
.page_table
[pde
] = vm
->scratch_pt
;
1509 free_pt(vm
->dev
, pt
);
1512 mark_tlbs_dirty(ppgtt
);
1516 static int gen6_init_scratch(struct i915_address_space
*vm
)
1518 struct drm_device
*dev
= vm
->dev
;
1520 vm
->scratch_page
= alloc_scratch_page(dev
);
1521 if (IS_ERR(vm
->scratch_page
))
1522 return PTR_ERR(vm
->scratch_page
);
1524 vm
->scratch_pt
= alloc_pt(dev
);
1525 if (IS_ERR(vm
->scratch_pt
)) {
1526 free_scratch_page(dev
, vm
->scratch_page
);
1527 return PTR_ERR(vm
->scratch_pt
);
1530 gen6_initialize_pt(vm
, vm
->scratch_pt
);
1535 static void gen6_free_scratch(struct i915_address_space
*vm
)
1537 struct drm_device
*dev
= vm
->dev
;
1539 free_pt(dev
, vm
->scratch_pt
);
1540 free_scratch_page(dev
, vm
->scratch_page
);
1543 static void gen6_ppgtt_cleanup(struct i915_address_space
*vm
)
1545 struct i915_hw_ppgtt
*ppgtt
=
1546 container_of(vm
, struct i915_hw_ppgtt
, base
);
1547 struct i915_page_table
*pt
;
1550 drm_mm_remove_node(&ppgtt
->node
);
1552 gen6_for_all_pdes(pt
, ppgtt
, pde
) {
1553 if (pt
!= vm
->scratch_pt
)
1554 free_pt(ppgtt
->base
.dev
, pt
);
1557 gen6_free_scratch(vm
);
1560 static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt
*ppgtt
)
1562 struct i915_address_space
*vm
= &ppgtt
->base
;
1563 struct drm_device
*dev
= ppgtt
->base
.dev
;
1564 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1565 bool retried
= false;
1568 /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
1569 * allocator works in address space sizes, so it's multiplied by page
1570 * size. We allocate at the top of the GTT to avoid fragmentation.
1572 BUG_ON(!drm_mm_initialized(&dev_priv
->gtt
.base
.mm
));
1574 ret
= gen6_init_scratch(vm
);
1579 ret
= drm_mm_insert_node_in_range_generic(&dev_priv
->gtt
.base
.mm
,
1580 &ppgtt
->node
, GEN6_PD_SIZE
,
1582 0, dev_priv
->gtt
.base
.total
,
1584 if (ret
== -ENOSPC
&& !retried
) {
1585 ret
= i915_gem_evict_something(dev
, &dev_priv
->gtt
.base
,
1586 GEN6_PD_SIZE
, GEN6_PD_ALIGN
,
1588 0, dev_priv
->gtt
.base
.total
,
1601 if (ppgtt
->node
.start
< dev_priv
->gtt
.mappable_end
)
1602 DRM_DEBUG("Forced to use aperture for PDEs\n");
1607 gen6_free_scratch(vm
);
1611 static int gen6_ppgtt_alloc(struct i915_hw_ppgtt
*ppgtt
)
1613 return gen6_ppgtt_allocate_page_directories(ppgtt
);
1616 static void gen6_scratch_va_range(struct i915_hw_ppgtt
*ppgtt
,
1617 uint64_t start
, uint64_t length
)
1619 struct i915_page_table
*unused
;
1622 gen6_for_each_pde(unused
, &ppgtt
->pd
, start
, length
, temp
, pde
)
1623 ppgtt
->pd
.page_table
[pde
] = ppgtt
->base
.scratch_pt
;
1626 static int gen6_ppgtt_init(struct i915_hw_ppgtt
*ppgtt
, bool aliasing
)
1628 struct drm_device
*dev
= ppgtt
->base
.dev
;
1629 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1632 ppgtt
->base
.pte_encode
= dev_priv
->gtt
.base
.pte_encode
;
1634 ppgtt
->switch_mm
= gen6_mm_switch
;
1635 } else if (IS_HASWELL(dev
)) {
1636 ppgtt
->switch_mm
= hsw_mm_switch
;
1637 } else if (IS_GEN7(dev
)) {
1638 ppgtt
->switch_mm
= gen7_mm_switch
;
1642 if (intel_vgpu_active(dev
))
1643 ppgtt
->switch_mm
= vgpu_mm_switch
;
1645 ret
= gen6_ppgtt_alloc(ppgtt
);
1650 /* preallocate all pts */
1651 ret
= alloc_pt_range(&ppgtt
->pd
, 0, I915_PDES
,
1655 gen6_ppgtt_cleanup(&ppgtt
->base
);
1660 ppgtt
->base
.allocate_va_range
= gen6_alloc_va_range
;
1661 ppgtt
->base
.clear_range
= gen6_ppgtt_clear_range
;
1662 ppgtt
->base
.insert_entries
= gen6_ppgtt_insert_entries
;
1663 ppgtt
->base
.unbind_vma
= ppgtt_unbind_vma
;
1664 ppgtt
->base
.bind_vma
= ppgtt_bind_vma
;
1665 ppgtt
->base
.cleanup
= gen6_ppgtt_cleanup
;
1666 ppgtt
->base
.start
= 0;
1667 ppgtt
->base
.total
= I915_PDES
* GEN6_PTES
* PAGE_SIZE
;
1668 ppgtt
->debug_dump
= gen6_dump_ppgtt
;
1670 ppgtt
->pd
.base
.ggtt_offset
=
1671 ppgtt
->node
.start
/ PAGE_SIZE
* sizeof(gen6_pte_t
);
1673 ppgtt
->pd_addr
= (gen6_pte_t __iomem
*)dev_priv
->gtt
.gsm
+
1674 ppgtt
->pd
.base
.ggtt_offset
/ sizeof(gen6_pte_t
);
1677 ppgtt
->base
.clear_range(&ppgtt
->base
, 0, ppgtt
->base
.total
, true);
1679 gen6_scratch_va_range(ppgtt
, 0, ppgtt
->base
.total
);
1681 gen6_write_page_range(dev_priv
, &ppgtt
->pd
, 0, ppgtt
->base
.total
);
1683 DRM_DEBUG_DRIVER("Allocated pde space (%ldM) at GTT entry: %lx\n",
1684 ppgtt
->node
.size
>> 20,
1685 ppgtt
->node
.start
/ PAGE_SIZE
);
1687 DRM_DEBUG("Adding PPGTT at offset %x\n",
1688 ppgtt
->pd
.base
.ggtt_offset
<< 10);
1693 static int __hw_ppgtt_init(struct drm_device
*dev
, struct i915_hw_ppgtt
*ppgtt
,
1696 ppgtt
->base
.dev
= dev
;
1698 if (INTEL_INFO(dev
)->gen
< 8)
1699 return gen6_ppgtt_init(ppgtt
, aliasing
);
1701 return gen8_aliasing_ppgtt_init(ppgtt
);
1703 return gen8_ppgtt_init(ppgtt
);
1706 int i915_ppgtt_init(struct drm_device
*dev
, struct i915_hw_ppgtt
*ppgtt
)
1708 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1711 ret
= __hw_ppgtt_init(dev
, ppgtt
, false);
1713 kref_init(&ppgtt
->ref
);
1714 drm_mm_init(&ppgtt
->base
.mm
, ppgtt
->base
.start
,
1716 i915_init_vm(dev_priv
, &ppgtt
->base
);
1722 int i915_ppgtt_init_hw(struct drm_device
*dev
)
1724 /* In the case of execlists, PPGTT is enabled by the context descriptor
1725 * and the PDPs are contained within the context itself. We don't
1726 * need to do anything here. */
1727 if (i915
.enable_execlists
)
1730 if (!USES_PPGTT(dev
))
1734 gen6_ppgtt_enable(dev
);
1735 else if (IS_GEN7(dev
))
1736 gen7_ppgtt_enable(dev
);
1737 else if (INTEL_INFO(dev
)->gen
>= 8)
1738 gen8_ppgtt_enable(dev
);
1740 MISSING_CASE(INTEL_INFO(dev
)->gen
);
1745 int i915_ppgtt_init_ring(struct drm_i915_gem_request
*req
)
1747 struct drm_i915_private
*dev_priv
= req
->ring
->dev
->dev_private
;
1748 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
1750 if (i915
.enable_execlists
)
1756 return ppgtt
->switch_mm(ppgtt
, req
);
1759 struct i915_hw_ppgtt
*
1760 i915_ppgtt_create(struct drm_device
*dev
, struct drm_i915_file_private
*fpriv
)
1762 struct i915_hw_ppgtt
*ppgtt
;
1765 ppgtt
= kzalloc(sizeof(*ppgtt
), GFP_KERNEL
);
1767 return ERR_PTR(-ENOMEM
);
1769 ret
= i915_ppgtt_init(dev
, ppgtt
);
1772 return ERR_PTR(ret
);
1775 ppgtt
->file_priv
= fpriv
;
1777 trace_i915_ppgtt_create(&ppgtt
->base
);
1782 void i915_ppgtt_release(struct kref
*kref
)
1784 struct i915_hw_ppgtt
*ppgtt
=
1785 container_of(kref
, struct i915_hw_ppgtt
, ref
);
1787 trace_i915_ppgtt_release(&ppgtt
->base
);
1789 /* vmas should already be unbound */
1790 WARN_ON(!list_empty(&ppgtt
->base
.active_list
));
1791 WARN_ON(!list_empty(&ppgtt
->base
.inactive_list
));
1793 list_del(&ppgtt
->base
.global_link
);
1794 drm_mm_takedown(&ppgtt
->base
.mm
);
1796 ppgtt
->base
.cleanup(&ppgtt
->base
);
1800 extern int intel_iommu_gfx_mapped
;
1801 /* Certain Gen5 chipsets require require idling the GPU before
1802 * unmapping anything from the GTT when VT-d is enabled.
1804 static bool needs_idle_maps(struct drm_device
*dev
)
1806 #ifdef CONFIG_INTEL_IOMMU
1807 /* Query intel_iommu to see if we need the workaround. Presumably that
1810 if (IS_GEN5(dev
) && IS_MOBILE(dev
) && intel_iommu_gfx_mapped
)
1816 static bool do_idling(struct drm_i915_private
*dev_priv
)
1818 bool ret
= dev_priv
->mm
.interruptible
;
1820 if (unlikely(dev_priv
->gtt
.do_idle_maps
)) {
1821 dev_priv
->mm
.interruptible
= false;
1822 if (i915_gpu_idle(dev_priv
->dev
)) {
1823 DRM_ERROR("Couldn't idle GPU\n");
1824 /* Wait a bit, in hopes it avoids the hang */
1832 static void undo_idling(struct drm_i915_private
*dev_priv
, bool interruptible
)
1834 if (unlikely(dev_priv
->gtt
.do_idle_maps
))
1835 dev_priv
->mm
.interruptible
= interruptible
;
1838 void i915_check_and_clear_faults(struct drm_device
*dev
)
1840 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1841 struct intel_engine_cs
*ring
;
1844 if (INTEL_INFO(dev
)->gen
< 6)
1847 for_each_ring(ring
, dev_priv
, i
) {
1849 fault_reg
= I915_READ(RING_FAULT_REG(ring
));
1850 if (fault_reg
& RING_FAULT_VALID
) {
1852 DRM_DEBUG_DRIVER("Unexpected fault\n"
1854 "\tAddress space: %s\n"
1857 fault_reg
& PAGE_MASK
,
1858 fault_reg
& RING_FAULT_GTTSEL_MASK
? "GGTT" : "PPGTT",
1859 RING_FAULT_SRCID(fault_reg
),
1860 RING_FAULT_FAULT_TYPE(fault_reg
));
1862 I915_WRITE(RING_FAULT_REG(ring
),
1863 fault_reg
& ~RING_FAULT_VALID
);
1866 POSTING_READ(RING_FAULT_REG(&dev_priv
->ring
[RCS
]));
1869 static void i915_ggtt_flush(struct drm_i915_private
*dev_priv
)
1871 if (INTEL_INFO(dev_priv
->dev
)->gen
< 6) {
1872 intel_gtt_chipset_flush();
1874 I915_WRITE(GFX_FLSH_CNTL_GEN6
, GFX_FLSH_CNTL_EN
);
1875 POSTING_READ(GFX_FLSH_CNTL_GEN6
);
1879 void i915_gem_suspend_gtt_mappings(struct drm_device
*dev
)
1881 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1883 /* Don't bother messing with faults pre GEN6 as we have little
1884 * documentation supporting that it's a good idea.
1886 if (INTEL_INFO(dev
)->gen
< 6)
1889 i915_check_and_clear_faults(dev
);
1891 dev_priv
->gtt
.base
.clear_range(&dev_priv
->gtt
.base
,
1892 dev_priv
->gtt
.base
.start
,
1893 dev_priv
->gtt
.base
.total
,
1896 i915_ggtt_flush(dev_priv
);
1899 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object
*obj
)
1901 if (!dma_map_sg(obj
->base
.dev
->pdev
->dev
,
1902 obj
->pages
->sgl
, obj
->pages
->nents
,
1903 PCI_DMA_BIDIRECTIONAL
))
1909 static void gen8_set_pte(void __iomem
*addr
, gen8_pte_t pte
)
1914 iowrite32((u32
)pte
, addr
);
1915 iowrite32(pte
>> 32, addr
+ 4);
1919 static void gen8_ggtt_insert_entries(struct i915_address_space
*vm
,
1920 struct sg_table
*st
,
1922 enum i915_cache_level level
, u32 unused
)
1924 struct drm_i915_private
*dev_priv
= vm
->dev
->dev_private
;
1925 unsigned first_entry
= start
>> PAGE_SHIFT
;
1926 gen8_pte_t __iomem
*gtt_entries
=
1927 (gen8_pte_t __iomem
*)dev_priv
->gtt
.gsm
+ first_entry
;
1929 struct sg_page_iter sg_iter
;
1930 dma_addr_t addr
= 0; /* shut up gcc */
1932 for_each_sg_page(st
->sgl
, &sg_iter
, st
->nents
, 0) {
1933 addr
= sg_dma_address(sg_iter
.sg
) +
1934 (sg_iter
.sg_pgoffset
<< PAGE_SHIFT
);
1935 gen8_set_pte(>t_entries
[i
],
1936 gen8_pte_encode(addr
, level
, true));
1941 * XXX: This serves as a posting read to make sure that the PTE has
1942 * actually been updated. There is some concern that even though
1943 * registers and PTEs are within the same BAR that they are potentially
1944 * of NUMA access patterns. Therefore, even with the way we assume
1945 * hardware should work, we must keep this posting read for paranoia.
1948 WARN_ON(readq(>t_entries
[i
-1])
1949 != gen8_pte_encode(addr
, level
, true));
1951 /* This next bit makes the above posting read even more important. We
1952 * want to flush the TLBs only after we're certain all the PTE updates
1955 I915_WRITE(GFX_FLSH_CNTL_GEN6
, GFX_FLSH_CNTL_EN
);
1956 POSTING_READ(GFX_FLSH_CNTL_GEN6
);
1960 * Binds an object into the global gtt with the specified cache level. The object
1961 * will be accessible to the GPU via commands whose operands reference offsets
1962 * within the global GTT as well as accessible by the GPU through the GMADR
1963 * mapped BAR (dev_priv->mm.gtt->gtt).
1965 static void gen6_ggtt_insert_entries(struct i915_address_space
*vm
,
1966 struct sg_table
*st
,
1968 enum i915_cache_level level
, u32 flags
)
1970 struct drm_i915_private
*dev_priv
= vm
->dev
->dev_private
;
1971 unsigned first_entry
= start
>> PAGE_SHIFT
;
1972 gen6_pte_t __iomem
*gtt_entries
=
1973 (gen6_pte_t __iomem
*)dev_priv
->gtt
.gsm
+ first_entry
;
1975 struct sg_page_iter sg_iter
;
1976 dma_addr_t addr
= 0;
1978 for_each_sg_page(st
->sgl
, &sg_iter
, st
->nents
, 0) {
1979 addr
= sg_page_iter_dma_address(&sg_iter
);
1980 iowrite32(vm
->pte_encode(addr
, level
, true, flags
), >t_entries
[i
]);
1984 /* XXX: This serves as a posting read to make sure that the PTE has
1985 * actually been updated. There is some concern that even though
1986 * registers and PTEs are within the same BAR that they are potentially
1987 * of NUMA access patterns. Therefore, even with the way we assume
1988 * hardware should work, we must keep this posting read for paranoia.
1991 unsigned long gtt
= readl(>t_entries
[i
-1]);
1992 WARN_ON(gtt
!= vm
->pte_encode(addr
, level
, true, flags
));
1995 /* This next bit makes the above posting read even more important. We
1996 * want to flush the TLBs only after we're certain all the PTE updates
1999 I915_WRITE(GFX_FLSH_CNTL_GEN6
, GFX_FLSH_CNTL_EN
);
2000 POSTING_READ(GFX_FLSH_CNTL_GEN6
);
2003 static void gen8_ggtt_clear_range(struct i915_address_space
*vm
,
2008 struct drm_i915_private
*dev_priv
= vm
->dev
->dev_private
;
2009 unsigned first_entry
= start
>> PAGE_SHIFT
;
2010 unsigned num_entries
= length
>> PAGE_SHIFT
;
2011 gen8_pte_t scratch_pte
, __iomem
*gtt_base
=
2012 (gen8_pte_t __iomem
*) dev_priv
->gtt
.gsm
+ first_entry
;
2013 const int max_entries
= gtt_total_entries(dev_priv
->gtt
) - first_entry
;
2016 if (WARN(num_entries
> max_entries
,
2017 "First entry = %d; Num entries = %d (max=%d)\n",
2018 first_entry
, num_entries
, max_entries
))
2019 num_entries
= max_entries
;
2021 scratch_pte
= gen8_pte_encode(px_dma(vm
->scratch_page
),
2024 for (i
= 0; i
< num_entries
; i
++)
2025 gen8_set_pte(>t_base
[i
], scratch_pte
);
2029 static void gen6_ggtt_clear_range(struct i915_address_space
*vm
,
2034 struct drm_i915_private
*dev_priv
= vm
->dev
->dev_private
;
2035 unsigned first_entry
= start
>> PAGE_SHIFT
;
2036 unsigned num_entries
= length
>> PAGE_SHIFT
;
2037 gen6_pte_t scratch_pte
, __iomem
*gtt_base
=
2038 (gen6_pte_t __iomem
*) dev_priv
->gtt
.gsm
+ first_entry
;
2039 const int max_entries
= gtt_total_entries(dev_priv
->gtt
) - first_entry
;
2042 if (WARN(num_entries
> max_entries
,
2043 "First entry = %d; Num entries = %d (max=%d)\n",
2044 first_entry
, num_entries
, max_entries
))
2045 num_entries
= max_entries
;
2047 scratch_pte
= vm
->pte_encode(px_dma(vm
->scratch_page
),
2048 I915_CACHE_LLC
, use_scratch
, 0);
2050 for (i
= 0; i
< num_entries
; i
++)
2051 iowrite32(scratch_pte
, >t_base
[i
]);
2055 static void i915_ggtt_insert_entries(struct i915_address_space
*vm
,
2056 struct sg_table
*pages
,
2058 enum i915_cache_level cache_level
, u32 unused
)
2060 unsigned int flags
= (cache_level
== I915_CACHE_NONE
) ?
2061 AGP_USER_MEMORY
: AGP_USER_CACHED_MEMORY
;
2063 intel_gtt_insert_sg_entries(pages
, start
>> PAGE_SHIFT
, flags
);
2066 static void i915_ggtt_clear_range(struct i915_address_space
*vm
,
2071 unsigned first_entry
= start
>> PAGE_SHIFT
;
2072 unsigned num_entries
= length
>> PAGE_SHIFT
;
2073 intel_gtt_clear_range(first_entry
, num_entries
);
2076 static int ggtt_bind_vma(struct i915_vma
*vma
,
2077 enum i915_cache_level cache_level
,
2080 struct drm_device
*dev
= vma
->vm
->dev
;
2081 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2082 struct drm_i915_gem_object
*obj
= vma
->obj
;
2083 struct sg_table
*pages
= obj
->pages
;
2087 ret
= i915_get_ggtt_vma_pages(vma
);
2090 pages
= vma
->ggtt_view
.pages
;
2092 /* Currently applicable only to VLV */
2094 pte_flags
|= PTE_READ_ONLY
;
2097 if (!dev_priv
->mm
.aliasing_ppgtt
|| flags
& GLOBAL_BIND
) {
2098 vma
->vm
->insert_entries(vma
->vm
, pages
,
2100 cache_level
, pte_flags
);
2103 if (dev_priv
->mm
.aliasing_ppgtt
&& flags
& LOCAL_BIND
) {
2104 struct i915_hw_ppgtt
*appgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2105 appgtt
->base
.insert_entries(&appgtt
->base
, pages
,
2107 cache_level
, pte_flags
);
2113 static void ggtt_unbind_vma(struct i915_vma
*vma
)
2115 struct drm_device
*dev
= vma
->vm
->dev
;
2116 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2117 struct drm_i915_gem_object
*obj
= vma
->obj
;
2118 const uint64_t size
= min_t(uint64_t,
2122 if (vma
->bound
& GLOBAL_BIND
) {
2123 vma
->vm
->clear_range(vma
->vm
,
2129 if (dev_priv
->mm
.aliasing_ppgtt
&& vma
->bound
& LOCAL_BIND
) {
2130 struct i915_hw_ppgtt
*appgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2132 appgtt
->base
.clear_range(&appgtt
->base
,
2139 void i915_gem_gtt_finish_object(struct drm_i915_gem_object
*obj
)
2141 struct drm_device
*dev
= obj
->base
.dev
;
2142 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2145 interruptible
= do_idling(dev_priv
);
2147 dma_unmap_sg(dev
->pdev
->dev
, obj
->pages
->sgl
, obj
->pages
->nents
,
2148 PCI_DMA_BIDIRECTIONAL
);
2150 undo_idling(dev_priv
, interruptible
);
2153 static void i915_gtt_color_adjust(struct drm_mm_node
*node
,
2154 unsigned long color
,
2158 if (node
->color
!= color
)
2161 if (!list_empty(&node
->node_list
)) {
2162 node
= list_entry(node
->node_list
.next
,
2165 if (node
->allocated
&& node
->color
!= color
)
2170 static int i915_gem_setup_global_gtt(struct drm_device
*dev
,
2171 unsigned long start
,
2172 unsigned long mappable_end
,
2175 /* Let GEM Manage all of the aperture.
2177 * However, leave one page at the end still bound to the scratch page.
2178 * There are a number of places where the hardware apparently prefetches
2179 * past the end of the object, and we've seen multiple hangs with the
2180 * GPU head pointer stuck in a batchbuffer bound at the last page of the
2181 * aperture. One page should be enough to keep any prefetching inside
2184 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2185 struct i915_address_space
*ggtt_vm
= &dev_priv
->gtt
.base
;
2186 unsigned long mappable
;
2188 struct drm_mm_node
*entry
;
2189 struct drm_i915_gem_object
*obj
;
2190 unsigned long hole_start
, hole_end
;
2193 mappable
= min(end
, mappable_end
) - start
;
2194 BUG_ON(mappable_end
> end
);
2196 /* Subtract the guard page ... */
2197 drm_mm_init(&ggtt_vm
->mm
, start
, end
- start
- PAGE_SIZE
);
2199 dev_priv
->gtt
.base
.start
= start
;
2200 dev_priv
->gtt
.base
.total
= end
- start
;
2202 if (intel_vgpu_active(dev
)) {
2203 ret
= intel_vgt_balloon(dev
);
2209 dev_priv
->gtt
.base
.mm
.color_adjust
= i915_gtt_color_adjust
;
2211 /* Mark any preallocated objects as occupied */
2212 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
2213 struct i915_vma
*vma
= i915_gem_obj_to_vma(obj
, ggtt_vm
);
2215 DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n",
2216 i915_gem_obj_ggtt_offset(obj
), obj
->base
.size
);
2218 WARN_ON(i915_gem_obj_ggtt_bound(obj
));
2219 ret
= drm_mm_reserve_node(&ggtt_vm
->mm
, &vma
->node
);
2221 DRM_DEBUG_KMS("Reservation failed: %i\n", ret
);
2224 vma
->bound
|= GLOBAL_BIND
;
2227 /* Clear any non-preallocated blocks */
2228 drm_mm_for_each_hole(entry
, &ggtt_vm
->mm
, hole_start
, hole_end
) {
2229 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
2230 hole_start
, hole_end
);
2231 ggtt_vm
->clear_range(ggtt_vm
, hole_start
,
2232 hole_end
- hole_start
, true);
2235 #ifdef __DragonFly__
2236 device_printf(dev
->dev
,
2237 "taking over the fictitious range 0x%lx-0x%lx\n",
2238 dev_priv
->gtt
.mappable_base
+ start
, dev_priv
->gtt
.mappable_base
+ start
+ mappable
);
2239 error
= -vm_phys_fictitious_reg_range(dev_priv
->gtt
.mappable_base
+ start
,
2240 dev_priv
->gtt
.mappable_base
+ start
+ mappable
, VM_MEMATTR_WRITE_COMBINING
);
2243 /* And finally clear the reserved guard page */
2244 ggtt_vm
->clear_range(ggtt_vm
, end
- PAGE_SIZE
, PAGE_SIZE
, true);
2246 if (USES_PPGTT(dev
) && !USES_FULL_PPGTT(dev
)) {
2247 struct i915_hw_ppgtt
*ppgtt
;
2249 ppgtt
= kzalloc(sizeof(*ppgtt
), GFP_KERNEL
);
2253 ret
= __hw_ppgtt_init(dev
, ppgtt
, true);
2255 ppgtt
->base
.cleanup(&ppgtt
->base
);
2260 if (ppgtt
->base
.allocate_va_range
)
2261 ret
= ppgtt
->base
.allocate_va_range(&ppgtt
->base
, 0,
2264 ppgtt
->base
.cleanup(&ppgtt
->base
);
2269 ppgtt
->base
.clear_range(&ppgtt
->base
,
2274 dev_priv
->mm
.aliasing_ppgtt
= ppgtt
;
2280 void i915_gem_init_global_gtt(struct drm_device
*dev
)
2282 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2283 u64 gtt_size
, mappable_size
;
2285 gtt_size
= dev_priv
->gtt
.base
.total
;
2286 mappable_size
= dev_priv
->gtt
.mappable_end
;
2288 i915_gem_setup_global_gtt(dev
, 0, mappable_size
, gtt_size
);
2291 void i915_global_gtt_cleanup(struct drm_device
*dev
)
2293 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2294 struct i915_address_space
*vm
= &dev_priv
->gtt
.base
;
2296 if (dev_priv
->mm
.aliasing_ppgtt
) {
2297 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2299 ppgtt
->base
.cleanup(&ppgtt
->base
);
2302 if (drm_mm_initialized(&vm
->mm
)) {
2303 if (intel_vgpu_active(dev
))
2304 intel_vgt_deballoon();
2306 drm_mm_takedown(&vm
->mm
);
2307 list_del(&vm
->global_link
);
2313 static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl
)
2315 snb_gmch_ctl
>>= SNB_GMCH_GGMS_SHIFT
;
2316 snb_gmch_ctl
&= SNB_GMCH_GGMS_MASK
;
2317 return snb_gmch_ctl
<< 20;
2320 static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl
)
2322 bdw_gmch_ctl
>>= BDW_GMCH_GGMS_SHIFT
;
2323 bdw_gmch_ctl
&= BDW_GMCH_GGMS_MASK
;
2325 bdw_gmch_ctl
= 1 << bdw_gmch_ctl
;
2327 #ifdef CONFIG_X86_32
2328 /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */
2329 if (bdw_gmch_ctl
> 4)
2333 return bdw_gmch_ctl
<< 20;
2336 static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl
)
2338 gmch_ctrl
>>= SNB_GMCH_GGMS_SHIFT
;
2339 gmch_ctrl
&= SNB_GMCH_GGMS_MASK
;
2342 return 1 << (20 + gmch_ctrl
);
2347 static size_t gen6_get_stolen_size(u16 snb_gmch_ctl
)
2349 snb_gmch_ctl
>>= SNB_GMCH_GMS_SHIFT
;
2350 snb_gmch_ctl
&= SNB_GMCH_GMS_MASK
;
2351 return snb_gmch_ctl
<< 25; /* 32 MB units */
2354 static size_t gen8_get_stolen_size(u16 bdw_gmch_ctl
)
2356 bdw_gmch_ctl
>>= BDW_GMCH_GMS_SHIFT
;
2357 bdw_gmch_ctl
&= BDW_GMCH_GMS_MASK
;
2358 return bdw_gmch_ctl
<< 25; /* 32 MB units */
2361 static size_t chv_get_stolen_size(u16 gmch_ctrl
)
2363 gmch_ctrl
>>= SNB_GMCH_GMS_SHIFT
;
2364 gmch_ctrl
&= SNB_GMCH_GMS_MASK
;
2367 * 0x0 to 0x10: 32MB increments starting at 0MB
2368 * 0x11 to 0x16: 4MB increments starting at 8MB
2369 * 0x17 to 0x1d: 4MB increments start at 36MB
2371 if (gmch_ctrl
< 0x11)
2372 return gmch_ctrl
<< 25;
2373 else if (gmch_ctrl
< 0x17)
2374 return (gmch_ctrl
- 0x11 + 2) << 22;
2376 return (gmch_ctrl
- 0x17 + 9) << 22;
2379 static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl
)
2381 gen9_gmch_ctl
>>= BDW_GMCH_GMS_SHIFT
;
2382 gen9_gmch_ctl
&= BDW_GMCH_GMS_MASK
;
2384 if (gen9_gmch_ctl
< 0xf0)
2385 return gen9_gmch_ctl
<< 25; /* 32 MB units */
2387 /* 4MB increments starting at 0xf0 for 4MB */
2388 return (gen9_gmch_ctl
- 0xf0 + 1) << 22;
2391 static int ggtt_probe_common(struct drm_device
*dev
,
2394 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2395 struct i915_page_scratch
*scratch_page
;
2396 phys_addr_t gtt_phys_addr
;
2398 /* For Modern GENs the PTEs and register space are split in the BAR */
2399 gtt_phys_addr
= pci_resource_start(dev
->pdev
, 0) +
2400 (pci_resource_len(dev
->pdev
, 0) / 2);
2403 * On BXT writes larger than 64 bit to the GTT pagetable range will be
2404 * dropped. For WC mappings in general we have 64 byte burst writes
2405 * when the WC buffer is flushed, so we can't use it, but have to
2406 * resort to an uncached mapping. The WC issue is easily caught by the
2407 * readback check when writing GTT PTE entries.
2409 if (IS_BROXTON(dev
))
2410 dev_priv
->gtt
.gsm
= ioremap_nocache(gtt_phys_addr
, gtt_size
);
2412 dev_priv
->gtt
.gsm
= ioremap_wc(gtt_phys_addr
, gtt_size
);
2413 if (!dev_priv
->gtt
.gsm
) {
2414 DRM_ERROR("Failed to map the gtt page table\n");
2418 scratch_page
= alloc_scratch_page(dev
);
2419 if (IS_ERR(scratch_page
)) {
2420 DRM_ERROR("Scratch setup failed\n");
2421 /* iounmap will also get called at remove, but meh */
2422 iounmap(dev_priv
->gtt
.gsm
);
2423 return PTR_ERR(scratch_page
);
2426 dev_priv
->gtt
.base
.scratch_page
= scratch_page
;
2431 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
2432 * bits. When using advanced contexts each context stores its own PAT, but
2433 * writing this data shouldn't be harmful even in those cases. */
2434 static void bdw_setup_private_ppat(struct drm_i915_private
*dev_priv
)
2438 pat
= GEN8_PPAT(0, GEN8_PPAT_WB
| GEN8_PPAT_LLC
) | /* for normal objects, no eLLC */
2439 GEN8_PPAT(1, GEN8_PPAT_WC
| GEN8_PPAT_LLCELLC
) | /* for something pointing to ptes? */
2440 GEN8_PPAT(2, GEN8_PPAT_WT
| GEN8_PPAT_LLCELLC
) | /* for scanout with eLLC */
2441 GEN8_PPAT(3, GEN8_PPAT_UC
) | /* Uncached objects, mostly for scanout */
2442 GEN8_PPAT(4, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(0)) |
2443 GEN8_PPAT(5, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(1)) |
2444 GEN8_PPAT(6, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(2)) |
2445 GEN8_PPAT(7, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(3));
2447 if (!USES_PPGTT(dev_priv
->dev
))
2448 /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
2449 * so RTL will always use the value corresponding to
2451 * So let's disable cache for GGTT to avoid screen corruptions.
2452 * MOCS still can be used though.
2453 * - System agent ggtt writes (i.e. cpu gtt mmaps) already work
2454 * before this patch, i.e. the same uncached + snooping access
2455 * like on gen6/7 seems to be in effect.
2456 * - So this just fixes blitter/render access. Again it looks
2457 * like it's not just uncached access, but uncached + snooping.
2458 * So we can still hold onto all our assumptions wrt cpu
2459 * clflushing on LLC machines.
2461 pat
= GEN8_PPAT(0, GEN8_PPAT_UC
);
2463 /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
2464 * write would work. */
2465 I915_WRITE(GEN8_PRIVATE_PAT
, pat
);
2466 I915_WRITE(GEN8_PRIVATE_PAT
+ 4, pat
>> 32);
2469 static void chv_setup_private_ppat(struct drm_i915_private
*dev_priv
)
2474 * Map WB on BDW to snooped on CHV.
2476 * Only the snoop bit has meaning for CHV, the rest is
2479 * The hardware will never snoop for certain types of accesses:
2480 * - CPU GTT (GMADR->GGTT->no snoop->memory)
2481 * - PPGTT page tables
2482 * - some other special cycles
2484 * As with BDW, we also need to consider the following for GT accesses:
2485 * "For GGTT, there is NO pat_sel[2:0] from the entry,
2486 * so RTL will always use the value corresponding to
2488 * Which means we must set the snoop bit in PAT entry 0
2489 * in order to keep the global status page working.
2491 pat
= GEN8_PPAT(0, CHV_PPAT_SNOOP
) |
2495 GEN8_PPAT(4, CHV_PPAT_SNOOP
) |
2496 GEN8_PPAT(5, CHV_PPAT_SNOOP
) |
2497 GEN8_PPAT(6, CHV_PPAT_SNOOP
) |
2498 GEN8_PPAT(7, CHV_PPAT_SNOOP
);
2500 I915_WRITE(GEN8_PRIVATE_PAT
, pat
);
2501 I915_WRITE(GEN8_PRIVATE_PAT
+ 4, pat
>> 32);
2504 static int gen8_gmch_probe(struct drm_device
*dev
,
2507 phys_addr_t
*mappable_base
,
2510 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2515 /* TODO: We're not aware of mappable constraints on gen8 yet */
2516 *mappable_base
= pci_resource_start(dev
->pdev
, 2);
2517 *mappable_end
= pci_resource_len(dev
->pdev
, 2);
2520 if (!pci_set_dma_mask(dev
->pdev
, DMA_BIT_MASK(39)))
2521 pci_set_consistent_dma_mask(dev
->pdev
, DMA_BIT_MASK(39));
2524 pci_read_config_word(dev
->pdev
, SNB_GMCH_CTRL
, &snb_gmch_ctl
);
2526 if (INTEL_INFO(dev
)->gen
>= 9) {
2527 *stolen
= gen9_get_stolen_size(snb_gmch_ctl
);
2528 gtt_size
= gen8_get_total_gtt_size(snb_gmch_ctl
);
2529 } else if (IS_CHERRYVIEW(dev
)) {
2530 *stolen
= chv_get_stolen_size(snb_gmch_ctl
);
2531 gtt_size
= chv_get_total_gtt_size(snb_gmch_ctl
);
2533 *stolen
= gen8_get_stolen_size(snb_gmch_ctl
);
2534 gtt_size
= gen8_get_total_gtt_size(snb_gmch_ctl
);
2537 *gtt_total
= (gtt_size
/ sizeof(gen8_pte_t
)) << PAGE_SHIFT
;
2539 if (IS_CHERRYVIEW(dev
) || IS_BROXTON(dev
))
2540 chv_setup_private_ppat(dev_priv
);
2542 bdw_setup_private_ppat(dev_priv
);
2544 ret
= ggtt_probe_common(dev
, gtt_size
);
2546 dev_priv
->gtt
.base
.clear_range
= gen8_ggtt_clear_range
;
2547 dev_priv
->gtt
.base
.insert_entries
= gen8_ggtt_insert_entries
;
2548 dev_priv
->gtt
.base
.bind_vma
= ggtt_bind_vma
;
2549 dev_priv
->gtt
.base
.unbind_vma
= ggtt_unbind_vma
;
2554 static int gen6_gmch_probe(struct drm_device
*dev
,
2557 phys_addr_t
*mappable_base
,
2560 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2561 unsigned int gtt_size
;
2565 *mappable_base
= pci_resource_start(dev
->pdev
, 2);
2566 *mappable_end
= pci_resource_len(dev
->pdev
, 2);
2568 /* 64/512MB is the current min/max we actually know of, but this is just
2569 * a coarse sanity check.
2571 if ((*mappable_end
< (64<<20) || (*mappable_end
> (512<<20)))) {
2572 DRM_ERROR("Unknown GMADR size (%lx)\n",
2573 dev_priv
->gtt
.mappable_end
);
2578 if (!pci_set_dma_mask(dev
->pdev
, DMA_BIT_MASK(40)))
2579 pci_set_consistent_dma_mask(dev
->pdev
, DMA_BIT_MASK(40));
2581 pci_read_config_word(dev
->pdev
, SNB_GMCH_CTRL
, &snb_gmch_ctl
);
2583 *stolen
= gen6_get_stolen_size(snb_gmch_ctl
);
2585 gtt_size
= gen6_get_total_gtt_size(snb_gmch_ctl
);
2586 *gtt_total
= (gtt_size
/ sizeof(gen6_pte_t
)) << PAGE_SHIFT
;
2588 ret
= ggtt_probe_common(dev
, gtt_size
);
2590 dev_priv
->gtt
.base
.clear_range
= gen6_ggtt_clear_range
;
2591 dev_priv
->gtt
.base
.insert_entries
= gen6_ggtt_insert_entries
;
2592 dev_priv
->gtt
.base
.bind_vma
= ggtt_bind_vma
;
2593 dev_priv
->gtt
.base
.unbind_vma
= ggtt_unbind_vma
;
2598 static void gen6_gmch_remove(struct i915_address_space
*vm
)
2600 struct i915_gtt
*gtt
= container_of(vm
, struct i915_gtt
, base
);
2603 free_scratch_page(vm
->dev
, vm
->scratch_page
);
2606 static int i915_gmch_probe(struct drm_device
*dev
,
2609 phys_addr_t
*mappable_base
,
2612 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2616 ret
= intel_gmch_probe(dev_priv
->bridge_dev
, dev_priv
->dev
->pdev
, NULL
);
2618 DRM_ERROR("failed to set up gmch\n");
2623 intel_gtt_get(gtt_total
, stolen
, mappable_base
, mappable_end
);
2625 dev_priv
->gtt
.do_idle_maps
= needs_idle_maps(dev_priv
->dev
);
2626 dev_priv
->gtt
.base
.insert_entries
= i915_ggtt_insert_entries
;
2627 dev_priv
->gtt
.base
.clear_range
= i915_ggtt_clear_range
;
2628 dev_priv
->gtt
.base
.bind_vma
= ggtt_bind_vma
;
2629 dev_priv
->gtt
.base
.unbind_vma
= ggtt_unbind_vma
;
2631 if (unlikely(dev_priv
->gtt
.do_idle_maps
))
2632 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
2637 static void i915_gmch_remove(struct i915_address_space
*vm
)
2639 intel_gmch_remove();
2642 int i915_gem_gtt_init(struct drm_device
*dev
)
2644 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2645 struct i915_gtt
*gtt
= &dev_priv
->gtt
;
2648 if (INTEL_INFO(dev
)->gen
<= 5) {
2649 gtt
->gtt_probe
= i915_gmch_probe
;
2650 gtt
->base
.cleanup
= i915_gmch_remove
;
2651 } else if (INTEL_INFO(dev
)->gen
< 8) {
2652 gtt
->gtt_probe
= gen6_gmch_probe
;
2653 gtt
->base
.cleanup
= gen6_gmch_remove
;
2654 if (IS_HASWELL(dev
) && dev_priv
->ellc_size
)
2655 gtt
->base
.pte_encode
= iris_pte_encode
;
2656 else if (IS_HASWELL(dev
))
2657 gtt
->base
.pte_encode
= hsw_pte_encode
;
2658 else if (IS_VALLEYVIEW(dev
))
2659 gtt
->base
.pte_encode
= byt_pte_encode
;
2660 else if (INTEL_INFO(dev
)->gen
>= 7)
2661 gtt
->base
.pte_encode
= ivb_pte_encode
;
2663 gtt
->base
.pte_encode
= snb_pte_encode
;
2665 dev_priv
->gtt
.gtt_probe
= gen8_gmch_probe
;
2666 dev_priv
->gtt
.base
.cleanup
= gen6_gmch_remove
;
2669 gtt
->base
.dev
= dev
;
2671 ret
= gtt
->gtt_probe(dev
, >t
->base
.total
, >t
->stolen_size
,
2672 >t
->mappable_base
, >t
->mappable_end
);
2676 /* GMADR is the PCI mmio aperture into the global GTT. */
2677 DRM_INFO("Memory usable by graphics device = %luM\n",
2678 gtt
->base
.total
>> 20);
2679 DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt
->mappable_end
>> 20);
2680 DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt
->stolen_size
>> 20);
2681 #ifdef CONFIG_INTEL_IOMMU
2682 if (intel_iommu_gfx_mapped
)
2683 DRM_INFO("VT-d active for gfx access\n");
2686 * i915.enable_ppgtt is read-only, so do an early pass to validate the
2687 * user's requested state against the hardware/driver capabilities. We
2688 * do this now so that we can print out any log messages once rather
2689 * than every time we check intel_enable_ppgtt().
2691 i915
.enable_ppgtt
= sanitize_enable_ppgtt(dev
, i915
.enable_ppgtt
);
2692 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915
.enable_ppgtt
);
2697 void i915_gem_restore_gtt_mappings(struct drm_device
*dev
)
2699 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2700 struct drm_i915_gem_object
*obj
;
2701 struct i915_address_space
*vm
;
2703 i915_check_and_clear_faults(dev
);
2705 /* First fill our portion of the GTT with scratch pages */
2706 dev_priv
->gtt
.base
.clear_range(&dev_priv
->gtt
.base
,
2707 dev_priv
->gtt
.base
.start
,
2708 dev_priv
->gtt
.base
.total
,
2711 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
2712 struct i915_vma
*vma
= i915_gem_obj_to_vma(obj
,
2713 &dev_priv
->gtt
.base
);
2717 i915_gem_clflush_object(obj
, obj
->pin_display
);
2718 WARN_ON(i915_vma_bind(vma
, obj
->cache_level
, PIN_UPDATE
));
2722 if (INTEL_INFO(dev
)->gen
>= 8) {
2723 if (IS_CHERRYVIEW(dev
) || IS_BROXTON(dev
))
2724 chv_setup_private_ppat(dev_priv
);
2726 bdw_setup_private_ppat(dev_priv
);
2731 if (USES_PPGTT(dev
)) {
2732 list_for_each_entry(vm
, &dev_priv
->vm_list
, global_link
) {
2733 /* TODO: Perhaps it shouldn't be gen6 specific */
2735 struct i915_hw_ppgtt
*ppgtt
=
2736 container_of(vm
, struct i915_hw_ppgtt
,
2739 if (i915_is_ggtt(vm
))
2740 ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2742 gen6_write_page_range(dev_priv
, &ppgtt
->pd
,
2743 0, ppgtt
->base
.total
);
2747 i915_ggtt_flush(dev_priv
);
2750 static struct i915_vma
*
2751 __i915_gem_vma_create(struct drm_i915_gem_object
*obj
,
2752 struct i915_address_space
*vm
,
2753 const struct i915_ggtt_view
*ggtt_view
)
2755 struct i915_vma
*vma
;
2757 if (WARN_ON(i915_is_ggtt(vm
) != !!ggtt_view
))
2758 return ERR_PTR(-EINVAL
);
2760 vma
= kzalloc(sizeof(*vma
), GFP_KERNEL
);
2762 return ERR_PTR(-ENOMEM
);
2764 INIT_LIST_HEAD(&vma
->vma_link
);
2765 INIT_LIST_HEAD(&vma
->mm_list
);
2766 INIT_LIST_HEAD(&vma
->exec_list
);
2770 if (i915_is_ggtt(vm
))
2771 vma
->ggtt_view
= *ggtt_view
;
2773 list_add_tail(&vma
->vma_link
, &obj
->vma_list
);
2774 if (!i915_is_ggtt(vm
))
2775 i915_ppgtt_get(i915_vm_to_ppgtt(vm
));
2781 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object
*obj
,
2782 struct i915_address_space
*vm
)
2784 struct i915_vma
*vma
;
2786 vma
= i915_gem_obj_to_vma(obj
, vm
);
2788 vma
= __i915_gem_vma_create(obj
, vm
,
2789 i915_is_ggtt(vm
) ? &i915_ggtt_view_normal
: NULL
);
2795 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object
*obj
,
2796 const struct i915_ggtt_view
*view
)
2798 struct i915_address_space
*ggtt
= i915_obj_to_ggtt(obj
);
2799 struct i915_vma
*vma
;
2802 return ERR_PTR(-EINVAL
);
2804 vma
= i915_gem_obj_to_ggtt_view(obj
, view
);
2810 vma
= __i915_gem_vma_create(obj
, ggtt
, view
);
2817 rotate_pages(dma_addr_t
*in
, unsigned int width
, unsigned int height
,
2818 struct sg_table
*st
)
2820 unsigned int column
, row
;
2821 unsigned int src_idx
;
2822 struct scatterlist
*sg
= st
->sgl
;
2826 for (column
= 0; column
< width
; column
++) {
2827 src_idx
= width
* (height
- 1) + column
;
2828 for (row
= 0; row
< height
; row
++) {
2830 /* We don't need the pages, but need to initialize
2831 * the entries so the sg list can be happily traversed.
2832 * The only thing we need are DMA addresses.
2834 sg_set_page(sg
, NULL
, PAGE_SIZE
, 0);
2835 sg_dma_address(sg
) = in
[src_idx
];
2836 sg_dma_len(sg
) = PAGE_SIZE
;
2843 static struct sg_table
*
2844 intel_rotate_fb_obj_pages(struct i915_ggtt_view
*ggtt_view
,
2845 struct drm_i915_gem_object
*obj
)
2847 struct intel_rotation_info
*rot_info
= &ggtt_view
->rotation_info
;
2848 unsigned int size_pages
= rot_info
->size
>> PAGE_SHIFT
;
2849 struct sg_page_iter sg_iter
;
2851 dma_addr_t
*page_addr_list
;
2852 struct sg_table
*st
;
2855 /* Allocate a temporary list of source pages for random access. */
2856 page_addr_list
= drm_malloc_ab(obj
->base
.size
/ PAGE_SIZE
,
2857 sizeof(dma_addr_t
));
2858 if (!page_addr_list
)
2859 return ERR_PTR(ret
);
2861 /* Allocate target SG list. */
2862 st
= kmalloc(sizeof(*st
), M_DRM
, M_WAITOK
);
2866 ret
= sg_alloc_table(st
, size_pages
, GFP_KERNEL
);
2870 /* Populate source page list from the object. */
2872 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
, 0) {
2873 page_addr_list
[i
] = sg_page_iter_dma_address(&sg_iter
);
2877 /* Rotate the pages. */
2878 rotate_pages(page_addr_list
,
2879 rot_info
->width_pages
, rot_info
->height_pages
,
2883 "Created rotated page mapping for object size %zu (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages).\n",
2884 obj
->base
.size
, rot_info
->pitch
, rot_info
->height
,
2885 rot_info
->pixel_format
, rot_info
->width_pages
,
2886 rot_info
->height_pages
, size_pages
);
2888 drm_free_large(page_addr_list
);
2895 drm_free_large(page_addr_list
);
2898 "Failed to create rotated mapping for object size %zu! (%d) (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages)\n",
2899 obj
->base
.size
, ret
, rot_info
->pitch
, rot_info
->height
,
2900 rot_info
->pixel_format
, rot_info
->width_pages
,
2901 rot_info
->height_pages
, size_pages
);
2902 return ERR_PTR(ret
);
2905 static struct sg_table
*
2906 intel_partial_pages(const struct i915_ggtt_view
*view
,
2907 struct drm_i915_gem_object
*obj
)
2909 struct sg_table
*st
;
2910 struct scatterlist
*sg
;
2911 struct sg_page_iter obj_sg_iter
;
2914 st
= kmalloc(sizeof(*st
), M_DRM
, M_WAITOK
);
2918 ret
= sg_alloc_table(st
, view
->params
.partial
.size
, GFP_KERNEL
);
2924 for_each_sg_page(obj
->pages
->sgl
, &obj_sg_iter
, obj
->pages
->nents
,
2925 view
->params
.partial
.offset
)
2927 if (st
->nents
>= view
->params
.partial
.size
)
2930 sg_set_page(sg
, NULL
, PAGE_SIZE
, 0);
2931 sg_dma_address(sg
) = sg_page_iter_dma_address(&obj_sg_iter
);
2932 sg_dma_len(sg
) = PAGE_SIZE
;
2943 return ERR_PTR(ret
);
2947 i915_get_ggtt_vma_pages(struct i915_vma
*vma
)
2951 if (vma
->ggtt_view
.pages
)
2954 if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
)
2955 vma
->ggtt_view
.pages
= vma
->obj
->pages
;
2956 else if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_ROTATED
)
2957 vma
->ggtt_view
.pages
=
2958 intel_rotate_fb_obj_pages(&vma
->ggtt_view
, vma
->obj
);
2959 else if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_PARTIAL
)
2960 vma
->ggtt_view
.pages
=
2961 intel_partial_pages(&vma
->ggtt_view
, vma
->obj
);
2963 WARN_ONCE(1, "GGTT view %u not implemented!\n",
2964 vma
->ggtt_view
.type
);
2966 if (!vma
->ggtt_view
.pages
) {
2967 DRM_ERROR("Failed to get pages for GGTT view type %u!\n",
2968 vma
->ggtt_view
.type
);
2970 } else if (IS_ERR(vma
->ggtt_view
.pages
)) {
2971 ret
= PTR_ERR(vma
->ggtt_view
.pages
);
2972 vma
->ggtt_view
.pages
= NULL
;
2973 DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n",
2974 vma
->ggtt_view
.type
, ret
);
2981 * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space.
2983 * @cache_level: mapping cache level
2984 * @flags: flags like global or local mapping
2986 * DMA addresses are taken from the scatter-gather table of this object (or of
2987 * this VMA in case of non-default GGTT views) and PTE entries set up.
2988 * Note that DMA addresses are also the only part of the SG table we care about.
2990 int i915_vma_bind(struct i915_vma
*vma
, enum i915_cache_level cache_level
,
2996 if (WARN_ON(flags
== 0))
3000 if (flags
& PIN_GLOBAL
)
3001 bind_flags
|= GLOBAL_BIND
;
3002 if (flags
& PIN_USER
)
3003 bind_flags
|= LOCAL_BIND
;
3005 if (flags
& PIN_UPDATE
)
3006 bind_flags
|= vma
->bound
;
3008 bind_flags
&= ~vma
->bound
;
3010 if (bind_flags
== 0)
3013 if (vma
->bound
== 0 && vma
->vm
->allocate_va_range
) {
3014 trace_i915_va_alloc(vma
->vm
,
3017 VM_TO_TRACE_NAME(vma
->vm
));
3019 /* XXX: i915_vma_pin() will fix this +- hack */
3021 ret
= vma
->vm
->allocate_va_range(vma
->vm
,
3029 ret
= vma
->vm
->bind_vma(vma
, cache_level
, bind_flags
);
3033 vma
->bound
|= bind_flags
;
3039 * i915_ggtt_view_size - Get the size of a GGTT view.
3040 * @obj: Object the view is of.
3041 * @view: The view in question.
3043 * @return The size of the GGTT view in bytes.
3046 i915_ggtt_view_size(struct drm_i915_gem_object
*obj
,
3047 const struct i915_ggtt_view
*view
)
3049 if (view
->type
== I915_GGTT_VIEW_NORMAL
) {
3050 return obj
->base
.size
;
3051 } else if (view
->type
== I915_GGTT_VIEW_ROTATED
) {
3052 return view
->rotation_info
.size
;
3053 } else if (view
->type
== I915_GGTT_VIEW_PARTIAL
) {
3054 return view
->params
.partial
.size
<< PAGE_SHIFT
;
3056 WARN_ONCE(1, "GGTT view %u not implemented!\n", view
->type
);
3057 return obj
->base
.size
;