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pci: Bring back 3f607eb6e6bf8981c33dc29fd477005f364fa9ce
[dragonfly.git] / sys / bus / pci / pci.c
blob7b02833fe358b1843397199d1c678a975062a7f2
1 /*-
2 * Copyright (c) 1997, Stefan Esser <se@kfreebsd.org>
3 * Copyright (c) 2000, Michael Smith <msmith@kfreebsd.org>
4 * Copyright (c) 2000, BSDi
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
12 * disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 * __FBSDID("$FreeBSD: src/sys/dev/pci/pci.c,v 1.355.2.9.2.1 2009/04/15 03:14:26 kensmith Exp $");
28 */
29
30 #include <sys/cdefs.h>
31
32 #include "opt_bus.h"
33
34 #include <sys/param.h>
35 #include <sys/systm.h>
36 #include <sys/malloc.h>
37 #include <sys/module.h>
38 #include <sys/linker.h>
39 #include <sys/fcntl.h>
40 #include <sys/conf.h>
41 #include <sys/kernel.h>
42 #include <sys/queue.h>
43 #include <sys/sysctl.h>
44 #include <sys/endian.h>
45
46 #ifdef APIC_IO
47 #include <machine/smp.h>
48 #endif
49
50 #include <vm/vm.h>
51 #include <vm/pmap.h>
52 #include <vm/vm_extern.h>
53
54 #include <sys/bus.h>
55 #include <sys/rman.h>
56 #include <sys/device.h>
57
58 #include <sys/pciio.h>
59 #include <bus/pci/pcireg.h>
60 #include <bus/pci/pcivar.h>
61 #include <bus/pci/pci_private.h>
62
63 #include "pcib_if.h"
64 #include "pci_if.h"
65
66 #ifdef __HAVE_ACPI
67 #include <contrib/dev/acpica/acpi.h>
68 #include "acpi_if.h"
69 #else
70 #define ACPI_PWR_FOR_SLEEP(x, y, z)
71 #endif
72
73 static uint32_t pci_mapbase(unsigned mapreg);
74 static const char *pci_maptype(unsigned mapreg);
75 static int pci_mapsize(unsigned testval);
76 static int pci_maprange(unsigned mapreg);
77 static void pci_fixancient(pcicfgregs *cfg);
78
79 static int pci_porten(device_t pcib, int b, int s, int f);
80 static int pci_memen(device_t pcib, int b, int s, int f);
81 static void pci_assign_interrupt(device_t bus, device_t dev,
82 int force_route);
83 static int pci_add_map(device_t pcib, device_t bus, device_t dev,
84 int b, int s, int f, int reg,
85 struct resource_list *rl, int force, int prefetch);
86 static int pci_probe(device_t dev);
87 static int pci_attach(device_t dev);
88 static void pci_child_detached(device_t, device_t);
89 static void pci_load_vendor_data(void);
90 static int pci_describe_parse_line(char **ptr, int *vendor,
91 int *device, char **desc);
92 static char *pci_describe_device(device_t dev);
93 static int pci_modevent(module_t mod, int what, void *arg);
94 static void pci_hdrtypedata(device_t pcib, int b, int s, int f,
95 pcicfgregs *cfg);
96 static void pci_read_extcap(device_t pcib, pcicfgregs *cfg);
97 static int pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg,
98 int reg, uint32_t *data);
99 #if 0
100 static int pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg,
101 int reg, uint32_t data);
102 #endif
103 static void pci_read_vpd(device_t pcib, pcicfgregs *cfg);
104 static void pci_disable_msi(device_t dev);
105 static void pci_enable_msi(device_t dev, uint64_t address,
106 uint16_t data);
107 static void pci_enable_msix(device_t dev, u_int index,
108 uint64_t address, uint32_t data);
109 static void pci_mask_msix(device_t dev, u_int index);
110 static void pci_unmask_msix(device_t dev, u_int index);
111 static int pci_msi_blacklisted(void);
112 static void pci_resume_msi(device_t dev);
113 static void pci_resume_msix(device_t dev);
114
115 static device_method_t pci_methods[] = {
116 /* Device interface */
117 DEVMETHOD(device_probe, pci_probe),
118 DEVMETHOD(device_attach, pci_attach),
119 DEVMETHOD(device_detach, bus_generic_detach),
120 DEVMETHOD(device_shutdown, bus_generic_shutdown),
121 DEVMETHOD(device_suspend, pci_suspend),
122 DEVMETHOD(device_resume, pci_resume),
123
124 /* Bus interface */
125 DEVMETHOD(bus_print_child, pci_print_child),
126 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
127 DEVMETHOD(bus_read_ivar, pci_read_ivar),
128 DEVMETHOD(bus_write_ivar, pci_write_ivar),
129 DEVMETHOD(bus_driver_added, pci_driver_added),
130 DEVMETHOD(bus_child_detached, pci_child_detached),
131 DEVMETHOD(bus_setup_intr, pci_setup_intr),
132 DEVMETHOD(bus_teardown_intr, pci_teardown_intr),
133
134 DEVMETHOD(bus_get_resource_list,pci_get_resource_list),
135 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
136 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
137 DEVMETHOD(bus_delete_resource, pci_delete_resource),
138 DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
139 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource),
140 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
141 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
142 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method),
143 DEVMETHOD(bus_child_location_str, pci_child_location_str_method),
144
145 /* PCI interface */
146 DEVMETHOD(pci_read_config, pci_read_config_method),
147 DEVMETHOD(pci_write_config, pci_write_config_method),
148 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method),
149 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method),
150 DEVMETHOD(pci_enable_io, pci_enable_io_method),
151 DEVMETHOD(pci_disable_io, pci_disable_io_method),
152 DEVMETHOD(pci_get_vpd_ident, pci_get_vpd_ident_method),
153 DEVMETHOD(pci_get_vpd_readonly, pci_get_vpd_readonly_method),
154 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method),
155 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method),
156 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method),
157 DEVMETHOD(pci_find_extcap, pci_find_extcap_method),
158 DEVMETHOD(pci_alloc_msi, pci_alloc_msi_method),
159 DEVMETHOD(pci_alloc_msix, pci_alloc_msix_method),
160 DEVMETHOD(pci_remap_msix, pci_remap_msix_method),
161 DEVMETHOD(pci_release_msi, pci_release_msi_method),
162 DEVMETHOD(pci_msi_count, pci_msi_count_method),
163 DEVMETHOD(pci_msix_count, pci_msix_count_method),
164
165 { 0, 0 }
166 };
167
168 DEFINE_CLASS_0(pci, pci_driver, pci_methods, 0);
169
170 static devclass_t pci_devclass;
171 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0);
172 MODULE_VERSION(pci, 1);
173
174 static char *pci_vendordata;
175 static size_t pci_vendordata_size;
176
177
178 struct pci_quirk {
179 uint32_t devid; /* Vendor/device of the card */
180 int type;
181 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */
182 #define PCI_QUIRK_DISABLE_MSI 2 /* MSI/MSI-X doesn't work */
183 int arg1;
184 int arg2;
185 };
186
187 struct pci_quirk pci_quirks[] = {
188 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */
189 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },
190 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 },
191 /* As does the Serverworks OSB4 (the SMBus mapping register) */
192 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 },
193
194 /*
195 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge
196 * or the CMIC-SL (AKA ServerWorks GC_LE).
197 */
198 { 0x00141166, PCI_QUIRK_DISABLE_MSI, 0, 0 },
199 { 0x00171166, PCI_QUIRK_DISABLE_MSI, 0, 0 },
200
201 /*
202 * MSI doesn't work on earlier Intel chipsets including
203 * E7500, E7501, E7505, 845, 865, 875/E7210, and 855.
204 */
205 { 0x25408086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
206 { 0x254c8086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
207 { 0x25508086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
208 { 0x25608086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
209 { 0x25708086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
210 { 0x25788086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
211 { 0x35808086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
212
213 /*
214 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX
215 * bridge.
216 */
217 { 0x74501022, PCI_QUIRK_DISABLE_MSI, 0, 0 },
218
219 { 0 }
220 };
221
222 /* map register information */
223 #define PCI_MAPMEM 0x01 /* memory map */
224 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */
225 #define PCI_MAPPORT 0x04 /* port map */
226
227 struct devlist pci_devq;
228 uint32_t pci_generation;
229 uint32_t pci_numdevs = 0;
230 static int pcie_chipset, pcix_chipset;
231
232 /* sysctl vars */
233 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters");
234
235 static int pci_enable_io_modes = 1;
236 TUNABLE_INT("hw.pci.enable_io_modes", &pci_enable_io_modes);
237 SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW,
238 &pci_enable_io_modes, 1,
239 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\
240 enable these bits correctly. We'd like to do this all the time, but there\n\
241 are some peripherals that this causes problems with.");
242
243 static int pci_do_power_nodriver = 0;
244 TUNABLE_INT("hw.pci.do_power_nodriver", &pci_do_power_nodriver);
245 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RW,
246 &pci_do_power_nodriver, 0,
247 "Place a function into D3 state when no driver attaches to it. 0 means\n\
248 disable. 1 means conservatively place devices into D3 state. 2 means\n\
249 aggressively place devices into D3 state. 3 means put absolutely everything\n\
250 in D3 state.");
251
252 static int pci_do_power_resume = 1;
253 TUNABLE_INT("hw.pci.do_power_resume", &pci_do_power_resume);
254 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RW,
255 &pci_do_power_resume, 1,
256 "Transition from D3 -> D0 on resume.");
257
258 static int pci_do_msi = 1;
259 TUNABLE_INT("hw.pci.enable_msi", &pci_do_msi);
260 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msi, CTLFLAG_RW, &pci_do_msi, 1,
261 "Enable support for MSI interrupts");
262
263 static int pci_do_msix = 1;
264 TUNABLE_INT("hw.pci.enable_msix", &pci_do_msix);
265 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msix, CTLFLAG_RW, &pci_do_msix, 1,
266 "Enable support for MSI-X interrupts");
267
268 static int pci_honor_msi_blacklist = 1;
269 TUNABLE_INT("hw.pci.honor_msi_blacklist", &pci_honor_msi_blacklist);
270 SYSCTL_INT(_hw_pci, OID_AUTO, honor_msi_blacklist, CTLFLAG_RD,
271 &pci_honor_msi_blacklist, 1, "Honor chipset blacklist for MSI");
272
273 /* Find a device_t by bus/slot/function in domain 0 */
274
275 device_t
276 pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func)
277 {
278
279 return (pci_find_dbsf(0, bus, slot, func));
280 }
281
282 /* Find a device_t by domain/bus/slot/function */
283
284 device_t
285 pci_find_dbsf(uint32_t domain, uint8_t bus, uint8_t slot, uint8_t func)
286 {
287 struct pci_devinfo *dinfo;
288
289 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
290 if ((dinfo->cfg.domain == domain) &&
291 (dinfo->cfg.bus == bus) &&
292 (dinfo->cfg.slot == slot) &&
293 (dinfo->cfg.func == func)) {
294 return (dinfo->cfg.dev);
295 }
296 }
297
298 return (NULL);
299 }
300
301 /* Find a device_t by vendor/device ID */
302
303 device_t
304 pci_find_device(uint16_t vendor, uint16_t device)
305 {
306 struct pci_devinfo *dinfo;
307
308 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
309 if ((dinfo->cfg.vendor == vendor) &&
310 (dinfo->cfg.device == device)) {
311 return (dinfo->cfg.dev);
312 }
313 }
314
315 return (NULL);
316 }
317
318 /* return base address of memory or port map */
319
320 static uint32_t
321 pci_mapbase(uint32_t mapreg)
322 {
323
324 if (PCI_BAR_MEM(mapreg))
325 return (mapreg & PCIM_BAR_MEM_BASE);
326 else
327 return (mapreg & PCIM_BAR_IO_BASE);
328 }
329
330 /* return map type of memory or port map */
331
332 static const char *
333 pci_maptype(unsigned mapreg)
334 {
335
336 if (PCI_BAR_IO(mapreg))
337 return ("I/O Port");
338 if (mapreg & PCIM_BAR_MEM_PREFETCH)
339 return ("Prefetchable Memory");
340 return ("Memory");
341 }
342
343 /* return log2 of map size decoded for memory or port map */
344
345 static int
346 pci_mapsize(uint32_t testval)
347 {
348 int ln2size;
349
350 testval = pci_mapbase(testval);
351 ln2size = 0;
352 if (testval != 0) {
353 while ((testval & 1) == 0)
354 {
355 ln2size++;
356 testval >>= 1;
357 }
358 }
359 return (ln2size);
360 }
361
362 /* return log2 of address range supported by map register */
363
364 static int
365 pci_maprange(unsigned mapreg)
366 {
367 int ln2range = 0;
368
369 if (PCI_BAR_IO(mapreg))
370 ln2range = 32;
371 else
372 switch (mapreg & PCIM_BAR_MEM_TYPE) {
373 case PCIM_BAR_MEM_32:
374 ln2range = 32;
375 break;
376 case PCIM_BAR_MEM_1MB:
377 ln2range = 20;
378 break;
379 case PCIM_BAR_MEM_64:
380 ln2range = 64;
381 break;
382 }
383 return (ln2range);
384 }
385
386 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */
387
388 static void
389 pci_fixancient(pcicfgregs *cfg)
390 {
391 if (cfg->hdrtype != 0)
392 return;
393
394 /* PCI to PCI bridges use header type 1 */
395 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
396 cfg->hdrtype = 1;
397 }
398
399 /* extract header type specific config data */
400
401 static void
402 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg)
403 {
404 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
405 switch (cfg->hdrtype) {
406 case 0:
407 cfg->subvendor = REG(PCIR_SUBVEND_0, 2);
408 cfg->subdevice = REG(PCIR_SUBDEV_0, 2);
409 cfg->nummaps = PCI_MAXMAPS_0;
410 break;
411 case 1:
412 cfg->nummaps = PCI_MAXMAPS_1;
413 break;
414 case 2:
415 cfg->subvendor = REG(PCIR_SUBVEND_2, 2);
416 cfg->subdevice = REG(PCIR_SUBDEV_2, 2);
417 cfg->nummaps = PCI_MAXMAPS_2;
418 break;
419 }
420 #undef REG
421 }
422
423 /* read configuration header into pcicfgregs structure */
424 struct pci_devinfo *
425 pci_read_device(device_t pcib, int d, int b, int s, int f, size_t size)
426 {
427 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
428 pcicfgregs *cfg = NULL;
429 struct pci_devinfo *devlist_entry;
430 struct devlist *devlist_head;
431
432 devlist_head = &pci_devq;
433
434 devlist_entry = NULL;
435
436 if (REG(PCIR_DEVVENDOR, 4) != -1) {
437 devlist_entry = kmalloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
438
439 cfg = &devlist_entry->cfg;
440
441 cfg->domain = d;
442 cfg->bus = b;
443 cfg->slot = s;
444 cfg->func = f;
445 cfg->vendor = REG(PCIR_VENDOR, 2);
446 cfg->device = REG(PCIR_DEVICE, 2);
447 cfg->cmdreg = REG(PCIR_COMMAND, 2);
448 cfg->statreg = REG(PCIR_STATUS, 2);
449 cfg->baseclass = REG(PCIR_CLASS, 1);
450 cfg->subclass = REG(PCIR_SUBCLASS, 1);
451 cfg->progif = REG(PCIR_PROGIF, 1);
452 cfg->revid = REG(PCIR_REVID, 1);
453 cfg->hdrtype = REG(PCIR_HDRTYPE, 1);
454 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1);
455 cfg->lattimer = REG(PCIR_LATTIMER, 1);
456 cfg->intpin = REG(PCIR_INTPIN, 1);
457 cfg->intline = REG(PCIR_INTLINE, 1);
458
459 #ifdef APIC_IO
460 /*
461 * If using the APIC the intpin is probably wrong, since it
462 * is often setup by the BIOS with the PIC in mind.
463 */
464 if (cfg->intpin != 0) {
465 int airq;
466
467 airq = pci_apic_irq(cfg->bus, cfg->slot, cfg->intpin);
468 if (airq >= 0) {
469 /* PCI specific entry found in MP table */
470 if (airq != cfg->intline) {
471 undirect_pci_irq(cfg->intline);
472 cfg->intline = airq;
473 }
474 } else {
475 /*
476 * PCI interrupts might be redirected to the
477 * ISA bus according to some MP tables. Use the
478 * same methods as used by the ISA devices
479 * devices to find the proper IOAPIC int pin.
480 */
481 airq = isa_apic_irq(cfg->intline);
482 if ((airq >= 0) && (airq != cfg->intline)) {
483 /* XXX: undirect_pci_irq() ? */
484 undirect_isa_irq(cfg->intline);
485 cfg->intline = airq;
486 }
487 }
488 }
489 #endif /* APIC_IO */
490
491 cfg->mingnt = REG(PCIR_MINGNT, 1);
492 cfg->maxlat = REG(PCIR_MAXLAT, 1);
493
494 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0;
495 cfg->hdrtype &= ~PCIM_MFDEV;
496
497 pci_fixancient(cfg);
498 pci_hdrtypedata(pcib, b, s, f, cfg);
499
500 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT)
501 pci_read_extcap(pcib, cfg);
502
503 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links);
504
505 devlist_entry->conf.pc_sel.pc_domain = cfg->domain;
506 devlist_entry->conf.pc_sel.pc_bus = cfg->bus;
507 devlist_entry->conf.pc_sel.pc_dev = cfg->slot;
508 devlist_entry->conf.pc_sel.pc_func = cfg->func;
509 devlist_entry->conf.pc_hdr = cfg->hdrtype;
510
511 devlist_entry->conf.pc_subvendor = cfg->subvendor;
512 devlist_entry->conf.pc_subdevice = cfg->subdevice;
513 devlist_entry->conf.pc_vendor = cfg->vendor;
514 devlist_entry->conf.pc_device = cfg->device;
515
516 devlist_entry->conf.pc_class = cfg->baseclass;
517 devlist_entry->conf.pc_subclass = cfg->subclass;
518 devlist_entry->conf.pc_progif = cfg->progif;
519 devlist_entry->conf.pc_revid = cfg->revid;
520
521 pci_numdevs++;
522 pci_generation++;
523 }
524 return (devlist_entry);
525 #undef REG
526 }
527
528 static void
529 pci_read_extcap(device_t pcib, pcicfgregs *cfg)
530 {
531 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
532 #define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w)
533 #if defined(__i386__) || defined(__amd64__)
534 uint64_t addr;
535 #endif
536 uint32_t val;
537 int ptr, nextptr, ptrptr;
538
539 switch (cfg->hdrtype & PCIM_HDRTYPE) {
540 case 0:
541 case 1:
542 ptrptr = PCIR_CAP_PTR;
543 break;
544 case 2:
545 ptrptr = PCIR_CAP_PTR_2; /* cardbus capabilities ptr */
546 break;
547 default:
548 return; /* no extended capabilities support */
549 }
550 nextptr = REG(ptrptr, 1); /* sanity check? */
551
552 /*
553 * Read capability entries.
554 */
555 while (nextptr != 0) {
556 /* Sanity check */
557 if (nextptr > 255) {
558 kprintf("illegal PCI extended capability offset %d\n",
559 nextptr);
560 return;
561 }
562 /* Find the next entry */
563 ptr = nextptr;
564 nextptr = REG(ptr + PCICAP_NEXTPTR, 1);
565
566 /* Process this entry */
567 switch (REG(ptr + PCICAP_ID, 1)) {
568 case PCIY_PMG: /* PCI power management */
569 if (cfg->pp.pp_cap == 0) {
570 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
571 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS;
572 cfg->pp.pp_pmcsr = ptr + PCIR_POWER_PMCSR;
573 if ((nextptr - ptr) > PCIR_POWER_DATA)
574 cfg->pp.pp_data = ptr + PCIR_POWER_DATA;
575 }
576 break;
577 #if notyet
578 #if defined(__i386__) || defined(__amd64__)
579 case PCIY_HT: /* HyperTransport */
580 /* Determine HT-specific capability type. */
581 val = REG(ptr + PCIR_HT_COMMAND, 2);
582 switch (val & PCIM_HTCMD_CAP_MASK) {
583 case PCIM_HTCAP_MSI_MAPPING:
584 if (!(val & PCIM_HTCMD_MSI_FIXED)) {
585 /* Sanity check the mapping window. */
586 addr = REG(ptr + PCIR_HTMSI_ADDRESS_HI,
587 4);
588 addr <<= 32;
589 addr |= REG(ptr + PCIR_HTMSI_ADDRESS_LO,
590 4);
591 if (addr != MSI_INTEL_ADDR_BASE)
592 device_printf(pcib,
593 "HT Bridge at pci%d:%d:%d:%d has non-default MSI window 0x%llx\n",
594 cfg->domain, cfg->bus,
595 cfg->slot, cfg->func,
596 (long long)addr);
597 } else
598 addr = MSI_INTEL_ADDR_BASE;
599
600 cfg->ht.ht_msimap = ptr;
601 cfg->ht.ht_msictrl = val;
602 cfg->ht.ht_msiaddr = addr;
603 break;
604 }
605 break;
606 #endif
607 case PCIY_MSI: /* PCI MSI */
608 cfg->msi.msi_location = ptr;
609 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2);
610 cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl &
611 PCIM_MSICTRL_MMC_MASK)>>1);
612 break;
613 case PCIY_MSIX: /* PCI MSI-X */
614 cfg->msix.msix_location = ptr;
615 cfg->msix.msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2);
616 cfg->msix.msix_msgnum = (cfg->msix.msix_ctrl &
617 PCIM_MSIXCTRL_TABLE_SIZE) + 1;
618 val = REG(ptr + PCIR_MSIX_TABLE, 4);
619 cfg->msix.msix_table_bar = PCIR_BAR(val &
620 PCIM_MSIX_BIR_MASK);
621 cfg->msix.msix_table_offset = val & ~PCIM_MSIX_BIR_MASK;
622 val = REG(ptr + PCIR_MSIX_PBA, 4);
623 cfg->msix.msix_pba_bar = PCIR_BAR(val &
624 PCIM_MSIX_BIR_MASK);
625 cfg->msix.msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK;
626 break;
627 #endif
628 case PCIY_VPD: /* PCI Vital Product Data */
629 cfg->vpd.vpd_reg = ptr;
630 break;
631 case PCIY_SUBVENDOR:
632 /* Should always be true. */
633 if ((cfg->hdrtype & PCIM_HDRTYPE) == 1) {
634 val = REG(ptr + PCIR_SUBVENDCAP_ID, 4);
635 cfg->subvendor = val & 0xffff;
636 cfg->subdevice = val >> 16;
637 }
638 break;
639 case PCIY_PCIX: /* PCI-X */
640 /*
641 * Assume we have a PCI-X chipset if we have
642 * at least one PCI-PCI bridge with a PCI-X
643 * capability. Note that some systems with
644 * PCI-express or HT chipsets might match on
645 * this check as well.
646 */
647 if ((cfg->hdrtype & PCIM_HDRTYPE) == 1)
648 pcix_chipset = 1;
649 break;
650 case PCIY_EXPRESS: /* PCI-express */
651 /*
652 * Assume we have a PCI-express chipset if we have
653 * at least one PCI-express device.
654 */
655 pcie_chipset = 1;
656 break;
657 default:
658 break;
659 }
660 }
661 /* REG and WREG use carry through to next functions */
662 }
663
664 /*
665 * PCI Vital Product Data
666 */
667
668 #define PCI_VPD_TIMEOUT 1000000
669
670 static int
671 pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t *data)
672 {
673 int count = PCI_VPD_TIMEOUT;
674
675 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
676
677 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg, 2);
678
679 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) != 0x8000) {
680 if (--count < 0)
681 return (ENXIO);
682 DELAY(1); /* limit looping */
683 }
684 *data = (REG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, 4));
685
686 return (0);
687 }
688
689 #if 0
690 static int
691 pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t data)
692 {
693 int count = PCI_VPD_TIMEOUT;
694
695 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
696
697 WREG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, data, 4);
698 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg | 0x8000, 2);
699 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) == 0x8000) {
700 if (--count < 0)
701 return (ENXIO);
702 DELAY(1); /* limit looping */
703 }
704
705 return (0);
706 }
707 #endif
708
709 #undef PCI_VPD_TIMEOUT
710
711 struct vpd_readstate {
712 device_t pcib;
713 pcicfgregs *cfg;
714 uint32_t val;
715 int bytesinval;
716 int off;
717 uint8_t cksum;
718 };
719
720 static int
721 vpd_nextbyte(struct vpd_readstate *vrs, uint8_t *data)
722 {
723 uint32_t reg;
724 uint8_t byte;
725
726 if (vrs->bytesinval == 0) {
727 if (pci_read_vpd_reg(vrs->pcib, vrs->cfg, vrs->off, &reg))
728 return (ENXIO);
729 vrs->val = le32toh(reg);
730 vrs->off += 4;
731 byte = vrs->val & 0xff;
732 vrs->bytesinval = 3;
733 } else {
734 vrs->val = vrs->val >> 8;
735 byte = vrs->val & 0xff;
736 vrs->bytesinval--;
737 }
738
739 vrs->cksum += byte;
740 *data = byte;
741 return (0);
742 }
743
744 void
745 pcie_set_max_readrq(device_t dev, uint16_t rqsize)
746 {
747 int expr_ptr;
748 uint16_t val;
749 rqsize &= PCIEM_DEVCTL_MAX_READRQ_MASK;
750 if (rqsize > PCIEM_DEVCTL_MAX_READRQ_4096) {
751 panic("%s: invalid max read request size 0x%02x\n",
752 device_get_nameunit(dev), rqsize);
753 }
754 #warning "this code is incorrect, I think"
755 pci_find_extcap_method(device_get_parent(dev), dev, PCIY_EXPRESS, &expr_ptr);
756 if(!expr_ptr)
757 panic("%s: not PCI Express\n", device_get_nameunit(dev));
758 val = pci_read_config(dev, expr_ptr + PCIER_DEVCTRL, 2);
759 if ((val & PCIEM_DEVCTL_MAX_READRQ_MASK) != rqsize) {
760 if (bootverbose)
761 device_printf(dev, "adjust device control 0x%04x", val);
762 val &= ~PCIEM_DEVCTL_MAX_READRQ_MASK;
763 val |= rqsize;
764 pci_write_config(dev, expr_ptr + PCIER_DEVCTRL, val, 2);
765
766 if (bootverbose)
767 kprintf(" -> 0x%04x\n", val);
768 }
769 }
770
771 static void
772 pci_read_vpd(device_t pcib, pcicfgregs *cfg)
773 {
774 struct vpd_readstate vrs;
775 int state;
776 int name;
777 int remain;
778 int i;
779 int alloc, off; /* alloc/off for RO/W arrays */
780 int cksumvalid;
781 int dflen;
782 uint8_t byte;
783 uint8_t byte2;
784
785 /* init vpd reader */
786 vrs.bytesinval = 0;
787 vrs.off = 0;
788 vrs.pcib = pcib;
789 vrs.cfg = cfg;
790 vrs.cksum = 0;
791
792 state = 0;
793 name = remain = i = 0; /* shut up stupid gcc */
794 alloc = off = 0; /* shut up stupid gcc */
795 dflen = 0; /* shut up stupid gcc */
796 cksumvalid = -1;
797 while (state >= 0) {
798 if (vpd_nextbyte(&vrs, &byte)) {
799 state = -2;
800 break;
801 }
802 #if 0
803 kprintf("vpd: val: %#x, off: %d, bytesinval: %d, byte: %#hhx, " \
804 "state: %d, remain: %d, name: %#x, i: %d\n", vrs.val,
805 vrs.off, vrs.bytesinval, byte, state, remain, name, i);
806 #endif
807 switch (state) {
808 case 0: /* item name */
809 if (byte & 0x80) {
810 if (vpd_nextbyte(&vrs, &byte2)) {
811 state = -2;
812 break;
813 }
814 remain = byte2;
815 if (vpd_nextbyte(&vrs, &byte2)) {
816 state = -2;
817 break;
818 }
819 remain |= byte2 << 8;
820 if (remain > (0x7f*4 - vrs.off)) {
821 state = -1;
822 kprintf(
823 "pci%d:%d:%d:%d: invalid VPD data, remain %#x\n",
824 cfg->domain, cfg->bus, cfg->slot,
825 cfg->func, remain);
826 }
827 name = byte & 0x7f;
828 } else {
829 remain = byte & 0x7;
830 name = (byte >> 3) & 0xf;
831 }
832 switch (name) {
833 case 0x2: /* String */
834 cfg->vpd.vpd_ident = kmalloc(remain + 1,
835 M_DEVBUF, M_WAITOK);
836 i = 0;
837 state = 1;
838 break;
839 case 0xf: /* End */
840 state = -1;
841 break;
842 case 0x10: /* VPD-R */
843 alloc = 8;
844 off = 0;
845 cfg->vpd.vpd_ros = kmalloc(alloc *
846 sizeof(*cfg->vpd.vpd_ros), M_DEVBUF,
847 M_WAITOK | M_ZERO);
848 state = 2;
849 break;
850 case 0x11: /* VPD-W */
851 alloc = 8;
852 off = 0;
853 cfg->vpd.vpd_w = kmalloc(alloc *
854 sizeof(*cfg->vpd.vpd_w), M_DEVBUF,
855 M_WAITOK | M_ZERO);
856 state = 5;
857 break;
858 default: /* Invalid data, abort */
859 state = -1;
860 break;
861 }
862 break;
863
864 case 1: /* Identifier String */
865 cfg->vpd.vpd_ident[i++] = byte;
866 remain--;
867 if (remain == 0) {
868 cfg->vpd.vpd_ident[i] = '\0';
869 state = 0;
870 }
871 break;
872
873 case 2: /* VPD-R Keyword Header */
874 if (off == alloc) {
875 cfg->vpd.vpd_ros = krealloc(cfg->vpd.vpd_ros,
876 (alloc *= 2) * sizeof(*cfg->vpd.vpd_ros),
877 M_DEVBUF, M_WAITOK | M_ZERO);
878 }
879 cfg->vpd.vpd_ros[off].keyword[0] = byte;
880 if (vpd_nextbyte(&vrs, &byte2)) {
881 state = -2;
882 break;
883 }
884 cfg->vpd.vpd_ros[off].keyword[1] = byte2;
885 if (vpd_nextbyte(&vrs, &byte2)) {
886 state = -2;
887 break;
888 }
889 dflen = byte2;
890 if (dflen == 0 &&
891 strncmp(cfg->vpd.vpd_ros[off].keyword, "RV",
892 2) == 0) {
893 /*
894 * if this happens, we can't trust the rest
895 * of the VPD.
896 */
897 kprintf(
898 "pci%d:%d:%d:%d: bad keyword length: %d\n",
899 cfg->domain, cfg->bus, cfg->slot,
900 cfg->func, dflen);
901 cksumvalid = 0;
902 state = -1;
903 break;
904 } else if (dflen == 0) {
905 cfg->vpd.vpd_ros[off].value = kmalloc(1 *
906 sizeof(*cfg->vpd.vpd_ros[off].value),
907 M_DEVBUF, M_WAITOK);
908 cfg->vpd.vpd_ros[off].value[0] = '\x00';
909 } else
910 cfg->vpd.vpd_ros[off].value = kmalloc(
911 (dflen + 1) *
912 sizeof(*cfg->vpd.vpd_ros[off].value),
913 M_DEVBUF, M_WAITOK);
914 remain -= 3;
915 i = 0;
916 /* keep in sync w/ state 3's transistions */
917 if (dflen == 0 && remain == 0)
918 state = 0;
919 else if (dflen == 0)
920 state = 2;
921 else
922 state = 3;
923 break;
924
925 case 3: /* VPD-R Keyword Value */
926 cfg->vpd.vpd_ros[off].value[i++] = byte;
927 if (strncmp(cfg->vpd.vpd_ros[off].keyword,
928 "RV", 2) == 0 && cksumvalid == -1) {
929 if (vrs.cksum == 0)
930 cksumvalid = 1;
931 else {
932 if (bootverbose)
933 kprintf(
934 "pci%d:%d:%d:%d: bad VPD cksum, remain %hhu\n",
935 cfg->domain, cfg->bus,
936 cfg->slot, cfg->func,
937 vrs.cksum);
938 cksumvalid = 0;
939 state = -1;
940 break;
941 }
942 }
943 dflen--;
944 remain--;
945 /* keep in sync w/ state 2's transistions */
946 if (dflen == 0)
947 cfg->vpd.vpd_ros[off++].value[i++] = '\0';
948 if (dflen == 0 && remain == 0) {
949 cfg->vpd.vpd_rocnt = off;
950 cfg->vpd.vpd_ros = krealloc(cfg->vpd.vpd_ros,
951 off * sizeof(*cfg->vpd.vpd_ros),
952 M_DEVBUF, M_WAITOK | M_ZERO);
953 state = 0;
954 } else if (dflen == 0)
955 state = 2;
956 break;
957
958 case 4:
959 remain--;
960 if (remain == 0)
961 state = 0;
962 break;
963
964 case 5: /* VPD-W Keyword Header */
965 if (off == alloc) {
966 cfg->vpd.vpd_w = krealloc(cfg->vpd.vpd_w,
967 (alloc *= 2) * sizeof(*cfg->vpd.vpd_w),
968 M_DEVBUF, M_WAITOK | M_ZERO);
969 }
970 cfg->vpd.vpd_w[off].keyword[0] = byte;
971 if (vpd_nextbyte(&vrs, &byte2)) {
972 state = -2;
973 break;
974 }
975 cfg->vpd.vpd_w[off].keyword[1] = byte2;
976 if (vpd_nextbyte(&vrs, &byte2)) {
977 state = -2;
978 break;
979 }
980 cfg->vpd.vpd_w[off].len = dflen = byte2;
981 cfg->vpd.vpd_w[off].start = vrs.off - vrs.bytesinval;
982 cfg->vpd.vpd_w[off].value = kmalloc((dflen + 1) *
983 sizeof(*cfg->vpd.vpd_w[off].value),
984 M_DEVBUF, M_WAITOK);
985 remain -= 3;
986 i = 0;
987 /* keep in sync w/ state 6's transistions */
988 if (dflen == 0 && remain == 0)
989 state = 0;
990 else if (dflen == 0)
991 state = 5;
992 else
993 state = 6;
994 break;
995
996 case 6: /* VPD-W Keyword Value */
997 cfg->vpd.vpd_w[off].value[i++] = byte;
998 dflen--;
999 remain--;
1000 /* keep in sync w/ state 5's transistions */
1001 if (dflen == 0)
1002 cfg->vpd.vpd_w[off++].value[i++] = '\0';
1003 if (dflen == 0 && remain == 0) {
1004 cfg->vpd.vpd_wcnt = off;
1005 cfg->vpd.vpd_w = krealloc(cfg->vpd.vpd_w,
1006 off * sizeof(*cfg->vpd.vpd_w),
1007 M_DEVBUF, M_WAITOK | M_ZERO);
1008 state = 0;
1009 } else if (dflen == 0)
1010 state = 5;
1011 break;
1012
1013 default:
1014 kprintf("pci%d:%d:%d:%d: invalid state: %d\n",
1015 cfg->domain, cfg->bus, cfg->slot, cfg->func,
1016 state);
1017 state = -1;
1018 break;
1019 }
1020 }
1021
1022 if (cksumvalid == 0 || state < -1) {
1023 /* read-only data bad, clean up */
1024 if (cfg->vpd.vpd_ros != NULL) {
1025 for (off = 0; cfg->vpd.vpd_ros[off].value; off++)
1026 kfree(cfg->vpd.vpd_ros[off].value, M_DEVBUF);
1027 kfree(cfg->vpd.vpd_ros, M_DEVBUF);
1028 cfg->vpd.vpd_ros = NULL;
1029 }
1030 }
1031 if (state < -1) {
1032 /* I/O error, clean up */
1033 kprintf("pci%d:%d:%d:%d: failed to read VPD data.\n",
1034 cfg->domain, cfg->bus, cfg->slot, cfg->func);
1035 if (cfg->vpd.vpd_ident != NULL) {
1036 kfree(cfg->vpd.vpd_ident, M_DEVBUF);
1037 cfg->vpd.vpd_ident = NULL;
1038 }
1039 if (cfg->vpd.vpd_w != NULL) {
1040 for (off = 0; cfg->vpd.vpd_w[off].value; off++)
1041 kfree(cfg->vpd.vpd_w[off].value, M_DEVBUF);
1042 kfree(cfg->vpd.vpd_w, M_DEVBUF);
1043 cfg->vpd.vpd_w = NULL;
1044 }
1045 }
1046 cfg->vpd.vpd_cached = 1;
1047 #undef REG
1048 #undef WREG
1049 }
1050
1051 int
1052 pci_get_vpd_ident_method(device_t dev, device_t child, const char **identptr)
1053 {
1054 struct pci_devinfo *dinfo = device_get_ivars(child);
1055 pcicfgregs *cfg = &dinfo->cfg;
1056
1057 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1058 pci_read_vpd(device_get_parent(dev), cfg);
1059
1060 *identptr = cfg->vpd.vpd_ident;
1061
1062 if (*identptr == NULL)
1063 return (ENXIO);
1064
1065 return (0);
1066 }
1067
1068 int
1069 pci_get_vpd_readonly_method(device_t dev, device_t child, const char *kw,
1070 const char **vptr)
1071 {
1072 struct pci_devinfo *dinfo = device_get_ivars(child);
1073 pcicfgregs *cfg = &dinfo->cfg;
1074 int i;
1075
1076 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1077 pci_read_vpd(device_get_parent(dev), cfg);
1078
1079 for (i = 0; i < cfg->vpd.vpd_rocnt; i++)
1080 if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword,
1081 sizeof(cfg->vpd.vpd_ros[i].keyword)) == 0) {
1082 *vptr = cfg->vpd.vpd_ros[i].value;
1083 }
1084
1085 if (i != cfg->vpd.vpd_rocnt)
1086 return (0);
1087
1088 *vptr = NULL;
1089 return (ENXIO);
1090 }
1091
1092 /*
1093 * Return the offset in configuration space of the requested extended
1094 * capability entry or 0 if the specified capability was not found.
1095 */
1096 int
1097 pci_find_extcap_method(device_t dev, device_t child, int capability,
1098 int *capreg)
1099 {
1100 struct pci_devinfo *dinfo = device_get_ivars(child);
1101 pcicfgregs *cfg = &dinfo->cfg;
1102 u_int32_t status;
1103 u_int8_t ptr;
1104
1105 /*
1106 * Check the CAP_LIST bit of the PCI status register first.
1107 */
1108 status = pci_read_config(child, PCIR_STATUS, 2);
1109 if (!(status & PCIM_STATUS_CAPPRESENT))
1110 return (ENXIO);
1111
1112 /*
1113 * Determine the start pointer of the capabilities list.
1114 */
1115 switch (cfg->hdrtype & PCIM_HDRTYPE) {
1116 case 0:
1117 case 1:
1118 ptr = PCIR_CAP_PTR;
1119 break;
1120 case 2:
1121 ptr = PCIR_CAP_PTR_2;
1122 break;
1123 default:
1124 /* XXX: panic? */
1125 return (ENXIO); /* no extended capabilities support */
1126 }
1127 ptr = pci_read_config(child, ptr, 1);
1128
1129 /*
1130 * Traverse the capabilities list.
1131 */
1132 while (ptr != 0) {
1133 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) {
1134 if (capreg != NULL)
1135 *capreg = ptr;
1136 return (0);
1137 }
1138 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1);
1139 }
1140
1141 return (ENOENT);
1142 }
1143
1144 /*
1145 * Support for MSI-X message interrupts.
1146 */
1147 void
1148 pci_enable_msix(device_t dev, u_int index, uint64_t address, uint32_t data)
1149 {
1150 struct pci_devinfo *dinfo = device_get_ivars(dev);
1151 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1152 uint32_t offset;
1153
1154 KASSERT(msix->msix_table_len > index, ("bogus index"));
1155 offset = msix->msix_table_offset + index * 16;
1156 bus_write_4(msix->msix_table_res, offset, address & 0xffffffff);
1157 bus_write_4(msix->msix_table_res, offset + 4, address >> 32);
1158 bus_write_4(msix->msix_table_res, offset + 8, data);
1159
1160 /* Enable MSI -> HT mapping. */
1161 pci_ht_map_msi(dev, address);
1162 }
1163
1164 void
1165 pci_mask_msix(device_t dev, u_int index)
1166 {
1167 struct pci_devinfo *dinfo = device_get_ivars(dev);
1168 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1169 uint32_t offset, val;
1170
1171 KASSERT(msix->msix_msgnum > index, ("bogus index"));
1172 offset = msix->msix_table_offset + index * 16 + 12;
1173 val = bus_read_4(msix->msix_table_res, offset);
1174 if (!(val & PCIM_MSIX_VCTRL_MASK)) {
1175 val |= PCIM_MSIX_VCTRL_MASK;
1176 bus_write_4(msix->msix_table_res, offset, val);
1177 }
1178 }
1179
1180 void
1181 pci_unmask_msix(device_t dev, u_int index)
1182 {
1183 struct pci_devinfo *dinfo = device_get_ivars(dev);
1184 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1185 uint32_t offset, val;
1186
1187 KASSERT(msix->msix_table_len > index, ("bogus index"));
1188 offset = msix->msix_table_offset + index * 16 + 12;
1189 val = bus_read_4(msix->msix_table_res, offset);
1190 if (val & PCIM_MSIX_VCTRL_MASK) {
1191 val &= ~PCIM_MSIX_VCTRL_MASK;
1192 bus_write_4(msix->msix_table_res, offset, val);
1193 }
1194 }
1195
1196 int
1197 pci_pending_msix(device_t dev, u_int index)
1198 {
1199 struct pci_devinfo *dinfo = device_get_ivars(dev);
1200 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1201 uint32_t offset, bit;
1202
1203 KASSERT(msix->msix_table_len > index, ("bogus index"));
1204 offset = msix->msix_pba_offset + (index / 32) * 4;
1205 bit = 1 << index % 32;
1206 return (bus_read_4(msix->msix_pba_res, offset) & bit);
1207 }
1208
1209 /*
1210 * Restore MSI-X registers and table during resume. If MSI-X is
1211 * enabled then walk the virtual table to restore the actual MSI-X
1212 * table.
1213 */
1214 static void
1215 pci_resume_msix(device_t dev)
1216 {
1217 struct pci_devinfo *dinfo = device_get_ivars(dev);
1218 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1219 struct msix_table_entry *mte;
1220 struct msix_vector *mv;
1221 int i;
1222
1223 if (msix->msix_alloc > 0) {
1224 /* First, mask all vectors. */
1225 for (i = 0; i < msix->msix_msgnum; i++)
1226 pci_mask_msix(dev, i);
1227
1228 /* Second, program any messages with at least one handler. */
1229 for (i = 0; i < msix->msix_table_len; i++) {
1230 mte = &msix->msix_table[i];
1231 if (mte->mte_vector == 0 || mte->mte_handlers == 0)
1232 continue;
1233 mv = &msix->msix_vectors[mte->mte_vector - 1];
1234 pci_enable_msix(dev, i, mv->mv_address, mv->mv_data);
1235 pci_unmask_msix(dev, i);
1236 }
1237 }
1238 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL,
1239 msix->msix_ctrl, 2);
1240 }
1241
1242 /*
1243 * Attempt to allocate *count MSI-X messages. The actual number allocated is
1244 * returned in *count. After this function returns, each message will be
1245 * available to the driver as SYS_RES_IRQ resources starting at rid 1.
1246 */
1247 int
1248 pci_alloc_msix_method(device_t dev, device_t child, int *count)
1249 {
1250 struct pci_devinfo *dinfo = device_get_ivars(child);
1251 pcicfgregs *cfg = &dinfo->cfg;
1252 struct resource_list_entry *rle;
1253 int actual, error, i, irq, max;
1254
1255 /* Don't let count == 0 get us into trouble. */
1256 if (*count == 0)
1257 return (EINVAL);
1258
1259 /* If rid 0 is allocated, then fail. */
1260 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
1261 if (rle != NULL && rle->res != NULL)
1262 return (ENXIO);
1263
1264 /* Already have allocated messages? */
1265 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0)
1266 return (ENXIO);
1267
1268 /* If MSI is blacklisted for this system, fail. */
1269 if (pci_msi_blacklisted())
1270 return (ENXIO);
1271
1272 /* MSI-X capability present? */
1273 if (cfg->msix.msix_location == 0 || !pci_do_msix)
1274 return (ENODEV);
1275
1276 /* Make sure the appropriate BARs are mapped. */
1277 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
1278 cfg->msix.msix_table_bar);
1279 if (rle == NULL || rle->res == NULL ||
1280 !(rman_get_flags(rle->res) & RF_ACTIVE))
1281 return (ENXIO);
1282 cfg->msix.msix_table_res = rle->res;
1283 if (cfg->msix.msix_pba_bar != cfg->msix.msix_table_bar) {
1284 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
1285 cfg->msix.msix_pba_bar);
1286 if (rle == NULL || rle->res == NULL ||
1287 !(rman_get_flags(rle->res) & RF_ACTIVE))
1288 return (ENXIO);
1289 }
1290 cfg->msix.msix_pba_res = rle->res;
1291
1292 if (bootverbose)
1293 device_printf(child,
1294 "attempting to allocate %d MSI-X vectors (%d supported)\n",
1295 *count, cfg->msix.msix_msgnum);
1296 max = min(*count, cfg->msix.msix_msgnum);
1297 for (i = 0; i < max; i++) {
1298 /* Allocate a message. */
1299 error = PCIB_ALLOC_MSIX(device_get_parent(dev), child, &irq);
1300 if (error)
1301 break;
1302 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq,
1303 irq, 1);
1304 }
1305 actual = i;
1306
1307 if (bootverbose) {
1308 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 1);
1309 if (actual == 1)
1310 device_printf(child, "using IRQ %lu for MSI-X\n",
1311 rle->start);
1312 else {
1313 int run;
1314
1315 /*
1316 * Be fancy and try to print contiguous runs of
1317 * IRQ values as ranges. 'irq' is the previous IRQ.
1318 * 'run' is true if we are in a range.
1319 */
1320 device_printf(child, "using IRQs %lu", rle->start);
1321 irq = rle->start;
1322 run = 0;
1323 for (i = 1; i < actual; i++) {
1324 rle = resource_list_find(&dinfo->resources,
1325 SYS_RES_IRQ, i + 1);
1326
1327 /* Still in a run? */
1328 if (rle->start == irq + 1) {
1329 run = 1;
1330 irq++;
1331 continue;
1332 }
1333
1334 /* Finish previous range. */
1335 if (run) {
1336 kprintf("-%d", irq);
1337 run = 0;
1338 }
1339
1340 /* Start new range. */
1341 kprintf(",%lu", rle->start);
1342 irq = rle->start;
1343 }
1344
1345 /* Unfinished range? */
1346 if (run)
1347 kprintf("-%d", irq);
1348 kprintf(" for MSI-X\n");
1349 }
1350 }
1351
1352 /* Mask all vectors. */
1353 for (i = 0; i < cfg->msix.msix_msgnum; i++)
1354 pci_mask_msix(child, i);
1355
1356 /* Allocate and initialize vector data and virtual table. */
1357 cfg->msix.msix_vectors = kmalloc(sizeof(struct msix_vector) * actual,
1358 M_DEVBUF, M_WAITOK | M_ZERO);
1359 cfg->msix.msix_table = kmalloc(sizeof(struct msix_table_entry) * actual,
1360 M_DEVBUF, M_WAITOK | M_ZERO);
1361 for (i = 0; i < actual; i++) {
1362 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1363 cfg->msix.msix_vectors[i].mv_irq = rle->start;
1364 cfg->msix.msix_table[i].mte_vector = i + 1;
1365 }
1366
1367 /* Update control register to enable MSI-X. */
1368 cfg->msix.msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE;
1369 pci_write_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL,
1370 cfg->msix.msix_ctrl, 2);
1371
1372 /* Update counts of alloc'd messages. */
1373 cfg->msix.msix_alloc = actual;
1374 cfg->msix.msix_table_len = actual;
1375 *count = actual;
1376 return (0);
1377 }
1378
1379 /*
1380 * By default, pci_alloc_msix() will assign the allocated IRQ
1381 * resources consecutively to the first N messages in the MSI-X table.
1382 * However, device drivers may want to use different layouts if they
1383 * either receive fewer messages than they asked for, or they wish to
1384 * populate the MSI-X table sparsely. This method allows the driver
1385 * to specify what layout it wants. It must be called after a
1386 * successful pci_alloc_msix() but before any of the associated
1387 * SYS_RES_IRQ resources are allocated via bus_alloc_resource().
1388 *
1389 * The 'vectors' array contains 'count' message vectors. The array
1390 * maps directly to the MSI-X table in that index 0 in the array
1391 * specifies the vector for the first message in the MSI-X table, etc.
1392 * The vector value in each array index can either be 0 to indicate
1393 * that no vector should be assigned to a message slot, or it can be a
1394 * number from 1 to N (where N is the count returned from a
1395 * succcessful call to pci_alloc_msix()) to indicate which message
1396 * vector (IRQ) to be used for the corresponding message.
1397 *
1398 * On successful return, each message with a non-zero vector will have
1399 * an associated SYS_RES_IRQ whose rid is equal to the array index +
1400 * 1. Additionally, if any of the IRQs allocated via the previous
1401 * call to pci_alloc_msix() are not used in the mapping, those IRQs
1402 * will be kfreed back to the system automatically.
1403 *
1404 * For example, suppose a driver has a MSI-X table with 6 messages and
1405 * asks for 6 messages, but pci_alloc_msix() only returns a count of
1406 * 3. Call the three vectors allocated by pci_alloc_msix() A, B, and
1407 * C. After the call to pci_alloc_msix(), the device will be setup to
1408 * have an MSI-X table of ABC--- (where - means no vector assigned).
1409 * If the driver ten passes a vector array of { 1, 0, 1, 2, 0, 2 },
1410 * then the MSI-X table will look like A-AB-B, and the 'C' vector will
1411 * be kfreed back to the system. This device will also have valid
1412 * SYS_RES_IRQ rids of 1, 3, 4, and 6.
1413 *
1414 * In any case, the SYS_RES_IRQ rid X will always map to the message
1415 * at MSI-X table index X - 1 and will only be valid if a vector is
1416 * assigned to that table entry.
1417 */
1418 int
1419 pci_remap_msix_method(device_t dev, device_t child, int count,
1420 const u_int *vectors)
1421 {
1422 struct pci_devinfo *dinfo = device_get_ivars(child);
1423 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1424 struct resource_list_entry *rle;
1425 int i, irq, j, *used;
1426
1427 /*
1428 * Have to have at least one message in the table but the
1429 * table can't be bigger than the actual MSI-X table in the
1430 * device.
1431 */
1432 if (count == 0 || count > msix->msix_msgnum)
1433 return (EINVAL);
1434
1435 /* Sanity check the vectors. */
1436 for (i = 0; i < count; i++)
1437 if (vectors[i] > msix->msix_alloc)
1438 return (EINVAL);
1439
1440 /*
1441 * Make sure there aren't any holes in the vectors to be used.
1442 * It's a big pain to support it, and it doesn't really make
1443 * sense anyway. Also, at least one vector must be used.
1444 */
1445 used = kmalloc(sizeof(int) * msix->msix_alloc, M_DEVBUF, M_WAITOK |
1446 M_ZERO);
1447 for (i = 0; i < count; i++)
1448 if (vectors[i] != 0)
1449 used[vectors[i] - 1] = 1;
1450 for (i = 0; i < msix->msix_alloc - 1; i++)
1451 if (used[i] == 0 && used[i + 1] == 1) {
1452 kfree(used, M_DEVBUF);
1453 return (EINVAL);
1454 }
1455 if (used[0] != 1) {
1456 kfree(used, M_DEVBUF);
1457 return (EINVAL);
1458 }
1459
1460 /* Make sure none of the resources are allocated. */
1461 for (i = 0; i < msix->msix_table_len; i++) {
1462 if (msix->msix_table[i].mte_vector == 0)
1463 continue;
1464 if (msix->msix_table[i].mte_handlers > 0)
1465 return (EBUSY);
1466 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1467 KASSERT(rle != NULL, ("missing resource"));
1468 if (rle->res != NULL)
1469 return (EBUSY);
1470 }
1471
1472 /* Free the existing resource list entries. */
1473 for (i = 0; i < msix->msix_table_len; i++) {
1474 if (msix->msix_table[i].mte_vector == 0)
1475 continue;
1476 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
1477 }
1478
1479 /*
1480 * Build the new virtual table keeping track of which vectors are
1481 * used.
1482 */
1483 kfree(msix->msix_table, M_DEVBUF);
1484 msix->msix_table = kmalloc(sizeof(struct msix_table_entry) * count,
1485 M_DEVBUF, M_WAITOK | M_ZERO);
1486 for (i = 0; i < count; i++)
1487 msix->msix_table[i].mte_vector = vectors[i];
1488 msix->msix_table_len = count;
1489
1490 /* Free any unused IRQs and resize the vectors array if necessary. */
1491 j = msix->msix_alloc - 1;
1492 if (used[j] == 0) {
1493 struct msix_vector *vec;
1494
1495 while (used[j] == 0) {
1496 PCIB_RELEASE_MSIX(device_get_parent(dev), child,
1497 msix->msix_vectors[j].mv_irq);
1498 j--;
1499 }
1500 vec = kmalloc(sizeof(struct msix_vector) * (j + 1), M_DEVBUF,
1501 M_WAITOK);
1502 bcopy(msix->msix_vectors, vec, sizeof(struct msix_vector) *
1503 (j + 1));
1504 kfree(msix->msix_vectors, M_DEVBUF);
1505 msix->msix_vectors = vec;
1506 msix->msix_alloc = j + 1;
1507 }
1508 kfree(used, M_DEVBUF);
1509
1510 /* Map the IRQs onto the rids. */
1511 for (i = 0; i < count; i++) {
1512 if (vectors[i] == 0)
1513 continue;
1514 irq = msix->msix_vectors[vectors[i]].mv_irq;
1515 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq,
1516 irq, 1);
1517 }
1518
1519 if (bootverbose) {
1520 device_printf(child, "Remapped MSI-X IRQs as: ");
1521 for (i = 0; i < count; i++) {
1522 if (i != 0)
1523 kprintf(", ");
1524 if (vectors[i] == 0)
1525 kprintf("---");
1526 else
1527 kprintf("%d",
1528 msix->msix_vectors[vectors[i]].mv_irq);
1529 }
1530 kprintf("\n");
1531 }
1532
1533 return (0);
1534 }
1535
1536 static int
1537 pci_release_msix(device_t dev, device_t child)
1538 {
1539 struct pci_devinfo *dinfo = device_get_ivars(child);
1540 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1541 struct resource_list_entry *rle;
1542 int i;
1543
1544 /* Do we have any messages to release? */
1545 if (msix->msix_alloc == 0)
1546 return (ENODEV);
1547
1548 /* Make sure none of the resources are allocated. */
1549 for (i = 0; i < msix->msix_table_len; i++) {
1550 if (msix->msix_table[i].mte_vector == 0)
1551 continue;
1552 if (msix->msix_table[i].mte_handlers > 0)
1553 return (EBUSY);
1554 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1555 KASSERT(rle != NULL, ("missing resource"));
1556 if (rle->res != NULL)
1557 return (EBUSY);
1558 }
1559
1560 /* Update control register to disable MSI-X. */
1561 msix->msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE;
1562 pci_write_config(child, msix->msix_location + PCIR_MSIX_CTRL,
1563 msix->msix_ctrl, 2);
1564
1565 /* Free the resource list entries. */
1566 for (i = 0; i < msix->msix_table_len; i++) {
1567 if (msix->msix_table[i].mte_vector == 0)
1568 continue;
1569 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
1570 }
1571 kfree(msix->msix_table, M_DEVBUF);
1572 msix->msix_table_len = 0;
1573
1574 /* Release the IRQs. */
1575 for (i = 0; i < msix->msix_alloc; i++)
1576 PCIB_RELEASE_MSIX(device_get_parent(dev), child,
1577 msix->msix_vectors[i].mv_irq);
1578 kfree(msix->msix_vectors, M_DEVBUF);
1579 msix->msix_alloc = 0;
1580 return (0);
1581 }
1582
1583 /*
1584 * Return the max supported MSI-X messages this device supports.
1585 * Basically, assuming the MD code can alloc messages, this function
1586 * should return the maximum value that pci_alloc_msix() can return.
1587 * Thus, it is subject to the tunables, etc.
1588 */
1589 int
1590 pci_msix_count_method(device_t dev, device_t child)
1591 {
1592 struct pci_devinfo *dinfo = device_get_ivars(child);
1593 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1594
1595 if (pci_do_msix && msix->msix_location != 0)
1596 return (msix->msix_msgnum);
1597 return (0);
1598 }
1599
1600 /*
1601 * HyperTransport MSI mapping control
1602 */
1603 void
1604 pci_ht_map_msi(device_t dev, uint64_t addr)
1605 {
1606 struct pci_devinfo *dinfo = device_get_ivars(dev);
1607 struct pcicfg_ht *ht = &dinfo->cfg.ht;
1608
1609 if (!ht->ht_msimap)
1610 return;
1611
1612 if (addr && !(ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) &&
1613 ht->ht_msiaddr >> 20 == addr >> 20) {
1614 /* Enable MSI -> HT mapping. */
1615 ht->ht_msictrl |= PCIM_HTCMD_MSI_ENABLE;
1616 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
1617 ht->ht_msictrl, 2);
1618 }
1619
1620 if (!addr && ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) {
1621 /* Disable MSI -> HT mapping. */
1622 ht->ht_msictrl &= ~PCIM_HTCMD_MSI_ENABLE;
1623 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
1624 ht->ht_msictrl, 2);
1625 }
1626 }
1627
1628 /*
1629 * Support for MSI message signalled interrupts.
1630 */
1631 void
1632 pci_enable_msi(device_t dev, uint64_t address, uint16_t data)
1633 {
1634 struct pci_devinfo *dinfo = device_get_ivars(dev);
1635 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1636
1637 /* Write data and address values. */
1638 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR,
1639 address & 0xffffffff, 4);
1640 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
1641 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR_HIGH,
1642 address >> 32, 4);
1643 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA_64BIT,
1644 data, 2);
1645 } else
1646 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA, data,
1647 2);
1648
1649 /* Enable MSI in the control register. */
1650 msi->msi_ctrl |= PCIM_MSICTRL_MSI_ENABLE;
1651 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1652 2);
1653
1654 /* Enable MSI -> HT mapping. */
1655 pci_ht_map_msi(dev, address);
1656 }
1657
1658 void
1659 pci_disable_msi(device_t dev)
1660 {
1661 struct pci_devinfo *dinfo = device_get_ivars(dev);
1662 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1663
1664 /* Disable MSI -> HT mapping. */
1665 pci_ht_map_msi(dev, 0);
1666
1667 /* Disable MSI in the control register. */
1668 msi->msi_ctrl &= ~PCIM_MSICTRL_MSI_ENABLE;
1669 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1670 2);
1671 }
1672
1673 /*
1674 * Restore MSI registers during resume. If MSI is enabled then
1675 * restore the data and address registers in addition to the control
1676 * register.
1677 */
1678 static void
1679 pci_resume_msi(device_t dev)
1680 {
1681 struct pci_devinfo *dinfo = device_get_ivars(dev);
1682 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1683 uint64_t address;
1684 uint16_t data;
1685
1686 if (msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE) {
1687 address = msi->msi_addr;
1688 data = msi->msi_data;
1689 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR,
1690 address & 0xffffffff, 4);
1691 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
1692 pci_write_config(dev, msi->msi_location +
1693 PCIR_MSI_ADDR_HIGH, address >> 32, 4);
1694 pci_write_config(dev, msi->msi_location +
1695 PCIR_MSI_DATA_64BIT, data, 2);
1696 } else
1697 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA,
1698 data, 2);
1699 }
1700 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1701 2);
1702 }
1703
1704 int
1705 pci_remap_msi_irq(device_t dev, u_int irq)
1706 {
1707 struct pci_devinfo *dinfo = device_get_ivars(dev);
1708 pcicfgregs *cfg = &dinfo->cfg;
1709 struct resource_list_entry *rle;
1710 struct msix_table_entry *mte;
1711 struct msix_vector *mv;
1712 device_t bus;
1713 uint64_t addr;
1714 uint32_t data;
1715 int error, i, j;
1716
1717 bus = device_get_parent(dev);
1718
1719 /*
1720 * Handle MSI first. We try to find this IRQ among our list
1721 * of MSI IRQs. If we find it, we request updated address and
1722 * data registers and apply the results.
1723 */
1724 if (cfg->msi.msi_alloc > 0) {
1725
1726 /* If we don't have any active handlers, nothing to do. */
1727 if (cfg->msi.msi_handlers == 0)
1728 return (0);
1729 for (i = 0; i < cfg->msi.msi_alloc; i++) {
1730 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ,
1731 i + 1);
1732 if (rle->start == irq) {
1733 error = PCIB_MAP_MSI(device_get_parent(bus),
1734 dev, irq, &addr, &data);
1735 if (error)
1736 return (error);
1737 pci_disable_msi(dev);
1738 dinfo->cfg.msi.msi_addr = addr;
1739 dinfo->cfg.msi.msi_data = data;
1740 pci_enable_msi(dev, addr, data);
1741 return (0);
1742 }
1743 }
1744 return (ENOENT);
1745 }
1746
1747 /*
1748 * For MSI-X, we check to see if we have this IRQ. If we do,
1749 * we request the updated mapping info. If that works, we go
1750 * through all the slots that use this IRQ and update them.
1751 */
1752 if (cfg->msix.msix_alloc > 0) {
1753 for (i = 0; i < cfg->msix.msix_alloc; i++) {
1754 mv = &cfg->msix.msix_vectors[i];
1755 if (mv->mv_irq == irq) {
1756 error = PCIB_MAP_MSI(device_get_parent(bus),
1757 dev, irq, &addr, &data);
1758 if (error)
1759 return (error);
1760 mv->mv_address = addr;
1761 mv->mv_data = data;
1762 for (j = 0; j < cfg->msix.msix_table_len; j++) {
1763 mte = &cfg->msix.msix_table[j];
1764 if (mte->mte_vector != i + 1)
1765 continue;
1766 if (mte->mte_handlers == 0)
1767 continue;
1768 pci_mask_msix(dev, j);
1769 pci_enable_msix(dev, j, addr, data);
1770 pci_unmask_msix(dev, j);
1771 }
1772 }
1773 }
1774 return (ENOENT);
1775 }
1776
1777 return (ENOENT);
1778 }
1779
1780 /*
1781 * Returns true if the specified device is blacklisted because MSI
1782 * doesn't work.
1783 */
1784 int
1785 pci_msi_device_blacklisted(device_t dev)
1786 {
1787 struct pci_quirk *q;
1788
1789 if (!pci_honor_msi_blacklist)
1790 return (0);
1791
1792 for (q = &pci_quirks[0]; q->devid; q++) {
1793 if (q->devid == pci_get_devid(dev) &&
1794 q->type == PCI_QUIRK_DISABLE_MSI)
1795 return (1);
1796 }
1797 return (0);
1798 }
1799
1800 /*
1801 * Determine if MSI is blacklisted globally on this sytem. Currently,
1802 * we just check for blacklisted chipsets as represented by the
1803 * host-PCI bridge at device 0:0:0. In the future, it may become
1804 * necessary to check other system attributes, such as the kenv values
1805 * that give the motherboard manufacturer and model number.
1806 */
1807 static int
1808 pci_msi_blacklisted(void)
1809 {
1810 device_t dev;
1811
1812 if (!pci_honor_msi_blacklist)
1813 return (0);
1814
1815 /* Blacklist all non-PCI-express and non-PCI-X chipsets. */
1816 if (!(pcie_chipset || pcix_chipset))
1817 return (1);
1818
1819 dev = pci_find_bsf(0, 0, 0);
1820 if (dev != NULL)
1821 return (pci_msi_device_blacklisted(dev));
1822 return (0);
1823 }
1824
1825 /*
1826 * Attempt to allocate *count MSI messages. The actual number allocated is
1827 * returned in *count. After this function returns, each message will be
1828 * available to the driver as SYS_RES_IRQ resources starting at a rid 1.
1829 */
1830 int
1831 pci_alloc_msi_method(device_t dev, device_t child, int *count)
1832 {
1833 struct pci_devinfo *dinfo = device_get_ivars(child);
1834 pcicfgregs *cfg = &dinfo->cfg;
1835 struct resource_list_entry *rle;
1836 int actual, error, i, irqs[32];
1837 uint16_t ctrl;
1838
1839 /* Don't let count == 0 get us into trouble. */
1840 if (*count == 0)
1841 return (EINVAL);
1842
1843 /* If rid 0 is allocated, then fail. */
1844 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
1845 if (rle != NULL && rle->res != NULL)
1846 return (ENXIO);
1847
1848 /* Already have allocated messages? */
1849 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0)
1850 return (ENXIO);
1851
1852 /* If MSI is blacklisted for this system, fail. */
1853 if (pci_msi_blacklisted())
1854 return (ENXIO);
1855
1856 /* MSI capability present? */
1857 if (cfg->msi.msi_location == 0 || !pci_do_msi)
1858 return (ENODEV);
1859
1860 if (bootverbose)
1861 device_printf(child,
1862 "attempting to allocate %d MSI vectors (%d supported)\n",
1863 *count, cfg->msi.msi_msgnum);
1864
1865 /* Don't ask for more than the device supports. */
1866 actual = min(*count, cfg->msi.msi_msgnum);
1867
1868 /* Don't ask for more than 32 messages. */
1869 actual = min(actual, 32);
1870
1871 /* MSI requires power of 2 number of messages. */
1872 if (!powerof2(actual))
1873 return (EINVAL);
1874
1875 for (;;) {
1876 /* Try to allocate N messages. */
1877 error = PCIB_ALLOC_MSI(device_get_parent(dev), child, actual,
1878 cfg->msi.msi_msgnum, irqs);
1879 if (error == 0)
1880 break;
1881 if (actual == 1)
1882 return (error);
1883
1884 /* Try N / 2. */
1885 actual >>= 1;
1886 }
1887
1888 /*
1889 * We now have N actual messages mapped onto SYS_RES_IRQ
1890 * resources in the irqs[] array, so add new resources
1891 * starting at rid 1.
1892 */
1893 for (i = 0; i < actual; i++)
1894 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1,
1895 irqs[i], irqs[i], 1);
1896
1897 if (bootverbose) {
1898 if (actual == 1)
1899 device_printf(child, "using IRQ %d for MSI\n", irqs[0]);
1900 else {
1901 int run;
1902
1903 /*
1904 * Be fancy and try to print contiguous runs
1905 * of IRQ values as ranges. 'run' is true if
1906 * we are in a range.
1907 */
1908 device_printf(child, "using IRQs %d", irqs[0]);
1909 run = 0;
1910 for (i = 1; i < actual; i++) {
1911
1912 /* Still in a run? */
1913 if (irqs[i] == irqs[i - 1] + 1) {
1914 run = 1;
1915 continue;
1916 }
1917
1918 /* Finish previous range. */
1919 if (run) {
1920 kprintf("-%d", irqs[i - 1]);
1921 run = 0;
1922 }
1923
1924 /* Start new range. */
1925 kprintf(",%d", irqs[i]);
1926 }
1927
1928 /* Unfinished range? */
1929 if (run)
1930 kprintf("-%d", irqs[actual - 1]);
1931 kprintf(" for MSI\n");
1932 }
1933 }
1934
1935 /* Update control register with actual count. */
1936 ctrl = cfg->msi.msi_ctrl;
1937 ctrl &= ~PCIM_MSICTRL_MME_MASK;
1938 ctrl |= (ffs(actual) - 1) << 4;
1939 cfg->msi.msi_ctrl = ctrl;
1940 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, ctrl, 2);
1941
1942 /* Update counts of alloc'd messages. */
1943 cfg->msi.msi_alloc = actual;
1944 cfg->msi.msi_handlers = 0;
1945 *count = actual;
1946 return (0);
1947 }
1948
1949 /* Release the MSI messages associated with this device. */
1950 int
1951 pci_release_msi_method(device_t dev, device_t child)
1952 {
1953 struct pci_devinfo *dinfo = device_get_ivars(child);
1954 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1955 struct resource_list_entry *rle;
1956 int error, i, irqs[32];
1957
1958 /* Try MSI-X first. */
1959 error = pci_release_msix(dev, child);
1960 if (error != ENODEV)
1961 return (error);
1962
1963 /* Do we have any messages to release? */
1964 if (msi->msi_alloc == 0)
1965 return (ENODEV);
1966 KASSERT(msi->msi_alloc <= 32, ("more than 32 alloc'd messages"));
1967
1968 /* Make sure none of the resources are allocated. */
1969 if (msi->msi_handlers > 0)
1970 return (EBUSY);
1971 for (i = 0; i < msi->msi_alloc; i++) {
1972 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1973 KASSERT(rle != NULL, ("missing MSI resource"));
1974 if (rle->res != NULL)
1975 return (EBUSY);
1976 irqs[i] = rle->start;
1977 }
1978
1979 /* Update control register with 0 count. */
1980 KASSERT(!(msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE),
1981 ("%s: MSI still enabled", __func__));
1982 msi->msi_ctrl &= ~PCIM_MSICTRL_MME_MASK;
1983 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL,
1984 msi->msi_ctrl, 2);
1985
1986 /* Release the messages. */
1987 PCIB_RELEASE_MSI(device_get_parent(dev), child, msi->msi_alloc, irqs);
1988 for (i = 0; i < msi->msi_alloc; i++)
1989 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
1990
1991 /* Update alloc count. */
1992 msi->msi_alloc = 0;
1993 msi->msi_addr = 0;
1994 msi->msi_data = 0;
1995 return (0);
1996 }
1997
1998 /*
1999 * Return the max supported MSI messages this device supports.
2000 * Basically, assuming the MD code can alloc messages, this function
2001 * should return the maximum value that pci_alloc_msi() can return.
2002 * Thus, it is subject to the tunables, etc.
2003 */
2004 int
2005 pci_msi_count_method(device_t dev, device_t child)
2006 {
2007 struct pci_devinfo *dinfo = device_get_ivars(child);
2008 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2009
2010 if (pci_do_msi && msi->msi_location != 0)
2011 return (msi->msi_msgnum);
2012 return (0);
2013 }
2014
2015 /* kfree pcicfgregs structure and all depending data structures */
2016
2017 int
2018 pci_freecfg(struct pci_devinfo *dinfo)
2019 {
2020 struct devlist *devlist_head;
2021 int i;
2022
2023 devlist_head = &pci_devq;
2024
2025 if (dinfo->cfg.vpd.vpd_reg) {
2026 kfree(dinfo->cfg.vpd.vpd_ident, M_DEVBUF);
2027 for (i = 0; i < dinfo->cfg.vpd.vpd_rocnt; i++)
2028 kfree(dinfo->cfg.vpd.vpd_ros[i].value, M_DEVBUF);
2029 kfree(dinfo->cfg.vpd.vpd_ros, M_DEVBUF);
2030 for (i = 0; i < dinfo->cfg.vpd.vpd_wcnt; i++)
2031 kfree(dinfo->cfg.vpd.vpd_w[i].value, M_DEVBUF);
2032 kfree(dinfo->cfg.vpd.vpd_w, M_DEVBUF);
2033 }
2034 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links);
2035 kfree(dinfo, M_DEVBUF);
2036
2037 /* increment the generation count */
2038 pci_generation++;
2039
2040 /* we're losing one device */
2041 pci_numdevs--;
2042 return (0);
2043 }
2044
2045 /*
2046 * PCI power manangement
2047 */
2048 int
2049 pci_set_powerstate_method(device_t dev, device_t child, int state)
2050 {
2051 struct pci_devinfo *dinfo = device_get_ivars(child);
2052 pcicfgregs *cfg = &dinfo->cfg;
2053 uint16_t status;
2054 int result, oldstate, highest, delay;
2055
2056 if (cfg->pp.pp_cap == 0)
2057 return (EOPNOTSUPP);
2058
2059 /*
2060 * Optimize a no state change request away. While it would be OK to
2061 * write to the hardware in theory, some devices have shown odd
2062 * behavior when going from D3 -> D3.
2063 */
2064 oldstate = pci_get_powerstate(child);
2065 if (oldstate == state)
2066 return (0);
2067
2068 /*
2069 * The PCI power management specification states that after a state
2070 * transition between PCI power states, system software must
2071 * guarantee a minimal delay before the function accesses the device.
2072 * Compute the worst case delay that we need to guarantee before we
2073 * access the device. Many devices will be responsive much more
2074 * quickly than this delay, but there are some that don't respond
2075 * instantly to state changes. Transitions to/from D3 state require
2076 * 10ms, while D2 requires 200us, and D0/1 require none. The delay
2077 * is done below with DELAY rather than a sleeper function because
2078 * this function can be called from contexts where we cannot sleep.
2079 */
2080 highest = (oldstate > state) ? oldstate : state;
2081 if (highest == PCI_POWERSTATE_D3)
2082 delay = 10000;
2083 else if (highest == PCI_POWERSTATE_D2)
2084 delay = 200;
2085 else
2086 delay = 0;
2087 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2)
2088 & ~PCIM_PSTAT_DMASK;
2089 result = 0;
2090 switch (state) {
2091 case PCI_POWERSTATE_D0:
2092 status |= PCIM_PSTAT_D0;
2093 break;
2094 case PCI_POWERSTATE_D1:
2095 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0)
2096 return (EOPNOTSUPP);
2097 status |= PCIM_PSTAT_D1;
2098 break;
2099 case PCI_POWERSTATE_D2:
2100 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0)
2101 return (EOPNOTSUPP);
2102 status |= PCIM_PSTAT_D2;
2103 break;
2104 case PCI_POWERSTATE_D3:
2105 status |= PCIM_PSTAT_D3;
2106 break;
2107 default:
2108 return (EINVAL);
2109 }
2110
2111 if (bootverbose)
2112 kprintf(
2113 "pci%d:%d:%d:%d: Transition from D%d to D%d\n",
2114 dinfo->cfg.domain, dinfo->cfg.bus, dinfo->cfg.slot,
2115 dinfo->cfg.func, oldstate, state);
2116
2117 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2);
2118 if (delay)
2119 DELAY(delay);
2120 return (0);
2121 }
2122
2123 int
2124 pci_get_powerstate_method(device_t dev, device_t child)
2125 {
2126 struct pci_devinfo *dinfo = device_get_ivars(child);
2127 pcicfgregs *cfg = &dinfo->cfg;
2128 uint16_t status;
2129 int result;
2130
2131 if (cfg->pp.pp_cap != 0) {
2132 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2);
2133 switch (status & PCIM_PSTAT_DMASK) {
2134 case PCIM_PSTAT_D0:
2135 result = PCI_POWERSTATE_D0;
2136 break;
2137 case PCIM_PSTAT_D1:
2138 result = PCI_POWERSTATE_D1;
2139 break;
2140 case PCIM_PSTAT_D2:
2141 result = PCI_POWERSTATE_D2;
2142 break;
2143 case PCIM_PSTAT_D3:
2144 result = PCI_POWERSTATE_D3;
2145 break;
2146 default:
2147 result = PCI_POWERSTATE_UNKNOWN;
2148 break;
2149 }
2150 } else {
2151 /* No support, device is always at D0 */
2152 result = PCI_POWERSTATE_D0;
2153 }
2154 return (result);
2155 }
2156
2157 /*
2158 * Some convenience functions for PCI device drivers.
2159 */
2160
2161 static __inline void
2162 pci_set_command_bit(device_t dev, device_t child, uint16_t bit)
2163 {
2164 uint16_t command;
2165
2166 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2167 command |= bit;
2168 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
2169 }
2170
2171 static __inline void
2172 pci_clear_command_bit(device_t dev, device_t child, uint16_t bit)
2173 {
2174 uint16_t command;
2175
2176 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2177 command &= ~bit;
2178 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
2179 }
2180
2181 int
2182 pci_enable_busmaster_method(device_t dev, device_t child)
2183 {
2184 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
2185 return (0);
2186 }
2187
2188 int
2189 pci_disable_busmaster_method(device_t dev, device_t child)
2190 {
2191 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
2192 return (0);
2193 }
2194
2195 int
2196 pci_enable_io_method(device_t dev, device_t child, int space)
2197 {
2198 uint16_t command;
2199 uint16_t bit;
2200 char *error;
2201
2202 bit = 0;
2203 error = NULL;
2204
2205 switch(space) {
2206 case SYS_RES_IOPORT:
2207 bit = PCIM_CMD_PORTEN;
2208 error = "port";
2209 break;
2210 case SYS_RES_MEMORY:
2211 bit = PCIM_CMD_MEMEN;
2212 error = "memory";
2213 break;
2214 default:
2215 return (EINVAL);
2216 }
2217 pci_set_command_bit(dev, child, bit);
2218 /* Some devices seem to need a brief stall here, what do to? */
2219 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2220 if (command & bit)
2221 return (0);
2222 device_printf(child, "failed to enable %s mapping!\n", error);
2223 return (ENXIO);
2224 }
2225
2226 int
2227 pci_disable_io_method(device_t dev, device_t child, int space)
2228 {
2229 uint16_t command;
2230 uint16_t bit;
2231 char *error;
2232
2233 bit = 0;
2234 error = NULL;
2235
2236 switch(space) {
2237 case SYS_RES_IOPORT:
2238 bit = PCIM_CMD_PORTEN;
2239 error = "port";
2240 break;
2241 case SYS_RES_MEMORY:
2242 bit = PCIM_CMD_MEMEN;
2243 error = "memory";
2244 break;
2245 default:
2246 return (EINVAL);
2247 }
2248 pci_clear_command_bit(dev, child, bit);
2249 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2250 if (command & bit) {
2251 device_printf(child, "failed to disable %s mapping!\n", error);
2252 return (ENXIO);
2253 }
2254 return (0);
2255 }
2256
2257 /*
2258 * New style pci driver. Parent device is either a pci-host-bridge or a
2259 * pci-pci-bridge. Both kinds are represented by instances of pcib.
2260 */
2261
2262 void
2263 pci_print_verbose(struct pci_devinfo *dinfo)
2264 {
2265
2266 if (bootverbose) {
2267 pcicfgregs *cfg = &dinfo->cfg;
2268
2269 kprintf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
2270 cfg->vendor, cfg->device, cfg->revid);
2271 kprintf("\tdomain=%d, bus=%d, slot=%d, func=%d\n",
2272 cfg->domain, cfg->bus, cfg->slot, cfg->func);
2273 kprintf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
2274 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype,
2275 cfg->mfdev);
2276 kprintf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n",
2277 cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
2278 kprintf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n",
2279 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt,
2280 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
2281 if (cfg->intpin > 0)
2282 kprintf("\tintpin=%c, irq=%d\n",
2283 cfg->intpin +'a' -1, cfg->intline);
2284 if (cfg->pp.pp_cap) {
2285 uint16_t status;
2286
2287 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2);
2288 kprintf("\tpowerspec %d supports D0%s%s D3 current D%d\n",
2289 cfg->pp.pp_cap & PCIM_PCAP_SPEC,
2290 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "",
2291 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "",
2292 status & PCIM_PSTAT_DMASK);
2293 }
2294 if (cfg->msi.msi_location) {
2295 int ctrl;
2296
2297 ctrl = cfg->msi.msi_ctrl;
2298 kprintf("\tMSI supports %d message%s%s%s\n",
2299 cfg->msi.msi_msgnum,
2300 (cfg->msi.msi_msgnum == 1) ? "" : "s",
2301 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "",
2302 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":"");
2303 }
2304 if (cfg->msix.msix_location) {
2305 kprintf("\tMSI-X supports %d message%s ",
2306 cfg->msix.msix_msgnum,
2307 (cfg->msix.msix_msgnum == 1) ? "" : "s");
2308 if (cfg->msix.msix_table_bar == cfg->msix.msix_pba_bar)
2309 kprintf("in map 0x%x\n",
2310 cfg->msix.msix_table_bar);
2311 else
2312 kprintf("in maps 0x%x and 0x%x\n",
2313 cfg->msix.msix_table_bar,
2314 cfg->msix.msix_pba_bar);
2315 }
2316 }
2317 }
2318
2319 static int
2320 pci_porten(device_t pcib, int b, int s, int f)
2321 {
2322 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
2323 & PCIM_CMD_PORTEN) != 0;
2324 }
2325
2326 static int
2327 pci_memen(device_t pcib, int b, int s, int f)
2328 {
2329 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
2330 & PCIM_CMD_MEMEN) != 0;
2331 }
2332
2333 /*
2334 * Add a resource based on a pci map register. Return 1 if the map
2335 * register is a 32bit map register or 2 if it is a 64bit register.
2336 */
2337 static int
2338 pci_add_map(device_t pcib, device_t bus, device_t dev,
2339 int b, int s, int f, int reg, struct resource_list *rl, int force,
2340 int prefetch)
2341 {
2342 uint32_t map;
2343 pci_addr_t base;
2344 pci_addr_t start, end, count;
2345 uint8_t ln2size;
2346 uint8_t ln2range;
2347 uint32_t testval;
2348 uint16_t cmd;
2349 int type;
2350 int barlen;
2351 struct resource *res;
2352
2353 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
2354 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4);
2355 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
2356 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4);
2357
2358 if (PCI_BAR_MEM(map)) {
2359 type = SYS_RES_MEMORY;
2360 if (map & PCIM_BAR_MEM_PREFETCH)
2361 prefetch = 1;
2362 } else
2363 type = SYS_RES_IOPORT;
2364 ln2size = pci_mapsize(testval);
2365 ln2range = pci_maprange(testval);
2366 base = pci_mapbase(map);
2367 barlen = ln2range == 64 ? 2 : 1;
2368
2369 /*
2370 * For I/O registers, if bottom bit is set, and the next bit up
2371 * isn't clear, we know we have a BAR that doesn't conform to the
2372 * spec, so ignore it. Also, sanity check the size of the data
2373 * areas to the type of memory involved. Memory must be at least
2374 * 16 bytes in size, while I/O ranges must be at least 4.
2375 */
2376 if (PCI_BAR_IO(testval) && (testval & PCIM_BAR_IO_RESERVED) != 0)
2377 return (barlen);
2378 if ((type == SYS_RES_MEMORY && ln2size < 4) ||
2379 (type == SYS_RES_IOPORT && ln2size < 2))
2380 return (barlen);
2381
2382 if (ln2range == 64)
2383 /* Read the other half of a 64bit map register */
2384 base |= (uint64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32;
2385 if (bootverbose) {
2386 kprintf("\tmap[%02x]: type %s, range %2d, base %#jx, size %2d",
2387 reg, pci_maptype(map), ln2range, (uintmax_t)base, ln2size);
2388 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
2389 kprintf(", port disabled\n");
2390 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
2391 kprintf(", memory disabled\n");
2392 else
2393 kprintf(", enabled\n");
2394 }
2395
2396 /*
2397 * If base is 0, then we have problems. It is best to ignore
2398 * such entries for the moment. These will be allocated later if
2399 * the driver specifically requests them. However, some
2400 * removable busses look better when all resources are allocated,
2401 * so allow '0' to be overriden.
2402 *
2403 * Similarly treat maps whose values is the same as the test value
2404 * read back. These maps have had all f's written to them by the
2405 * BIOS in an attempt to disable the resources.
2406 */
2407 if (!force && (base == 0 || map == testval))
2408 return (barlen);
2409 if ((u_long)base != base) {
2410 device_printf(bus,
2411 "pci%d:%d:%d:%d bar %#x too many address bits",
2412 pci_get_domain(dev), b, s, f, reg);
2413 return (barlen);
2414 }
2415
2416 /*
2417 * This code theoretically does the right thing, but has
2418 * undesirable side effects in some cases where peripherals
2419 * respond oddly to having these bits enabled. Let the user
2420 * be able to turn them off (since pci_enable_io_modes is 1 by
2421 * default).
2422 */
2423 if (pci_enable_io_modes) {
2424 /* Turn on resources that have been left off by a lazy BIOS */
2425 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) {
2426 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
2427 cmd |= PCIM_CMD_PORTEN;
2428 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
2429 }
2430 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) {
2431 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
2432 cmd |= PCIM_CMD_MEMEN;
2433 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
2434 }
2435 } else {
2436 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
2437 return (barlen);
2438 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
2439 return (barlen);
2440 }
2441
2442 count = 1 << ln2size;
2443 if (base == 0 || base == pci_mapbase(testval)) {
2444 start = 0; /* Let the parent decide. */
2445 end = ~0ULL;
2446 } else {
2447 start = base;
2448 end = base + (1 << ln2size) - 1;
2449 }
2450 resource_list_add(rl, type, reg, start, end, count);
2451
2452 /*
2453 * Try to allocate the resource for this BAR from our parent
2454 * so that this resource range is already reserved. The
2455 * driver for this device will later inherit this resource in
2456 * pci_alloc_resource().
2457 */
2458 res = resource_list_alloc(rl, bus, dev, type, &reg, start, end, count,
2459 prefetch ? RF_PREFETCHABLE : 0);
2460 if (res == NULL) {
2461 /*
2462 * If the allocation fails, clear the BAR and delete
2463 * the resource list entry to force
2464 * pci_alloc_resource() to allocate resources from the
2465 * parent.
2466 */
2467 resource_list_delete(rl, type, reg);
2468 start = 0;
2469 } else
2470 start = rman_get_start(res);
2471 pci_write_config(dev, reg, start, 4);
2472 if (ln2range == 64)
2473 pci_write_config(dev, reg + 4, start >> 32, 4);
2474 return (barlen);
2475 }
2476
2477 /*
2478 * For ATA devices we need to decide early what addressing mode to use.
2479 * Legacy demands that the primary and secondary ATA ports sits on the
2480 * same addresses that old ISA hardware did. This dictates that we use
2481 * those addresses and ignore the BAR's if we cannot set PCI native
2482 * addressing mode.
2483 */
2484 static void
2485 pci_ata_maps(device_t pcib, device_t bus, device_t dev, int b,
2486 int s, int f, struct resource_list *rl, int force, uint32_t prefetchmask)
2487 {
2488 int rid, type, progif;
2489 #if 0
2490 /* if this device supports PCI native addressing use it */
2491 progif = pci_read_config(dev, PCIR_PROGIF, 1);
2492 if ((progif & 0x8a) == 0x8a) {
2493 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) &&
2494 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) {
2495 kprintf("Trying ATA native PCI addressing mode\n");
2496 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1);
2497 }
2498 }
2499 #endif
2500 progif = pci_read_config(dev, PCIR_PROGIF, 1);
2501 type = SYS_RES_IOPORT;
2502 if (progif & PCIP_STORAGE_IDE_MODEPRIM) {
2503 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(0), rl, force,
2504 prefetchmask & (1 << 0));
2505 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(1), rl, force,
2506 prefetchmask & (1 << 1));
2507 } else {
2508 rid = PCIR_BAR(0);
2509 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8);
2510 resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7, 8,
2511 0);
2512 rid = PCIR_BAR(1);
2513 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1);
2514 resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6, 1,
2515 0);
2516 }
2517 if (progif & PCIP_STORAGE_IDE_MODESEC) {
2518 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(2), rl, force,
2519 prefetchmask & (1 << 2));
2520 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(3), rl, force,
2521 prefetchmask & (1 << 3));
2522 } else {
2523 rid = PCIR_BAR(2);
2524 resource_list_add(rl, type, rid, 0x170, 0x177, 8);
2525 resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177, 8,
2526 0);
2527 rid = PCIR_BAR(3);
2528 resource_list_add(rl, type, rid, 0x376, 0x376, 1);
2529 resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376, 1,
2530 0);
2531 }
2532 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(4), rl, force,
2533 prefetchmask & (1 << 4));
2534 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(5), rl, force,
2535 prefetchmask & (1 << 5));
2536 }
2537
2538 static void
2539 pci_assign_interrupt(device_t bus, device_t dev, int force_route)
2540 {
2541 struct pci_devinfo *dinfo = device_get_ivars(dev);
2542 pcicfgregs *cfg = &dinfo->cfg;
2543 char tunable_name[64];
2544 int irq;
2545
2546 /* Has to have an intpin to have an interrupt. */
2547 if (cfg->intpin == 0)
2548 return;
2549
2550 /* Let the user override the IRQ with a tunable. */
2551 irq = PCI_INVALID_IRQ;
2552 ksnprintf(tunable_name, sizeof(tunable_name),
2553 "hw.pci%d.%d.%d.INT%c.irq",
2554 cfg->domain, cfg->bus, cfg->slot, cfg->intpin + 'A' - 1);
2555 if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0))
2556 irq = PCI_INVALID_IRQ;
2557
2558 /*
2559 * If we didn't get an IRQ via the tunable, then we either use the
2560 * IRQ value in the intline register or we ask the bus to route an
2561 * interrupt for us. If force_route is true, then we only use the
2562 * value in the intline register if the bus was unable to assign an
2563 * IRQ.
2564 */
2565 if (!PCI_INTERRUPT_VALID(irq)) {
2566 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route)
2567 irq = PCI_ASSIGN_INTERRUPT(bus, dev);
2568 if (!PCI_INTERRUPT_VALID(irq))
2569 irq = cfg->intline;
2570 }
2571
2572 /* If after all that we don't have an IRQ, just bail. */
2573 if (!PCI_INTERRUPT_VALID(irq))
2574 return;
2575
2576 /* Update the config register if it changed. */
2577 if (irq != cfg->intline) {
2578 cfg->intline = irq;
2579 pci_write_config(dev, PCIR_INTLINE, irq, 1);
2580 }
2581
2582 /* Add this IRQ as rid 0 interrupt resource. */
2583 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1);
2584 }
2585
2586 void
2587 pci_add_resources(device_t pcib, device_t bus, device_t dev, int force, uint32_t prefetchmask)
2588 {
2589 struct pci_devinfo *dinfo = device_get_ivars(dev);
2590 pcicfgregs *cfg = &dinfo->cfg;
2591 struct resource_list *rl = &dinfo->resources;
2592 struct pci_quirk *q;
2593 int b, i, f, s;
2594
2595 b = cfg->bus;
2596 s = cfg->slot;
2597 f = cfg->func;
2598
2599 /* ATA devices needs special map treatment */
2600 if ((pci_get_class(dev) == PCIC_STORAGE) &&
2601 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) &&
2602 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) ||
2603 (!pci_read_config(dev, PCIR_BAR(0), 4) &&
2604 !pci_read_config(dev, PCIR_BAR(2), 4))) )
2605 pci_ata_maps(pcib, bus, dev, b, s, f, rl, force, prefetchmask);
2606 else
2607 for (i = 0; i < cfg->nummaps;)
2608 i += pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(i),
2609 rl, force, prefetchmask & (1 << i));
2610
2611 /*
2612 * Add additional, quirked resources.
2613 */
2614 for (q = &pci_quirks[0]; q->devid; q++) {
2615 if (q->devid == ((cfg->device << 16) | cfg->vendor)
2616 && q->type == PCI_QUIRK_MAP_REG)
2617 pci_add_map(pcib, bus, dev, b, s, f, q->arg1, rl,
2618 force, 0);
2619 }
2620
2621 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {
2622 #ifdef __PCI_REROUTE_INTERRUPT
2623 /*
2624 * Try to re-route interrupts. Sometimes the BIOS or
2625 * firmware may leave bogus values in these registers.
2626 * If the re-route fails, then just stick with what we
2627 * have.
2628 */
2629 pci_assign_interrupt(bus, dev, 1);
2630 #else
2631 pci_assign_interrupt(bus, dev, 0);
2632 #endif
2633 }
2634 }
2635
2636 void
2637 pci_add_children(device_t dev, int domain, int busno, size_t dinfo_size)
2638 {
2639 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w)
2640 device_t pcib = device_get_parent(dev);
2641 struct pci_devinfo *dinfo;
2642 int maxslots;
2643 int s, f, pcifunchigh;
2644 uint8_t hdrtype;
2645
2646 KASSERT(dinfo_size >= sizeof(struct pci_devinfo),
2647 ("dinfo_size too small"));
2648 maxslots = PCIB_MAXSLOTS(pcib);
2649 for (s = 0; s <= maxslots; s++) {
2650 pcifunchigh = 0;
2651 f = 0;
2652 DELAY(1);
2653 hdrtype = REG(PCIR_HDRTYPE, 1);
2654 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
2655 continue;
2656 if (hdrtype & PCIM_MFDEV)
2657 pcifunchigh = PCI_FUNCMAX;
2658 for (f = 0; f <= pcifunchigh; f++) {
2659 dinfo = pci_read_device(pcib, domain, busno, s, f,
2660 dinfo_size);
2661 if (dinfo != NULL) {
2662 pci_add_child(dev, dinfo);
2663 }
2664 }
2665 }
2666 #undef REG
2667 }
2668
2669 void
2670 pci_add_child(device_t bus, struct pci_devinfo *dinfo)
2671 {
2672 device_t pcib;
2673
2674 pcib = device_get_parent(bus);
2675 dinfo->cfg.dev = device_add_child(bus, NULL, -1);
2676 device_set_ivars(dinfo->cfg.dev, dinfo);
2677 resource_list_init(&dinfo->resources);
2678 pci_cfg_save(dinfo->cfg.dev, dinfo, 0);
2679 pci_cfg_restore(dinfo->cfg.dev, dinfo);
2680 pci_print_verbose(dinfo);
2681 pci_add_resources(pcib, bus, dinfo->cfg.dev, 0, 0);
2682 }
2683
2684 static int
2685 pci_probe(device_t dev)
2686 {
2687 device_set_desc(dev, "PCI bus");
2688
2689 /* Allow other subclasses to override this driver. */
2690 return (-1000);
2691 }
2692
2693 static int
2694 pci_attach(device_t dev)
2695 {
2696 int busno, domain;
2697
2698 /*
2699 * Since there can be multiple independantly numbered PCI
2700 * busses on systems with multiple PCI domains, we can't use
2701 * the unit number to decide which bus we are probing. We ask
2702 * the parent pcib what our domain and bus numbers are.
2703 */
2704 domain = pcib_get_domain(dev);
2705 busno = pcib_get_bus(dev);
2706 if (bootverbose)
2707 device_printf(dev, "domain=%d, physical bus=%d\n",
2708 domain, busno);
2709
2710 pci_add_children(dev, domain, busno, sizeof(struct pci_devinfo));
2711
2712 return (bus_generic_attach(dev));
2713 }
2714
2715 int
2716 pci_suspend(device_t dev)
2717 {
2718 int dstate, error, i, numdevs;
2719 device_t acpi_dev, child, *devlist;
2720 struct pci_devinfo *dinfo;
2721
2722 /*
2723 * Save the PCI configuration space for each child and set the
2724 * device in the appropriate power state for this sleep state.
2725 */
2726 acpi_dev = NULL;
2727 if (pci_do_power_resume)
2728 acpi_dev = devclass_get_device(devclass_find("acpi"), 0);
2729 device_get_children(dev, &devlist, &numdevs);
2730 for (i = 0; i < numdevs; i++) {
2731 child = devlist[i];
2732 dinfo = (struct pci_devinfo *) device_get_ivars(child);
2733 pci_cfg_save(child, dinfo, 0);
2734 }
2735
2736 /* Suspend devices before potentially powering them down. */
2737 error = bus_generic_suspend(dev);
2738 if (error) {
2739 kfree(devlist, M_TEMP);
2740 return (error);
2741 }
2742
2743 /*
2744 * Always set the device to D3. If ACPI suggests a different
2745 * power state, use it instead. If ACPI is not present, the
2746 * firmware is responsible for managing device power. Skip
2747 * children who aren't attached since they are powered down
2748 * separately. Only manage type 0 devices for now.
2749 */
2750 for (i = 0; acpi_dev && i < numdevs; i++) {
2751 child = devlist[i];
2752 dinfo = (struct pci_devinfo *) device_get_ivars(child);
2753 if (device_is_attached(child) && dinfo->cfg.hdrtype == 0) {
2754 dstate = PCI_POWERSTATE_D3;
2755 ACPI_PWR_FOR_SLEEP(acpi_dev, child, &dstate);
2756 pci_set_powerstate(child, dstate);
2757 }
2758 }
2759 kfree(devlist, M_TEMP);
2760 return (0);
2761 }
2762
2763 int
2764 pci_resume(device_t dev)
2765 {
2766 int i, numdevs;
2767 device_t acpi_dev, child, *devlist;
2768 struct pci_devinfo *dinfo;
2769
2770 /*
2771 * Set each child to D0 and restore its PCI configuration space.
2772 */
2773 acpi_dev = NULL;
2774 if (pci_do_power_resume)
2775 acpi_dev = devclass_get_device(devclass_find("acpi"), 0);
2776 device_get_children(dev, &devlist, &numdevs);
2777 for (i = 0; i < numdevs; i++) {
2778 /*
2779 * Notify ACPI we're going to D0 but ignore the result. If
2780 * ACPI is not present, the firmware is responsible for
2781 * managing device power. Only manage type 0 devices for now.
2782 */
2783 child = devlist[i];
2784 dinfo = (struct pci_devinfo *) device_get_ivars(child);
2785 if (acpi_dev && device_is_attached(child) &&
2786 dinfo->cfg.hdrtype == 0) {
2787 ACPI_PWR_FOR_SLEEP(acpi_dev, child, NULL);
2788 pci_set_powerstate(child, PCI_POWERSTATE_D0);
2789 }
2790
2791 /* Now the device is powered up, restore its config space. */
2792 pci_cfg_restore(child, dinfo);
2793 }
2794 kfree(devlist, M_TEMP);
2795 return (bus_generic_resume(dev));
2796 }
2797
2798 static void
2799 pci_load_vendor_data(void)
2800 {
2801 caddr_t vendordata, info;
2802
2803 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) {
2804 info = preload_search_info(vendordata, MODINFO_ADDR);
2805 pci_vendordata = *(char **)info;
2806 info = preload_search_info(vendordata, MODINFO_SIZE);
2807 pci_vendordata_size = *(size_t *)info;
2808 /* terminate the database */
2809 pci_vendordata[pci_vendordata_size] = '\n';
2810 }
2811 }
2812
2813 void
2814 pci_driver_added(device_t dev, driver_t *driver)
2815 {
2816 int numdevs;
2817 device_t *devlist;
2818 device_t child;
2819 struct pci_devinfo *dinfo;
2820 int i;
2821
2822 if (bootverbose)
2823 device_printf(dev, "driver added\n");
2824 DEVICE_IDENTIFY(driver, dev);
2825 device_get_children(dev, &devlist, &numdevs);
2826 for (i = 0; i < numdevs; i++) {
2827 child = devlist[i];
2828 if (device_get_state(child) != DS_NOTPRESENT)
2829 continue;
2830 dinfo = device_get_ivars(child);
2831 pci_print_verbose(dinfo);
2832 if (bootverbose)
2833 kprintf("pci%d:%d:%d:%d: reprobing on driver added\n",
2834 dinfo->cfg.domain, dinfo->cfg.bus, dinfo->cfg.slot,
2835 dinfo->cfg.func);
2836 pci_cfg_restore(child, dinfo);
2837 if (device_probe_and_attach(child) != 0)
2838 pci_cfg_save(child, dinfo, 1);
2839 }
2840 kfree(devlist, M_TEMP);
2841 }
2842
2843 static void
2844 pci_child_detached(device_t parent __unused, device_t child)
2845 {
2846 /* Turn child's power off */
2847 pci_cfg_save(child, device_get_ivars(child), 1);
2848 }
2849
2850 int
2851 pci_setup_intr(device_t dev, device_t child, struct resource *irq, int flags,
2852 driver_intr_t *intr, void *arg, void **cookiep, lwkt_serialize_t serializer)
2853 {
2854 #ifdef MSI
2855 struct pci_devinfo *dinfo;
2856 struct msix_table_entry *mte;
2857 struct msix_vector *mv;
2858 uint64_t addr;
2859 uint32_t data;
2860 #endif
2861 int error, rid;
2862 void *cookie;
2863 error = bus_generic_setup_intr(dev, child, irq, flags, intr,
2864 arg, &cookie, serializer);
2865 if (error)
2866 return (error);
2867
2868 /* If this is not a direct child, just bail out. */
2869 if (device_get_parent(child) != dev) {
2870 *cookiep = cookie;
2871 return(0);
2872 }
2873
2874 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS);
2875 #ifdef MSI
2876 rid = rman_get_rid(irq);
2877 if (rid == 0) {
2878 /* Make sure that INTx is enabled */
2879 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS);
2880 } else {
2881 /*
2882 * Check to see if the interrupt is MSI or MSI-X.
2883 * Ask our parent to map the MSI and give
2884 * us the address and data register values.
2885 * If we fail for some reason, teardown the
2886 * interrupt handler.
2887 */
2888 dinfo = device_get_ivars(child);
2889 if (dinfo->cfg.msi.msi_alloc > 0) {
2890 if (dinfo->cfg.msi.msi_addr == 0) {
2891 KASSERT(dinfo->cfg.msi.msi_handlers == 0,
2892 ("MSI has handlers, but vectors not mapped"));
2893 error = PCIB_MAP_MSI(device_get_parent(dev),
2894 child, rman_get_start(irq), &addr, &data);
2895 if (error)
2896 goto bad;
2897 dinfo->cfg.msi.msi_addr = addr;
2898 dinfo->cfg.msi.msi_data = data;
2899 pci_enable_msi(child, addr, data);
2900 }
2901 dinfo->cfg.msi.msi_handlers++;
2902 } else {
2903 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
2904 ("No MSI or MSI-X interrupts allocated"));
2905 KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
2906 ("MSI-X index too high"));
2907 mte = &dinfo->cfg.msix.msix_table[rid - 1];
2908 KASSERT(mte->mte_vector != 0, ("no message vector"));
2909 mv = &dinfo->cfg.msix.msix_vectors[mte->mte_vector - 1];
2910 KASSERT(mv->mv_irq == rman_get_start(irq),
2911 ("IRQ mismatch"));
2912 if (mv->mv_address == 0) {
2913 KASSERT(mte->mte_handlers == 0,
2914 ("MSI-X table entry has handlers, but vector not mapped"));
2915 error = PCIB_MAP_MSI(device_get_parent(dev),
2916 child, rman_get_start(irq), &addr, &data);
2917 if (error)
2918 goto bad;
2919 mv->mv_address = addr;
2920 mv->mv_data = data;
2921 }
2922 if (mte->mte_handlers == 0) {
2923 pci_enable_msix(child, rid - 1, mv->mv_address,
2924 mv->mv_data);
2925 pci_unmask_msix(child, rid - 1);
2926 }
2927 mte->mte_handlers++;
2928 }
2929
2930 /* Make sure that INTx is disabled if we are using MSI/MSIX */
2931 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
2932 bad:
2933 if (error) {
2934 (void)bus_generic_teardown_intr(dev, child, irq,
2935 cookie);
2936 return (error);
2937 }
2938 }
2939 #endif
2940 *cookiep = cookie;
2941 return (0);
2942 }
2943
2944 int
2945 pci_teardown_intr(device_t dev, device_t child, struct resource *irq,
2946 void *cookie)
2947 {
2948 #ifdef MSI
2949 struct msix_table_entry *mte;
2950 struct resource_list_entry *rle;
2951 struct pci_devinfo *dinfo;
2952 #endif
2953 int error, rid;
2954
2955 if (irq == NULL || !(rman_get_flags(irq) & RF_ACTIVE))
2956 return (EINVAL);
2957
2958 /* If this isn't a direct child, just bail out */
2959 if (device_get_parent(child) != dev)
2960 return(bus_generic_teardown_intr(dev, child, irq, cookie));
2961
2962 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
2963 #ifdef MSI
2964 rid = rman_get_rid(irq);
2965 if (rid == 0) {
2966 /* Mask INTx */
2967 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
2968 } else {
2969 /*
2970 * Check to see if the interrupt is MSI or MSI-X. If so,
2971 * decrement the appropriate handlers count and mask the
2972 * MSI-X message, or disable MSI messages if the count
2973 * drops to 0.
2974 */
2975 dinfo = device_get_ivars(child);
2976 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, rid);
2977 if (rle->res != irq)
2978 return (EINVAL);
2979 if (dinfo->cfg.msi.msi_alloc > 0) {
2980 KASSERT(rid <= dinfo->cfg.msi.msi_alloc,
2981 ("MSI-X index too high"));
2982 if (dinfo->cfg.msi.msi_handlers == 0)
2983 return (EINVAL);
2984 dinfo->cfg.msi.msi_handlers--;
2985 if (dinfo->cfg.msi.msi_handlers == 0)
2986 pci_disable_msi(child);
2987 } else {
2988 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
2989 ("No MSI or MSI-X interrupts allocated"));
2990 KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
2991 ("MSI-X index too high"));
2992 mte = &dinfo->cfg.msix.msix_table[rid - 1];
2993 if (mte->mte_handlers == 0)
2994 return (EINVAL);
2995 mte->mte_handlers--;
2996 if (mte->mte_handlers == 0)
2997 pci_mask_msix(child, rid - 1);
2998 }
2999 }
3000 error = bus_generic_teardown_intr(dev, child, irq, cookie);
3001 if (rid > 0)
3002 KASSERT(error == 0,
3003 ("%s: generic teardown failed for MSI/MSI-X", __func__));
3004 #endif
3005 error = bus_generic_teardown_intr(dev, child, irq, cookie);
3006 return (error);
3007 }
3008
3009 int
3010 pci_print_child(device_t dev, device_t child)
3011 {
3012 struct pci_devinfo *dinfo;
3013 struct resource_list *rl;
3014 int retval = 0;
3015
3016 dinfo = device_get_ivars(child);
3017 rl = &dinfo->resources;
3018
3019 retval += bus_print_child_header(dev, child);
3020
3021 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx");
3022 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx");
3023 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld");
3024 if (device_get_flags(dev))
3025 retval += kprintf(" flags %#x", device_get_flags(dev));
3026
3027 retval += kprintf(" at device %d.%d", pci_get_slot(child),
3028 pci_get_function(child));
3029
3030 retval += bus_print_child_footer(dev, child);
3031
3032 return (retval);
3033 }
3034
3035 static struct
3036 {
3037 int class;
3038 int subclass;
3039 char *desc;
3040 } pci_nomatch_tab[] = {
3041 {PCIC_OLD, -1, "old"},
3042 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"},
3043 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"},
3044 {PCIC_STORAGE, -1, "mass storage"},
3045 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"},
3046 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"},
3047 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"},
3048 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"},
3049 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"},
3050 {PCIC_STORAGE, PCIS_STORAGE_ATA_ADMA, "ATA (ADMA)"},
3051 {PCIC_STORAGE, PCIS_STORAGE_SATA, "SATA"},
3052 {PCIC_STORAGE, PCIS_STORAGE_SAS, "SAS"},
3053 {PCIC_NETWORK, -1, "network"},
3054 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"},
3055 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"},
3056 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"},
3057 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"},
3058 {PCIC_NETWORK, PCIS_NETWORK_ISDN, "ISDN"},
3059 {PCIC_DISPLAY, -1, "display"},
3060 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"},
3061 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"},
3062 {PCIC_DISPLAY, PCIS_DISPLAY_3D, "3D"},
3063 {PCIC_MULTIMEDIA, -1, "multimedia"},
3064 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"},
3065 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"},
3066 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, "telephony"},
3067 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_HDA, "HDA"},
3068 {PCIC_MEMORY, -1, "memory"},
3069 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"},
3070 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"},
3071 {PCIC_BRIDGE, -1, "bridge"},
3072 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"},
3073 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"},
3074 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"},
3075 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"},
3076 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"},
3077 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"},
3078 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"},
3079 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"},
3080 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, "PCI-RACEway"},
3081 {PCIC_SIMPLECOMM, -1, "simple comms"},
3082 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */
3083 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"},
3084 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, "multiport serial"},
3085 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, "generic modem"},
3086 {PCIC_BASEPERIPH, -1, "base peripheral"},
3087 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"},
3088 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"},
3089 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"},
3090 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"},
3091 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, "PCI hot-plug controller"},
3092 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_SDHC, "SD host controller"},
3093 {PCIC_INPUTDEV, -1, "input device"},
3094 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"},
3095 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"},
3096 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"},
3097 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, "scanner"},
3098 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, "gameport"},
3099 {PCIC_DOCKING, -1, "docking station"},
3100 {PCIC_PROCESSOR, -1, "processor"},
3101 {PCIC_SERIALBUS, -1, "serial bus"},
3102 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"},
3103 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"},
3104 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"},
3105 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"},
3106 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"},
3107 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"},
3108 {PCIC_WIRELESS, -1, "wireless controller"},
3109 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, "iRDA"},
3110 {PCIC_WIRELESS, PCIS_WIRELESS_IR, "IR"},
3111 {PCIC_WIRELESS, PCIS_WIRELESS_RF, "RF"},
3112 {PCIC_INTELLIIO, -1, "intelligent I/O controller"},
3113 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, "I2O"},
3114 {PCIC_SATCOM, -1, "satellite communication"},
3115 {PCIC_SATCOM, PCIS_SATCOM_TV, "sat TV"},
3116 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, "sat audio"},
3117 {PCIC_SATCOM, PCIS_SATCOM_VOICE, "sat voice"},
3118 {PCIC_SATCOM, PCIS_SATCOM_DATA, "sat data"},
3119 {PCIC_CRYPTO, -1, "encrypt/decrypt"},
3120 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, "network/computer crypto"},
3121 {PCIC_CRYPTO, PCIS_CRYPTO_ENTERTAIN, "entertainment crypto"},
3122 {PCIC_DASP, -1, "dasp"},
3123 {PCIC_DASP, PCIS_DASP_DPIO, "DPIO module"},
3124 {0, 0, NULL}
3125 };
3126
3127 void
3128 pci_probe_nomatch(device_t dev, device_t child)
3129 {
3130 int i;
3131 char *cp, *scp, *device;
3132
3133 /*
3134 * Look for a listing for this device in a loaded device database.
3135 */
3136 if ((device = pci_describe_device(child)) != NULL) {
3137 device_printf(dev, "<%s>", device);
3138 kfree(device, M_DEVBUF);
3139 } else {
3140 /*
3141 * Scan the class/subclass descriptions for a general
3142 * description.
3143 */
3144 cp = "unknown";
3145 scp = NULL;
3146 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) {
3147 if (pci_nomatch_tab[i].class == pci_get_class(child)) {
3148 if (pci_nomatch_tab[i].subclass == -1) {
3149 cp = pci_nomatch_tab[i].desc;
3150 } else if (pci_nomatch_tab[i].subclass ==
3151 pci_get_subclass(child)) {
3152 scp = pci_nomatch_tab[i].desc;
3153 }
3154 }
3155 }
3156 device_printf(dev, "<%s%s%s>",
3157 cp ? cp : "",
3158 ((cp != NULL) && (scp != NULL)) ? ", " : "",
3159 scp ? scp : "");
3160 }
3161 kprintf(" at device %d.%d (no driver attached)\n",
3162 pci_get_slot(child), pci_get_function(child));
3163 pci_cfg_save(child, (struct pci_devinfo *)device_get_ivars(child), 1);
3164 return;
3165 }
3166
3167 /*
3168 * Parse the PCI device database, if loaded, and return a pointer to a
3169 * description of the device.
3170 *
3171 * The database is flat text formatted as follows:
3172 *
3173 * Any line not in a valid format is ignored.
3174 * Lines are terminated with newline '\n' characters.
3175 *
3176 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then
3177 * the vendor name.
3178 *
3179 * A DEVICE line is entered immediately below the corresponding VENDOR ID.
3180 * - devices cannot be listed without a corresponding VENDOR line.
3181 * A DEVICE line consists of a TAB, the 4 digit (hex) device code,
3182 * another TAB, then the device name.
3183 */
3184
3185 /*
3186 * Assuming (ptr) points to the beginning of a line in the database,
3187 * return the vendor or device and description of the next entry.
3188 * The value of (vendor) or (device) inappropriate for the entry type
3189 * is set to -1. Returns nonzero at the end of the database.
3190 *
3191 * Note that this is slightly unrobust in the face of corrupt data;
3192 * we attempt to safeguard against this by spamming the end of the
3193 * database with a newline when we initialise.
3194 */
3195 static int
3196 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc)
3197 {
3198 char *cp = *ptr;
3199 int left;
3200
3201 *device = -1;
3202 *vendor = -1;
3203 **desc = '\0';
3204 for (;;) {
3205 left = pci_vendordata_size - (cp - pci_vendordata);
3206 if (left <= 0) {
3207 *ptr = cp;
3208 return(1);
3209 }
3210
3211 /* vendor entry? */
3212 if (*cp != '\t' &&
3213 ksscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2)
3214 break;
3215 /* device entry? */
3216 if (*cp == '\t' &&
3217 ksscanf(cp, "%x\t%80[^\n]", device, *desc) == 2)
3218 break;
3219
3220 /* skip to next line */
3221 while (*cp != '\n' && left > 0) {
3222 cp++;
3223 left--;
3224 }
3225 if (*cp == '\n') {
3226 cp++;
3227 left--;
3228 }
3229 }
3230 /* skip to next line */
3231 while (*cp != '\n' && left > 0) {
3232 cp++;
3233 left--;
3234 }
3235 if (*cp == '\n' && left > 0)
3236 cp++;
3237 *ptr = cp;
3238 return(0);
3239 }
3240
3241 static char *
3242 pci_describe_device(device_t dev)
3243 {
3244 int vendor, device;
3245 char *desc, *vp, *dp, *line;
3246
3247 desc = vp = dp = NULL;
3248
3249 /*
3250 * If we have no vendor data, we can't do anything.
3251 */
3252 if (pci_vendordata == NULL)
3253 goto out;
3254
3255 /*
3256 * Scan the vendor data looking for this device
3257 */
3258 line = pci_vendordata;
3259 if ((vp = kmalloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
3260 goto out;
3261 for (;;) {
3262 if (pci_describe_parse_line(&line, &vendor, &device, &vp))
3263 goto out;
3264 if (vendor == pci_get_vendor(dev))
3265 break;
3266 }
3267 if ((dp = kmalloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
3268 goto out;
3269 for (;;) {
3270 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) {
3271 *dp = 0;
3272 break;
3273 }
3274 if (vendor != -1) {
3275 *dp = 0;
3276 break;
3277 }
3278 if (device == pci_get_device(dev))
3279 break;
3280 }
3281 if (dp[0] == '\0')
3282 ksnprintf(dp, 80, "0x%x", pci_get_device(dev));
3283 if ((desc = kmalloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) !=
3284 NULL)
3285 ksprintf(desc, "%s, %s", vp, dp);
3286 out:
3287 if (vp != NULL)
3288 kfree(vp, M_DEVBUF);
3289 if (dp != NULL)
3290 kfree(dp, M_DEVBUF);
3291 return(desc);
3292 }
3293
3294 int
3295 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
3296 {
3297 struct pci_devinfo *dinfo;
3298 pcicfgregs *cfg;
3299
3300 dinfo = device_get_ivars(child);
3301 cfg = &dinfo->cfg;
3302
3303 switch (which) {
3304 case PCI_IVAR_ETHADDR:
3305 /*
3306 * The generic accessor doesn't deal with failure, so
3307 * we set the return value, then return an error.
3308 */
3309 *((uint8_t **) result) = NULL;
3310 return (EINVAL);
3311 case PCI_IVAR_SUBVENDOR:
3312 *result = cfg->subvendor;
3313 break;
3314 case PCI_IVAR_SUBDEVICE:
3315 *result = cfg->subdevice;
3316 break;
3317 case PCI_IVAR_VENDOR:
3318 *result = cfg->vendor;
3319 break;
3320 case PCI_IVAR_DEVICE:
3321 *result = cfg->device;
3322 break;
3323 case PCI_IVAR_DEVID:
3324 *result = (cfg->device << 16) | cfg->vendor;
3325 break;
3326 case PCI_IVAR_CLASS:
3327 *result = cfg->baseclass;
3328 break;
3329 case PCI_IVAR_SUBCLASS:
3330 *result = cfg->subclass;
3331 break;
3332 case PCI_IVAR_PROGIF:
3333 *result = cfg->progif;
3334 break;
3335 case PCI_IVAR_REVID:
3336 *result = cfg->revid;
3337 break;
3338 case PCI_IVAR_INTPIN:
3339 *result = cfg->intpin;
3340 break;
3341 case PCI_IVAR_IRQ:
3342 *result = cfg->intline;
3343 break;
3344 case PCI_IVAR_DOMAIN:
3345 *result = cfg->domain;
3346 break;
3347 case PCI_IVAR_BUS:
3348 *result = cfg->bus;
3349 break;
3350 case PCI_IVAR_SLOT:
3351 *result = cfg->slot;
3352 break;
3353 case PCI_IVAR_FUNCTION:
3354 *result = cfg->func;
3355 break;
3356 case PCI_IVAR_CMDREG:
3357 *result = cfg->cmdreg;
3358 break;
3359 case PCI_IVAR_CACHELNSZ:
3360 *result = cfg->cachelnsz;
3361 break;
3362 case PCI_IVAR_MINGNT:
3363 *result = cfg->mingnt;
3364 break;
3365 case PCI_IVAR_MAXLAT:
3366 *result = cfg->maxlat;
3367 break;
3368 case PCI_IVAR_LATTIMER:
3369 *result = cfg->lattimer;
3370 break;
3371 default:
3372 return (ENOENT);
3373 }
3374 return (0);
3375 }
3376
3377 int
3378 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
3379 {
3380 struct pci_devinfo *dinfo;
3381
3382 dinfo = device_get_ivars(child);
3383
3384 switch (which) {
3385 case PCI_IVAR_INTPIN:
3386 dinfo->cfg.intpin = value;
3387 return (0);
3388 case PCI_IVAR_ETHADDR:
3389 case PCI_IVAR_SUBVENDOR:
3390 case PCI_IVAR_SUBDEVICE:
3391 case PCI_IVAR_VENDOR:
3392 case PCI_IVAR_DEVICE:
3393 case PCI_IVAR_DEVID:
3394 case PCI_IVAR_CLASS:
3395 case PCI_IVAR_SUBCLASS:
3396 case PCI_IVAR_PROGIF:
3397 case PCI_IVAR_REVID:
3398 case PCI_IVAR_IRQ:
3399 case PCI_IVAR_DOMAIN:
3400 case PCI_IVAR_BUS:
3401 case PCI_IVAR_SLOT:
3402 case PCI_IVAR_FUNCTION:
3403 return (EINVAL); /* disallow for now */
3404
3405 default:
3406 return (ENOENT);
3407 }
3408 }
3409 #ifdef notyet
3410 #include "opt_ddb.h"
3411 #ifdef DDB
3412 #include <ddb/ddb.h>
3413 #include <sys/cons.h>
3414
3415 /*
3416 * List resources based on pci map registers, used for within ddb
3417 */
3418
3419 DB_SHOW_COMMAND(pciregs, db_pci_dump)
3420 {
3421 struct pci_devinfo *dinfo;
3422 struct devlist *devlist_head;
3423 struct pci_conf *p;
3424 const char *name;
3425 int i, error, none_count;
3426
3427 none_count = 0;
3428 /* get the head of the device queue */
3429 devlist_head = &pci_devq;
3430
3431 /*
3432 * Go through the list of devices and print out devices
3433 */
3434 for (error = 0, i = 0,
3435 dinfo = STAILQ_FIRST(devlist_head);
3436 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !db_pager_quit;
3437 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
3438
3439 /* Populate pd_name and pd_unit */
3440 name = NULL;
3441 if (dinfo->cfg.dev)
3442 name = device_get_name(dinfo->cfg.dev);
3443
3444 p = &dinfo->conf;
3445 db_kprintf("%s%d@pci%d:%d:%d:%d:\tclass=0x%06x card=0x%08x "
3446 "chip=0x%08x rev=0x%02x hdr=0x%02x\n",
3447 (name && *name) ? name : "none",
3448 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) :
3449 none_count++,
3450 p->pc_sel.pc_domain, p->pc_sel.pc_bus, p->pc_sel.pc_dev,
3451 p->pc_sel.pc_func, (p->pc_class << 16) |
3452 (p->pc_subclass << 8) | p->pc_progif,
3453 (p->pc_subdevice << 16) | p->pc_subvendor,
3454 (p->pc_device << 16) | p->pc_vendor,
3455 p->pc_revid, p->pc_hdr);
3456 }
3457 }
3458 #endif /* DDB */
3459 #endif
3460
3461 static struct resource *
3462 pci_alloc_map(device_t dev, device_t child, int type, int *rid,
3463 u_long start, u_long end, u_long count, u_int flags)
3464 {
3465 struct pci_devinfo *dinfo = device_get_ivars(child);
3466 struct resource_list *rl = &dinfo->resources;
3467 struct resource_list_entry *rle;
3468 struct resource *res;
3469 pci_addr_t map, testval;
3470 int mapsize;
3471
3472 /*
3473 * Weed out the bogons, and figure out how large the BAR/map
3474 * is. Bars that read back 0 here are bogus and unimplemented.
3475 * Note: atapci in legacy mode are special and handled elsewhere
3476 * in the code. If you have a atapci device in legacy mode and
3477 * it fails here, that other code is broken.
3478 */
3479 res = NULL;
3480 map = pci_read_config(child, *rid, 4);
3481 pci_write_config(child, *rid, 0xffffffff, 4);
3482 testval = pci_read_config(child, *rid, 4);
3483 if (pci_maprange(testval) == 64)
3484 map |= (pci_addr_t)pci_read_config(child, *rid + 4, 4) << 32;
3485 if (pci_mapbase(testval) == 0)
3486 goto out;
3487
3488 /*
3489 * Restore the original value of the BAR. We may have reprogrammed
3490 * the BAR of the low-level console device and when booting verbose,
3491 * we need the console device addressable.
3492 */
3493 pci_write_config(child, *rid, map, 4);
3494
3495 if (PCI_BAR_MEM(testval)) {
3496 if (type != SYS_RES_MEMORY) {
3497 if (bootverbose)
3498 device_printf(dev,
3499 "child %s requested type %d for rid %#x,"
3500 " but the BAR says it is an memio\n",
3501 device_get_nameunit(child), type, *rid);
3502 goto out;
3503 }
3504 } else {
3505 if (type != SYS_RES_IOPORT) {
3506 if (bootverbose)
3507 device_printf(dev,
3508 "child %s requested type %d for rid %#x,"
3509 " but the BAR says it is an ioport\n",
3510 device_get_nameunit(child), type, *rid);
3511 goto out;
3512 }
3513 }
3514 /*
3515 * For real BARs, we need to override the size that
3516 * the driver requests, because that's what the BAR
3517 * actually uses and we would otherwise have a
3518 * situation where we might allocate the excess to
3519 * another driver, which won't work.
3520 */
3521 mapsize = pci_mapsize(testval);
3522 count = 1UL << mapsize;
3523 if (RF_ALIGNMENT(flags) < mapsize)
3524 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize);
3525 if (PCI_BAR_MEM(testval) && (testval & PCIM_BAR_MEM_PREFETCH))
3526 flags |= RF_PREFETCHABLE;
3527
3528 /*
3529 * Allocate enough resource, and then write back the
3530 * appropriate bar for that resource.
3531 */
3532 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid,
3533 start, end, count, flags);
3534 if (res == NULL) {
3535 device_printf(child,
3536 "%#lx bytes of rid %#x res %d failed (%#lx, %#lx).\n",
3537 count, *rid, type, start, end);
3538 goto out;
3539 }
3540 resource_list_add(rl, type, *rid, start, end, count);
3541 rle = resource_list_find(rl, type, *rid);
3542 if (rle == NULL)
3543 panic("pci_alloc_map: unexpectedly can't find resource.");
3544 rle->res = res;
3545 rle->start = rman_get_start(res);
3546 rle->end = rman_get_end(res);
3547 rle->count = count;
3548 if (bootverbose)
3549 device_printf(child,
3550 "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n",
3551 count, *rid, type, rman_get_start(res));
3552 map = rman_get_start(res);
3553 out:;
3554 pci_write_config(child, *rid, map, 4);
3555 if (pci_maprange(testval) == 64)
3556 pci_write_config(child, *rid + 4, map >> 32, 4);
3557 return (res);
3558 }
3559
3560
3561 struct resource *
3562 pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
3563 u_long start, u_long end, u_long count, u_int flags)
3564 {
3565 struct pci_devinfo *dinfo = device_get_ivars(child);
3566 struct resource_list *rl = &dinfo->resources;
3567 struct resource_list_entry *rle;
3568 pcicfgregs *cfg = &dinfo->cfg;
3569 //kprintf("%s on %s: requesting resource\n", device_get_desc(child), device_get_desc(dev));
3570 /*
3571 * Perform lazy resource allocation
3572 */
3573 if (device_get_parent(child) == dev) {
3574 switch (type) {
3575 case SYS_RES_IRQ:
3576 /*
3577 * Can't alloc legacy interrupt once MSI messages
3578 * have been allocated.
3579 */
3580 #ifdef MSI
3581 if (*rid == 0 && (cfg->msi.msi_alloc > 0 ||
3582 cfg->msix.msix_alloc > 0))
3583 return (NULL);
3584 #endif
3585 /*
3586 * If the child device doesn't have an
3587 * interrupt routed and is deserving of an
3588 * interrupt, try to assign it one.
3589 */
3590 if (*rid == 0 && !PCI_INTERRUPT_VALID(cfg->intline) &&
3591 (cfg->intpin != 0))
3592 pci_assign_interrupt(dev, child, 0);
3593 break;
3594 case SYS_RES_IOPORT:
3595 case SYS_RES_MEMORY:
3596 if (*rid < PCIR_BAR(cfg->nummaps)) {
3597 /*
3598 * Enable the I/O mode. We should
3599 * also be assigning resources too
3600 * when none are present. The
3601 * resource_list_alloc kind of sorta does
3602 * this...
3603 */
3604 if (PCI_ENABLE_IO(dev, child, type))
3605 return (NULL);
3606 }
3607 rle = resource_list_find(rl, type, *rid);
3608 if (rle == NULL)
3609 return (pci_alloc_map(dev, child, type, rid,
3610 start, end, count, flags));
3611 break;
3612 }
3613 /*
3614 * If we've already allocated the resource, then
3615 * return it now. But first we may need to activate
3616 * it, since we don't allocate the resource as active
3617 * above. Normally this would be done down in the
3618 * nexus, but since we short-circuit that path we have
3619 * to do its job here. Not sure if we should kfree the
3620 * resource if it fails to activate.
3621 */
3622 rle = resource_list_find(rl, type, *rid);
3623 if (rle != NULL && rle->res != NULL) {
3624 if (bootverbose)
3625 device_printf(child,
3626 "Reserved %#lx bytes for rid %#x type %d at %#lx\n",
3627 rman_get_size(rle->res), *rid, type,
3628 rman_get_start(rle->res));
3629 if ((flags & RF_ACTIVE) &&
3630 bus_generic_activate_resource(dev, child, type,
3631 *rid, rle->res) != 0)
3632 return (NULL);
3633 return (rle->res);
3634 }
3635 }
3636 return (resource_list_alloc(rl, dev, child, type, rid,
3637 start, end, count, flags));
3638 }
3639
3640 void
3641 pci_delete_resource(device_t dev, device_t child, int type, int rid)
3642 {
3643 struct pci_devinfo *dinfo;
3644 struct resource_list *rl;
3645 struct resource_list_entry *rle;
3646
3647 if (device_get_parent(child) != dev)
3648 return;
3649
3650 dinfo = device_get_ivars(child);
3651 rl = &dinfo->resources;
3652 rle = resource_list_find(rl, type, rid);
3653 if (rle) {
3654 if (rle->res) {
3655 if (rman_get_device(rle->res) != dev ||
3656 rman_get_flags(rle->res) & RF_ACTIVE) {
3657 device_printf(dev, "delete_resource: "
3658 "Resource still owned by child, oops. "
3659 "(type=%d, rid=%d, addr=%lx)\n",
3660 rle->type, rle->rid,
3661 rman_get_start(rle->res));
3662 return;
3663 }
3664 bus_release_resource(dev, type, rid, rle->res);
3665 }
3666 resource_list_delete(rl, type, rid);
3667 }
3668 /*
3669 * Why do we turn off the PCI configuration BAR when we delete a
3670 * resource? -- imp
3671 */
3672 pci_write_config(child, rid, 0, 4);
3673 BUS_DELETE_RESOURCE(device_get_parent(dev), child, type, rid);
3674 }
3675
3676 struct resource_list *
3677 pci_get_resource_list (device_t dev, device_t child)
3678 {
3679 struct pci_devinfo *dinfo = device_get_ivars(child);
3680
3681 if (dinfo == NULL)
3682 return (NULL);
3683
3684 return (&dinfo->resources);
3685 }
3686
3687 uint32_t
3688 pci_read_config_method(device_t dev, device_t child, int reg, int width)
3689 {
3690 struct pci_devinfo *dinfo = device_get_ivars(child);
3691 pcicfgregs *cfg = &dinfo->cfg;
3692
3693 return (PCIB_READ_CONFIG(device_get_parent(dev),
3694 cfg->bus, cfg->slot, cfg->func, reg, width));
3695 }
3696
3697 void
3698 pci_write_config_method(device_t dev, device_t child, int reg,
3699 uint32_t val, int width)
3700 {
3701 struct pci_devinfo *dinfo = device_get_ivars(child);
3702 pcicfgregs *cfg = &dinfo->cfg;
3703
3704 PCIB_WRITE_CONFIG(device_get_parent(dev),
3705 cfg->bus, cfg->slot, cfg->func, reg, val, width);
3706 }
3707
3708 int
3709 pci_child_location_str_method(device_t dev, device_t child, char *buf,
3710 size_t buflen)
3711 {
3712
3713 ksnprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child),
3714 pci_get_function(child));
3715 return (0);
3716 }
3717
3718 int
3719 pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf,
3720 size_t buflen)
3721 {
3722 struct pci_devinfo *dinfo;
3723 pcicfgregs *cfg;
3724
3725 dinfo = device_get_ivars(child);
3726 cfg = &dinfo->cfg;
3727 ksnprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x "
3728 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device,
3729 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass,
3730 cfg->progif);
3731 return (0);
3732 }
3733
3734 int
3735 pci_assign_interrupt_method(device_t dev, device_t child)
3736 {
3737 struct pci_devinfo *dinfo = device_get_ivars(child);
3738 pcicfgregs *cfg = &dinfo->cfg;
3739
3740 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child,
3741 cfg->intpin));
3742 }
3743
3744 static int
3745 pci_modevent(module_t mod, int what, void *arg)
3746 {
3747 static struct cdev *pci_cdev;
3748 extern struct dev_ops pcic_ops;
3749
3750 switch (what) {
3751 case MOD_LOAD:
3752 STAILQ_INIT(&pci_devq);
3753 pci_generation = 0;
3754 dev_ops_add(&pcic_ops, -1, 0);
3755 pci_cdev = make_dev(&pcic_ops, 0, UID_ROOT, GID_WHEEL, 0644,
3756 "pci%d", 0);
3757 pci_load_vendor_data();
3758 break;
3759
3760 case MOD_UNLOAD:
3761 destroy_dev(pci_cdev);
3762 break;
3763 }
3764
3765 return (0);
3766 }
3767
3768 void
3769 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo)
3770 {
3771 int i;
3772
3773 /*
3774 * Only do header type 0 devices. Type 1 devices are bridges,
3775 * which we know need special treatment. Type 2 devices are
3776 * cardbus bridges which also require special treatment.
3777 * Other types are unknown, and we err on the side of safety
3778 * by ignoring them.
3779 */
3780 if (dinfo->cfg.hdrtype != 0)
3781 return;
3782
3783 /*
3784 * Restore the device to full power mode. We must do this
3785 * before we restore the registers because moving from D3 to
3786 * D0 will cause the chip's BARs and some other registers to
3787 * be reset to some unknown power on reset values. Cut down
3788 * the noise on boot by doing nothing if we are already in
3789 * state D0.
3790 */
3791 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
3792 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
3793 }
3794 for (i = 0; i < dinfo->cfg.nummaps; i++)
3795 pci_write_config(dev, PCIR_BAR(i), dinfo->cfg.bar[i], 4);
3796 pci_write_config(dev, PCIR_BIOS, dinfo->cfg.bios, 4);
3797 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2);
3798 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1);
3799 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1);
3800 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1);
3801 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1);
3802 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1);
3803 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1);
3804 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1);
3805 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1);
3806
3807 /* Restore MSI and MSI-X configurations if they are present. */
3808 if (dinfo->cfg.msi.msi_location != 0)
3809 pci_resume_msi(dev);
3810 if (dinfo->cfg.msix.msix_location != 0)
3811 pci_resume_msix(dev);
3812 }
3813
3814 void
3815 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate)
3816 {
3817 int i;
3818 uint32_t cls;
3819 int ps;
3820
3821 /*
3822 * Only do header type 0 devices. Type 1 devices are bridges, which
3823 * we know need special treatment. Type 2 devices are cardbus bridges
3824 * which also require special treatment. Other types are unknown, and
3825 * we err on the side of safety by ignoring them. Powering down
3826 * bridges should not be undertaken lightly.
3827 */
3828 if (dinfo->cfg.hdrtype != 0)
3829 return;
3830 for (i = 0; i < dinfo->cfg.nummaps; i++)
3831 dinfo->cfg.bar[i] = pci_read_config(dev, PCIR_BAR(i), 4);
3832 dinfo->cfg.bios = pci_read_config(dev, PCIR_BIOS, 4);
3833
3834 /*
3835 * Some drivers apparently write to these registers w/o updating our
3836 * cached copy. No harm happens if we update the copy, so do so here
3837 * so we can restore them. The COMMAND register is modified by the
3838 * bus w/o updating the cache. This should represent the normally
3839 * writable portion of the 'defined' part of type 0 headers. In
3840 * theory we also need to save/restore the PCI capability structures
3841 * we know about, but apart from power we don't know any that are
3842 * writable.
3843 */
3844 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2);
3845 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2);
3846 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2);
3847 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2);
3848 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2);
3849 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1);
3850 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1);
3851 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1);
3852 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1);
3853 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
3854 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
3855 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1);
3856 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1);
3857 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1);
3858 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1);
3859
3860 /*
3861 * don't set the state for display devices, base peripherals and
3862 * memory devices since bad things happen when they are powered down.
3863 * We should (a) have drivers that can easily detach and (b) use
3864 * generic drivers for these devices so that some device actually
3865 * attaches. We need to make sure that when we implement (a) we don't
3866 * power the device down on a reattach.
3867 */
3868 cls = pci_get_class(dev);
3869 if (!setstate)
3870 return;
3871 switch (pci_do_power_nodriver)
3872 {
3873 case 0: /* NO powerdown at all */
3874 return;
3875 case 1: /* Conservative about what to power down */
3876 if (cls == PCIC_STORAGE)
3877 return;
3878 /*FALLTHROUGH*/
3879 case 2: /* Agressive about what to power down */
3880 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY ||
3881 cls == PCIC_BASEPERIPH)
3882 return;
3883 /*FALLTHROUGH*/
3884 case 3: /* Power down everything */
3885 break;
3886 }
3887 /*
3888 * PCI spec says we can only go into D3 state from D0 state.
3889 * Transition from D[12] into D0 before going to D3 state.
3890 */
3891 ps = pci_get_powerstate(dev);
3892 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3)
3893 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
3894 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3)
3895 pci_set_powerstate(dev, PCI_POWERSTATE_D3);
3896 }
DragonFly BSD