sys/dev/netif/ix/if_ix.h

   1 /*
   2  * Copyright (c) 2001-2013, Intel Corporation
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *
   8  *  1. Redistributions of source code must retain the above copyright notice,
   9  *     this list of conditions and the following disclaimer.
  10  *
  11  *  2. Redistributions in binary form must reproduce the above copyright
  12  *     notice, this list of conditions and the following disclaimer in the
  13  *     documentation and/or other materials provided with the distribution.
  14  *
  15  *  3. Neither the name of the Intel Corporation nor the names of its
  16  *     contributors may be used to endorse or promote products derived from
  17  *     this software without specific prior written permission.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  20  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  23  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29  * POSSIBILITY OF SUCH DAMAGE.
  30  */
  31
  32 #ifndef _IF_IX_H_
  33 #define _IF_IX_H_
  34
  35 /* Tunables */
  36
  37 /*
  38  * MSI-X count
  39  */
  40 #define IX_MAX_MSIX             64
  41 #define IX_MAX_MSIX_82598       16
  42
  43 /*
  44  * RX ring count
  45  */
  46 #define IX_MAX_RXRING           16
  47 #define IX_MIN_RXRING_RSS       2
  48
  49 /*
  50  * TX ring count
  51  */
  52 #define IX_MAX_TXRING_82598     32
  53 #define IX_MAX_TXRING_82599     64
  54 #define IX_MAX_TXRING_X540      64
  55
  56 /*
  57  * Default number of segments received before writing to RX related registers
  58  */
  59 #define IX_DEF_RXWREG_NSEGS     32
  60
  61 /*
  62  * Default number of segments sent before writing to TX related registers
  63  */
  64 #define IX_DEF_TXWREG_NSEGS     8
  65
  66 /*
  67  * TxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the
  68  * number of transmit descriptors allocated by the driver. Increasing this
  69  * value allows the driver to queue more transmits. Each descriptor is 16
  70  * bytes. Performance tests have show the 2K value to be optimal for top
  71  * performance.
  72  */
  73 #define IX_DEF_TXD              1024
  74 #define IX_PERF_TXD             2048
  75 #define IX_MAX_TXD              4096
  76 #define IX_MIN_TXD              64
  77
  78 /*
  79  * RxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the
  80  * number of receive descriptors allocated for each RX queue. Increasing this
  81  * value allows the driver to buffer more incoming packets. Each descriptor
  82  * is 16 bytes.  A receive buffer is also allocated for each descriptor.
  83  *
  84  * Note: with 8 rings and a dual port card, it is possible to bump up
  85  *      against the system mbuf pool limit, you can tune nmbclusters
  86  *      to adjust for this.
  87  */
  88 #define IX_DEF_RXD              1024
  89 #define IX_PERF_RXD             2048
  90 #define IX_MAX_RXD              4096
  91 #define IX_MIN_RXD              64
  92
  93 /* Alignment for rings */
  94 #define IX_DBA_ALIGN            128
  95
  96 #define IX_MAX_FRAME_SIZE       9728
  97 #define IX_MTU_HDR              (ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN)
  98 #define IX_MAX_MTU              (IX_MAX_FRAME_SIZE - IX_MTU_HDR)
  99
 100
 101 /* Flow control constants */
 102 #define IX_FC_PAUSE             0xFFFF
 103 #define IX_FC_HI                0x20000
 104 #define IX_FC_LO                0x10000
 105
 106 /*
 107  * RSS related registers
 108  */
 109 #define IX_NRSSRK               10
 110 #define IX_RSSRK_SIZE           4
 111 #define IX_RSSRK_VAL(key, i)    (key[(i) * IX_RSSRK_SIZE] | \
 112                                  key[(i) * IX_RSSRK_SIZE + 1] << 8 | \
 113                                  key[(i) * IX_RSSRK_SIZE + 2] << 16 | \
 114                                  key[(i) * IX_RSSRK_SIZE + 3] << 24)
 115 #define IX_NRETA                32
 116 #define IX_NRETA_X550           128
 117 #define IX_RETA_SIZE            4
 118
 119 /*
 120  * EITR
 121  */
 122 #define IX_EITR_INTVL_MASK_82598 0xffff
 123 #define IX_EITR_INTVL_MASK      0x0fff
 124 #define IX_EITR_INTVL_RSVD_MASK 0x0007
 125 #define IX_EITR_INTVL_MIN       IXGBE_MIN_EITR
 126 #define IX_EITR_INTVL_MAX       IXGBE_MAX_EITR
 127
 128 /*
 129  * Used for optimizing small rx mbufs.  Effort is made to keep the copy
 130  * small and aligned for the CPU L1 cache.
 131  *
 132  * MHLEN is typically 168 bytes, giving us 8-byte alignment.  Getting
 133  * 32 byte alignment needed for the fast bcopy results in 8 bytes being
 134  * wasted.  Getting 64 byte alignment, which _should_ be ideal for
 135  * modern Intel CPUs, results in 40 bytes wasted and a significant drop
 136  * in observed efficiency of the optimization, 97.9% -> 81.8%.
 137  */
 138 #define IX_RX_COPY_LEN          160
 139 #define IX_RX_COPY_ALIGN        (MHLEN - IX_RX_COPY_LEN)
 140
 141 #define IX_MAX_MCASTADDR        128
 142
 143 #define IX_MSIX_BAR_82598       3
 144 #define IX_MSIX_BAR_82599       4
 145
 146 #define IX_TSO_SIZE             (IP_MAXPACKET + \
 147                                  sizeof(struct ether_vlan_header))
 148
 149 /*
 150  * MUST be less than 38.  Though 82598 does not have this limit,
 151  * we don't want long TX chain.  33 should be large enough even
 152  * for 64K TSO (32 x 2K mbuf cluster and 1 x mbuf header).
 153  *
 154  * Reference:
 155  * - 82599 datasheet 7.2.1.1
 156  * - X540 datasheet 7.2.1.1
 157  */
 158 #define IX_MAX_SCATTER          33
 159 #define IX_TX_RESERVED          3       /* 1 for TX ctx, 2 reserved */
 160
 161 /* MSI and legacy interrupt */
 162 #define IX_TX_INTR_VEC          0
 163 #define IX_TX_INTR_MASK         (1 << IX_TX_INTR_VEC)
 164 #define IX_RX0_INTR_VEC         1
 165 #define IX_RX0_INTR_MASK        (1 << IX_RX0_INTR_VEC)
 166 #define IX_RX1_INTR_VEC         2
 167 #define IX_RX1_INTR_MASK        (1 << IX_RX1_INTR_VEC)
 168
 169 #define IX_INTR_RATE            8000
 170 #define IX_MSIX_RX_RATE         8000
 171 #define IX_MSIX_TX_RATE         6000
 172
 173 /* IOCTL define to gather SFP+ Diagnostic data */
 174 #define SIOCGI2C                SIOCGIFGENERIC
 175
 176 /* TX checksum offload */
 177 #define CSUM_OFFLOAD            (CSUM_IP|CSUM_TCP|CSUM_UDP)
 178
 179 #define IX_EICR_STATUS          (IXGBE_EICR_LSC | IXGBE_EICR_ECC | \
 180                                  IXGBE_EICR_GPI_SDP1 | IXGBE_EICR_GPI_SDP2 | \
 181                                  IXGBE_EICR_TS)
 182
 183 /* This is used to get SFP+ module data */
 184 struct ix_i2c_req {
 185         uint8_t         dev_addr;
 186         uint8_t         offset;
 187         uint8_t         len;
 188         uint8_t         data[8];
 189 };
 190
 191 struct ix_tx_buf {
 192         struct mbuf     *m_head;
 193         bus_dmamap_t    map;
 194 };
 195
 196 struct ix_rx_buf {
 197         struct mbuf     *m_head;
 198         struct mbuf     *fmp;
 199         struct mbuf     *lmp;
 200         bus_dmamap_t    map;
 201         bus_addr_t      paddr;
 202         u_int           flags;
 203 #define IX_RX_COPY      0x1
 204 };
 205
 206 struct ix_softc;
 207
 208 struct ix_tx_ring {
 209         struct lwkt_serialize   tx_serialize;
 210         struct ifaltq_subque    *tx_ifsq;
 211         struct ix_softc         *tx_sc;
 212         volatile uint32_t       *tx_hdr;
 213         union ixgbe_adv_tx_desc *tx_base;
 214         struct ix_tx_buf        *tx_buf;
 215         bus_dma_tag_t           tx_tag;
 216         uint16_t                tx_flags;
 217 #define IX_TXFLAG_ENABLED       0x1
 218         uint16_t                tx_pad;
 219         uint32_t                tx_idx;
 220         uint16_t                tx_avail;
 221         uint16_t                tx_next_avail;
 222         uint16_t                tx_next_clean;
 223         uint16_t                tx_ndesc;
 224         uint16_t                tx_wreg_nsegs;
 225         uint16_t                tx_intr_nsegs;
 226         uint16_t                tx_nsegs;
 227         int16_t                 tx_intr_vec;
 228         int                     tx_intr_cpuid;
 229         uint32_t                tx_eims;
 230         uint32_t                tx_eims_val;
 231         struct ifsubq_watchdog  tx_watchdog;
 232
 233         bus_dma_tag_t           tx_base_dtag;
 234         bus_dmamap_t            tx_base_map;
 235         bus_addr_t              tx_base_paddr;
 236
 237         bus_dma_tag_t           tx_hdr_dtag;
 238         bus_dmamap_t            tx_hdr_map;
 239         bus_addr_t              tx_hdr_paddr;
 240 } __cachealign;
 241
 242 struct ix_rx_ring {
 243         struct lwkt_serialize   rx_serialize;
 244         struct ix_softc         *rx_sc;
 245         union ixgbe_adv_rx_desc *rx_base;
 246         struct ix_rx_buf        *rx_buf;
 247         bus_dma_tag_t           rx_tag;
 248         bus_dmamap_t            rx_sparemap;
 249         uint32_t                rx_idx;
 250         uint16_t                rx_flags;
 251 #define IX_RXRING_FLAG_LRO      0x01
 252 #define IX_RXRING_FLAG_DISC     0x02
 253         uint16_t                rx_next_check;
 254         uint16_t                rx_ndesc;
 255         uint16_t                rx_mbuf_sz;
 256         uint16_t                rx_wreg_nsegs;
 257         int16_t                 rx_intr_vec;
 258         uint32_t                rx_eims;
 259         uint32_t                rx_eims_val;
 260         struct ix_tx_ring       *rx_txr;        /* piggybacked TX ring */
 261
 262 #ifdef IX_RSS_DEBUG
 263         u_long                  rx_pkts;
 264 #endif
 265
 266         bus_dma_tag_t           rx_base_dtag;
 267         bus_dmamap_t            rx_base_map;
 268         bus_addr_t              rx_base_paddr;
 269 } __cachealign;
 270
 271 struct ix_intr_data {
 272         struct lwkt_serialize   *intr_serialize;
 273         driver_intr_t           *intr_func;
 274         void                    *intr_hand;
 275         struct resource         *intr_res;
 276         void                    *intr_funcarg;
 277         int                     intr_rid;
 278         int                     intr_cpuid;
 279         int                     intr_rate;
 280         int                     intr_use;
 281 #define IX_INTR_USE_RXTX        0
 282 #define IX_INTR_USE_STATUS      1
 283 #define IX_INTR_USE_RX          2
 284 #define IX_INTR_USE_TX          3
 285         const char              *intr_desc;
 286         char                    intr_desc0[64];
 287 };
 288
 289 struct ix_softc {
 290         struct arpcom           arpcom;
 291
 292         struct ixgbe_hw         hw;
 293         struct ixgbe_osdep      osdep;
 294
 295         struct lwkt_serialize   main_serialize;
 296         uint32_t                intr_mask;
 297
 298         boolean_t               link_active;
 299
 300         int                     rx_ring_inuse;
 301         int                     tx_ring_inuse;
 302
 303         struct ix_rx_ring       *rx_rings;
 304         struct ix_tx_ring       *tx_rings;
 305
 306         struct callout          timer;
 307         int                     timer_cpuid;
 308
 309         int                     ifm_media;      /* IFM_ */
 310         uint32_t                link_speed;
 311         bool                    link_up;
 312         boolean_t               sfp_probe;      /* plyggable optics */
 313
 314         struct ixgbe_hw_stats   stats;
 315
 316         int                     rx_ring_cnt;
 317         int                     rx_ring_msix;
 318
 319         int                     tx_ring_cnt;
 320         int                     tx_ring_msix;
 321
 322         int                     intr_type;
 323         int                     intr_cnt;
 324         struct ix_intr_data     *intr_data;
 325
 326         device_t                dev;
 327         bus_dma_tag_t           parent_tag;
 328         struct ifmedia          media;
 329
 330         struct resource         *mem_res;
 331         int                     mem_rid;
 332
 333         struct resource         *msix_mem_res;
 334         int                     msix_mem_rid;
 335
 336         int                     nserialize;
 337         struct lwkt_serialize   **serializes;
 338
 339         uint8_t                 *mta;           /* Multicast array memory */
 340
 341         int                     if_flags;
 342         int                     advspeed;       /* advertised link speeds */
 343         uint32_t                wufc;           /* power management */
 344         uint16_t                dmac;           /* DMA coalescing */
 345         uint16_t                max_frame_size;
 346         int16_t                 sts_msix_vec;   /* status MSI-X vector */
 347
 348         int                     rx_npoll_off;
 349         int                     tx_npoll_off;
 350
 351 #ifdef IX_RSS_DEBUG
 352         int                     rss_debug;
 353 #endif
 354 };
 355
 356 #define IX_ENABLE_HWRSS(sc)     ((sc)->rx_ring_cnt > 1)
 357 #define IX_ENABLE_HWTSS(sc)     ((sc)->tx_ring_cnt > 1)
 358
 359 #endif /* _IF_IX_H_ */