2 * Copyright 2011 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Alex Deucher
27 #include "radeon_asic.h"
30 #include "rv770_dpm.h"
31 #include "cypress_dpm.h"
33 #include <linux/seq_file.h>
35 #define MC_CG_ARB_FREQ_F0 0x0a
36 #define MC_CG_ARB_FREQ_F1 0x0b
37 #define MC_CG_ARB_FREQ_F2 0x0c
38 #define MC_CG_ARB_FREQ_F3 0x0d
40 #define MC_CG_SEQ_DRAMCONF_S0 0x05
41 #define MC_CG_SEQ_DRAMCONF_S1 0x06
43 #define PCIE_BUS_CLK 10000
44 #define TCLK (PCIE_BUS_CLK / 10)
46 #define SMC_RAM_END 0xC000
48 struct rv7xx_ps
*rv770_get_ps(struct radeon_ps
*rps
);
49 struct rv7xx_power_info
*rv770_get_pi(struct radeon_device
*rdev
);
50 struct evergreen_power_info
*evergreen_get_pi(struct radeon_device
*rdev
);
52 struct rv7xx_ps
*rv770_get_ps(struct radeon_ps
*rps
)
54 struct rv7xx_ps
*ps
= rps
->ps_priv
;
59 struct rv7xx_power_info
*rv770_get_pi(struct radeon_device
*rdev
)
61 struct rv7xx_power_info
*pi
= rdev
->pm
.dpm
.priv
;
66 struct evergreen_power_info
*evergreen_get_pi(struct radeon_device
*rdev
)
68 struct evergreen_power_info
*pi
= rdev
->pm
.dpm
.priv
;
73 static void rv770_enable_bif_dynamic_pcie_gen2(struct radeon_device
*rdev
,
76 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
79 tmp
= RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL
);
81 tmp
&= ~LC_HW_VOLTAGE_IF_CONTROL_MASK
;
82 tmp
|= LC_HW_VOLTAGE_IF_CONTROL(1);
83 tmp
|= LC_GEN2_EN_STRAP
;
85 if (!pi
->boot_in_gen2
) {
86 tmp
&= ~LC_HW_VOLTAGE_IF_CONTROL_MASK
;
87 tmp
&= ~LC_GEN2_EN_STRAP
;
90 if ((tmp
& LC_OTHER_SIDE_EVER_SENT_GEN2
) ||
91 (tmp
& LC_OTHER_SIDE_SUPPORTS_GEN2
))
92 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL
, tmp
);
96 static void rv770_enable_l0s(struct radeon_device
*rdev
)
100 tmp
= RREG32_PCIE_PORT(PCIE_LC_CNTL
) & ~LC_L0S_INACTIVITY_MASK
;
101 tmp
|= LC_L0S_INACTIVITY(3);
102 WREG32_PCIE_PORT(PCIE_LC_CNTL
, tmp
);
105 static void rv770_enable_l1(struct radeon_device
*rdev
)
109 tmp
= RREG32_PCIE_PORT(PCIE_LC_CNTL
);
110 tmp
&= ~LC_L1_INACTIVITY_MASK
;
111 tmp
|= LC_L1_INACTIVITY(4);
112 tmp
&= ~LC_PMI_TO_L1_DIS
;
113 tmp
&= ~LC_ASPM_TO_L1_DIS
;
114 WREG32_PCIE_PORT(PCIE_LC_CNTL
, tmp
);
117 static void rv770_enable_pll_sleep_in_l1(struct radeon_device
*rdev
)
121 tmp
= RREG32_PCIE_PORT(PCIE_LC_CNTL
) & ~LC_L1_INACTIVITY_MASK
;
122 tmp
|= LC_L1_INACTIVITY(8);
123 WREG32_PCIE_PORT(PCIE_LC_CNTL
, tmp
);
125 /* NOTE, this is a PCIE indirect reg, not PCIE PORT */
126 tmp
= RREG32_PCIE(PCIE_P_CNTL
);
127 tmp
|= P_PLL_PWRDN_IN_L1L23
;
128 tmp
&= ~P_PLL_BUF_PDNB
;
130 tmp
|= P_ALLOW_PRX_FRONTEND_SHUTOFF
;
131 WREG32_PCIE(PCIE_P_CNTL
, tmp
);
134 static void rv770_gfx_clock_gating_enable(struct radeon_device
*rdev
,
138 WREG32_P(SCLK_PWRMGT_CNTL
, DYN_GFX_CLK_OFF_EN
, ~DYN_GFX_CLK_OFF_EN
);
140 WREG32_P(SCLK_PWRMGT_CNTL
, 0, ~DYN_GFX_CLK_OFF_EN
);
141 WREG32_P(SCLK_PWRMGT_CNTL
, GFX_CLK_FORCE_ON
, ~GFX_CLK_FORCE_ON
);
142 WREG32_P(SCLK_PWRMGT_CNTL
, 0, ~GFX_CLK_FORCE_ON
);
143 RREG32(GB_TILING_CONFIG
);
147 static void rv770_mg_clock_gating_enable(struct radeon_device
*rdev
,
150 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
153 u32 mgcg_cgtt_local0
;
155 if (rdev
->family
== CHIP_RV770
)
156 mgcg_cgtt_local0
= RV770_MGCGTTLOCAL0_DFLT
;
158 mgcg_cgtt_local0
= RV7XX_MGCGTTLOCAL0_DFLT
;
160 WREG32(CG_CGTT_LOCAL_0
, mgcg_cgtt_local0
);
161 WREG32(CG_CGTT_LOCAL_1
, (RV770_MGCGTTLOCAL1_DFLT
& 0xFFFFCFFF));
164 WREG32(CGTS_SM_CTRL_REG
, RV770_MGCGCGTSSMCTRL_DFLT
);
166 WREG32(CG_CGTT_LOCAL_0
, 0xFFFFFFFF);
167 WREG32(CG_CGTT_LOCAL_1
, 0xFFFFCFFF);
171 void rv770_restore_cgcg(struct radeon_device
*rdev
)
173 bool dpm_en
= false, cg_en
= false;
175 if (RREG32(GENERAL_PWRMGT
) & GLOBAL_PWRMGT_EN
)
177 if (RREG32(SCLK_PWRMGT_CNTL
) & DYN_GFX_CLK_OFF_EN
)
180 if (dpm_en
&& !cg_en
)
181 WREG32_P(SCLK_PWRMGT_CNTL
, DYN_GFX_CLK_OFF_EN
, ~DYN_GFX_CLK_OFF_EN
);
184 static void rv770_start_dpm(struct radeon_device
*rdev
)
186 WREG32_P(SCLK_PWRMGT_CNTL
, 0, ~SCLK_PWRMGT_OFF
);
188 WREG32_P(MCLK_PWRMGT_CNTL
, 0, ~MPLL_PWRMGT_OFF
);
190 WREG32_P(GENERAL_PWRMGT
, GLOBAL_PWRMGT_EN
, ~GLOBAL_PWRMGT_EN
);
193 void rv770_stop_dpm(struct radeon_device
*rdev
)
197 result
= rv770_send_msg_to_smc(rdev
, PPSMC_MSG_TwoLevelsDisabled
);
199 if (result
!= PPSMC_Result_OK
)
200 DRM_ERROR("Could not force DPM to low.\n");
202 WREG32_P(GENERAL_PWRMGT
, 0, ~GLOBAL_PWRMGT_EN
);
204 WREG32_P(SCLK_PWRMGT_CNTL
, SCLK_PWRMGT_OFF
, ~SCLK_PWRMGT_OFF
);
206 WREG32_P(MCLK_PWRMGT_CNTL
, MPLL_PWRMGT_OFF
, ~MPLL_PWRMGT_OFF
);
209 bool rv770_dpm_enabled(struct radeon_device
*rdev
)
211 if (RREG32(GENERAL_PWRMGT
) & GLOBAL_PWRMGT_EN
)
217 void rv770_enable_thermal_protection(struct radeon_device
*rdev
,
221 WREG32_P(GENERAL_PWRMGT
, 0, ~THERMAL_PROTECTION_DIS
);
223 WREG32_P(GENERAL_PWRMGT
, THERMAL_PROTECTION_DIS
, ~THERMAL_PROTECTION_DIS
);
226 void rv770_enable_acpi_pm(struct radeon_device
*rdev
)
228 WREG32_P(GENERAL_PWRMGT
, STATIC_PM_EN
, ~STATIC_PM_EN
);
231 u8
rv770_get_seq_value(struct radeon_device
*rdev
,
234 return (pl
->flags
& ATOM_PPLIB_R600_FLAGS_LOWPOWER
) ?
235 MC_CG_SEQ_DRAMCONF_S0
: MC_CG_SEQ_DRAMCONF_S1
;
239 int rv770_read_smc_soft_register(struct radeon_device
*rdev
,
240 u16 reg_offset
, u32
*value
)
242 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
244 return rv770_read_smc_sram_dword(rdev
,
245 pi
->soft_regs_start
+ reg_offset
,
246 value
, pi
->sram_end
);
250 int rv770_write_smc_soft_register(struct radeon_device
*rdev
,
251 u16 reg_offset
, u32 value
)
253 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
255 return rv770_write_smc_sram_dword(rdev
,
256 pi
->soft_regs_start
+ reg_offset
,
257 value
, pi
->sram_end
);
260 int rv770_populate_smc_t(struct radeon_device
*rdev
,
261 struct radeon_ps
*radeon_state
,
262 RV770_SMC_SWSTATE
*smc_state
)
264 struct rv7xx_ps
*state
= rv770_get_ps(radeon_state
);
265 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
269 u8 l
[RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE
];
270 u8 r
[RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE
];
276 a_n
= (int)state
->medium
.sclk
* pi
->lmp
+
277 (int)state
->low
.sclk
* (R600_AH_DFLT
- pi
->rlp
);
278 a_d
= (int)state
->low
.sclk
* (100 - (int)pi
->rlp
) +
279 (int)state
->medium
.sclk
* pi
->lmp
;
281 l
[1] = (u8
)(pi
->lmp
- (int)pi
->lmp
* a_n
/ a_d
);
282 r
[0] = (u8
)(pi
->rlp
+ (100 - (int)pi
->rlp
) * a_n
/ a_d
);
284 a_n
= (int)state
->high
.sclk
* pi
->lhp
+ (int)state
->medium
.sclk
*
285 (R600_AH_DFLT
- pi
->rmp
);
286 a_d
= (int)state
->medium
.sclk
* (100 - (int)pi
->rmp
) +
287 (int)state
->high
.sclk
* pi
->lhp
;
289 l
[2] = (u8
)(pi
->lhp
- (int)pi
->lhp
* a_n
/ a_d
);
290 r
[1] = (u8
)(pi
->rmp
+ (100 - (int)pi
->rmp
) * a_n
/ a_d
);
292 for (i
= 0; i
< (RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE
- 1); i
++) {
293 a_t
= CG_R(r
[i
] * pi
->bsp
/ 200) | CG_L(l
[i
] * pi
->bsp
/ 200);
294 smc_state
->levels
[i
].aT
= cpu_to_be32(a_t
);
297 a_t
= CG_R(r
[RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE
- 1] * pi
->pbsp
/ 200) |
298 CG_L(l
[RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE
- 1] * pi
->pbsp
/ 200);
300 smc_state
->levels
[RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE
- 1].aT
=
306 int rv770_populate_smc_sp(struct radeon_device
*rdev
,
307 struct radeon_ps
*radeon_state
,
308 RV770_SMC_SWSTATE
*smc_state
)
310 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
313 for (i
= 0; i
< (RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE
- 1); i
++)
314 smc_state
->levels
[i
].bSP
= cpu_to_be32(pi
->dsp
);
316 smc_state
->levels
[RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE
- 1].bSP
=
317 cpu_to_be32(pi
->psp
);
322 static void rv770_calculate_fractional_mpll_feedback_divider(u32 memory_clock
,
325 struct atom_clock_dividers
*dividers
,
329 u32 post_divider
, reference_divider
, feedback_divider8
;
333 fyclk
= (memory_clock
* 8) / 2;
335 fyclk
= (memory_clock
* 4) / 2;
337 post_divider
= dividers
->post_div
;
338 reference_divider
= dividers
->ref_div
;
341 (8 * fyclk
* reference_divider
* post_divider
) / reference_clock
;
343 *clkf
= feedback_divider8
/ 8;
344 *clkfrac
= feedback_divider8
% 8;
347 static int rv770_encode_yclk_post_div(u32 postdiv
, u32
*encoded_postdiv
)
353 *encoded_postdiv
= 0;
356 *encoded_postdiv
= 1;
359 *encoded_postdiv
= 2;
362 *encoded_postdiv
= 3;
365 *encoded_postdiv
= 4;
375 u32
rv770_map_clkf_to_ibias(struct radeon_device
*rdev
, u32 clkf
)
390 static int rv770_populate_mclk_value(struct radeon_device
*rdev
,
391 u32 engine_clock
, u32 memory_clock
,
392 RV7XX_SMC_MCLK_VALUE
*mclk
)
394 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
395 u8 encoded_reference_dividers
[] = { 0, 16, 17, 20, 21 };
396 u32 mpll_ad_func_cntl
=
397 pi
->clk_regs
.rv770
.mpll_ad_func_cntl
;
398 u32 mpll_ad_func_cntl_2
=
399 pi
->clk_regs
.rv770
.mpll_ad_func_cntl_2
;
400 u32 mpll_dq_func_cntl
=
401 pi
->clk_regs
.rv770
.mpll_dq_func_cntl
;
402 u32 mpll_dq_func_cntl_2
=
403 pi
->clk_regs
.rv770
.mpll_dq_func_cntl_2
;
404 u32 mclk_pwrmgt_cntl
=
405 pi
->clk_regs
.rv770
.mclk_pwrmgt_cntl
;
406 u32 dll_cntl
= pi
->clk_regs
.rv770
.dll_cntl
;
407 struct atom_clock_dividers dividers
;
408 u32 reference_clock
= rdev
->clock
.mpll
.reference_freq
;
414 ret
= radeon_atom_get_clock_dividers(rdev
, COMPUTE_MEMORY_PLL_PARAM
,
415 memory_clock
, false, ÷rs
);
419 if ((dividers
.ref_div
< 1) || (dividers
.ref_div
> 5))
422 rv770_calculate_fractional_mpll_feedback_divider(memory_clock
, reference_clock
,
424 ÷rs
, &clkf
, &clkfrac
);
426 ret
= rv770_encode_yclk_post_div(dividers
.post_div
, &postdiv_yclk
);
430 ibias
= rv770_map_clkf_to_ibias(rdev
, clkf
);
432 mpll_ad_func_cntl
&= ~(CLKR_MASK
|
437 mpll_ad_func_cntl
|= CLKR(encoded_reference_dividers
[dividers
.ref_div
- 1]);
438 mpll_ad_func_cntl
|= YCLK_POST_DIV(postdiv_yclk
);
439 mpll_ad_func_cntl
|= CLKF(clkf
);
440 mpll_ad_func_cntl
|= CLKFRAC(clkfrac
);
441 mpll_ad_func_cntl
|= IBIAS(ibias
);
443 if (dividers
.vco_mode
)
444 mpll_ad_func_cntl_2
|= VCO_MODE
;
446 mpll_ad_func_cntl_2
&= ~VCO_MODE
;
449 rv770_calculate_fractional_mpll_feedback_divider(memory_clock
,
452 ÷rs
, &clkf
, &clkfrac
);
454 ibias
= rv770_map_clkf_to_ibias(rdev
, clkf
);
456 ret
= rv770_encode_yclk_post_div(dividers
.post_div
, &postdiv_yclk
);
460 mpll_dq_func_cntl
&= ~(CLKR_MASK
|
465 mpll_dq_func_cntl
|= CLKR(encoded_reference_dividers
[dividers
.ref_div
- 1]);
466 mpll_dq_func_cntl
|= YCLK_POST_DIV(postdiv_yclk
);
467 mpll_dq_func_cntl
|= CLKF(clkf
);
468 mpll_dq_func_cntl
|= CLKFRAC(clkfrac
);
469 mpll_dq_func_cntl
|= IBIAS(ibias
);
471 if (dividers
.vco_mode
)
472 mpll_dq_func_cntl_2
|= VCO_MODE
;
474 mpll_dq_func_cntl_2
&= ~VCO_MODE
;
477 mclk
->mclk770
.mclk_value
= cpu_to_be32(memory_clock
);
478 mclk
->mclk770
.vMPLL_AD_FUNC_CNTL
= cpu_to_be32(mpll_ad_func_cntl
);
479 mclk
->mclk770
.vMPLL_AD_FUNC_CNTL_2
= cpu_to_be32(mpll_ad_func_cntl_2
);
480 mclk
->mclk770
.vMPLL_DQ_FUNC_CNTL
= cpu_to_be32(mpll_dq_func_cntl
);
481 mclk
->mclk770
.vMPLL_DQ_FUNC_CNTL_2
= cpu_to_be32(mpll_dq_func_cntl_2
);
482 mclk
->mclk770
.vMCLK_PWRMGT_CNTL
= cpu_to_be32(mclk_pwrmgt_cntl
);
483 mclk
->mclk770
.vDLL_CNTL
= cpu_to_be32(dll_cntl
);
488 static int rv770_populate_sclk_value(struct radeon_device
*rdev
,
490 RV770_SMC_SCLK_VALUE
*sclk
)
492 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
493 struct atom_clock_dividers dividers
;
495 pi
->clk_regs
.rv770
.cg_spll_func_cntl
;
496 u32 spll_func_cntl_2
=
497 pi
->clk_regs
.rv770
.cg_spll_func_cntl_2
;
498 u32 spll_func_cntl_3
=
499 pi
->clk_regs
.rv770
.cg_spll_func_cntl_3
;
500 u32 cg_spll_spread_spectrum
=
501 pi
->clk_regs
.rv770
.cg_spll_spread_spectrum
;
502 u32 cg_spll_spread_spectrum_2
=
503 pi
->clk_regs
.rv770
.cg_spll_spread_spectrum_2
;
505 u32 reference_clock
= rdev
->clock
.spll
.reference_freq
;
506 u32 reference_divider
, post_divider
;
510 ret
= radeon_atom_get_clock_dividers(rdev
, COMPUTE_ENGINE_PLL_PARAM
,
511 engine_clock
, false, ÷rs
);
515 reference_divider
= 1 + dividers
.ref_div
;
517 if (dividers
.enable_post_div
)
518 post_divider
= (0x0f & (dividers
.post_div
>> 4)) + (0x0f & dividers
.post_div
) + 2;
522 tmp
= (u64
) engine_clock
* reference_divider
* post_divider
* 16384;
523 do_div(tmp
, reference_clock
);
526 if (dividers
.enable_post_div
)
527 spll_func_cntl
|= SPLL_DIVEN
;
529 spll_func_cntl
&= ~SPLL_DIVEN
;
530 spll_func_cntl
&= ~(SPLL_HILEN_MASK
| SPLL_LOLEN_MASK
| SPLL_REF_DIV_MASK
);
531 spll_func_cntl
|= SPLL_REF_DIV(dividers
.ref_div
);
532 spll_func_cntl
|= SPLL_HILEN((dividers
.post_div
>> 4) & 0xf);
533 spll_func_cntl
|= SPLL_LOLEN(dividers
.post_div
& 0xf);
535 spll_func_cntl_2
&= ~SCLK_MUX_SEL_MASK
;
536 spll_func_cntl_2
|= SCLK_MUX_SEL(2);
538 spll_func_cntl_3
&= ~SPLL_FB_DIV_MASK
;
539 spll_func_cntl_3
|= SPLL_FB_DIV(fbdiv
);
540 spll_func_cntl_3
|= SPLL_DITHEN
;
543 struct radeon_atom_ss ss
;
544 u32 vco_freq
= engine_clock
* post_divider
;
546 if (radeon_atombios_get_asic_ss_info(rdev
, &ss
,
547 ASIC_INTERNAL_ENGINE_SS
, vco_freq
)) {
548 u32 clk_s
= reference_clock
* 5 / (reference_divider
* ss
.rate
);
549 u32 clk_v
= ss
.percentage
* fbdiv
/ (clk_s
* 10000);
551 cg_spll_spread_spectrum
&= ~CLKS_MASK
;
552 cg_spll_spread_spectrum
|= CLKS(clk_s
);
553 cg_spll_spread_spectrum
|= SSEN
;
555 cg_spll_spread_spectrum_2
&= ~CLKV_MASK
;
556 cg_spll_spread_spectrum_2
|= CLKV(clk_v
);
560 sclk
->sclk_value
= cpu_to_be32(engine_clock
);
561 sclk
->vCG_SPLL_FUNC_CNTL
= cpu_to_be32(spll_func_cntl
);
562 sclk
->vCG_SPLL_FUNC_CNTL_2
= cpu_to_be32(spll_func_cntl_2
);
563 sclk
->vCG_SPLL_FUNC_CNTL_3
= cpu_to_be32(spll_func_cntl_3
);
564 sclk
->vCG_SPLL_SPREAD_SPECTRUM
= cpu_to_be32(cg_spll_spread_spectrum
);
565 sclk
->vCG_SPLL_SPREAD_SPECTRUM_2
= cpu_to_be32(cg_spll_spread_spectrum_2
);
570 int rv770_populate_vddc_value(struct radeon_device
*rdev
, u16 vddc
,
571 RV770_SMC_VOLTAGE_VALUE
*voltage
)
573 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
576 if (!pi
->voltage_control
) {
582 for (i
= 0; i
< pi
->valid_vddc_entries
; i
++) {
583 if (vddc
<= pi
->vddc_table
[i
].vddc
) {
584 voltage
->index
= pi
->vddc_table
[i
].vddc_index
;
585 voltage
->value
= cpu_to_be16(vddc
);
590 if (i
== pi
->valid_vddc_entries
)
596 int rv770_populate_mvdd_value(struct radeon_device
*rdev
, u32 mclk
,
597 RV770_SMC_VOLTAGE_VALUE
*voltage
)
599 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
601 if (!pi
->mvdd_control
) {
602 voltage
->index
= MVDD_HIGH_INDEX
;
603 voltage
->value
= cpu_to_be16(MVDD_HIGH_VALUE
);
607 if (mclk
<= pi
->mvdd_split_frequency
) {
608 voltage
->index
= MVDD_LOW_INDEX
;
609 voltage
->value
= cpu_to_be16(MVDD_LOW_VALUE
);
611 voltage
->index
= MVDD_HIGH_INDEX
;
612 voltage
->value
= cpu_to_be16(MVDD_HIGH_VALUE
);
618 static int rv770_convert_power_level_to_smc(struct radeon_device
*rdev
,
620 RV770_SMC_HW_PERFORMANCE_LEVEL
*level
,
623 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
626 level
->gen2PCIE
= pi
->pcie_gen2
?
627 ((pl
->flags
& ATOM_PPLIB_R600_FLAGS_PCIEGEN2
) ? 1 : 0) : 0;
628 level
->gen2XSP
= (pl
->flags
& ATOM_PPLIB_R600_FLAGS_PCIEGEN2
) ? 1 : 0;
629 level
->backbias
= (pl
->flags
& ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE
) ? 1 : 0;
630 level
->displayWatermark
= watermark_level
;
632 if (rdev
->family
== CHIP_RV740
)
633 ret
= rv740_populate_sclk_value(rdev
, pl
->sclk
,
635 else if ((rdev
->family
== CHIP_RV730
) || (rdev
->family
== CHIP_RV710
))
636 ret
= rv730_populate_sclk_value(rdev
, pl
->sclk
,
639 ret
= rv770_populate_sclk_value(rdev
, pl
->sclk
,
644 if (rdev
->family
== CHIP_RV740
) {
646 if (pl
->mclk
<= pi
->mclk_strobe_mode_threshold
)
648 rv740_get_mclk_frequency_ratio(pl
->mclk
) | 0x10;
650 level
->strobeMode
= 0;
652 if (pl
->mclk
> pi
->mclk_edc_enable_threshold
)
653 level
->mcFlags
= SMC_MC_EDC_RD_FLAG
| SMC_MC_EDC_WR_FLAG
;
657 ret
= rv740_populate_mclk_value(rdev
, pl
->sclk
,
658 pl
->mclk
, &level
->mclk
);
659 } else if ((rdev
->family
== CHIP_RV730
) || (rdev
->family
== CHIP_RV710
))
660 ret
= rv730_populate_mclk_value(rdev
, pl
->sclk
,
661 pl
->mclk
, &level
->mclk
);
663 ret
= rv770_populate_mclk_value(rdev
, pl
->sclk
,
664 pl
->mclk
, &level
->mclk
);
668 ret
= rv770_populate_vddc_value(rdev
, pl
->vddc
,
673 ret
= rv770_populate_mvdd_value(rdev
, pl
->mclk
, &level
->mvdd
);
678 static int rv770_convert_power_state_to_smc(struct radeon_device
*rdev
,
679 struct radeon_ps
*radeon_state
,
680 RV770_SMC_SWSTATE
*smc_state
)
682 struct rv7xx_ps
*state
= rv770_get_ps(radeon_state
);
685 if (!(radeon_state
->caps
& ATOM_PPLIB_DISALLOW_ON_DC
))
686 smc_state
->flags
|= PPSMC_SWSTATE_FLAG_DC
;
688 ret
= rv770_convert_power_level_to_smc(rdev
,
690 &smc_state
->levels
[0],
691 PPSMC_DISPLAY_WATERMARK_LOW
);
695 ret
= rv770_convert_power_level_to_smc(rdev
,
697 &smc_state
->levels
[1],
698 PPSMC_DISPLAY_WATERMARK_LOW
);
702 ret
= rv770_convert_power_level_to_smc(rdev
,
704 &smc_state
->levels
[2],
705 PPSMC_DISPLAY_WATERMARK_HIGH
);
709 smc_state
->levels
[0].arbValue
= MC_CG_ARB_FREQ_F1
;
710 smc_state
->levels
[1].arbValue
= MC_CG_ARB_FREQ_F2
;
711 smc_state
->levels
[2].arbValue
= MC_CG_ARB_FREQ_F3
;
713 smc_state
->levels
[0].seqValue
= rv770_get_seq_value(rdev
,
715 smc_state
->levels
[1].seqValue
= rv770_get_seq_value(rdev
,
717 smc_state
->levels
[2].seqValue
= rv770_get_seq_value(rdev
,
720 rv770_populate_smc_sp(rdev
, radeon_state
, smc_state
);
722 return rv770_populate_smc_t(rdev
, radeon_state
, smc_state
);
726 u32
rv770_calculate_memory_refresh_rate(struct radeon_device
*rdev
,
730 u32 dram_refresh_rate
;
731 u32 mc_arb_rfsh_rate
;
734 tmp
= (RREG32(MC_ARB_RAMCFG
) & NOOFROWS_MASK
) >> NOOFROWS_SHIFT
;
735 dram_rows
= 1 << (tmp
+ 10);
736 tmp
= RREG32(MC_SEQ_MISC0
) & 3;
737 dram_refresh_rate
= 1 << (tmp
+ 3);
738 mc_arb_rfsh_rate
= ((engine_clock
* 10) * dram_refresh_rate
/ dram_rows
- 32) / 64;
740 return mc_arb_rfsh_rate
;
743 static void rv770_program_memory_timing_parameters(struct radeon_device
*rdev
,
744 struct radeon_ps
*radeon_state
)
746 struct rv7xx_ps
*state
= rv770_get_ps(radeon_state
);
747 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
749 u32 arb_refresh_rate
;
752 if (state
->high
.sclk
< (state
->low
.sclk
* 0xFF / 0x40))
753 high_clock
= state
->high
.sclk
;
755 high_clock
= (state
->low
.sclk
* 0xFF / 0x40);
757 radeon_atom_set_engine_dram_timings(rdev
, high_clock
,
761 STATE0(64 * high_clock
/ pi
->boot_sclk
) |
762 STATE1(64 * high_clock
/ state
->low
.sclk
) |
763 STATE2(64 * high_clock
/ state
->medium
.sclk
) |
764 STATE3(64 * high_clock
/ state
->high
.sclk
);
765 WREG32(MC_ARB_SQM_RATIO
, sqm_ratio
);
768 POWERMODE0(rv770_calculate_memory_refresh_rate(rdev
, pi
->boot_sclk
)) |
769 POWERMODE1(rv770_calculate_memory_refresh_rate(rdev
, state
->low
.sclk
)) |
770 POWERMODE2(rv770_calculate_memory_refresh_rate(rdev
, state
->medium
.sclk
)) |
771 POWERMODE3(rv770_calculate_memory_refresh_rate(rdev
, state
->high
.sclk
));
772 WREG32(MC_ARB_RFSH_RATE
, arb_refresh_rate
);
775 void rv770_enable_backbias(struct radeon_device
*rdev
,
779 WREG32_P(GENERAL_PWRMGT
, BACKBIAS_PAD_EN
, ~BACKBIAS_PAD_EN
);
781 WREG32_P(GENERAL_PWRMGT
, 0, ~(BACKBIAS_VALUE
| BACKBIAS_PAD_EN
));
784 static void rv770_enable_spread_spectrum(struct radeon_device
*rdev
,
787 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
791 WREG32_P(GENERAL_PWRMGT
, DYN_SPREAD_SPECTRUM_EN
, ~DYN_SPREAD_SPECTRUM_EN
);
794 if (rdev
->family
== CHIP_RV740
)
795 rv740_enable_mclk_spread_spectrum(rdev
, true);
798 WREG32_P(CG_SPLL_SPREAD_SPECTRUM
, 0, ~SSEN
);
800 WREG32_P(GENERAL_PWRMGT
, 0, ~DYN_SPREAD_SPECTRUM_EN
);
802 WREG32_P(CG_MPLL_SPREAD_SPECTRUM
, 0, ~SSEN
);
804 if (rdev
->family
== CHIP_RV740
)
805 rv740_enable_mclk_spread_spectrum(rdev
, false);
809 static void rv770_program_mpll_timing_parameters(struct radeon_device
*rdev
)
811 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
813 if ((rdev
->family
== CHIP_RV770
) && !pi
->mem_gddr5
) {
815 (MPLL_LOCK_TIME(R600_MPLLLOCKTIME_DFLT
* pi
->ref_div
) |
816 MPLL_RESET_TIME(R600_MPLLRESETTIME_DFLT
)));
820 void rv770_setup_bsp(struct radeon_device
*rdev
)
822 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
823 u32 xclk
= radeon_get_xclk(rdev
);
825 r600_calculate_u_and_p(pi
->asi
,
831 r600_calculate_u_and_p(pi
->pasi
,
837 pi
->dsp
= BSP(pi
->bsp
) | BSU(pi
->bsu
);
838 pi
->psp
= BSP(pi
->pbsp
) | BSU(pi
->pbsu
);
840 WREG32(CG_BSP
, pi
->dsp
);
844 void rv770_program_git(struct radeon_device
*rdev
)
846 WREG32_P(CG_GIT
, CG_GICST(R600_GICST_DFLT
), ~CG_GICST_MASK
);
849 void rv770_program_tp(struct radeon_device
*rdev
)
852 enum r600_td td
= R600_TD_DFLT
;
854 for (i
= 0; i
< R600_PM_NUMBER_OF_TC
; i
++)
855 WREG32(CG_FFCT_0
+ (i
* 4), (UTC_0(r600_utc
[i
]) | DTC_0(r600_dtc
[i
])));
857 if (td
== R600_TD_AUTO
)
858 WREG32_P(SCLK_PWRMGT_CNTL
, 0, ~FIR_FORCE_TREND_SEL
);
860 WREG32_P(SCLK_PWRMGT_CNTL
, FIR_FORCE_TREND_SEL
, ~FIR_FORCE_TREND_SEL
);
861 if (td
== R600_TD_UP
)
862 WREG32_P(SCLK_PWRMGT_CNTL
, 0, ~FIR_TREND_MODE
);
863 if (td
== R600_TD_DOWN
)
864 WREG32_P(SCLK_PWRMGT_CNTL
, FIR_TREND_MODE
, ~FIR_TREND_MODE
);
867 void rv770_program_tpp(struct radeon_device
*rdev
)
869 WREG32(CG_TPC
, R600_TPC_DFLT
);
872 void rv770_program_sstp(struct radeon_device
*rdev
)
874 WREG32(CG_SSP
, (SSTU(R600_SSTU_DFLT
) | SST(R600_SST_DFLT
)));
877 void rv770_program_engine_speed_parameters(struct radeon_device
*rdev
)
879 WREG32_P(SPLL_CNTL_MODE
, SPLL_DIV_SYNC
, ~SPLL_DIV_SYNC
);
882 static void rv770_enable_display_gap(struct radeon_device
*rdev
)
884 u32 tmp
= RREG32(CG_DISPLAY_GAP_CNTL
);
886 tmp
&= ~(DISP1_GAP_MCHG_MASK
| DISP2_GAP_MCHG_MASK
);
887 tmp
|= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE
) |
888 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE
));
889 WREG32(CG_DISPLAY_GAP_CNTL
, tmp
);
892 void rv770_program_vc(struct radeon_device
*rdev
)
894 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
896 WREG32(CG_FTV
, pi
->vrc
);
899 void rv770_clear_vc(struct radeon_device
*rdev
)
904 int rv770_upload_firmware(struct radeon_device
*rdev
)
906 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
909 rv770_reset_smc(rdev
);
910 rv770_stop_smc_clock(rdev
);
912 ret
= rv770_load_smc_ucode(rdev
, pi
->sram_end
);
919 static int rv770_populate_smc_acpi_state(struct radeon_device
*rdev
,
920 RV770_SMC_STATETABLE
*table
)
922 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
924 u32 mpll_ad_func_cntl
=
925 pi
->clk_regs
.rv770
.mpll_ad_func_cntl
;
926 u32 mpll_ad_func_cntl_2
=
927 pi
->clk_regs
.rv770
.mpll_ad_func_cntl_2
;
928 u32 mpll_dq_func_cntl
=
929 pi
->clk_regs
.rv770
.mpll_dq_func_cntl
;
930 u32 mpll_dq_func_cntl_2
=
931 pi
->clk_regs
.rv770
.mpll_dq_func_cntl_2
;
933 pi
->clk_regs
.rv770
.cg_spll_func_cntl
;
934 u32 spll_func_cntl_2
=
935 pi
->clk_regs
.rv770
.cg_spll_func_cntl_2
;
936 u32 spll_func_cntl_3
=
937 pi
->clk_regs
.rv770
.cg_spll_func_cntl_3
;
938 u32 mclk_pwrmgt_cntl
;
941 table
->ACPIState
= table
->initialState
;
943 table
->ACPIState
.flags
&= ~PPSMC_SWSTATE_FLAG_DC
;
946 rv770_populate_vddc_value(rdev
, pi
->acpi_vddc
,
947 &table
->ACPIState
.levels
[0].vddc
);
949 if (pi
->acpi_pcie_gen2
)
950 table
->ACPIState
.levels
[0].gen2PCIE
= 1;
952 table
->ACPIState
.levels
[0].gen2PCIE
= 0;
954 table
->ACPIState
.levels
[0].gen2PCIE
= 0;
955 if (pi
->acpi_pcie_gen2
)
956 table
->ACPIState
.levels
[0].gen2XSP
= 1;
958 table
->ACPIState
.levels
[0].gen2XSP
= 0;
960 rv770_populate_vddc_value(rdev
, pi
->min_vddc_in_table
,
961 &table
->ACPIState
.levels
[0].vddc
);
962 table
->ACPIState
.levels
[0].gen2PCIE
= 0;
966 mpll_ad_func_cntl_2
|= BIAS_GEN_PDNB
| RESET_EN
;
968 mpll_dq_func_cntl_2
|= BIAS_GEN_PDNB
| RESET_EN
;
970 mclk_pwrmgt_cntl
= (MRDCKA0_RESET
|
979 dll_cntl
= 0xff000000;
981 spll_func_cntl
|= SPLL_RESET
| SPLL_SLEEP
| SPLL_BYPASS_EN
;
983 spll_func_cntl_2
&= ~SCLK_MUX_SEL_MASK
;
984 spll_func_cntl_2
|= SCLK_MUX_SEL(4);
986 table
->ACPIState
.levels
[0].mclk
.mclk770
.vMPLL_AD_FUNC_CNTL
= cpu_to_be32(mpll_ad_func_cntl
);
987 table
->ACPIState
.levels
[0].mclk
.mclk770
.vMPLL_AD_FUNC_CNTL_2
= cpu_to_be32(mpll_ad_func_cntl_2
);
988 table
->ACPIState
.levels
[0].mclk
.mclk770
.vMPLL_DQ_FUNC_CNTL
= cpu_to_be32(mpll_dq_func_cntl
);
989 table
->ACPIState
.levels
[0].mclk
.mclk770
.vMPLL_DQ_FUNC_CNTL_2
= cpu_to_be32(mpll_dq_func_cntl_2
);
991 table
->ACPIState
.levels
[0].mclk
.mclk770
.vMCLK_PWRMGT_CNTL
= cpu_to_be32(mclk_pwrmgt_cntl
);
992 table
->ACPIState
.levels
[0].mclk
.mclk770
.vDLL_CNTL
= cpu_to_be32(dll_cntl
);
994 table
->ACPIState
.levels
[0].mclk
.mclk770
.mclk_value
= 0;
996 table
->ACPIState
.levels
[0].sclk
.vCG_SPLL_FUNC_CNTL
= cpu_to_be32(spll_func_cntl
);
997 table
->ACPIState
.levels
[0].sclk
.vCG_SPLL_FUNC_CNTL_2
= cpu_to_be32(spll_func_cntl_2
);
998 table
->ACPIState
.levels
[0].sclk
.vCG_SPLL_FUNC_CNTL_3
= cpu_to_be32(spll_func_cntl_3
);
1000 table
->ACPIState
.levels
[0].sclk
.sclk_value
= 0;
1002 rv770_populate_mvdd_value(rdev
, 0, &table
->ACPIState
.levels
[0].mvdd
);
1004 table
->ACPIState
.levels
[1] = table
->ACPIState
.levels
[0];
1005 table
->ACPIState
.levels
[2] = table
->ACPIState
.levels
[0];
1010 int rv770_populate_initial_mvdd_value(struct radeon_device
*rdev
,
1011 RV770_SMC_VOLTAGE_VALUE
*voltage
)
1013 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
1015 if ((pi
->s0_vid_lower_smio_cntl
& pi
->mvdd_mask_low
) ==
1016 (pi
->mvdd_low_smio
[MVDD_LOW_INDEX
] & pi
->mvdd_mask_low
) ) {
1017 voltage
->index
= MVDD_LOW_INDEX
;
1018 voltage
->value
= cpu_to_be16(MVDD_LOW_VALUE
);
1020 voltage
->index
= MVDD_HIGH_INDEX
;
1021 voltage
->value
= cpu_to_be16(MVDD_HIGH_VALUE
);
1027 static int rv770_populate_smc_initial_state(struct radeon_device
*rdev
,
1028 struct radeon_ps
*radeon_state
,
1029 RV770_SMC_STATETABLE
*table
)
1031 struct rv7xx_ps
*initial_state
= rv770_get_ps(radeon_state
);
1032 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
1035 table
->initialState
.levels
[0].mclk
.mclk770
.vMPLL_AD_FUNC_CNTL
=
1036 cpu_to_be32(pi
->clk_regs
.rv770
.mpll_ad_func_cntl
);
1037 table
->initialState
.levels
[0].mclk
.mclk770
.vMPLL_AD_FUNC_CNTL_2
=
1038 cpu_to_be32(pi
->clk_regs
.rv770
.mpll_ad_func_cntl_2
);
1039 table
->initialState
.levels
[0].mclk
.mclk770
.vMPLL_DQ_FUNC_CNTL
=
1040 cpu_to_be32(pi
->clk_regs
.rv770
.mpll_dq_func_cntl
);
1041 table
->initialState
.levels
[0].mclk
.mclk770
.vMPLL_DQ_FUNC_CNTL_2
=
1042 cpu_to_be32(pi
->clk_regs
.rv770
.mpll_dq_func_cntl_2
);
1043 table
->initialState
.levels
[0].mclk
.mclk770
.vMCLK_PWRMGT_CNTL
=
1044 cpu_to_be32(pi
->clk_regs
.rv770
.mclk_pwrmgt_cntl
);
1045 table
->initialState
.levels
[0].mclk
.mclk770
.vDLL_CNTL
=
1046 cpu_to_be32(pi
->clk_regs
.rv770
.dll_cntl
);
1048 table
->initialState
.levels
[0].mclk
.mclk770
.vMPLL_SS
=
1049 cpu_to_be32(pi
->clk_regs
.rv770
.mpll_ss1
);
1050 table
->initialState
.levels
[0].mclk
.mclk770
.vMPLL_SS2
=
1051 cpu_to_be32(pi
->clk_regs
.rv770
.mpll_ss2
);
1053 table
->initialState
.levels
[0].mclk
.mclk770
.mclk_value
=
1054 cpu_to_be32(initial_state
->low
.mclk
);
1056 table
->initialState
.levels
[0].sclk
.vCG_SPLL_FUNC_CNTL
=
1057 cpu_to_be32(pi
->clk_regs
.rv770
.cg_spll_func_cntl
);
1058 table
->initialState
.levels
[0].sclk
.vCG_SPLL_FUNC_CNTL_2
=
1059 cpu_to_be32(pi
->clk_regs
.rv770
.cg_spll_func_cntl_2
);
1060 table
->initialState
.levels
[0].sclk
.vCG_SPLL_FUNC_CNTL_3
=
1061 cpu_to_be32(pi
->clk_regs
.rv770
.cg_spll_func_cntl_3
);
1062 table
->initialState
.levels
[0].sclk
.vCG_SPLL_SPREAD_SPECTRUM
=
1063 cpu_to_be32(pi
->clk_regs
.rv770
.cg_spll_spread_spectrum
);
1064 table
->initialState
.levels
[0].sclk
.vCG_SPLL_SPREAD_SPECTRUM_2
=
1065 cpu_to_be32(pi
->clk_regs
.rv770
.cg_spll_spread_spectrum_2
);
1067 table
->initialState
.levels
[0].sclk
.sclk_value
=
1068 cpu_to_be32(initial_state
->low
.sclk
);
1070 table
->initialState
.levels
[0].arbValue
= MC_CG_ARB_FREQ_F0
;
1072 table
->initialState
.levels
[0].seqValue
=
1073 rv770_get_seq_value(rdev
, &initial_state
->low
);
1075 rv770_populate_vddc_value(rdev
,
1076 initial_state
->low
.vddc
,
1077 &table
->initialState
.levels
[0].vddc
);
1078 rv770_populate_initial_mvdd_value(rdev
,
1079 &table
->initialState
.levels
[0].mvdd
);
1081 a_t
= CG_R(0xffff) | CG_L(0);
1082 table
->initialState
.levels
[0].aT
= cpu_to_be32(a_t
);
1084 table
->initialState
.levels
[0].bSP
= cpu_to_be32(pi
->dsp
);
1086 if (pi
->boot_in_gen2
)
1087 table
->initialState
.levels
[0].gen2PCIE
= 1;
1089 table
->initialState
.levels
[0].gen2PCIE
= 0;
1090 if (initial_state
->low
.flags
& ATOM_PPLIB_R600_FLAGS_PCIEGEN2
)
1091 table
->initialState
.levels
[0].gen2XSP
= 1;
1093 table
->initialState
.levels
[0].gen2XSP
= 0;
1095 if (rdev
->family
== CHIP_RV740
) {
1096 if (pi
->mem_gddr5
) {
1097 if (initial_state
->low
.mclk
<= pi
->mclk_strobe_mode_threshold
)
1098 table
->initialState
.levels
[0].strobeMode
=
1099 rv740_get_mclk_frequency_ratio(initial_state
->low
.mclk
) | 0x10;
1101 table
->initialState
.levels
[0].strobeMode
= 0;
1103 if (initial_state
->low
.mclk
>= pi
->mclk_edc_enable_threshold
)
1104 table
->initialState
.levels
[0].mcFlags
= SMC_MC_EDC_RD_FLAG
| SMC_MC_EDC_WR_FLAG
;
1106 table
->initialState
.levels
[0].mcFlags
= 0;
1110 table
->initialState
.levels
[1] = table
->initialState
.levels
[0];
1111 table
->initialState
.levels
[2] = table
->initialState
.levels
[0];
1113 table
->initialState
.flags
|= PPSMC_SWSTATE_FLAG_DC
;
1118 static int rv770_populate_smc_vddc_table(struct radeon_device
*rdev
,
1119 RV770_SMC_STATETABLE
*table
)
1121 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
1124 for (i
= 0; i
< pi
->valid_vddc_entries
; i
++) {
1125 table
->highSMIO
[pi
->vddc_table
[i
].vddc_index
] =
1126 pi
->vddc_table
[i
].high_smio
;
1127 table
->lowSMIO
[pi
->vddc_table
[i
].vddc_index
] =
1128 cpu_to_be32(pi
->vddc_table
[i
].low_smio
);
1131 table
->voltageMaskTable
.highMask
[RV770_SMC_VOLTAGEMASK_VDDC
] = 0;
1132 table
->voltageMaskTable
.lowMask
[RV770_SMC_VOLTAGEMASK_VDDC
] =
1133 cpu_to_be32(pi
->vddc_mask_low
);
1136 ((i
< pi
->valid_vddc_entries
) &&
1137 (pi
->max_vddc_in_table
>
1138 pi
->vddc_table
[i
].vddc
));
1141 table
->maxVDDCIndexInPPTable
=
1142 pi
->vddc_table
[i
].vddc_index
;
1147 static int rv770_populate_smc_mvdd_table(struct radeon_device
*rdev
,
1148 RV770_SMC_STATETABLE
*table
)
1150 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
1152 if (pi
->mvdd_control
) {
1153 table
->lowSMIO
[MVDD_HIGH_INDEX
] |=
1154 cpu_to_be32(pi
->mvdd_low_smio
[MVDD_HIGH_INDEX
]);
1155 table
->lowSMIO
[MVDD_LOW_INDEX
] |=
1156 cpu_to_be32(pi
->mvdd_low_smio
[MVDD_LOW_INDEX
]);
1158 table
->voltageMaskTable
.highMask
[RV770_SMC_VOLTAGEMASK_MVDD
] = 0;
1159 table
->voltageMaskTable
.lowMask
[RV770_SMC_VOLTAGEMASK_MVDD
] =
1160 cpu_to_be32(pi
->mvdd_mask_low
);
1166 static int rv770_init_smc_table(struct radeon_device
*rdev
,
1167 struct radeon_ps
*radeon_boot_state
)
1169 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
1170 struct rv7xx_ps
*boot_state
= rv770_get_ps(radeon_boot_state
);
1171 RV770_SMC_STATETABLE
*table
= &pi
->smc_statetable
;
1174 memset(table
, 0, sizeof(RV770_SMC_STATETABLE
));
1176 pi
->boot_sclk
= boot_state
->low
.sclk
;
1178 rv770_populate_smc_vddc_table(rdev
, table
);
1179 rv770_populate_smc_mvdd_table(rdev
, table
);
1181 switch (rdev
->pm
.int_thermal_type
) {
1182 case THERMAL_TYPE_RV770
:
1183 case THERMAL_TYPE_ADT7473_WITH_INTERNAL
:
1184 table
->thermalProtectType
= PPSMC_THERMAL_PROTECT_TYPE_INTERNAL
;
1186 case THERMAL_TYPE_NONE
:
1187 table
->thermalProtectType
= PPSMC_THERMAL_PROTECT_TYPE_NONE
;
1189 case THERMAL_TYPE_EXTERNAL_GPIO
:
1191 table
->thermalProtectType
= PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL
;
1195 if (rdev
->pm
.dpm
.platform_caps
& ATOM_PP_PLATFORM_CAP_HARDWAREDC
) {
1196 table
->systemFlags
|= PPSMC_SYSTEMFLAG_GPIO_DC
;
1198 if (rdev
->pm
.dpm
.platform_caps
& ATOM_PP_PLATFORM_CAP_DONT_WAIT_FOR_VBLANK_ON_ALERT
)
1199 table
->extraFlags
|= PPSMC_EXTRAFLAGS_AC2DC_DONT_WAIT_FOR_VBLANK
;
1201 if (rdev
->pm
.dpm
.platform_caps
& ATOM_PP_PLATFORM_CAP_GOTO_BOOT_ON_ALERT
)
1202 table
->extraFlags
|= PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTOINITIALSTATE
;
1205 if (rdev
->pm
.dpm
.platform_caps
& ATOM_PP_PLATFORM_CAP_STEPVDDC
)
1206 table
->systemFlags
|= PPSMC_SYSTEMFLAG_STEPVDDC
;
1209 table
->systemFlags
|= PPSMC_SYSTEMFLAG_GDDR5
;
1211 if ((rdev
->family
== CHIP_RV730
) || (rdev
->family
== CHIP_RV710
))
1212 ret
= rv730_populate_smc_initial_state(rdev
, radeon_boot_state
, table
);
1214 ret
= rv770_populate_smc_initial_state(rdev
, radeon_boot_state
, table
);
1218 if (rdev
->family
== CHIP_RV740
)
1219 ret
= rv740_populate_smc_acpi_state(rdev
, table
);
1220 else if ((rdev
->family
== CHIP_RV730
) || (rdev
->family
== CHIP_RV710
))
1221 ret
= rv730_populate_smc_acpi_state(rdev
, table
);
1223 ret
= rv770_populate_smc_acpi_state(rdev
, table
);
1227 table
->driverState
= table
->initialState
;
1229 return rv770_copy_bytes_to_smc(rdev
,
1230 pi
->state_table_start
,
1232 sizeof(RV770_SMC_STATETABLE
),
1236 static int rv770_construct_vddc_table(struct radeon_device
*rdev
)
1238 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
1244 radeon_atom_get_min_voltage(rdev
, SET_VOLTAGE_TYPE_ASIC_VDDC
, &min
);
1245 radeon_atom_get_max_voltage(rdev
, SET_VOLTAGE_TYPE_ASIC_VDDC
, &max
);
1246 radeon_atom_get_voltage_step(rdev
, SET_VOLTAGE_TYPE_ASIC_VDDC
, &step
);
1248 steps
= (max
- min
) / step
+ 1;
1250 if (steps
> MAX_NO_VREG_STEPS
)
1253 for (i
= 0; i
< steps
; i
++) {
1254 u32 gpio_pins
, gpio_mask
;
1256 pi
->vddc_table
[i
].vddc
= (u16
)(min
+ i
* step
);
1257 radeon_atom_get_voltage_gpio_settings(rdev
,
1258 pi
->vddc_table
[i
].vddc
,
1259 SET_VOLTAGE_TYPE_ASIC_VDDC
,
1260 &gpio_pins
, &gpio_mask
);
1261 pi
->vddc_table
[i
].low_smio
= gpio_pins
& gpio_mask
;
1262 pi
->vddc_table
[i
].high_smio
= 0;
1263 pi
->vddc_mask_low
= gpio_mask
;
1265 if ((pi
->vddc_table
[i
].low_smio
!=
1266 pi
->vddc_table
[i
- 1].low_smio
) ||
1267 (pi
->vddc_table
[i
].high_smio
!=
1268 pi
->vddc_table
[i
- 1].high_smio
))
1271 pi
->vddc_table
[i
].vddc_index
= vddc_index
;
1274 pi
->valid_vddc_entries
= (u8
)steps
;
1279 static u32
rv770_get_mclk_split_point(struct atom_memory_info
*memory_info
)
1281 if (memory_info
->mem_type
== MEM_TYPE_GDDR3
)
1287 static int rv770_get_mvdd_pin_configuration(struct radeon_device
*rdev
)
1289 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
1290 u32 gpio_pins
, gpio_mask
;
1292 radeon_atom_get_voltage_gpio_settings(rdev
,
1293 MVDD_HIGH_VALUE
, SET_VOLTAGE_TYPE_ASIC_MVDDC
,
1294 &gpio_pins
, &gpio_mask
);
1295 pi
->mvdd_mask_low
= gpio_mask
;
1296 pi
->mvdd_low_smio
[MVDD_HIGH_INDEX
] =
1297 gpio_pins
& gpio_mask
;
1299 radeon_atom_get_voltage_gpio_settings(rdev
,
1300 MVDD_LOW_VALUE
, SET_VOLTAGE_TYPE_ASIC_MVDDC
,
1301 &gpio_pins
, &gpio_mask
);
1302 pi
->mvdd_low_smio
[MVDD_LOW_INDEX
] =
1303 gpio_pins
& gpio_mask
;
1308 u8
rv770_get_memory_module_index(struct radeon_device
*rdev
)
1310 return (u8
) ((RREG32(BIOS_SCRATCH_4
) >> 16) & 0xff);
1313 static int rv770_get_mvdd_configuration(struct radeon_device
*rdev
)
1315 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
1316 u8 memory_module_index
;
1317 struct atom_memory_info memory_info
;
1319 memory_module_index
= rv770_get_memory_module_index(rdev
);
1321 if (radeon_atom_get_memory_info(rdev
, memory_module_index
, &memory_info
)) {
1322 pi
->mvdd_control
= false;
1326 pi
->mvdd_split_frequency
=
1327 rv770_get_mclk_split_point(&memory_info
);
1329 if (pi
->mvdd_split_frequency
== 0) {
1330 pi
->mvdd_control
= false;
1334 return rv770_get_mvdd_pin_configuration(rdev
);
1337 void rv770_enable_voltage_control(struct radeon_device
*rdev
,
1341 WREG32_P(GENERAL_PWRMGT
, VOLT_PWRMGT_EN
, ~VOLT_PWRMGT_EN
);
1343 WREG32_P(GENERAL_PWRMGT
, 0, ~VOLT_PWRMGT_EN
);
1346 static void rv770_program_display_gap(struct radeon_device
*rdev
)
1348 u32 tmp
= RREG32(CG_DISPLAY_GAP_CNTL
);
1350 tmp
&= ~(DISP1_GAP_MCHG_MASK
| DISP2_GAP_MCHG_MASK
);
1351 if (rdev
->pm
.dpm
.new_active_crtcs
& 1) {
1352 tmp
|= DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK
);
1353 tmp
|= DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE
);
1354 } else if (rdev
->pm
.dpm
.new_active_crtcs
& 2) {
1355 tmp
|= DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE
);
1356 tmp
|= DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK
);
1358 tmp
|= DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE
);
1359 tmp
|= DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE
);
1361 WREG32(CG_DISPLAY_GAP_CNTL
, tmp
);
1364 static void rv770_enable_dynamic_pcie_gen2(struct radeon_device
*rdev
,
1367 rv770_enable_bif_dynamic_pcie_gen2(rdev
, enable
);
1370 WREG32_P(GENERAL_PWRMGT
, ENABLE_GEN2PCIE
, ~ENABLE_GEN2PCIE
);
1372 WREG32_P(GENERAL_PWRMGT
, 0, ~ENABLE_GEN2PCIE
);
1375 static void r7xx_program_memory_timing_parameters(struct radeon_device
*rdev
,
1376 struct radeon_ps
*radeon_new_state
)
1378 if ((rdev
->family
== CHIP_RV730
) ||
1379 (rdev
->family
== CHIP_RV710
) ||
1380 (rdev
->family
== CHIP_RV740
))
1381 rv730_program_memory_timing_parameters(rdev
, radeon_new_state
);
1383 rv770_program_memory_timing_parameters(rdev
, radeon_new_state
);
1386 static int rv770_upload_sw_state(struct radeon_device
*rdev
,
1387 struct radeon_ps
*radeon_new_state
)
1389 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
1390 u16 address
= pi
->state_table_start
+
1391 offsetof(RV770_SMC_STATETABLE
, driverState
);
1392 RV770_SMC_SWSTATE state
= { 0 };
1395 ret
= rv770_convert_power_state_to_smc(rdev
, radeon_new_state
, &state
);
1399 return rv770_copy_bytes_to_smc(rdev
, address
, (const u8
*)&state
,
1400 sizeof(RV770_SMC_SWSTATE
),
1404 int rv770_halt_smc(struct radeon_device
*rdev
)
1406 if (rv770_send_msg_to_smc(rdev
, PPSMC_MSG_Halt
) != PPSMC_Result_OK
)
1409 if (rv770_wait_for_smc_inactive(rdev
) != PPSMC_Result_OK
)
1415 int rv770_resume_smc(struct radeon_device
*rdev
)
1417 if (rv770_send_msg_to_smc(rdev
, PPSMC_MSG_Resume
) != PPSMC_Result_OK
)
1422 int rv770_set_sw_state(struct radeon_device
*rdev
)
1424 if (rv770_send_msg_to_smc(rdev
, PPSMC_MSG_SwitchToSwState
) != PPSMC_Result_OK
)
1429 int rv770_set_boot_state(struct radeon_device
*rdev
)
1431 if (rv770_send_msg_to_smc(rdev
, PPSMC_MSG_SwitchToInitialState
) != PPSMC_Result_OK
)
1436 void rv770_set_uvd_clock_before_set_eng_clock(struct radeon_device
*rdev
,
1437 struct radeon_ps
*new_ps
,
1438 struct radeon_ps
*old_ps
)
1440 struct rv7xx_ps
*new_state
= rv770_get_ps(new_ps
);
1441 struct rv7xx_ps
*current_state
= rv770_get_ps(old_ps
);
1443 if ((new_ps
->vclk
== old_ps
->vclk
) &&
1444 (new_ps
->dclk
== old_ps
->dclk
))
1447 if (new_state
->high
.sclk
>= current_state
->high
.sclk
)
1450 radeon_set_uvd_clocks(rdev
, new_ps
->vclk
, new_ps
->dclk
);
1453 void rv770_set_uvd_clock_after_set_eng_clock(struct radeon_device
*rdev
,
1454 struct radeon_ps
*new_ps
,
1455 struct radeon_ps
*old_ps
)
1457 struct rv7xx_ps
*new_state
= rv770_get_ps(new_ps
);
1458 struct rv7xx_ps
*current_state
= rv770_get_ps(old_ps
);
1460 if ((new_ps
->vclk
== old_ps
->vclk
) &&
1461 (new_ps
->dclk
== old_ps
->dclk
))
1464 if (new_state
->high
.sclk
< current_state
->high
.sclk
)
1467 radeon_set_uvd_clocks(rdev
, new_ps
->vclk
, new_ps
->dclk
);
1470 int rv770_restrict_performance_levels_before_switch(struct radeon_device
*rdev
)
1472 if (rv770_send_msg_to_smc(rdev
, (PPSMC_Msg
)(PPSMC_MSG_NoForcedLevel
)) != PPSMC_Result_OK
)
1475 if (rv770_send_msg_to_smc(rdev
, (PPSMC_Msg
)(PPSMC_MSG_TwoLevelsDisabled
)) != PPSMC_Result_OK
)
1481 int rv770_dpm_force_performance_level(struct radeon_device
*rdev
,
1482 enum radeon_dpm_forced_level level
)
1486 if (level
== RADEON_DPM_FORCED_LEVEL_HIGH
) {
1487 if (rv770_send_msg_to_smc(rdev
, PPSMC_MSG_ZeroLevelsDisabled
) != PPSMC_Result_OK
)
1489 msg
= PPSMC_MSG_ForceHigh
;
1490 } else if (level
== RADEON_DPM_FORCED_LEVEL_LOW
) {
1491 if (rv770_send_msg_to_smc(rdev
, PPSMC_MSG_NoForcedLevel
) != PPSMC_Result_OK
)
1493 msg
= (PPSMC_Msg
)(PPSMC_MSG_TwoLevelsDisabled
);
1495 if (rv770_send_msg_to_smc(rdev
, PPSMC_MSG_NoForcedLevel
) != PPSMC_Result_OK
)
1497 msg
= (PPSMC_Msg
)(PPSMC_MSG_ZeroLevelsDisabled
);
1500 if (rv770_send_msg_to_smc(rdev
, msg
) != PPSMC_Result_OK
)
1503 rdev
->pm
.dpm
.forced_level
= level
;
1508 void r7xx_start_smc(struct radeon_device
*rdev
)
1510 rv770_start_smc(rdev
);
1511 rv770_start_smc_clock(rdev
);
1515 void r7xx_stop_smc(struct radeon_device
*rdev
)
1517 rv770_reset_smc(rdev
);
1518 rv770_stop_smc_clock(rdev
);
1521 static void rv770_read_clock_registers(struct radeon_device
*rdev
)
1523 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
1525 pi
->clk_regs
.rv770
.cg_spll_func_cntl
=
1526 RREG32(CG_SPLL_FUNC_CNTL
);
1527 pi
->clk_regs
.rv770
.cg_spll_func_cntl_2
=
1528 RREG32(CG_SPLL_FUNC_CNTL_2
);
1529 pi
->clk_regs
.rv770
.cg_spll_func_cntl_3
=
1530 RREG32(CG_SPLL_FUNC_CNTL_3
);
1531 pi
->clk_regs
.rv770
.cg_spll_spread_spectrum
=
1532 RREG32(CG_SPLL_SPREAD_SPECTRUM
);
1533 pi
->clk_regs
.rv770
.cg_spll_spread_spectrum_2
=
1534 RREG32(CG_SPLL_SPREAD_SPECTRUM_2
);
1535 pi
->clk_regs
.rv770
.mpll_ad_func_cntl
=
1536 RREG32(MPLL_AD_FUNC_CNTL
);
1537 pi
->clk_regs
.rv770
.mpll_ad_func_cntl_2
=
1538 RREG32(MPLL_AD_FUNC_CNTL_2
);
1539 pi
->clk_regs
.rv770
.mpll_dq_func_cntl
=
1540 RREG32(MPLL_DQ_FUNC_CNTL
);
1541 pi
->clk_regs
.rv770
.mpll_dq_func_cntl_2
=
1542 RREG32(MPLL_DQ_FUNC_CNTL_2
);
1543 pi
->clk_regs
.rv770
.mclk_pwrmgt_cntl
=
1544 RREG32(MCLK_PWRMGT_CNTL
);
1545 pi
->clk_regs
.rv770
.dll_cntl
= RREG32(DLL_CNTL
);
1548 static void r7xx_read_clock_registers(struct radeon_device
*rdev
)
1550 if (rdev
->family
== CHIP_RV740
)
1551 rv740_read_clock_registers(rdev
);
1552 else if ((rdev
->family
== CHIP_RV730
) || (rdev
->family
== CHIP_RV710
))
1553 rv730_read_clock_registers(rdev
);
1555 rv770_read_clock_registers(rdev
);
1558 void rv770_read_voltage_smio_registers(struct radeon_device
*rdev
)
1560 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
1562 pi
->s0_vid_lower_smio_cntl
=
1563 RREG32(S0_VID_LOWER_SMIO_CNTL
);
1566 void rv770_reset_smio_status(struct radeon_device
*rdev
)
1568 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
1569 u32 sw_smio_index
, vid_smio_cntl
;
1572 (RREG32(GENERAL_PWRMGT
) & SW_SMIO_INDEX_MASK
) >> SW_SMIO_INDEX_SHIFT
;
1573 switch (sw_smio_index
) {
1575 vid_smio_cntl
= RREG32(S3_VID_LOWER_SMIO_CNTL
);
1578 vid_smio_cntl
= RREG32(S2_VID_LOWER_SMIO_CNTL
);
1581 vid_smio_cntl
= RREG32(S1_VID_LOWER_SMIO_CNTL
);
1586 vid_smio_cntl
= pi
->s0_vid_lower_smio_cntl
;
1590 WREG32(S0_VID_LOWER_SMIO_CNTL
, vid_smio_cntl
);
1591 WREG32_P(GENERAL_PWRMGT
, SW_SMIO_INDEX(0), ~SW_SMIO_INDEX_MASK
);
1594 void rv770_get_memory_type(struct radeon_device
*rdev
)
1596 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
1599 tmp
= RREG32(MC_SEQ_MISC0
);
1601 if (((tmp
& MC_SEQ_MISC0_GDDR5_MASK
) >> MC_SEQ_MISC0_GDDR5_SHIFT
) ==
1602 MC_SEQ_MISC0_GDDR5_VALUE
)
1603 pi
->mem_gddr5
= true;
1605 pi
->mem_gddr5
= false;
1609 void rv770_get_pcie_gen2_status(struct radeon_device
*rdev
)
1611 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
1614 tmp
= RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL
);
1616 if ((tmp
& LC_OTHER_SIDE_EVER_SENT_GEN2
) &&
1617 (tmp
& LC_OTHER_SIDE_SUPPORTS_GEN2
))
1618 pi
->pcie_gen2
= true;
1620 pi
->pcie_gen2
= false;
1622 if (pi
->pcie_gen2
) {
1623 if (tmp
& LC_CURRENT_DATA_RATE
)
1624 pi
->boot_in_gen2
= true;
1626 pi
->boot_in_gen2
= false;
1628 pi
->boot_in_gen2
= false;
1632 static int rv770_enter_ulp_state(struct radeon_device
*rdev
)
1634 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
1636 if (pi
->gfx_clock_gating
) {
1637 WREG32_P(SCLK_PWRMGT_CNTL
, 0, ~DYN_GFX_CLK_OFF_EN
);
1638 WREG32_P(SCLK_PWRMGT_CNTL
, GFX_CLK_FORCE_ON
, ~GFX_CLK_FORCE_ON
);
1639 WREG32_P(SCLK_PWRMGT_CNTL
, 0, ~GFX_CLK_FORCE_ON
);
1640 RREG32(GB_TILING_CONFIG
);
1643 WREG32_P(SMC_MSG
, HOST_SMC_MSG(PPSMC_MSG_SwitchToMinimumPower
),
1644 ~HOST_SMC_MSG_MASK
);
1651 static int rv770_exit_ulp_state(struct radeon_device
*rdev
)
1653 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
1656 WREG32_P(SMC_MSG
, HOST_SMC_MSG(PPSMC_MSG_ResumeFromMinimumPower
),
1657 ~HOST_SMC_MSG_MASK
);
1661 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
1662 if (((RREG32(SMC_MSG
) & HOST_SMC_RESP_MASK
) >> HOST_SMC_RESP_SHIFT
) == 1)
1667 if (pi
->gfx_clock_gating
)
1668 WREG32_P(SCLK_PWRMGT_CNTL
, DYN_GFX_CLK_OFF_EN
, ~DYN_GFX_CLK_OFF_EN
);
1674 static void rv770_get_mclk_odt_threshold(struct radeon_device
*rdev
)
1676 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
1677 u8 memory_module_index
;
1678 struct atom_memory_info memory_info
;
1680 pi
->mclk_odt_threshold
= 0;
1682 if ((rdev
->family
== CHIP_RV730
) || (rdev
->family
== CHIP_RV710
)) {
1683 memory_module_index
= rv770_get_memory_module_index(rdev
);
1685 if (radeon_atom_get_memory_info(rdev
, memory_module_index
, &memory_info
))
1688 if (memory_info
.mem_type
== MEM_TYPE_DDR2
||
1689 memory_info
.mem_type
== MEM_TYPE_DDR3
)
1690 pi
->mclk_odt_threshold
= 30000;
1694 void rv770_get_max_vddc(struct radeon_device
*rdev
)
1696 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
1699 if (radeon_atom_get_max_vddc(rdev
, 0, 0, &vddc
))
1702 pi
->max_vddc
= vddc
;
1705 void rv770_program_response_times(struct radeon_device
*rdev
)
1707 u32 voltage_response_time
, backbias_response_time
;
1708 u32 acpi_delay_time
, vbi_time_out
;
1709 u32 vddc_dly
, bb_dly
, acpi_dly
, vbi_dly
;
1710 u32 reference_clock
;
1712 voltage_response_time
= (u32
)rdev
->pm
.dpm
.voltage_response_time
;
1713 backbias_response_time
= (u32
)rdev
->pm
.dpm
.backbias_response_time
;
1715 if (voltage_response_time
== 0)
1716 voltage_response_time
= 1000;
1718 if (backbias_response_time
== 0)
1719 backbias_response_time
= 1000;
1721 acpi_delay_time
= 15000;
1722 vbi_time_out
= 100000;
1724 reference_clock
= radeon_get_xclk(rdev
);
1726 vddc_dly
= (voltage_response_time
* reference_clock
) / 1600;
1727 bb_dly
= (backbias_response_time
* reference_clock
) / 1600;
1728 acpi_dly
= (acpi_delay_time
* reference_clock
) / 1600;
1729 vbi_dly
= (vbi_time_out
* reference_clock
) / 1600;
1731 rv770_write_smc_soft_register(rdev
,
1732 RV770_SMC_SOFT_REGISTER_delay_vreg
, vddc_dly
);
1733 rv770_write_smc_soft_register(rdev
,
1734 RV770_SMC_SOFT_REGISTER_delay_bbias
, bb_dly
);
1735 rv770_write_smc_soft_register(rdev
,
1736 RV770_SMC_SOFT_REGISTER_delay_acpi
, acpi_dly
);
1737 rv770_write_smc_soft_register(rdev
,
1738 RV770_SMC_SOFT_REGISTER_mclk_chg_timeout
, vbi_dly
);
1740 /* XXX look up hw revision */
1742 rv770_write_smc_soft_register(rdev
,
1743 RV770_SMC_SOFT_REGISTER_baby_step_timer
,
1748 static void rv770_program_dcodt_before_state_switch(struct radeon_device
*rdev
,
1749 struct radeon_ps
*radeon_new_state
,
1750 struct radeon_ps
*radeon_current_state
)
1752 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
1753 struct rv7xx_ps
*new_state
= rv770_get_ps(radeon_new_state
);
1754 struct rv7xx_ps
*current_state
= rv770_get_ps(radeon_current_state
);
1755 bool current_use_dc
= false;
1756 bool new_use_dc
= false;
1758 if (pi
->mclk_odt_threshold
== 0)
1761 if (current_state
->high
.mclk
<= pi
->mclk_odt_threshold
)
1762 current_use_dc
= true;
1764 if (new_state
->high
.mclk
<= pi
->mclk_odt_threshold
)
1767 if (current_use_dc
== new_use_dc
)
1770 if (!current_use_dc
&& new_use_dc
)
1773 if ((rdev
->family
== CHIP_RV730
) || (rdev
->family
== CHIP_RV710
))
1774 rv730_program_dcodt(rdev
, new_use_dc
);
1777 static void rv770_program_dcodt_after_state_switch(struct radeon_device
*rdev
,
1778 struct radeon_ps
*radeon_new_state
,
1779 struct radeon_ps
*radeon_current_state
)
1781 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
1782 struct rv7xx_ps
*new_state
= rv770_get_ps(radeon_new_state
);
1783 struct rv7xx_ps
*current_state
= rv770_get_ps(radeon_current_state
);
1784 bool current_use_dc
= false;
1785 bool new_use_dc
= false;
1787 if (pi
->mclk_odt_threshold
== 0)
1790 if (current_state
->high
.mclk
<= pi
->mclk_odt_threshold
)
1791 current_use_dc
= true;
1793 if (new_state
->high
.mclk
<= pi
->mclk_odt_threshold
)
1796 if (current_use_dc
== new_use_dc
)
1799 if (current_use_dc
&& !new_use_dc
)
1802 if ((rdev
->family
== CHIP_RV730
) || (rdev
->family
== CHIP_RV710
))
1803 rv730_program_dcodt(rdev
, new_use_dc
);
1806 static void rv770_retrieve_odt_values(struct radeon_device
*rdev
)
1808 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
1810 if (pi
->mclk_odt_threshold
== 0)
1813 if ((rdev
->family
== CHIP_RV730
) || (rdev
->family
== CHIP_RV710
))
1814 rv730_get_odt_values(rdev
);
1817 static void rv770_set_dpm_event_sources(struct radeon_device
*rdev
, u32 sources
)
1819 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
1820 bool want_thermal_protection
;
1821 enum radeon_dpm_event_src dpm_event_src
;
1826 want_thermal_protection
= false;
1828 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL
):
1829 want_thermal_protection
= true;
1830 dpm_event_src
= RADEON_DPM_EVENT_SRC_DIGITAL
;
1833 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
):
1834 want_thermal_protection
= true;
1835 dpm_event_src
= RADEON_DPM_EVENT_SRC_EXTERNAL
;
1838 case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
) |
1839 (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL
)):
1840 want_thermal_protection
= true;
1841 dpm_event_src
= RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL
;
1845 if (want_thermal_protection
) {
1846 WREG32_P(CG_THERMAL_CTRL
, DPM_EVENT_SRC(dpm_event_src
), ~DPM_EVENT_SRC_MASK
);
1847 if (pi
->thermal_protection
)
1848 WREG32_P(GENERAL_PWRMGT
, 0, ~THERMAL_PROTECTION_DIS
);
1850 WREG32_P(GENERAL_PWRMGT
, THERMAL_PROTECTION_DIS
, ~THERMAL_PROTECTION_DIS
);
1854 void rv770_enable_auto_throttle_source(struct radeon_device
*rdev
,
1855 enum radeon_dpm_auto_throttle_src source
,
1858 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
1861 if (!(pi
->active_auto_throttle_sources
& (1 << source
))) {
1862 pi
->active_auto_throttle_sources
|= 1 << source
;
1863 rv770_set_dpm_event_sources(rdev
, pi
->active_auto_throttle_sources
);
1866 if (pi
->active_auto_throttle_sources
& (1 << source
)) {
1867 pi
->active_auto_throttle_sources
&= ~(1 << source
);
1868 rv770_set_dpm_event_sources(rdev
, pi
->active_auto_throttle_sources
);
1873 static int rv770_set_thermal_temperature_range(struct radeon_device
*rdev
,
1874 int min_temp
, int max_temp
)
1876 int low_temp
= 0 * 1000;
1877 int high_temp
= 255 * 1000;
1879 if (low_temp
< min_temp
)
1880 low_temp
= min_temp
;
1881 if (high_temp
> max_temp
)
1882 high_temp
= max_temp
;
1883 if (high_temp
< low_temp
) {
1884 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp
, high_temp
);
1888 WREG32_P(CG_THERMAL_INT
, DIG_THERM_INTH(high_temp
/ 1000), ~DIG_THERM_INTH_MASK
);
1889 WREG32_P(CG_THERMAL_INT
, DIG_THERM_INTL(low_temp
/ 1000), ~DIG_THERM_INTL_MASK
);
1890 WREG32_P(CG_THERMAL_CTRL
, DIG_THERM_DPM(high_temp
/ 1000), ~DIG_THERM_DPM_MASK
);
1892 rdev
->pm
.dpm
.thermal
.min_temp
= low_temp
;
1893 rdev
->pm
.dpm
.thermal
.max_temp
= high_temp
;
1898 int rv770_dpm_enable(struct radeon_device
*rdev
)
1900 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
1901 struct radeon_ps
*boot_ps
= rdev
->pm
.dpm
.boot_ps
;
1904 if (pi
->gfx_clock_gating
)
1905 rv770_restore_cgcg(rdev
);
1907 if (rv770_dpm_enabled(rdev
))
1910 if (pi
->voltage_control
) {
1911 rv770_enable_voltage_control(rdev
, true);
1912 ret
= rv770_construct_vddc_table(rdev
);
1914 DRM_ERROR("rv770_construct_vddc_table failed\n");
1920 rv770_retrieve_odt_values(rdev
);
1922 if (pi
->mvdd_control
) {
1923 ret
= rv770_get_mvdd_configuration(rdev
);
1925 DRM_ERROR("rv770_get_mvdd_configuration failed\n");
1930 if (rdev
->pm
.dpm
.platform_caps
& ATOM_PP_PLATFORM_CAP_BACKBIAS
)
1931 rv770_enable_backbias(rdev
, true);
1933 rv770_enable_spread_spectrum(rdev
, true);
1935 if (pi
->thermal_protection
)
1936 rv770_enable_thermal_protection(rdev
, true);
1938 rv770_program_mpll_timing_parameters(rdev
);
1939 rv770_setup_bsp(rdev
);
1940 rv770_program_git(rdev
);
1941 rv770_program_tp(rdev
);
1942 rv770_program_tpp(rdev
);
1943 rv770_program_sstp(rdev
);
1944 rv770_program_engine_speed_parameters(rdev
);
1945 rv770_enable_display_gap(rdev
);
1946 rv770_program_vc(rdev
);
1948 if (pi
->dynamic_pcie_gen2
)
1949 rv770_enable_dynamic_pcie_gen2(rdev
, true);
1951 ret
= rv770_upload_firmware(rdev
);
1953 DRM_ERROR("rv770_upload_firmware failed\n");
1956 ret
= rv770_init_smc_table(rdev
, boot_ps
);
1958 DRM_ERROR("rv770_init_smc_table failed\n");
1962 rv770_program_response_times(rdev
);
1963 r7xx_start_smc(rdev
);
1965 if ((rdev
->family
== CHIP_RV730
) || (rdev
->family
== CHIP_RV710
))
1966 rv730_start_dpm(rdev
);
1968 rv770_start_dpm(rdev
);
1970 if (pi
->gfx_clock_gating
)
1971 rv770_gfx_clock_gating_enable(rdev
, true);
1973 if (pi
->mg_clock_gating
)
1974 rv770_mg_clock_gating_enable(rdev
, true);
1976 rv770_enable_auto_throttle_source(rdev
, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL
, true);
1981 int rv770_dpm_late_enable(struct radeon_device
*rdev
)
1985 if (rdev
->irq
.installed
&&
1986 r600_is_internal_thermal_sensor(rdev
->pm
.int_thermal_type
)) {
1987 PPSMC_Result result
;
1989 ret
= rv770_set_thermal_temperature_range(rdev
, R600_TEMP_RANGE_MIN
, R600_TEMP_RANGE_MAX
);
1992 rdev
->irq
.dpm_thermal
= true;
1993 radeon_irq_set(rdev
);
1994 result
= rv770_send_msg_to_smc(rdev
, PPSMC_MSG_EnableThermalInterrupt
);
1996 if (result
!= PPSMC_Result_OK
)
1997 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
2003 void rv770_dpm_disable(struct radeon_device
*rdev
)
2005 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
2007 if (!rv770_dpm_enabled(rdev
))
2010 rv770_clear_vc(rdev
);
2012 if (pi
->thermal_protection
)
2013 rv770_enable_thermal_protection(rdev
, false);
2015 rv770_enable_spread_spectrum(rdev
, false);
2017 if (pi
->dynamic_pcie_gen2
)
2018 rv770_enable_dynamic_pcie_gen2(rdev
, false);
2020 if (rdev
->irq
.installed
&&
2021 r600_is_internal_thermal_sensor(rdev
->pm
.int_thermal_type
)) {
2022 rdev
->irq
.dpm_thermal
= false;
2023 radeon_irq_set(rdev
);
2026 if (pi
->gfx_clock_gating
)
2027 rv770_gfx_clock_gating_enable(rdev
, false);
2029 if (pi
->mg_clock_gating
)
2030 rv770_mg_clock_gating_enable(rdev
, false);
2032 if ((rdev
->family
== CHIP_RV730
) || (rdev
->family
== CHIP_RV710
))
2033 rv730_stop_dpm(rdev
);
2035 rv770_stop_dpm(rdev
);
2037 r7xx_stop_smc(rdev
);
2038 rv770_reset_smio_status(rdev
);
2041 int rv770_dpm_set_power_state(struct radeon_device
*rdev
)
2043 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
2044 struct radeon_ps
*new_ps
= rdev
->pm
.dpm
.requested_ps
;
2045 struct radeon_ps
*old_ps
= rdev
->pm
.dpm
.current_ps
;
2048 ret
= rv770_restrict_performance_levels_before_switch(rdev
);
2050 DRM_ERROR("rv770_restrict_performance_levels_before_switch failed\n");
2053 rv770_set_uvd_clock_before_set_eng_clock(rdev
, new_ps
, old_ps
);
2054 ret
= rv770_halt_smc(rdev
);
2056 DRM_ERROR("rv770_halt_smc failed\n");
2059 ret
= rv770_upload_sw_state(rdev
, new_ps
);
2061 DRM_ERROR("rv770_upload_sw_state failed\n");
2064 r7xx_program_memory_timing_parameters(rdev
, new_ps
);
2066 rv770_program_dcodt_before_state_switch(rdev
, new_ps
, old_ps
);
2067 ret
= rv770_resume_smc(rdev
);
2069 DRM_ERROR("rv770_resume_smc failed\n");
2072 ret
= rv770_set_sw_state(rdev
);
2074 DRM_ERROR("rv770_set_sw_state failed\n");
2078 rv770_program_dcodt_after_state_switch(rdev
, new_ps
, old_ps
);
2079 rv770_set_uvd_clock_after_set_eng_clock(rdev
, new_ps
, old_ps
);
2085 void rv770_dpm_reset_asic(struct radeon_device
*rdev
)
2087 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
2088 struct radeon_ps
*boot_ps
= rdev
->pm
.dpm
.boot_ps
;
2090 rv770_restrict_performance_levels_before_switch(rdev
);
2092 rv770_program_dcodt_before_state_switch(rdev
, boot_ps
, boot_ps
);
2093 rv770_set_boot_state(rdev
);
2095 rv770_program_dcodt_after_state_switch(rdev
, boot_ps
, boot_ps
);
2099 void rv770_dpm_setup_asic(struct radeon_device
*rdev
)
2101 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
2103 r7xx_read_clock_registers(rdev
);
2104 rv770_read_voltage_smio_registers(rdev
);
2105 rv770_get_memory_type(rdev
);
2107 rv770_get_mclk_odt_threshold(rdev
);
2108 rv770_get_pcie_gen2_status(rdev
);
2110 rv770_enable_acpi_pm(rdev
);
2112 if (radeon_aspm
!= 0) {
2113 if (rdev
->pm
.dpm
.platform_caps
& ATOM_PP_PLATFORM_CAP_ASPM_L0s
)
2114 rv770_enable_l0s(rdev
);
2115 if (rdev
->pm
.dpm
.platform_caps
& ATOM_PP_PLATFORM_CAP_ASPM_L1
)
2116 rv770_enable_l1(rdev
);
2117 if (rdev
->pm
.dpm
.platform_caps
& ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1
)
2118 rv770_enable_pll_sleep_in_l1(rdev
);
2122 void rv770_dpm_display_configuration_changed(struct radeon_device
*rdev
)
2124 rv770_program_display_gap(rdev
);
2128 struct _ATOM_POWERPLAY_INFO info
;
2129 struct _ATOM_POWERPLAY_INFO_V2 info_2
;
2130 struct _ATOM_POWERPLAY_INFO_V3 info_3
;
2131 struct _ATOM_PPLIB_POWERPLAYTABLE pplib
;
2132 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2
;
2133 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3
;
2136 union pplib_clock_info
{
2137 struct _ATOM_PPLIB_R600_CLOCK_INFO r600
;
2138 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780
;
2139 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen
;
2140 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo
;
2143 union pplib_power_state
{
2144 struct _ATOM_PPLIB_STATE v1
;
2145 struct _ATOM_PPLIB_STATE_V2 v2
;
2148 static void rv7xx_parse_pplib_non_clock_info(struct radeon_device
*rdev
,
2149 struct radeon_ps
*rps
,
2150 struct _ATOM_PPLIB_NONCLOCK_INFO
*non_clock_info
,
2153 rps
->caps
= le32_to_cpu(non_clock_info
->ulCapsAndSettings
);
2154 rps
->class = le16_to_cpu(non_clock_info
->usClassification
);
2155 rps
->class2
= le16_to_cpu(non_clock_info
->usClassification2
);
2157 if (ATOM_PPLIB_NONCLOCKINFO_VER1
< table_rev
) {
2158 rps
->vclk
= le32_to_cpu(non_clock_info
->ulVCLK
);
2159 rps
->dclk
= le32_to_cpu(non_clock_info
->ulDCLK
);
2165 if (r600_is_uvd_state(rps
->class, rps
->class2
)) {
2166 if ((rps
->vclk
== 0) || (rps
->dclk
== 0)) {
2167 rps
->vclk
= RV770_DEFAULT_VCLK_FREQ
;
2168 rps
->dclk
= RV770_DEFAULT_DCLK_FREQ
;
2172 if (rps
->class & ATOM_PPLIB_CLASSIFICATION_BOOT
)
2173 rdev
->pm
.dpm
.boot_ps
= rps
;
2174 if (rps
->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE
)
2175 rdev
->pm
.dpm
.uvd_ps
= rps
;
2178 static void rv7xx_parse_pplib_clock_info(struct radeon_device
*rdev
,
2179 struct radeon_ps
*rps
, int index
,
2180 union pplib_clock_info
*clock_info
)
2182 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
2183 struct evergreen_power_info
*eg_pi
= evergreen_get_pi(rdev
);
2184 struct rv7xx_ps
*ps
= rv770_get_ps(rps
);
2186 struct rv7xx_pl
*pl
;
2201 if (rdev
->family
>= CHIP_CEDAR
) {
2202 sclk
= le16_to_cpu(clock_info
->evergreen
.usEngineClockLow
);
2203 sclk
|= clock_info
->evergreen
.ucEngineClockHigh
<< 16;
2204 mclk
= le16_to_cpu(clock_info
->evergreen
.usMemoryClockLow
);
2205 mclk
|= clock_info
->evergreen
.ucMemoryClockHigh
<< 16;
2207 pl
->vddc
= le16_to_cpu(clock_info
->evergreen
.usVDDC
);
2208 pl
->vddci
= le16_to_cpu(clock_info
->evergreen
.usVDDCI
);
2209 pl
->flags
= le32_to_cpu(clock_info
->evergreen
.ulFlags
);
2211 sclk
= le16_to_cpu(clock_info
->r600
.usEngineClockLow
);
2212 sclk
|= clock_info
->r600
.ucEngineClockHigh
<< 16;
2213 mclk
= le16_to_cpu(clock_info
->r600
.usMemoryClockLow
);
2214 mclk
|= clock_info
->r600
.ucMemoryClockHigh
<< 16;
2216 pl
->vddc
= le16_to_cpu(clock_info
->r600
.usVDDC
);
2217 pl
->flags
= le32_to_cpu(clock_info
->r600
.ulFlags
);
2223 /* patch up vddc if necessary */
2224 if (pl
->vddc
== 0xff01) {
2226 pl
->vddc
= pi
->max_vddc
;
2229 if (rps
->class & ATOM_PPLIB_CLASSIFICATION_ACPI
) {
2230 pi
->acpi_vddc
= pl
->vddc
;
2231 if (rdev
->family
>= CHIP_CEDAR
)
2232 eg_pi
->acpi_vddci
= pl
->vddci
;
2233 if (ps
->low
.flags
& ATOM_PPLIB_R600_FLAGS_PCIEGEN2
)
2234 pi
->acpi_pcie_gen2
= true;
2236 pi
->acpi_pcie_gen2
= false;
2239 if (rps
->class2
& ATOM_PPLIB_CLASSIFICATION2_ULV
) {
2240 if (rdev
->family
>= CHIP_BARTS
) {
2241 eg_pi
->ulv
.supported
= true;
2246 if (pi
->min_vddc_in_table
> pl
->vddc
)
2247 pi
->min_vddc_in_table
= pl
->vddc
;
2249 if (pi
->max_vddc_in_table
< pl
->vddc
)
2250 pi
->max_vddc_in_table
= pl
->vddc
;
2252 /* patch up boot state */
2253 if (rps
->class & ATOM_PPLIB_CLASSIFICATION_BOOT
) {
2254 u16 vddc
, vddci
, mvdd
;
2255 radeon_atombios_get_default_voltages(rdev
, &vddc
, &vddci
, &mvdd
);
2256 pl
->mclk
= rdev
->clock
.default_mclk
;
2257 pl
->sclk
= rdev
->clock
.default_sclk
;
2262 if ((rps
->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK
) ==
2263 ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE
) {
2264 rdev
->pm
.dpm
.dyn_state
.max_clock_voltage_on_ac
.sclk
= pl
->sclk
;
2265 rdev
->pm
.dpm
.dyn_state
.max_clock_voltage_on_ac
.mclk
= pl
->mclk
;
2266 rdev
->pm
.dpm
.dyn_state
.max_clock_voltage_on_ac
.vddc
= pl
->vddc
;
2267 rdev
->pm
.dpm
.dyn_state
.max_clock_voltage_on_ac
.vddci
= pl
->vddci
;
2271 int rv7xx_parse_power_table(struct radeon_device
*rdev
)
2273 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
2274 struct _ATOM_PPLIB_NONCLOCK_INFO
*non_clock_info
;
2275 union pplib_power_state
*power_state
;
2277 union pplib_clock_info
*clock_info
;
2278 union power_info
*power_info
;
2279 int index
= GetIndexIntoMasterTable(DATA
, PowerPlayInfo
);
2282 struct rv7xx_ps
*ps
;
2284 if (!atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
2285 &frev
, &crev
, &data_offset
))
2287 power_info
= (union power_info
*)((uint8_t*)mode_info
->atom_context
->bios
+ data_offset
);
2289 rdev
->pm
.dpm
.ps
= kzalloc(sizeof(struct radeon_ps
) *
2290 power_info
->pplib
.ucNumStates
, GFP_KERNEL
);
2291 if (!rdev
->pm
.dpm
.ps
)
2294 for (i
= 0; i
< power_info
->pplib
.ucNumStates
; i
++) {
2295 power_state
= (union pplib_power_state
*)
2296 ((uint8_t*)mode_info
->atom_context
->bios
+ data_offset
+
2297 le16_to_cpu(power_info
->pplib
.usStateArrayOffset
) +
2298 i
* power_info
->pplib
.ucStateEntrySize
);
2299 non_clock_info
= (struct _ATOM_PPLIB_NONCLOCK_INFO
*)
2300 ((uint8_t*)mode_info
->atom_context
->bios
+ data_offset
+
2301 le16_to_cpu(power_info
->pplib
.usNonClockInfoArrayOffset
) +
2302 (power_state
->v1
.ucNonClockStateIndex
*
2303 power_info
->pplib
.ucNonClockSize
));
2304 if (power_info
->pplib
.ucStateEntrySize
- 1) {
2306 ps
= kzalloc(sizeof(struct rv7xx_ps
), GFP_KERNEL
);
2308 kfree(rdev
->pm
.dpm
.ps
);
2311 rdev
->pm
.dpm
.ps
[i
].ps_priv
= ps
;
2312 rv7xx_parse_pplib_non_clock_info(rdev
, &rdev
->pm
.dpm
.ps
[i
],
2314 power_info
->pplib
.ucNonClockSize
);
2315 idx
= (u8
*)&power_state
->v1
.ucClockStateIndices
[0];
2316 for (j
= 0; j
< (power_info
->pplib
.ucStateEntrySize
- 1); j
++) {
2317 clock_info
= (union pplib_clock_info
*)
2318 ((uint8_t*)mode_info
->atom_context
->bios
+ data_offset
+
2319 le16_to_cpu(power_info
->pplib
.usClockInfoArrayOffset
) +
2320 (idx
[j
] * power_info
->pplib
.ucClockInfoSize
));
2321 rv7xx_parse_pplib_clock_info(rdev
,
2322 &rdev
->pm
.dpm
.ps
[i
], j
,
2327 rdev
->pm
.dpm
.num_ps
= power_info
->pplib
.ucNumStates
;
2331 void rv770_get_engine_memory_ss(struct radeon_device
*rdev
)
2333 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
2334 struct radeon_atom_ss ss
;
2336 pi
->sclk_ss
= radeon_atombios_get_asic_ss_info(rdev
, &ss
,
2337 ASIC_INTERNAL_ENGINE_SS
, 0);
2338 pi
->mclk_ss
= radeon_atombios_get_asic_ss_info(rdev
, &ss
,
2339 ASIC_INTERNAL_MEMORY_SS
, 0);
2341 if (pi
->sclk_ss
|| pi
->mclk_ss
)
2342 pi
->dynamic_ss
= true;
2344 pi
->dynamic_ss
= false;
2347 int rv770_dpm_init(struct radeon_device
*rdev
)
2349 struct rv7xx_power_info
*pi
;
2350 struct atom_clock_dividers dividers
;
2353 pi
= kzalloc(sizeof(struct rv7xx_power_info
), GFP_KERNEL
);
2356 rdev
->pm
.dpm
.priv
= pi
;
2358 rv770_get_max_vddc(rdev
);
2361 pi
->min_vddc_in_table
= 0;
2362 pi
->max_vddc_in_table
= 0;
2364 ret
= r600_get_platform_caps(rdev
);
2368 ret
= rv7xx_parse_power_table(rdev
);
2372 if (rdev
->pm
.dpm
.voltage_response_time
== 0)
2373 rdev
->pm
.dpm
.voltage_response_time
= R600_VOLTAGERESPONSETIME_DFLT
;
2374 if (rdev
->pm
.dpm
.backbias_response_time
== 0)
2375 rdev
->pm
.dpm
.backbias_response_time
= R600_BACKBIASRESPONSETIME_DFLT
;
2377 ret
= radeon_atom_get_clock_dividers(rdev
, COMPUTE_ENGINE_PLL_PARAM
,
2378 0, false, ÷rs
);
2380 pi
->ref_div
= dividers
.ref_div
+ 1;
2382 pi
->ref_div
= R600_REFERENCEDIVIDER_DFLT
;
2384 pi
->mclk_strobe_mode_threshold
= 30000;
2385 pi
->mclk_edc_enable_threshold
= 30000;
2387 pi
->rlp
= RV770_RLP_DFLT
;
2388 pi
->rmp
= RV770_RMP_DFLT
;
2389 pi
->lhp
= RV770_LHP_DFLT
;
2390 pi
->lmp
= RV770_LMP_DFLT
;
2392 pi
->voltage_control
=
2393 radeon_atom_is_voltage_gpio(rdev
, SET_VOLTAGE_TYPE_ASIC_VDDC
, 0);
2396 radeon_atom_is_voltage_gpio(rdev
, SET_VOLTAGE_TYPE_ASIC_MVDDC
, 0);
2398 rv770_get_engine_memory_ss(rdev
);
2400 pi
->asi
= RV770_ASI_DFLT
;
2401 pi
->pasi
= RV770_HASI_DFLT
;
2402 pi
->vrc
= RV770_VRC_DFLT
;
2404 pi
->power_gating
= false;
2406 pi
->gfx_clock_gating
= true;
2408 pi
->mg_clock_gating
= true;
2409 pi
->mgcgtssm
= true;
2411 pi
->dynamic_pcie_gen2
= true;
2413 if (rdev
->pm
.int_thermal_type
!= THERMAL_TYPE_NONE
)
2414 pi
->thermal_protection
= true;
2416 pi
->thermal_protection
= false;
2418 pi
->display_gap
= true;
2420 if (rdev
->flags
& RADEON_IS_MOBILITY
)
2427 pi
->mclk_stutter_mode_threshold
= 0;
2429 pi
->sram_end
= SMC_RAM_END
;
2430 pi
->state_table_start
= RV770_SMC_TABLE_ADDRESS
;
2431 pi
->soft_regs_start
= RV770_SMC_SOFT_REGISTERS_START
;
2436 void rv770_dpm_print_power_state(struct radeon_device
*rdev
,
2437 struct radeon_ps
*rps
)
2439 struct rv7xx_ps
*ps
= rv770_get_ps(rps
);
2440 struct rv7xx_pl
*pl
;
2442 r600_dpm_print_class_info(rps
->class, rps
->class2
);
2443 r600_dpm_print_cap_info(rps
->caps
);
2444 printk("\tuvd vclk: %d dclk: %d\n", rps
->vclk
, rps
->dclk
);
2445 if (rdev
->family
>= CHIP_CEDAR
) {
2447 printk("\t\tpower level 0 sclk: %u mclk: %u vddc: %u vddci: %u\n",
2448 pl
->sclk
, pl
->mclk
, pl
->vddc
, pl
->vddci
);
2450 printk("\t\tpower level 1 sclk: %u mclk: %u vddc: %u vddci: %u\n",
2451 pl
->sclk
, pl
->mclk
, pl
->vddc
, pl
->vddci
);
2453 printk("\t\tpower level 2 sclk: %u mclk: %u vddc: %u vddci: %u\n",
2454 pl
->sclk
, pl
->mclk
, pl
->vddc
, pl
->vddci
);
2457 printk("\t\tpower level 0 sclk: %u mclk: %u vddc: %u\n",
2458 pl
->sclk
, pl
->mclk
, pl
->vddc
);
2460 printk("\t\tpower level 1 sclk: %u mclk: %u vddc: %u\n",
2461 pl
->sclk
, pl
->mclk
, pl
->vddc
);
2463 printk("\t\tpower level 2 sclk: %u mclk: %u vddc: %u\n",
2464 pl
->sclk
, pl
->mclk
, pl
->vddc
);
2466 r600_dpm_print_ps_status(rdev
, rps
);
2469 void rv770_dpm_debugfs_print_current_performance_level(struct radeon_device
*rdev
,
2472 struct radeon_ps
*rps
= rdev
->pm
.dpm
.current_ps
;
2473 struct rv7xx_ps
*ps
= rv770_get_ps(rps
);
2474 struct rv7xx_pl
*pl
;
2476 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX
) & CURRENT_PROFILE_INDEX_MASK
) >>
2477 CURRENT_PROFILE_INDEX_SHIFT
;
2479 if (current_index
> 2) {
2480 seq_printf(m
, "invalid dpm profile %d\n", current_index
);
2482 if (current_index
== 0)
2484 else if (current_index
== 1)
2486 else /* current_index == 2 */
2488 seq_printf(m
, "uvd vclk: %d dclk: %d\n", rps
->vclk
, rps
->dclk
);
2489 if (rdev
->family
>= CHIP_CEDAR
) {
2490 seq_printf(m
, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u\n",
2491 current_index
, pl
->sclk
, pl
->mclk
, pl
->vddc
, pl
->vddci
);
2493 seq_printf(m
, "power level %d sclk: %u mclk: %u vddc: %u\n",
2494 current_index
, pl
->sclk
, pl
->mclk
, pl
->vddc
);
2499 void rv770_dpm_fini(struct radeon_device
*rdev
)
2503 for (i
= 0; i
< rdev
->pm
.dpm
.num_ps
; i
++) {
2504 kfree(rdev
->pm
.dpm
.ps
[i
].ps_priv
);
2506 kfree(rdev
->pm
.dpm
.ps
);
2507 kfree(rdev
->pm
.dpm
.priv
);
2510 u32
rv770_dpm_get_sclk(struct radeon_device
*rdev
, bool low
)
2512 struct rv7xx_ps
*requested_state
= rv770_get_ps(rdev
->pm
.dpm
.requested_ps
);
2515 return requested_state
->low
.sclk
;
2517 return requested_state
->high
.sclk
;
2520 u32
rv770_dpm_get_mclk(struct radeon_device
*rdev
, bool low
)
2522 struct rv7xx_ps
*requested_state
= rv770_get_ps(rdev
->pm
.dpm
.requested_ps
);
2525 return requested_state
->low
.mclk
;
2527 return requested_state
->high
.mclk
;
2530 bool rv770_dpm_vblank_too_short(struct radeon_device
*rdev
)
2532 u32 vblank_time
= r600_dpm_get_vblank_time(rdev
);
2533 u32 switch_limit
= 200; /* 300 */
2536 /* mclk switching doesn't seem to work reliably on desktop RV770s */
2537 if ((rdev
->family
== CHIP_RV770
) &&
2538 !(rdev
->flags
& RADEON_IS_MOBILITY
))
2539 switch_limit
= 0xffffffff; /* disable mclk switching */
2541 if (vblank_time
< switch_limit
)