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drm/radeon: add missing ttm_eu_backoff_reservation to radeon_bo_list_validate
[dragonfly.git] / sys / dev / drm / radeon / rv515.c
blob597e4647aaf34e7b27f9e958760bcc9c171504b9
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #include <drm/drmP.h>
29 #include "rv515d.h"
30 #include "radeon.h"
31 #include "radeon_asic.h"
32 #include "atom.h"
33 #include "rv515_reg_safe.h"
34
35 /* This files gather functions specifics to: rv515 */
36 static int rv515_debugfs_pipes_info_init(struct radeon_device *rdev);
37 static int rv515_debugfs_ga_info_init(struct radeon_device *rdev);
38 static void rv515_gpu_init(struct radeon_device *rdev);
39
40 static const u32 crtc_offsets[2] =
41 {
42 0,
43 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL
44 };
45
46 void rv515_debugfs(struct radeon_device *rdev)
47 {
48 if (r100_debugfs_rbbm_init(rdev)) {
49 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
50 }
51 if (rv515_debugfs_pipes_info_init(rdev)) {
52 DRM_ERROR("Failed to register debugfs file for pipes !\n");
53 }
54 if (rv515_debugfs_ga_info_init(rdev)) {
55 DRM_ERROR("Failed to register debugfs file for pipes !\n");
56 }
57 }
58
59 void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)
60 {
61 int r;
62
63 r = radeon_ring_lock(rdev, ring, 64);
64 if (r) {
65 return;
66 }
67 radeon_ring_write(ring, PACKET0(ISYNC_CNTL, 0));
68 radeon_ring_write(ring,
69 ISYNC_ANY2D_IDLE3D |
70 ISYNC_ANY3D_IDLE2D |
71 ISYNC_WAIT_IDLEGUI |
72 ISYNC_CPSCRATCH_IDLEGUI);
73 radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0));
74 radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
75 radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0));
76 radeon_ring_write(ring, R300_PIPE_AUTO_CONFIG);
77 radeon_ring_write(ring, PACKET0(GB_SELECT, 0));
78 radeon_ring_write(ring, 0);
79 radeon_ring_write(ring, PACKET0(GB_ENABLE, 0));
80 radeon_ring_write(ring, 0);
81 radeon_ring_write(ring, PACKET0(R500_SU_REG_DEST, 0));
82 radeon_ring_write(ring, (1 << rdev->num_gb_pipes) - 1);
83 radeon_ring_write(ring, PACKET0(VAP_INDEX_OFFSET, 0));
84 radeon_ring_write(ring, 0);
85 radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
86 radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE);
87 radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
88 radeon_ring_write(ring, ZC_FLUSH | ZC_FREE);
89 radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0));
90 radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
91 radeon_ring_write(ring, PACKET0(GB_AA_CONFIG, 0));
92 radeon_ring_write(ring, 0);
93 radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
94 radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE);
95 radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
96 radeon_ring_write(ring, ZC_FLUSH | ZC_FREE);
97 radeon_ring_write(ring, PACKET0(GB_MSPOS0, 0));
98 radeon_ring_write(ring,
99 ((6 << MS_X0_SHIFT) |
100 (6 << MS_Y0_SHIFT) |
101 (6 << MS_X1_SHIFT) |
102 (6 << MS_Y1_SHIFT) |
103 (6 << MS_X2_SHIFT) |
104 (6 << MS_Y2_SHIFT) |
105 (6 << MSBD0_Y_SHIFT) |
106 (6 << MSBD0_X_SHIFT)));
107 radeon_ring_write(ring, PACKET0(GB_MSPOS1, 0));
108 radeon_ring_write(ring,
109 ((6 << MS_X3_SHIFT) |
110 (6 << MS_Y3_SHIFT) |
111 (6 << MS_X4_SHIFT) |
112 (6 << MS_Y4_SHIFT) |
113 (6 << MS_X5_SHIFT) |
114 (6 << MS_Y5_SHIFT) |
115 (6 << MSBD1_SHIFT)));
116 radeon_ring_write(ring, PACKET0(GA_ENHANCE, 0));
117 radeon_ring_write(ring, GA_DEADLOCK_CNTL | GA_FASTSYNC_CNTL);
118 radeon_ring_write(ring, PACKET0(GA_POLY_MODE, 0));
119 radeon_ring_write(ring, FRONT_PTYPE_TRIANGE | BACK_PTYPE_TRIANGE);
120 radeon_ring_write(ring, PACKET0(GA_ROUND_MODE, 0));
121 radeon_ring_write(ring, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST);
122 radeon_ring_write(ring, PACKET0(0x20C8, 0));
123 radeon_ring_write(ring, 0);
124 radeon_ring_unlock_commit(rdev, ring, false);
125 }
126
127 int rv515_mc_wait_for_idle(struct radeon_device *rdev)
128 {
129 unsigned i;
130 uint32_t tmp;
131
132 for (i = 0; i < rdev->usec_timeout; i++) {
133 /* read MC_STATUS */
134 tmp = RREG32_MC(MC_STATUS);
135 if (tmp & MC_STATUS_IDLE) {
136 return 0;
137 }
138 DRM_UDELAY(1);
139 }
140 return -1;
141 }
142
143 void rv515_vga_render_disable(struct radeon_device *rdev)
144 {
145 WREG32(R_000300_VGA_RENDER_CONTROL,
146 RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL);
147 }
148
149 static void rv515_gpu_init(struct radeon_device *rdev)
150 {
151 unsigned pipe_select_current, gb_pipe_select, tmp;
152
153 if (r100_gui_wait_for_idle(rdev)) {
154 printk(KERN_WARNING "Failed to wait GUI idle while "
155 "resetting GPU. Bad things might happen.\n");
156 }
157 rv515_vga_render_disable(rdev);
158 r420_pipes_init(rdev);
159 gb_pipe_select = RREG32(R400_GB_PIPE_SELECT);
160 tmp = RREG32(R300_DST_PIPE_CONFIG);
161 pipe_select_current = (tmp >> 2) & 3;
162 tmp = (1 << pipe_select_current) |
163 (((gb_pipe_select >> 8) & 0xF) << 4);
164 WREG32_PLL(0x000D, tmp);
165 if (r100_gui_wait_for_idle(rdev)) {
166 printk(KERN_WARNING "Failed to wait GUI idle while "
167 "resetting GPU. Bad things might happen.\n");
168 }
169 if (rv515_mc_wait_for_idle(rdev)) {
170 printk(KERN_WARNING "Failed to wait MC idle while "
171 "programming pipes. Bad things might happen.\n");
172 }
173 }
174
175 static void rv515_vram_get_type(struct radeon_device *rdev)
176 {
177 uint32_t tmp;
178
179 rdev->mc.vram_width = 128;
180 rdev->mc.vram_is_ddr = true;
181 tmp = RREG32_MC(RV515_MC_CNTL) & MEM_NUM_CHANNELS_MASK;
182 switch (tmp) {
183 case 0:
184 rdev->mc.vram_width = 64;
185 break;
186 case 1:
187 rdev->mc.vram_width = 128;
188 break;
189 default:
190 rdev->mc.vram_width = 128;
191 break;
192 }
193 }
194
195 static void rv515_mc_init(struct radeon_device *rdev)
196 {
197
198 rv515_vram_get_type(rdev);
199 r100_vram_init_sizes(rdev);
200 radeon_vram_location(rdev, &rdev->mc, 0);
201 rdev->mc.gtt_base_align = 0;
202 if (!(rdev->flags & RADEON_IS_AGP))
203 radeon_gtt_location(rdev, &rdev->mc);
204 radeon_update_bandwidth_info(rdev);
205 }
206
207 uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg)
208 {
209 uint32_t r;
210
211 spin_lock(&rdev->mc_idx_lock);
212 WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff));
213 r = RREG32(MC_IND_DATA);
214 WREG32(MC_IND_INDEX, 0);
215 spin_unlock(&rdev->mc_idx_lock);
216
217 return r;
218 }
219
220 void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
221 {
222 spin_lock(&rdev->mc_idx_lock);
223 WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff));
224 WREG32(MC_IND_DATA, (v));
225 WREG32(MC_IND_INDEX, 0);
226 spin_unlock(&rdev->mc_idx_lock);
227 }
228
229 #if defined(CONFIG_DEBUG_FS)
230 static int rv515_debugfs_pipes_info(struct seq_file *m, void *data)
231 {
232 struct drm_info_node *node = (struct drm_info_node *) m->private;
233 struct drm_device *dev = node->minor->dev;
234 struct radeon_device *rdev = dev->dev_private;
235 uint32_t tmp;
236
237 tmp = RREG32(GB_PIPE_SELECT);
238 seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
239 tmp = RREG32(SU_REG_DEST);
240 seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp);
241 tmp = RREG32(GB_TILE_CONFIG);
242 seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
243 tmp = RREG32(DST_PIPE_CONFIG);
244 seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
245 return 0;
246 }
247
248 static int rv515_debugfs_ga_info(struct seq_file *m, void *data)
249 {
250 struct drm_info_node *node = (struct drm_info_node *) m->private;
251 struct drm_device *dev = node->minor->dev;
252 struct radeon_device *rdev = dev->dev_private;
253 uint32_t tmp;
254
255 tmp = RREG32(0x2140);
256 seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp);
257 radeon_asic_reset(rdev);
258 tmp = RREG32(0x425C);
259 seq_printf(m, "GA_IDLE 0x%08x\n", tmp);
260 return 0;
261 }
262
263 static struct drm_info_list rv515_pipes_info_list[] = {
264 {"rv515_pipes_info", rv515_debugfs_pipes_info, 0, NULL},
265 };
266
267 static struct drm_info_list rv515_ga_info_list[] = {
268 {"rv515_ga_info", rv515_debugfs_ga_info, 0, NULL},
269 };
270 #endif
271
272 static int rv515_debugfs_pipes_info_init(struct radeon_device *rdev)
273 {
274 #if defined(CONFIG_DEBUG_FS)
275 return radeon_debugfs_add_files(rdev, rv515_pipes_info_list, 1);
276 #else
277 return 0;
278 #endif
279 }
280
281 static int rv515_debugfs_ga_info_init(struct radeon_device *rdev)
282 {
283 #if defined(CONFIG_DEBUG_FS)
284 return radeon_debugfs_add_files(rdev, rv515_ga_info_list, 1);
285 #else
286 return 0;
287 #endif
288 }
289
290 void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save)
291 {
292 u32 crtc_enabled, tmp, frame_count, blackout;
293 int i, j;
294
295 save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL);
296 save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL);
297
298 /* disable VGA render */
299 WREG32(R_000300_VGA_RENDER_CONTROL, 0);
300 /* blank the display controllers */
301 for (i = 0; i < rdev->num_crtc; i++) {
302 crtc_enabled = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN;
303 if (crtc_enabled) {
304 save->crtc_enabled[i] = true;
305 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
306 if (!(tmp & AVIVO_CRTC_DISP_READ_REQUEST_DISABLE)) {
307 radeon_wait_for_vblank(rdev, i);
308 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
309 tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
310 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
311 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
312 }
313 /* wait for the next frame */
314 frame_count = radeon_get_vblank_counter(rdev, i);
315 for (j = 0; j < rdev->usec_timeout; j++) {
316 if (radeon_get_vblank_counter(rdev, i) != frame_count)
317 break;
318 udelay(1);
319 }
320
321 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
322 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
323 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
324 tmp &= ~AVIVO_CRTC_EN;
325 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
326 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
327 save->crtc_enabled[i] = false;
328 /* ***** */
329 } else {
330 save->crtc_enabled[i] = false;
331 }
332 }
333
334 radeon_mc_wait_for_idle(rdev);
335
336 if (rdev->family >= CHIP_R600) {
337 if (rdev->family >= CHIP_RV770)
338 blackout = RREG32(R700_MC_CITF_CNTL);
339 else
340 blackout = RREG32(R600_CITF_CNTL);
341 if ((blackout & R600_BLACKOUT_MASK) != R600_BLACKOUT_MASK) {
342 /* Block CPU access */
343 WREG32(R600_BIF_FB_EN, 0);
344 /* blackout the MC */
345 blackout |= R600_BLACKOUT_MASK;
346 if (rdev->family >= CHIP_RV770)
347 WREG32(R700_MC_CITF_CNTL, blackout);
348 else
349 WREG32(R600_CITF_CNTL, blackout);
350 }
351 }
352 /* wait for the MC to settle */
353 udelay(100);
354
355 /* lock double buffered regs */
356 for (i = 0; i < rdev->num_crtc; i++) {
357 if (save->crtc_enabled[i]) {
358 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
359 if (!(tmp & AVIVO_D1GRPH_UPDATE_LOCK)) {
360 tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
361 WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp);
362 }
363 tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]);
364 if (!(tmp & 1)) {
365 tmp |= 1;
366 WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
367 }
368 }
369 }
370 }
371
372 void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save)
373 {
374 u32 tmp, frame_count;
375 int i, j;
376
377 /* update crtc base addresses */
378 for (i = 0; i < rdev->num_crtc; i++) {
379 if (rdev->family >= CHIP_RV770) {
380 if (i == 0) {
381 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH,
382 upper_32_bits(rdev->mc.vram_start));
383 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH,
384 upper_32_bits(rdev->mc.vram_start));
385 } else {
386 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH,
387 upper_32_bits(rdev->mc.vram_start));
388 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH,
389 upper_32_bits(rdev->mc.vram_start));
390 }
391 }
392 WREG32(R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
393 (u32)rdev->mc.vram_start);
394 WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
395 (u32)rdev->mc.vram_start);
396 }
397 WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
398
399 /* unlock regs and wait for update */
400 for (i = 0; i < rdev->num_crtc; i++) {
401 if (save->crtc_enabled[i]) {
402 tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i]);
403 if ((tmp & 0x7) != 3) {
404 tmp &= ~0x7;
405 tmp |= 0x3;
406 WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i], tmp);
407 }
408 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
409 if (tmp & AVIVO_D1GRPH_UPDATE_LOCK) {
410 tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
411 WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp);
412 }
413 tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]);
414 if (tmp & 1) {
415 tmp &= ~1;
416 WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
417 }
418 for (j = 0; j < rdev->usec_timeout; j++) {
419 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
420 if ((tmp & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) == 0)
421 break;
422 udelay(1);
423 }
424 }
425 }
426
427 if (rdev->family >= CHIP_R600) {
428 /* unblackout the MC */
429 if (rdev->family >= CHIP_RV770)
430 tmp = RREG32(R700_MC_CITF_CNTL);
431 else
432 tmp = RREG32(R600_CITF_CNTL);
433 tmp &= ~R600_BLACKOUT_MASK;
434 if (rdev->family >= CHIP_RV770)
435 WREG32(R700_MC_CITF_CNTL, tmp);
436 else
437 WREG32(R600_CITF_CNTL, tmp);
438 /* allow CPU access */
439 WREG32(R600_BIF_FB_EN, R600_FB_READ_EN | R600_FB_WRITE_EN);
440 }
441
442 for (i = 0; i < rdev->num_crtc; i++) {
443 if (save->crtc_enabled[i]) {
444 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
445 tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
446 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
447 /* wait for the next frame */
448 frame_count = radeon_get_vblank_counter(rdev, i);
449 for (j = 0; j < rdev->usec_timeout; j++) {
450 if (radeon_get_vblank_counter(rdev, i) != frame_count)
451 break;
452 udelay(1);
453 }
454 }
455 }
456 /* Unlock vga access */
457 WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control);
458 mdelay(1);
459 WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control);
460 }
461
462 static void rv515_mc_program(struct radeon_device *rdev)
463 {
464 struct rv515_mc_save save;
465
466 /* Stops all mc clients */
467 rv515_mc_stop(rdev, &save);
468
469 /* Wait for mc idle */
470 if (rv515_mc_wait_for_idle(rdev))
471 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
472 /* Write VRAM size in case we are limiting it */
473 WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
474 /* Program MC, should be a 32bits limited address space */
475 WREG32_MC(R_000001_MC_FB_LOCATION,
476 S_000001_MC_FB_START(rdev->mc.vram_start >> 16) |
477 S_000001_MC_FB_TOP(rdev->mc.vram_end >> 16));
478 WREG32(R_000134_HDP_FB_LOCATION,
479 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
480 if (rdev->flags & RADEON_IS_AGP) {
481 WREG32_MC(R_000002_MC_AGP_LOCATION,
482 S_000002_MC_AGP_START(rdev->mc.gtt_start >> 16) |
483 S_000002_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
484 WREG32_MC(R_000003_MC_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
485 WREG32_MC(R_000004_MC_AGP_BASE_2,
486 S_000004_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base)));
487 } else {
488 WREG32_MC(R_000002_MC_AGP_LOCATION, 0xFFFFFFFF);
489 WREG32_MC(R_000003_MC_AGP_BASE, 0);
490 WREG32_MC(R_000004_MC_AGP_BASE_2, 0);
491 }
492
493 rv515_mc_resume(rdev, &save);
494 }
495
496 void rv515_clock_startup(struct radeon_device *rdev)
497 {
498 if (radeon_dynclks != -1 && radeon_dynclks)
499 radeon_atom_set_clock_gating(rdev, 1);
500 /* We need to force on some of the block */
501 WREG32_PLL(R_00000F_CP_DYN_CNTL,
502 RREG32_PLL(R_00000F_CP_DYN_CNTL) | S_00000F_CP_FORCEON(1));
503 WREG32_PLL(R_000011_E2_DYN_CNTL,
504 RREG32_PLL(R_000011_E2_DYN_CNTL) | S_000011_E2_FORCEON(1));
505 WREG32_PLL(R_000013_IDCT_DYN_CNTL,
506 RREG32_PLL(R_000013_IDCT_DYN_CNTL) | S_000013_IDCT_FORCEON(1));
507 }
508
509 static int rv515_startup(struct radeon_device *rdev)
510 {
511 int r;
512
513 rv515_mc_program(rdev);
514 /* Resume clock */
515 rv515_clock_startup(rdev);
516 /* Initialize GPU configuration (# pipes, ...) */
517 rv515_gpu_init(rdev);
518 /* Initialize GART (initialize after TTM so we can allocate
519 * memory through TTM but finalize after TTM) */
520 if (rdev->flags & RADEON_IS_PCIE) {
521 r = rv370_pcie_gart_enable(rdev);
522 if (r)
523 return r;
524 }
525
526 /* allocate wb buffer */
527 r = radeon_wb_init(rdev);
528 if (r)
529 return r;
530
531 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
532 if (r) {
533 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
534 return r;
535 }
536
537 /* Enable IRQ */
538 if (!rdev->irq.installed) {
539 r = radeon_irq_kms_init(rdev);
540 if (r)
541 return r;
542 }
543
544 rs600_irq_set(rdev);
545 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
546 /* 1M ring buffer */
547 r = r100_cp_init(rdev, 1024 * 1024);
548 if (r) {
549 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
550 return r;
551 }
552
553 r = radeon_ib_pool_init(rdev);
554 if (r) {
555 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
556 return r;
557 }
558
559 return 0;
560 }
561
562 int rv515_resume(struct radeon_device *rdev)
563 {
564 int r;
565
566 /* Make sur GART are not working */
567 if (rdev->flags & RADEON_IS_PCIE)
568 rv370_pcie_gart_disable(rdev);
569 /* Resume clock before doing reset */
570 rv515_clock_startup(rdev);
571 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
572 if (radeon_asic_reset(rdev)) {
573 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
574 RREG32(R_000E40_RBBM_STATUS),
575 RREG32(R_0007C0_CP_STAT));
576 }
577 /* post */
578 atom_asic_init(rdev->mode_info.atom_context);
579 /* Resume clock after posting */
580 rv515_clock_startup(rdev);
581 /* Initialize surface registers */
582 radeon_surface_init(rdev);
583
584 rdev->accel_working = true;
585 r = rv515_startup(rdev);
586 if (r) {
587 rdev->accel_working = false;
588 }
589 return r;
590 }
591
592 int rv515_suspend(struct radeon_device *rdev)
593 {
594 radeon_pm_suspend(rdev);
595 r100_cp_disable(rdev);
596 radeon_wb_disable(rdev);
597 rs600_irq_disable(rdev);
598 if (rdev->flags & RADEON_IS_PCIE)
599 rv370_pcie_gart_disable(rdev);
600 return 0;
601 }
602
603 void rv515_set_safe_registers(struct radeon_device *rdev)
604 {
605 rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm;
606 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm);
607 }
608
609 void rv515_fini(struct radeon_device *rdev)
610 {
611 radeon_pm_fini(rdev);
612 r100_cp_fini(rdev);
613 radeon_wb_fini(rdev);
614 radeon_ib_pool_fini(rdev);
615 radeon_gem_fini(rdev);
616 rv370_pcie_gart_fini(rdev);
617 radeon_agp_fini(rdev);
618 radeon_irq_kms_fini(rdev);
619 radeon_fence_driver_fini(rdev);
620 radeon_bo_fini(rdev);
621 radeon_atombios_fini(rdev);
622 kfree(rdev->bios);
623 rdev->bios = NULL;
624 }
625
626 int rv515_init(struct radeon_device *rdev)
627 {
628 int r;
629
630 /* Initialize scratch registers */
631 radeon_scratch_init(rdev);
632 /* Initialize surface registers */
633 radeon_surface_init(rdev);
634 /* TODO: disable VGA need to use VGA request */
635 /* restore some register to sane defaults */
636 r100_restore_sanity(rdev);
637 /* BIOS*/
638 if (!radeon_get_bios(rdev)) {
639 if (ASIC_IS_AVIVO(rdev))
640 return -EINVAL;
641 }
642 if (rdev->is_atom_bios) {
643 r = radeon_atombios_init(rdev);
644 if (r)
645 return r;
646 } else {
647 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
648 return -EINVAL;
649 }
650 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
651 if (radeon_asic_reset(rdev)) {
652 dev_warn(rdev->dev,
653 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
654 RREG32(R_000E40_RBBM_STATUS),
655 RREG32(R_0007C0_CP_STAT));
656 }
657 /* check if cards are posted or not */
658 if (radeon_boot_test_post_card(rdev) == false)
659 return -EINVAL;
660 /* Initialize clocks */
661 radeon_get_clock_info(rdev->ddev);
662 /* initialize AGP */
663 if (rdev->flags & RADEON_IS_AGP) {
664 r = radeon_agp_init(rdev);
665 if (r) {
666 radeon_agp_disable(rdev);
667 }
668 }
669 /* initialize memory controller */
670 rv515_mc_init(rdev);
671 rv515_debugfs(rdev);
672 /* Fence driver */
673 r = radeon_fence_driver_init(rdev);
674 if (r)
675 return r;
676 /* Memory manager */
677 r = radeon_bo_init(rdev);
678 if (r)
679 return r;
680 r = rv370_pcie_gart_init(rdev);
681 if (r)
682 return r;
683 rv515_set_safe_registers(rdev);
684
685 /* Initialize power management */
686 radeon_pm_init(rdev);
687
688 rdev->accel_working = true;
689 r = rv515_startup(rdev);
690 if (r) {
691 /* Somethings want wront with the accel init stop accel */
692 dev_err(rdev->dev, "Disabling GPU acceleration\n");
693 r100_cp_fini(rdev);
694 radeon_wb_fini(rdev);
695 radeon_ib_pool_fini(rdev);
696 radeon_irq_kms_fini(rdev);
697 rv370_pcie_gart_fini(rdev);
698 radeon_agp_fini(rdev);
699 rdev->accel_working = false;
700 }
701 return 0;
702 }
703
704 void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *crtc)
705 {
706 int index_reg = 0x6578 + crtc->crtc_offset;
707 int data_reg = 0x657c + crtc->crtc_offset;
708
709 WREG32(0x659C + crtc->crtc_offset, 0x0);
710 WREG32(0x6594 + crtc->crtc_offset, 0x705);
711 WREG32(0x65A4 + crtc->crtc_offset, 0x10001);
712 WREG32(0x65D8 + crtc->crtc_offset, 0x0);
713 WREG32(0x65B0 + crtc->crtc_offset, 0x0);
714 WREG32(0x65C0 + crtc->crtc_offset, 0x0);
715 WREG32(0x65D4 + crtc->crtc_offset, 0x0);
716 WREG32(index_reg, 0x0);
717 WREG32(data_reg, 0x841880A8);
718 WREG32(index_reg, 0x1);
719 WREG32(data_reg, 0x84208680);
720 WREG32(index_reg, 0x2);
721 WREG32(data_reg, 0xBFF880B0);
722 WREG32(index_reg, 0x100);
723 WREG32(data_reg, 0x83D88088);
724 WREG32(index_reg, 0x101);
725 WREG32(data_reg, 0x84608680);
726 WREG32(index_reg, 0x102);
727 WREG32(data_reg, 0xBFF080D0);
728 WREG32(index_reg, 0x200);
729 WREG32(data_reg, 0x83988068);
730 WREG32(index_reg, 0x201);
731 WREG32(data_reg, 0x84A08680);
732 WREG32(index_reg, 0x202);
733 WREG32(data_reg, 0xBFF080F8);
734 WREG32(index_reg, 0x300);
735 WREG32(data_reg, 0x83588058);
736 WREG32(index_reg, 0x301);
737 WREG32(data_reg, 0x84E08660);
738 WREG32(index_reg, 0x302);
739 WREG32(data_reg, 0xBFF88120);
740 WREG32(index_reg, 0x400);
741 WREG32(data_reg, 0x83188040);
742 WREG32(index_reg, 0x401);
743 WREG32(data_reg, 0x85008660);
744 WREG32(index_reg, 0x402);
745 WREG32(data_reg, 0xBFF88150);
746 WREG32(index_reg, 0x500);
747 WREG32(data_reg, 0x82D88030);
748 WREG32(index_reg, 0x501);
749 WREG32(data_reg, 0x85408640);
750 WREG32(index_reg, 0x502);
751 WREG32(data_reg, 0xBFF88180);
752 WREG32(index_reg, 0x600);
753 WREG32(data_reg, 0x82A08018);
754 WREG32(index_reg, 0x601);
755 WREG32(data_reg, 0x85808620);
756 WREG32(index_reg, 0x602);
757 WREG32(data_reg, 0xBFF081B8);
758 WREG32(index_reg, 0x700);
759 WREG32(data_reg, 0x82608010);
760 WREG32(index_reg, 0x701);
761 WREG32(data_reg, 0x85A08600);
762 WREG32(index_reg, 0x702);
763 WREG32(data_reg, 0x800081F0);
764 WREG32(index_reg, 0x800);
765 WREG32(data_reg, 0x8228BFF8);
766 WREG32(index_reg, 0x801);
767 WREG32(data_reg, 0x85E085E0);
768 WREG32(index_reg, 0x802);
769 WREG32(data_reg, 0xBFF88228);
770 WREG32(index_reg, 0x10000);
771 WREG32(data_reg, 0x82A8BF00);
772 WREG32(index_reg, 0x10001);
773 WREG32(data_reg, 0x82A08CC0);
774 WREG32(index_reg, 0x10002);
775 WREG32(data_reg, 0x8008BEF8);
776 WREG32(index_reg, 0x10100);
777 WREG32(data_reg, 0x81F0BF28);
778 WREG32(index_reg, 0x10101);
779 WREG32(data_reg, 0x83608CA0);
780 WREG32(index_reg, 0x10102);
781 WREG32(data_reg, 0x8018BED0);
782 WREG32(index_reg, 0x10200);
783 WREG32(data_reg, 0x8148BF38);
784 WREG32(index_reg, 0x10201);
785 WREG32(data_reg, 0x84408C80);
786 WREG32(index_reg, 0x10202);
787 WREG32(data_reg, 0x8008BEB8);
788 WREG32(index_reg, 0x10300);
789 WREG32(data_reg, 0x80B0BF78);
790 WREG32(index_reg, 0x10301);
791 WREG32(data_reg, 0x85008C20);
792 WREG32(index_reg, 0x10302);
793 WREG32(data_reg, 0x8020BEA0);
794 WREG32(index_reg, 0x10400);
795 WREG32(data_reg, 0x8028BF90);
796 WREG32(index_reg, 0x10401);
797 WREG32(data_reg, 0x85E08BC0);
798 WREG32(index_reg, 0x10402);
799 WREG32(data_reg, 0x8018BE90);
800 WREG32(index_reg, 0x10500);
801 WREG32(data_reg, 0xBFB8BFB0);
802 WREG32(index_reg, 0x10501);
803 WREG32(data_reg, 0x86C08B40);
804 WREG32(index_reg, 0x10502);
805 WREG32(data_reg, 0x8010BE90);
806 WREG32(index_reg, 0x10600);
807 WREG32(data_reg, 0xBF58BFC8);
808 WREG32(index_reg, 0x10601);
809 WREG32(data_reg, 0x87A08AA0);
810 WREG32(index_reg, 0x10602);
811 WREG32(data_reg, 0x8010BE98);
812 WREG32(index_reg, 0x10700);
813 WREG32(data_reg, 0xBF10BFF0);
814 WREG32(index_reg, 0x10701);
815 WREG32(data_reg, 0x886089E0);
816 WREG32(index_reg, 0x10702);
817 WREG32(data_reg, 0x8018BEB0);
818 WREG32(index_reg, 0x10800);
819 WREG32(data_reg, 0xBED8BFE8);
820 WREG32(index_reg, 0x10801);
821 WREG32(data_reg, 0x89408940);
822 WREG32(index_reg, 0x10802);
823 WREG32(data_reg, 0xBFE8BED8);
824 WREG32(index_reg, 0x20000);
825 WREG32(data_reg, 0x80008000);
826 WREG32(index_reg, 0x20001);
827 WREG32(data_reg, 0x90008000);
828 WREG32(index_reg, 0x20002);
829 WREG32(data_reg, 0x80008000);
830 WREG32(index_reg, 0x20003);
831 WREG32(data_reg, 0x80008000);
832 WREG32(index_reg, 0x20100);
833 WREG32(data_reg, 0x80108000);
834 WREG32(index_reg, 0x20101);
835 WREG32(data_reg, 0x8FE0BF70);
836 WREG32(index_reg, 0x20102);
837 WREG32(data_reg, 0xBFE880C0);
838 WREG32(index_reg, 0x20103);
839 WREG32(data_reg, 0x80008000);
840 WREG32(index_reg, 0x20200);
841 WREG32(data_reg, 0x8018BFF8);
842 WREG32(index_reg, 0x20201);
843 WREG32(data_reg, 0x8F80BF08);
844 WREG32(index_reg, 0x20202);
845 WREG32(data_reg, 0xBFD081A0);
846 WREG32(index_reg, 0x20203);
847 WREG32(data_reg, 0xBFF88000);
848 WREG32(index_reg, 0x20300);
849 WREG32(data_reg, 0x80188000);
850 WREG32(index_reg, 0x20301);
851 WREG32(data_reg, 0x8EE0BEC0);
852 WREG32(index_reg, 0x20302);
853 WREG32(data_reg, 0xBFB082A0);
854 WREG32(index_reg, 0x20303);
855 WREG32(data_reg, 0x80008000);
856 WREG32(index_reg, 0x20400);
857 WREG32(data_reg, 0x80188000);
858 WREG32(index_reg, 0x20401);
859 WREG32(data_reg, 0x8E00BEA0);
860 WREG32(index_reg, 0x20402);
861 WREG32(data_reg, 0xBF8883C0);
862 WREG32(index_reg, 0x20403);
863 WREG32(data_reg, 0x80008000);
864 WREG32(index_reg, 0x20500);
865 WREG32(data_reg, 0x80188000);
866 WREG32(index_reg, 0x20501);
867 WREG32(data_reg, 0x8D00BE90);
868 WREG32(index_reg, 0x20502);
869 WREG32(data_reg, 0xBF588500);
870 WREG32(index_reg, 0x20503);
871 WREG32(data_reg, 0x80008008);
872 WREG32(index_reg, 0x20600);
873 WREG32(data_reg, 0x80188000);
874 WREG32(index_reg, 0x20601);
875 WREG32(data_reg, 0x8BC0BE98);
876 WREG32(index_reg, 0x20602);
877 WREG32(data_reg, 0xBF308660);
878 WREG32(index_reg, 0x20603);
879 WREG32(data_reg, 0x80008008);
880 WREG32(index_reg, 0x20700);
881 WREG32(data_reg, 0x80108000);
882 WREG32(index_reg, 0x20701);
883 WREG32(data_reg, 0x8A80BEB0);
884 WREG32(index_reg, 0x20702);
885 WREG32(data_reg, 0xBF0087C0);
886 WREG32(index_reg, 0x20703);
887 WREG32(data_reg, 0x80008008);
888 WREG32(index_reg, 0x20800);
889 WREG32(data_reg, 0x80108000);
890 WREG32(index_reg, 0x20801);
891 WREG32(data_reg, 0x8920BED0);
892 WREG32(index_reg, 0x20802);
893 WREG32(data_reg, 0xBED08920);
894 WREG32(index_reg, 0x20803);
895 WREG32(data_reg, 0x80008010);
896 WREG32(index_reg, 0x30000);
897 WREG32(data_reg, 0x90008000);
898 WREG32(index_reg, 0x30001);
899 WREG32(data_reg, 0x80008000);
900 WREG32(index_reg, 0x30100);
901 WREG32(data_reg, 0x8FE0BF90);
902 WREG32(index_reg, 0x30101);
903 WREG32(data_reg, 0xBFF880A0);
904 WREG32(index_reg, 0x30200);
905 WREG32(data_reg, 0x8F60BF40);
906 WREG32(index_reg, 0x30201);
907 WREG32(data_reg, 0xBFE88180);
908 WREG32(index_reg, 0x30300);
909 WREG32(data_reg, 0x8EC0BF00);
910 WREG32(index_reg, 0x30301);
911 WREG32(data_reg, 0xBFC88280);
912 WREG32(index_reg, 0x30400);
913 WREG32(data_reg, 0x8DE0BEE0);
914 WREG32(index_reg, 0x30401);
915 WREG32(data_reg, 0xBFA083A0);
916 WREG32(index_reg, 0x30500);
917 WREG32(data_reg, 0x8CE0BED0);
918 WREG32(index_reg, 0x30501);
919 WREG32(data_reg, 0xBF7884E0);
920 WREG32(index_reg, 0x30600);
921 WREG32(data_reg, 0x8BA0BED8);
922 WREG32(index_reg, 0x30601);
923 WREG32(data_reg, 0xBF508640);
924 WREG32(index_reg, 0x30700);
925 WREG32(data_reg, 0x8A60BEE8);
926 WREG32(index_reg, 0x30701);
927 WREG32(data_reg, 0xBF2087A0);
928 WREG32(index_reg, 0x30800);
929 WREG32(data_reg, 0x8900BF00);
930 WREG32(index_reg, 0x30801);
931 WREG32(data_reg, 0xBF008900);
932 }
933
934 struct rv515_watermark {
935 u32 lb_request_fifo_depth;
936 fixed20_12 num_line_pair;
937 fixed20_12 estimated_width;
938 fixed20_12 worst_case_latency;
939 fixed20_12 consumption_rate;
940 fixed20_12 active_time;
941 fixed20_12 dbpp;
942 fixed20_12 priority_mark_max;
943 fixed20_12 priority_mark;
944 fixed20_12 sclk;
945 };
946
947 static void rv515_crtc_bandwidth_compute(struct radeon_device *rdev,
948 struct radeon_crtc *crtc,
949 struct rv515_watermark *wm,
950 bool low)
951 {
952 struct drm_display_mode *mode = &crtc->base.mode;
953 fixed20_12 a, b, c;
954 fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
955 fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
956 fixed20_12 sclk;
957 u32 selected_sclk;
958
959 bzero(wm, sizeof(*wm)); /* avoid gcc warning */
960 if (!crtc->base.enabled) {
961 /* FIXME: wouldn't it better to set priority mark to maximum */
962 wm->lb_request_fifo_depth = 4;
963 return;
964 }
965
966 /* rv6xx, rv7xx */
967 if ((rdev->family >= CHIP_RV610) &&
968 (rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled)
969 selected_sclk = radeon_dpm_get_sclk(rdev, low);
970 else
971 selected_sclk = rdev->pm.current_sclk;
972
973 /* sclk in Mhz */
974 a.full = dfixed_const(100);
975 sclk.full = dfixed_const(selected_sclk);
976 sclk.full = dfixed_div(sclk, a);
977
978 if (crtc->vsc.full > dfixed_const(2))
979 wm->num_line_pair.full = dfixed_const(2);
980 else
981 wm->num_line_pair.full = dfixed_const(1);
982
983 b.full = dfixed_const(mode->crtc_hdisplay);
984 c.full = dfixed_const(256);
985 a.full = dfixed_div(b, c);
986 request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair);
987 request_fifo_depth.full = dfixed_ceil(request_fifo_depth);
988 if (a.full < dfixed_const(4)) {
989 wm->lb_request_fifo_depth = 4;
990 } else {
991 wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth);
992 }
993
994 /* Determine consumption rate
995 * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
996 * vtaps = number of vertical taps,
997 * vsc = vertical scaling ratio, defined as source/destination
998 * hsc = horizontal scaling ration, defined as source/destination
999 */
1000 a.full = dfixed_const(mode->clock);
1001 b.full = dfixed_const(1000);
1002 a.full = dfixed_div(a, b);
1003 pclk.full = dfixed_div(b, a);
1004 if (crtc->rmx_type != RMX_OFF) {
1005 b.full = dfixed_const(2);
1006 if (crtc->vsc.full > b.full)
1007 b.full = crtc->vsc.full;
1008 b.full = dfixed_mul(b, crtc->hsc);
1009 c.full = dfixed_const(2);
1010 b.full = dfixed_div(b, c);
1011 consumption_time.full = dfixed_div(pclk, b);
1012 } else {
1013 consumption_time.full = pclk.full;
1014 }
1015 a.full = dfixed_const(1);
1016 wm->consumption_rate.full = dfixed_div(a, consumption_time);
1017
1018
1019 /* Determine line time
1020 * LineTime = total time for one line of displayhtotal
1021 * LineTime = total number of horizontal pixels
1022 * pclk = pixel clock period(ns)
1023 */
1024 a.full = dfixed_const(crtc->base.mode.crtc_htotal);
1025 line_time.full = dfixed_mul(a, pclk);
1026
1027 /* Determine active time
1028 * ActiveTime = time of active region of display within one line,
1029 * hactive = total number of horizontal active pixels
1030 * htotal = total number of horizontal pixels
1031 */
1032 a.full = dfixed_const(crtc->base.mode.crtc_htotal);
1033 b.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
1034 wm->active_time.full = dfixed_mul(line_time, b);
1035 wm->active_time.full = dfixed_div(wm->active_time, a);
1036
1037 /* Determine chunk time
1038 * ChunkTime = the time it takes the DCP to send one chunk of data
1039 * to the LB which consists of pipeline delay and inter chunk gap
1040 * sclk = system clock(Mhz)
1041 */
1042 a.full = dfixed_const(600 * 1000);
1043 chunk_time.full = dfixed_div(a, sclk);
1044 read_delay_latency.full = dfixed_const(1000);
1045
1046 /* Determine the worst case latency
1047 * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
1048 * WorstCaseLatency = worst case time from urgent to when the MC starts
1049 * to return data
1050 * READ_DELAY_IDLE_MAX = constant of 1us
1051 * ChunkTime = time it takes the DCP to send one chunk of data to the LB
1052 * which consists of pipeline delay and inter chunk gap
1053 */
1054 if (dfixed_trunc(wm->num_line_pair) > 1) {
1055 a.full = dfixed_const(3);
1056 wm->worst_case_latency.full = dfixed_mul(a, chunk_time);
1057 wm->worst_case_latency.full += read_delay_latency.full;
1058 } else {
1059 wm->worst_case_latency.full = chunk_time.full + read_delay_latency.full;
1060 }
1061
1062 /* Determine the tolerable latency
1063 * TolerableLatency = Any given request has only 1 line time
1064 * for the data to be returned
1065 * LBRequestFifoDepth = Number of chunk requests the LB can
1066 * put into the request FIFO for a display
1067 * LineTime = total time for one line of display
1068 * ChunkTime = the time it takes the DCP to send one chunk
1069 * of data to the LB which consists of
1070 * pipeline delay and inter chunk gap
1071 */
1072 if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) {
1073 tolerable_latency.full = line_time.full;
1074 } else {
1075 tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2);
1076 tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full;
1077 tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time);
1078 tolerable_latency.full = line_time.full - tolerable_latency.full;
1079 }
1080 /* We assume worst case 32bits (4 bytes) */
1081 wm->dbpp.full = dfixed_const(2 * 16);
1082
1083 /* Determine the maximum priority mark
1084 * width = viewport width in pixels
1085 */
1086 a.full = dfixed_const(16);
1087 wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
1088 wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a);
1089 wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max);
1090
1091 /* Determine estimated width */
1092 estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
1093 estimated_width.full = dfixed_div(estimated_width, consumption_time);
1094 if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
1095 wm->priority_mark.full = wm->priority_mark_max.full;
1096 } else {
1097 a.full = dfixed_const(16);
1098 wm->priority_mark.full = dfixed_div(estimated_width, a);
1099 wm->priority_mark.full = dfixed_ceil(wm->priority_mark);
1100 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
1101 }
1102 }
1103
1104 static void rv515_compute_mode_priority(struct radeon_device *rdev,
1105 struct rv515_watermark *wm0,
1106 struct rv515_watermark *wm1,
1107 struct drm_display_mode *mode0,
1108 struct drm_display_mode *mode1,
1109 u32 *d1mode_priority_a_cnt,
1110 u32 *d2mode_priority_a_cnt)
1111 {
1112 fixed20_12 priority_mark02, priority_mark12, fill_rate;
1113 fixed20_12 a, b;
1114
1115 *d1mode_priority_a_cnt = MODE_PRIORITY_OFF;
1116 *d2mode_priority_a_cnt = MODE_PRIORITY_OFF;
1117
1118 if (mode0 && mode1) {
1119 if (dfixed_trunc(wm0->dbpp) > 64)
1120 a.full = dfixed_div(wm0->dbpp, wm0->num_line_pair);
1121 else
1122 a.full = wm0->num_line_pair.full;
1123 if (dfixed_trunc(wm1->dbpp) > 64)
1124 b.full = dfixed_div(wm1->dbpp, wm1->num_line_pair);
1125 else
1126 b.full = wm1->num_line_pair.full;
1127 a.full += b.full;
1128 fill_rate.full = dfixed_div(wm0->sclk, a);
1129 if (wm0->consumption_rate.full > fill_rate.full) {
1130 b.full = wm0->consumption_rate.full - fill_rate.full;
1131 b.full = dfixed_mul(b, wm0->active_time);
1132 a.full = dfixed_const(16);
1133 b.full = dfixed_div(b, a);
1134 a.full = dfixed_mul(wm0->worst_case_latency,
1135 wm0->consumption_rate);
1136 priority_mark02.full = a.full + b.full;
1137 } else {
1138 a.full = dfixed_mul(wm0->worst_case_latency,
1139 wm0->consumption_rate);
1140 b.full = dfixed_const(16 * 1000);
1141 priority_mark02.full = dfixed_div(a, b);
1142 }
1143 if (wm1->consumption_rate.full > fill_rate.full) {
1144 b.full = wm1->consumption_rate.full - fill_rate.full;
1145 b.full = dfixed_mul(b, wm1->active_time);
1146 a.full = dfixed_const(16);
1147 b.full = dfixed_div(b, a);
1148 a.full = dfixed_mul(wm1->worst_case_latency,
1149 wm1->consumption_rate);
1150 priority_mark12.full = a.full + b.full;
1151 } else {
1152 a.full = dfixed_mul(wm1->worst_case_latency,
1153 wm1->consumption_rate);
1154 b.full = dfixed_const(16 * 1000);
1155 priority_mark12.full = dfixed_div(a, b);
1156 }
1157 if (wm0->priority_mark.full > priority_mark02.full)
1158 priority_mark02.full = wm0->priority_mark.full;
1159 if (wm0->priority_mark_max.full > priority_mark02.full)
1160 priority_mark02.full = wm0->priority_mark_max.full;
1161 if (wm1->priority_mark.full > priority_mark12.full)
1162 priority_mark12.full = wm1->priority_mark.full;
1163 if (wm1->priority_mark_max.full > priority_mark12.full)
1164 priority_mark12.full = wm1->priority_mark_max.full;
1165 *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
1166 *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
1167 if (rdev->disp_priority == 2) {
1168 *d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1169 *d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1170 }
1171 } else if (mode0) {
1172 if (dfixed_trunc(wm0->dbpp) > 64)
1173 a.full = dfixed_div(wm0->dbpp, wm0->num_line_pair);
1174 else
1175 a.full = wm0->num_line_pair.full;
1176 fill_rate.full = dfixed_div(wm0->sclk, a);
1177 if (wm0->consumption_rate.full > fill_rate.full) {
1178 b.full = wm0->consumption_rate.full - fill_rate.full;
1179 b.full = dfixed_mul(b, wm0->active_time);
1180 a.full = dfixed_const(16);
1181 b.full = dfixed_div(b, a);
1182 a.full = dfixed_mul(wm0->worst_case_latency,
1183 wm0->consumption_rate);
1184 priority_mark02.full = a.full + b.full;
1185 } else {
1186 a.full = dfixed_mul(wm0->worst_case_latency,
1187 wm0->consumption_rate);
1188 b.full = dfixed_const(16);
1189 priority_mark02.full = dfixed_div(a, b);
1190 }
1191 if (wm0->priority_mark.full > priority_mark02.full)
1192 priority_mark02.full = wm0->priority_mark.full;
1193 if (wm0->priority_mark_max.full > priority_mark02.full)
1194 priority_mark02.full = wm0->priority_mark_max.full;
1195 *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
1196 if (rdev->disp_priority == 2)
1197 *d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1198 } else if (mode1) {
1199 if (dfixed_trunc(wm1->dbpp) > 64)
1200 a.full = dfixed_div(wm1->dbpp, wm1->num_line_pair);
1201 else
1202 a.full = wm1->num_line_pair.full;
1203 fill_rate.full = dfixed_div(wm1->sclk, a);
1204 if (wm1->consumption_rate.full > fill_rate.full) {
1205 b.full = wm1->consumption_rate.full - fill_rate.full;
1206 b.full = dfixed_mul(b, wm1->active_time);
1207 a.full = dfixed_const(16);
1208 b.full = dfixed_div(b, a);
1209 a.full = dfixed_mul(wm1->worst_case_latency,
1210 wm1->consumption_rate);
1211 priority_mark12.full = a.full + b.full;
1212 } else {
1213 a.full = dfixed_mul(wm1->worst_case_latency,
1214 wm1->consumption_rate);
1215 b.full = dfixed_const(16 * 1000);
1216 priority_mark12.full = dfixed_div(a, b);
1217 }
1218 if (wm1->priority_mark.full > priority_mark12.full)
1219 priority_mark12.full = wm1->priority_mark.full;
1220 if (wm1->priority_mark_max.full > priority_mark12.full)
1221 priority_mark12.full = wm1->priority_mark_max.full;
1222 *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
1223 if (rdev->disp_priority == 2)
1224 *d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1225 }
1226 }
1227
1228 void rv515_bandwidth_avivo_update(struct radeon_device *rdev)
1229 {
1230 struct drm_display_mode *mode0 = NULL;
1231 struct drm_display_mode *mode1 = NULL;
1232 struct rv515_watermark wm0_high, wm0_low;
1233 struct rv515_watermark wm1_high, wm1_low;
1234 u32 tmp;
1235 u32 d1mode_priority_a_cnt, d1mode_priority_b_cnt;
1236 u32 d2mode_priority_a_cnt, d2mode_priority_b_cnt;
1237
1238 if (rdev->mode_info.crtcs[0]->base.enabled)
1239 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
1240 if (rdev->mode_info.crtcs[1]->base.enabled)
1241 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
1242 rs690_line_buffer_adjust(rdev, mode0, mode1);
1243
1244 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_high, false);
1245 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_high, false);
1246
1247 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_low, false);
1248 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_low, false);
1249
1250 tmp = wm0_high.lb_request_fifo_depth;
1251 tmp |= wm1_high.lb_request_fifo_depth << 16;
1252 WREG32(LB_MAX_REQ_OUTSTANDING, tmp);
1253
1254 rv515_compute_mode_priority(rdev,
1255 &wm0_high, &wm1_high,
1256 mode0, mode1,
1257 &d1mode_priority_a_cnt, &d2mode_priority_a_cnt);
1258 rv515_compute_mode_priority(rdev,
1259 &wm0_low, &wm1_low,
1260 mode0, mode1,
1261 &d1mode_priority_b_cnt, &d2mode_priority_b_cnt);
1262
1263 WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
1264 WREG32(D1MODE_PRIORITY_B_CNT, d1mode_priority_b_cnt);
1265 WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
1266 WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_b_cnt);
1267 }
1268
1269 void rv515_bandwidth_update(struct radeon_device *rdev)
1270 {
1271 uint32_t tmp;
1272 struct drm_display_mode *mode0 = NULL;
1273 struct drm_display_mode *mode1 = NULL;
1274
1275 if (!rdev->mode_info.mode_config_initialized)
1276 return;
1277
1278 radeon_update_display_priority(rdev);
1279
1280 if (rdev->mode_info.crtcs[0]->base.enabled)
1281 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
1282 if (rdev->mode_info.crtcs[1]->base.enabled)
1283 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
1284 /*
1285 * Set display0/1 priority up in the memory controller for
1286 * modes if the user specifies HIGH for displaypriority
1287 * option.
1288 */
1289 if ((rdev->disp_priority == 2) &&
1290 (rdev->family == CHIP_RV515)) {
1291 tmp = RREG32_MC(MC_MISC_LAT_TIMER);
1292 tmp &= ~MC_DISP1R_INIT_LAT_MASK;
1293 tmp &= ~MC_DISP0R_INIT_LAT_MASK;
1294 if (mode1)
1295 tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT);
1296 if (mode0)
1297 tmp |= (1 << MC_DISP0R_INIT_LAT_SHIFT);
1298 WREG32_MC(MC_MISC_LAT_TIMER, tmp);
1299 }
1300 rv515_bandwidth_avivo_update(rdev);
1301 }
DragonFly BSD