sys/dev/drm/radeon/radeon_mode.h

   1 /*
   2  * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
   3  *                VA Linux Systems Inc., Fremont, California.
   4  * Copyright 2008 Red Hat Inc.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Original Authors:
  25  *   Kevin E. Martin, Rickard E. Faith, Alan Hourihane
  26  *
  27  * Kernel port Author: Dave Airlie
  28  */
  29
  30 #ifndef RADEON_MODE_H
  31 #define RADEON_MODE_H
  32
  33 #include <drm/drm_crtc.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drm_dp_helper.h>
  36 #include <drm/drm_fixed.h>
  37 #include <drm/drm_crtc_helper.h>
  38
  39 struct radeon_bo;
  40 struct radeon_device;
  41
  42 #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base)
  43 #define to_radeon_connector(x) container_of(x, struct radeon_connector, base)
  44 #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base)
  45 #define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base)
  46
  47 #define RADEON_MAX_HPD_PINS 7
  48 #define RADEON_MAX_CRTCS 6
  49 #define RADEON_MAX_AFMT_BLOCKS 7
  50
  51 enum radeon_rmx_type {
  52         RMX_OFF,
  53         RMX_FULL,
  54         RMX_CENTER,
  55         RMX_ASPECT
  56 };
  57
  58 enum radeon_tv_std {
  59         TV_STD_NTSC,
  60         TV_STD_PAL,
  61         TV_STD_PAL_M,
  62         TV_STD_PAL_60,
  63         TV_STD_NTSC_J,
  64         TV_STD_SCART_PAL,
  65         TV_STD_SECAM,
  66         TV_STD_PAL_CN,
  67         TV_STD_PAL_N,
  68 };
  69
  70 enum radeon_underscan_type {
  71         UNDERSCAN_OFF,
  72         UNDERSCAN_ON,
  73         UNDERSCAN_AUTO,
  74 };
  75
  76 enum radeon_hpd_id {
  77         RADEON_HPD_1 = 0,
  78         RADEON_HPD_2,
  79         RADEON_HPD_3,
  80         RADEON_HPD_4,
  81         RADEON_HPD_5,
  82         RADEON_HPD_6,
  83         RADEON_HPD_NONE = 0xff,
  84 };
  85
  86 #define RADEON_MAX_I2C_BUS 16
  87
  88 /* radeon gpio-based i2c
  89  * 1. "mask" reg and bits
  90  *    grabs the gpio pins for software use
  91  *    0=not held  1=held
  92  * 2. "a" reg and bits
  93  *    output pin value
  94  *    0=low 1=high
  95  * 3. "en" reg and bits
  96  *    sets the pin direction
  97  *    0=input 1=output
  98  * 4. "y" reg and bits
  99  *    input pin value
 100  *    0=low 1=high
 101  */
 102 struct radeon_i2c_bus_rec {
 103         bool valid;
 104         /* id used by atom */
 105         uint8_t i2c_id;
 106         /* id used by atom */
 107         enum radeon_hpd_id hpd;
 108         /* can be used with hw i2c engine */
 109         bool hw_capable;
 110         /* uses multi-media i2c engine */
 111         bool mm_i2c;
 112         /* regs and bits */
 113         uint32_t mask_clk_reg;
 114         uint32_t mask_data_reg;
 115         uint32_t a_clk_reg;
 116         uint32_t a_data_reg;
 117         uint32_t en_clk_reg;
 118         uint32_t en_data_reg;
 119         uint32_t y_clk_reg;
 120         uint32_t y_data_reg;
 121         uint32_t mask_clk_mask;
 122         uint32_t mask_data_mask;
 123         uint32_t a_clk_mask;
 124         uint32_t a_data_mask;
 125         uint32_t en_clk_mask;
 126         uint32_t en_data_mask;
 127         uint32_t y_clk_mask;
 128         uint32_t y_data_mask;
 129 };
 130
 131 struct radeon_tmds_pll {
 132     uint32_t freq;
 133     uint32_t value;
 134 };
 135
 136 #define RADEON_MAX_BIOS_CONNECTOR 16
 137
 138 /* pll flags */
 139 #define RADEON_PLL_USE_BIOS_DIVS        (1 << 0)
 140 #define RADEON_PLL_NO_ODD_POST_DIV      (1 << 1)
 141 #define RADEON_PLL_USE_REF_DIV          (1 << 2)
 142 #define RADEON_PLL_LEGACY               (1 << 3)
 143 #define RADEON_PLL_PREFER_LOW_REF_DIV   (1 << 4)
 144 #define RADEON_PLL_PREFER_HIGH_REF_DIV  (1 << 5)
 145 #define RADEON_PLL_PREFER_LOW_FB_DIV    (1 << 6)
 146 #define RADEON_PLL_PREFER_HIGH_FB_DIV   (1 << 7)
 147 #define RADEON_PLL_PREFER_LOW_POST_DIV  (1 << 8)
 148 #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9)
 149 #define RADEON_PLL_USE_FRAC_FB_DIV      (1 << 10)
 150 #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11)
 151 #define RADEON_PLL_USE_POST_DIV         (1 << 12)
 152 #define RADEON_PLL_IS_LCD               (1 << 13)
 153 #define RADEON_PLL_PREFER_MINM_OVER_MAXP (1 << 14)
 154
 155 struct radeon_pll {
 156         /* reference frequency */
 157         uint32_t reference_freq;
 158
 159         /* fixed dividers */
 160         uint32_t reference_div;
 161         uint32_t post_div;
 162
 163         /* pll in/out limits */
 164         uint32_t pll_in_min;
 165         uint32_t pll_in_max;
 166         uint32_t pll_out_min;
 167         uint32_t pll_out_max;
 168         uint32_t lcd_pll_out_min;
 169         uint32_t lcd_pll_out_max;
 170         uint32_t best_vco;
 171
 172         /* divider limits */
 173         uint32_t min_ref_div;
 174         uint32_t max_ref_div;
 175         uint32_t min_post_div;
 176         uint32_t max_post_div;
 177         uint32_t min_feedback_div;
 178         uint32_t max_feedback_div;
 179         uint32_t min_frac_feedback_div;
 180         uint32_t max_frac_feedback_div;
 181
 182         /* flags for the current clock */
 183         uint32_t flags;
 184
 185         /* pll id */
 186         uint32_t id;
 187 };
 188
 189 struct radeon_i2c_chan {
 190         device_t adapter;
 191         device_t iic_bus;
 192         struct drm_device *dev;
 193         struct radeon_i2c_bus_rec rec;
 194         struct drm_dp_aux aux;
 195         struct lock mutex;
 196         char   name[48];
 197 };
 198
 199 /* mostly for macs, but really any system without connector tables */
 200 enum radeon_connector_table {
 201         CT_NONE = 0,
 202         CT_GENERIC,
 203         CT_IBOOK,
 204         CT_POWERBOOK_EXTERNAL,
 205         CT_POWERBOOK_INTERNAL,
 206         CT_POWERBOOK_VGA,
 207         CT_MINI_EXTERNAL,
 208         CT_MINI_INTERNAL,
 209         CT_IMAC_G5_ISIGHT,
 210         CT_EMAC,
 211         CT_RN50_POWER,
 212         CT_MAC_X800,
 213         CT_MAC_G5_9600,
 214         CT_SAM440EP,
 215         CT_MAC_G4_SILVER
 216 };
 217
 218 enum radeon_dvo_chip {
 219         DVO_SIL164,
 220         DVO_SIL1178,
 221 };
 222
 223 struct radeon_fbdev;
 224
 225 struct radeon_afmt {
 226         bool enabled;
 227         int offset;
 228         bool last_buffer_filled_status;
 229         int id;
 230         struct r600_audio_pin *pin;
 231 };
 232
 233 struct radeon_mode_info {
 234         struct atom_context *atom_context;
 235         struct card_info *atom_card_info;
 236         enum radeon_connector_table connector_table;
 237         bool mode_config_initialized;
 238         struct radeon_crtc *crtcs[RADEON_MAX_CRTCS];
 239         struct radeon_afmt *afmt[RADEON_MAX_AFMT_BLOCKS];
 240         /* DVI-I properties */
 241         struct drm_property *coherent_mode_property;
 242         /* DAC enable load detect */
 243         struct drm_property *load_detect_property;
 244         /* TV standard */
 245         struct drm_property *tv_std_property;
 246         /* legacy TMDS PLL detect */
 247         struct drm_property *tmds_pll_property;
 248         /* underscan */
 249         struct drm_property *underscan_property;
 250         struct drm_property *underscan_hborder_property;
 251         struct drm_property *underscan_vborder_property;
 252         /* audio */
 253         struct drm_property *audio_property;
 254         /* FMT dithering */
 255         struct drm_property *dither_property;
 256         /* hardcoded DFP edid from BIOS */
 257         struct edid *bios_hardcoded_edid;
 258         int bios_hardcoded_edid_size;
 259
 260         /* pointer to fbdev info structure */
 261         struct radeon_fbdev *rfbdev;
 262         /* firmware flags */
 263         u16 firmware_flags;
 264         /* pointer to backlight encoder */
 265         struct radeon_encoder *bl_encoder;
 266 };
 267
 268 #define RADEON_MAX_BL_LEVEL 0xFF
 269
 270 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
 271
 272 struct radeon_backlight_privdata {
 273         struct radeon_encoder *encoder;
 274         uint8_t negative;
 275 };
 276
 277 #endif
 278
 279 #define MAX_H_CODE_TIMING_LEN 32
 280 #define MAX_V_CODE_TIMING_LEN 32
 281
 282 /* need to store these as reading
 283    back code tables is excessive */
 284 struct radeon_tv_regs {
 285         uint32_t tv_uv_adr;
 286         uint32_t timing_cntl;
 287         uint32_t hrestart;
 288         uint32_t vrestart;
 289         uint32_t frestart;
 290         uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN];
 291         uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN];
 292 };
 293
 294 struct radeon_atom_ss {
 295         uint16_t percentage;
 296         uint16_t percentage_divider;
 297         uint8_t type;
 298         uint16_t step;
 299         uint8_t delay;
 300         uint8_t range;
 301         uint8_t refdiv;
 302         /* asic_ss */
 303         uint16_t rate;
 304         uint16_t amount;
 305 };
 306
 307 enum radeon_flip_status {
 308         RADEON_FLIP_NONE,
 309         RADEON_FLIP_PENDING,
 310         RADEON_FLIP_SUBMITTED
 311 };
 312
 313 struct radeon_crtc {
 314         struct drm_crtc base;
 315         int crtc_id;
 316         u16 lut_r[256], lut_g[256], lut_b[256];
 317         bool enabled;
 318         bool can_tile;
 319         uint32_t crtc_offset;
 320         struct drm_gem_object *cursor_bo;
 321         uint64_t cursor_addr;
 322         int cursor_width;
 323         int cursor_height;
 324         int max_cursor_width;
 325         int max_cursor_height;
 326         uint32_t legacy_display_base_addr;
 327         uint32_t legacy_cursor_offset;
 328         enum radeon_rmx_type rmx_type;
 329         u8 h_border;
 330         u8 v_border;
 331         fixed20_12 vsc;
 332         fixed20_12 hsc;
 333         struct drm_display_mode native_mode;
 334         int pll_id;
 335         /* page flipping */
 336         struct workqueue_struct *flip_queue;
 337         struct radeon_flip_work *flip_work;
 338         enum radeon_flip_status flip_status;
 339         /* pll sharing */
 340         struct radeon_atom_ss ss;
 341         bool ss_enabled;
 342         u32 adjusted_clock;
 343         int bpc;
 344         u32 pll_reference_div;
 345         u32 pll_post_div;
 346         u32 pll_flags;
 347         struct drm_encoder *encoder;
 348         struct drm_connector *connector;
 349         /* for dpm */
 350         u32 line_time;
 351         u32 wm_low;
 352         u32 wm_high;
 353         struct drm_display_mode hw_mode;
 354 };
 355
 356 struct radeon_encoder_primary_dac {
 357         /* legacy primary dac */
 358         uint32_t ps2_pdac_adj;
 359 };
 360
 361 struct radeon_encoder_lvds {
 362         /* legacy lvds */
 363         uint16_t panel_vcc_delay;
 364         uint8_t  panel_pwr_delay;
 365         uint8_t  panel_digon_delay;
 366         uint8_t  panel_blon_delay;
 367         uint16_t panel_ref_divider;
 368         uint8_t  panel_post_divider;
 369         uint16_t panel_fb_divider;
 370         bool     use_bios_dividers;
 371         uint32_t lvds_gen_cntl;
 372         /* panel mode */
 373         struct drm_display_mode native_mode;
 374         struct backlight_device *bl_dev;
 375         int      dpms_mode;
 376         uint8_t  backlight_level;
 377 };
 378
 379 struct radeon_encoder_tv_dac {
 380         /* legacy tv dac */
 381         uint32_t ps2_tvdac_adj;
 382         uint32_t ntsc_tvdac_adj;
 383         uint32_t pal_tvdac_adj;
 384
 385         int               h_pos;
 386         int               v_pos;
 387         int               h_size;
 388         int               supported_tv_stds;
 389         bool              tv_on;
 390         enum radeon_tv_std tv_std;
 391         struct radeon_tv_regs tv;
 392 };
 393
 394 struct radeon_encoder_int_tmds {
 395         /* legacy int tmds */
 396         struct radeon_tmds_pll tmds_pll[4];
 397 };
 398
 399 struct radeon_encoder_ext_tmds {
 400         /* tmds over dvo */
 401         struct radeon_i2c_chan *i2c_bus;
 402         uint8_t slave_addr;
 403         enum radeon_dvo_chip dvo_chip;
 404 };
 405
 406 /* spread spectrum */
 407 struct radeon_encoder_atom_dig {
 408         bool linkb;
 409         /* atom dig */
 410         bool coherent_mode;
 411         int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */
 412         /* atom lvds/edp */
 413         uint32_t lcd_misc;
 414         uint16_t panel_pwr_delay;
 415         uint32_t lcd_ss_id;
 416         /* panel mode */
 417         struct drm_display_mode native_mode;
 418         struct backlight_device *bl_dev;
 419         int dpms_mode;
 420         uint8_t backlight_level;
 421         int panel_mode;
 422         struct radeon_afmt *afmt;
 423 };
 424
 425 struct radeon_encoder_atom_dac {
 426         enum radeon_tv_std tv_std;
 427 };
 428
 429 struct radeon_encoder {
 430         struct drm_encoder base;
 431         uint32_t encoder_enum;
 432         uint32_t encoder_id;
 433         uint32_t devices;
 434         uint32_t active_device;
 435         uint32_t flags;
 436         uint32_t pixel_clock;
 437         enum radeon_rmx_type rmx_type;
 438         enum radeon_underscan_type underscan_type;
 439         uint32_t underscan_hborder;
 440         uint32_t underscan_vborder;
 441         struct drm_display_mode native_mode;
 442         void *enc_priv;
 443         int audio_polling_active;
 444         bool is_ext_encoder;
 445         u16 caps;
 446 };
 447
 448 struct radeon_connector_atom_dig {
 449         uint32_t igp_lane_info;
 450         /* displayport */
 451         struct radeon_i2c_chan *dp_i2c_bus;
 452         u8 dpcd[DP_RECEIVER_CAP_SIZE];
 453         u8 dp_sink_type;
 454         int dp_clock;
 455         int dp_lane_count;
 456         bool edp_on;
 457 };
 458
 459 struct radeon_gpio_rec {
 460         bool valid;
 461         u8 id;
 462         u32 reg;
 463         u32 mask;
 464 };
 465
 466 struct radeon_hpd {
 467         enum radeon_hpd_id hpd;
 468         u8 plugged_state;
 469         struct radeon_gpio_rec gpio;
 470 };
 471
 472 struct radeon_router {
 473         u32 router_id;
 474         struct radeon_i2c_bus_rec i2c_info;
 475         u8 i2c_addr;
 476         /* i2c mux */
 477         bool ddc_valid;
 478         u8 ddc_mux_type;
 479         u8 ddc_mux_control_pin;
 480         u8 ddc_mux_state;
 481         /* clock/data mux */
 482         bool cd_valid;
 483         u8 cd_mux_type;
 484         u8 cd_mux_control_pin;
 485         u8 cd_mux_state;
 486 };
 487
 488 enum radeon_connector_audio {
 489         RADEON_AUDIO_DISABLE = 0,
 490         RADEON_AUDIO_ENABLE = 1,
 491         RADEON_AUDIO_AUTO = 2
 492 };
 493
 494 enum radeon_connector_dither {
 495         RADEON_FMT_DITHER_DISABLE = 0,
 496         RADEON_FMT_DITHER_ENABLE = 1,
 497 };
 498
 499 struct radeon_connector {
 500         struct drm_connector base;
 501         uint32_t connector_id;
 502         uint32_t devices;
 503         struct radeon_i2c_chan *ddc_bus;
 504         /* some systems have an hdmi and vga port with a shared ddc line */
 505         bool shared_ddc;
 506         bool use_digital;
 507         /* we need to mind the EDID between detect
 508            and get modes due to analog/digital/tvencoder */
 509         struct edid *edid;
 510         void *con_priv;
 511         bool dac_load_detect;
 512         bool detected_by_load; /* if the connection status was determined by load */
 513         uint16_t connector_object_id;
 514         struct radeon_hpd hpd;
 515         struct radeon_router router;
 516         struct radeon_i2c_chan *router_bus;
 517         enum radeon_connector_audio audio;
 518         enum radeon_connector_dither dither;
 519         int pixelclock_for_modeset;
 520 };
 521
 522 struct radeon_framebuffer {
 523         struct drm_framebuffer base;
 524         struct drm_gem_object *obj;
 525 };
 526
 527 #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \
 528                                 ((em) == ATOM_ENCODER_MODE_DP_MST))
 529
 530 struct atom_clock_dividers {
 531         u32 post_div;
 532         union {
 533                 struct {
 534 #ifdef __BIG_ENDIAN
 535                         u32 reserved : 6;
 536                         u32 whole_fb_div : 12;
 537                         u32 frac_fb_div : 14;
 538 #else
 539                         u32 frac_fb_div : 14;
 540                         u32 whole_fb_div : 12;
 541                         u32 reserved : 6;
 542 #endif
 543                 };
 544                 u32 fb_div;
 545         };
 546         u32 ref_div;
 547         bool enable_post_div;
 548         bool enable_dithen;
 549         u32 vco_mode;
 550         u32 real_clock;
 551         /* added for CI */
 552         u32 post_divider;
 553         u32 flags;
 554 };
 555
 556 struct atom_mpll_param {
 557         union {
 558                 struct {
 559 #ifdef __BIG_ENDIAN
 560                         u32 reserved : 8;
 561                         u32 clkfrac : 12;
 562                         u32 clkf : 12;
 563 #else
 564                         u32 clkf : 12;
 565                         u32 clkfrac : 12;
 566                         u32 reserved : 8;
 567 #endif
 568                 };
 569                 u32 fb_div;
 570         };
 571         u32 post_div;
 572         u32 bwcntl;
 573         u32 dll_speed;
 574         u32 vco_mode;
 575         u32 yclk_sel;
 576         u32 qdr;
 577         u32 half_rate;
 578 };
 579
 580 #define MEM_TYPE_GDDR5  0x50
 581 #define MEM_TYPE_GDDR4  0x40
 582 #define MEM_TYPE_GDDR3  0x30
 583 #define MEM_TYPE_DDR2   0x20
 584 #define MEM_TYPE_GDDR1  0x10
 585 #define MEM_TYPE_DDR3   0xb0
 586 #define MEM_TYPE_MASK   0xf0
 587
 588 struct atom_memory_info {
 589         u8 mem_vendor;
 590         u8 mem_type;
 591 };
 592
 593 #define MAX_AC_TIMING_ENTRIES 16
 594
 595 struct atom_memory_clock_range_table
 596 {
 597         u8 num_entries;
 598         u8 rsv[3];
 599         u32 mclk[MAX_AC_TIMING_ENTRIES];
 600 };
 601
 602 #define VBIOS_MC_REGISTER_ARRAY_SIZE 32
 603 #define VBIOS_MAX_AC_TIMING_ENTRIES 20
 604
 605 struct atom_mc_reg_entry {
 606         u32 mclk_max;
 607         u32 mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE];
 608 };
 609
 610 struct atom_mc_register_address {
 611         u16 s1;
 612         u8 pre_reg_data;
 613 };
 614
 615 struct atom_mc_reg_table {
 616         u8 last;
 617         u8 num_entries;
 618         struct atom_mc_reg_entry mc_reg_table_entry[VBIOS_MAX_AC_TIMING_ENTRIES];
 619         struct atom_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE];
 620 };
 621
 622 #define MAX_VOLTAGE_ENTRIES 32
 623
 624 struct atom_voltage_table_entry
 625 {
 626         u16 value;
 627         u32 smio_low;
 628 };
 629
 630 struct atom_voltage_table
 631 {
 632         u32 count;
 633         u32 mask_low;
 634         u32 phase_delay;
 635         struct atom_voltage_table_entry entries[MAX_VOLTAGE_ENTRIES];
 636 };
 637
 638 /* Driver internal use only flags of radeon_get_crtc_scanoutpos() */
 639 #define USE_REAL_VBLANKSTART            (1 << 30)
 640 #define GET_DISTANCE_TO_VBLANKSTART     (1 << 31)
 641
 642 extern void
 643 radeon_add_atom_connector(struct drm_device *dev,
 644                           uint32_t connector_id,
 645                           uint32_t supported_device,
 646                           int connector_type,
 647                           struct radeon_i2c_bus_rec *i2c_bus,
 648                           uint32_t igp_lane_info,
 649                           uint16_t connector_object_id,
 650                           struct radeon_hpd *hpd,
 651                           struct radeon_router *router);
 652 extern void
 653 radeon_add_legacy_connector(struct drm_device *dev,
 654                             uint32_t connector_id,
 655                             uint32_t supported_device,
 656                             int connector_type,
 657                             struct radeon_i2c_bus_rec *i2c_bus,
 658                             uint16_t connector_object_id,
 659                             struct radeon_hpd *hpd);
 660 extern uint32_t
 661 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
 662                         uint8_t dac);
 663 extern void radeon_link_encoder_connector(struct drm_device *dev);
 664
 665 extern enum radeon_tv_std
 666 radeon_combios_get_tv_info(struct radeon_device *rdev);
 667 extern enum radeon_tv_std
 668 radeon_atombios_get_tv_info(struct radeon_device *rdev);
 669 extern void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
 670                                                  u16 *vddc, u16 *vddci, u16 *mvdd);
 671
 672 extern void
 673 radeon_combios_connected_scratch_regs(struct drm_connector *connector,
 674                                       struct drm_encoder *encoder,
 675                                       bool connected);
 676 extern void
 677 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
 678                                        struct drm_encoder *encoder,
 679                                        bool connected);
 680
 681 extern struct drm_connector *
 682 radeon_get_connector_for_encoder(struct drm_encoder *encoder);
 683 extern struct drm_connector *
 684 radeon_get_connector_for_encoder_init(struct drm_encoder *encoder);
 685 extern bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder,
 686                                     u32 pixel_clock);
 687
 688 extern u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder);
 689 extern u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector);
 690 extern bool radeon_connector_is_dp12_capable(struct drm_connector *connector);
 691 extern int radeon_get_monitor_bpc(struct drm_connector *connector);
 692
 693 extern struct edid *radeon_connector_edid(struct drm_connector *connector);
 694
 695 extern void radeon_connector_hotplug(struct drm_connector *connector);
 696 extern int radeon_dp_mode_valid_helper(struct drm_connector *connector,
 697                                        struct drm_display_mode *mode);
 698 extern void radeon_dp_set_link_config(struct drm_connector *connector,
 699                                       const struct drm_display_mode *mode);
 700 extern void radeon_dp_link_train(struct drm_encoder *encoder,
 701                                  struct drm_connector *connector);
 702 extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector);
 703 extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector);
 704 extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector);
 705 extern int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
 706                                     struct drm_connector *connector);
 707 extern void radeon_dp_set_rx_power_state(struct drm_connector *connector,
 708                                          u8 power_state);
 709 extern void radeon_dp_aux_init(struct radeon_connector *radeon_connector);
 710 extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode);
 711 extern void radeon_atom_encoder_init(struct radeon_device *rdev);
 712 extern void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev);
 713 extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder,
 714                                            int action, uint8_t lane_num,
 715                                            uint8_t lane_set);
 716 extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder);
 717 extern struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder);
 718 extern int radeon_dp_i2c_aux_ch(device_t dev, int mode,
 719                                 u8 write_byte, u8 *read_byte);
 720 void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le);
 721
 722 extern void radeon_i2c_init(struct radeon_device *rdev);
 723 extern void radeon_i2c_fini(struct radeon_device *rdev);
 724 extern void radeon_combios_i2c_init(struct radeon_device *rdev);
 725 extern void radeon_atombios_i2c_init(struct radeon_device *rdev);
 726 extern void radeon_i2c_add(struct radeon_device *rdev,
 727                            struct radeon_i2c_bus_rec *rec,
 728                            const char *name);
 729 extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev,
 730                                                  struct radeon_i2c_bus_rec *i2c_bus);
 731 extern struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev,
 732                                                     struct radeon_i2c_bus_rec *rec,
 733                                                     const char *name);
 734 extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
 735                                                  struct radeon_i2c_bus_rec *rec,
 736                                                  const char *name);
 737 extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c);
 738 extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
 739                                 u8 slave_addr,
 740                                 u8 addr,
 741                                 u8 *val);
 742 extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c,
 743                                 u8 slave_addr,
 744                                 u8 addr,
 745                                 u8 val);
 746 extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector);
 747 extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector);
 748 extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux);
 749
 750 extern bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
 751                                              struct radeon_atom_ss *ss,
 752                                              int id);
 753 extern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
 754                                              struct radeon_atom_ss *ss,
 755                                              int id, u32 clock);
 756
 757 extern void radeon_compute_pll_legacy(struct radeon_pll *pll,
 758                                       uint64_t freq,
 759                                       uint32_t *dot_clock_p,
 760                                       uint32_t *fb_div_p,
 761                                       uint32_t *frac_fb_div_p,
 762                                       uint32_t *ref_div_p,
 763                                       uint32_t *post_div_p);
 764
 765 extern void radeon_compute_pll_avivo(struct radeon_pll *pll,
 766                                      u32 freq,
 767                                      u32 *dot_clock_p,
 768                                      u32 *fb_div_p,
 769                                      u32 *frac_fb_div_p,
 770                                      u32 *ref_div_p,
 771                                      u32 *post_div_p);
 772
 773 extern void radeon_setup_encoder_clones(struct drm_device *dev);
 774
 775 struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index);
 776 struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv);
 777 struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv);
 778 struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index);
 779 struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index);
 780 extern void atombios_dvo_setup(struct drm_encoder *encoder, int action);
 781 extern void atombios_digital_setup(struct drm_encoder *encoder, int action);
 782 extern int atombios_get_encoder_mode(struct drm_encoder *encoder);
 783 extern bool atombios_set_edp_panel_power(struct drm_connector *connector, int action);
 784 extern void radeon_encoder_set_active_device(struct drm_encoder *encoder);
 785 extern bool radeon_encoder_is_digital(struct drm_encoder *encoder);
 786
 787 extern void radeon_crtc_load_lut(struct drm_crtc *crtc);
 788 extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
 789                                    struct drm_framebuffer *old_fb);
 790 extern int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
 791                                          struct drm_framebuffer *fb,
 792                                          int x, int y,
 793                                          enum mode_set_atomic state);
 794 extern int atombios_crtc_mode_set(struct drm_crtc *crtc,
 795                                    struct drm_display_mode *mode,
 796                                    struct drm_display_mode *adjusted_mode,
 797                                    int x, int y,
 798                                    struct drm_framebuffer *old_fb);
 799 extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode);
 800
 801 extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
 802                                  struct drm_framebuffer *old_fb);
 803 extern int radeon_crtc_set_base_atomic(struct drm_crtc *crtc,
 804                                        struct drm_framebuffer *fb,
 805                                        int x, int y,
 806                                        enum mode_set_atomic state);
 807 extern int radeon_crtc_do_set_base(struct drm_crtc *crtc,
 808                                    struct drm_framebuffer *fb,
 809                                    int x, int y, int atomic);
 810 extern int radeon_crtc_cursor_set(struct drm_crtc *crtc,
 811                                   struct drm_file *file_priv,
 812                                   uint32_t handle,
 813                                   uint32_t width,
 814                                   uint32_t height);
 815 extern int radeon_crtc_cursor_move(struct drm_crtc *crtc,
 816                                    int x, int y);
 817
 818 extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc,
 819                                       unsigned int flags,
 820                                       int *vpos, int *hpos,
 821                                       ktime_t *stime, ktime_t *etime,
 822                                       const struct drm_display_mode *mode);
 823
 824 extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev);
 825 extern struct edid *
 826 radeon_bios_get_hardcoded_edid(struct radeon_device *rdev);
 827 extern bool radeon_atom_get_clock_info(struct drm_device *dev);
 828 extern bool radeon_combios_get_clock_info(struct drm_device *dev);
 829 extern struct radeon_encoder_atom_dig *
 830 radeon_atombios_get_lvds_info(struct radeon_encoder *encoder);
 831 extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
 832                                           struct radeon_encoder_int_tmds *tmds);
 833 extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
 834                                                      struct radeon_encoder_int_tmds *tmds);
 835 extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
 836                                                    struct radeon_encoder_int_tmds *tmds);
 837 extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
 838                                                          struct radeon_encoder_ext_tmds *tmds);
 839 extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
 840                                                        struct radeon_encoder_ext_tmds *tmds);
 841 extern struct radeon_encoder_primary_dac *
 842 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder);
 843 extern struct radeon_encoder_tv_dac *
 844 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder);
 845 extern struct radeon_encoder_lvds *
 846 radeon_combios_get_lvds_info(struct radeon_encoder *encoder);
 847 extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder);
 848 extern struct radeon_encoder_tv_dac *
 849 radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder);
 850 extern struct radeon_encoder_primary_dac *
 851 radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder);
 852 extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder);
 853 extern void radeon_external_tmds_setup(struct drm_encoder *encoder);
 854 extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock);
 855 extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev);
 856 extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock);
 857 extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev);
 858 extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev);
 859 extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev);
 860 extern void
 861 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
 862 extern void
 863 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
 864 extern void
 865 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
 866 extern void
 867 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
 868 extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
 869                                      u16 blue, int regno);
 870 extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
 871                                      u16 *blue, int regno);
 872 int radeon_framebuffer_init(struct drm_device *dev,
 873                              struct radeon_framebuffer *rfb,
 874                              const struct drm_mode_fb_cmd2 *mode_cmd,
 875                              struct drm_gem_object *obj);
 876
 877 int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
 878 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev);
 879 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev);
 880 void radeon_atombios_init_crtc(struct drm_device *dev,
 881                                struct radeon_crtc *radeon_crtc);
 882 void radeon_legacy_init_crtc(struct drm_device *dev,
 883                              struct radeon_crtc *radeon_crtc);
 884
 885 void radeon_get_clock_info(struct drm_device *dev);
 886
 887 extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev);
 888 extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev);
 889
 890 void radeon_enc_destroy(struct drm_encoder *encoder);
 891 void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
 892 void radeon_combios_asic_init(struct drm_device *dev);
 893 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
 894                                         const struct drm_display_mode *mode,
 895                                         struct drm_display_mode *adjusted_mode);
 896 void radeon_panel_mode_fixup(struct drm_encoder *encoder,
 897                              struct drm_display_mode *adjusted_mode);
 898 void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc);
 899
 900 /* legacy tv */
 901 void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder,
 902                                       uint32_t *h_total_disp, uint32_t *h_sync_strt_wid,
 903                                       uint32_t *v_total_disp, uint32_t *v_sync_strt_wid);
 904 void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder,
 905                                   uint32_t *htotal_cntl, uint32_t *ppll_ref_div,
 906                                   uint32_t *ppll_div_3, uint32_t *pixclks_cntl);
 907 void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder,
 908                                   uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div,
 909                                   uint32_t *p2pll_div_0, uint32_t *pixclks_cntl);
 910 void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
 911                                struct drm_display_mode *mode,
 912                                struct drm_display_mode *adjusted_mode);
 913
 914 /* fmt blocks */
 915 void avivo_program_fmt(struct drm_encoder *encoder);
 916 void dce3_program_fmt(struct drm_encoder *encoder);
 917 void dce4_program_fmt(struct drm_encoder *encoder);
 918 void dce8_program_fmt(struct drm_encoder *encoder);
 919
 920 /* fbdev layer */
 921 int radeon_fbdev_init(struct radeon_device *rdev);
 922 void radeon_fbdev_fini(struct radeon_device *rdev);
 923 void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state);
 924 bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj);
 925 void radeon_fbdev_restore_mode(struct radeon_device *rdev);
 926
 927 void radeon_fb_output_poll_changed(struct radeon_device *rdev);
 928
 929 void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id);
 930 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id);
 931
 932 int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled);
 933 #endif