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drm/radeon: add missing ttm_eu_backoff_reservation to radeon_bo_list_validate
[dragonfly.git] / sys / dev / drm / radeon / radeon_display.c
blob89d5413503c277f164276dfdd82180a7736955df
1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 *
26 * $FreeBSD: head/sys/dev/drm2/radeon/radeon_display.c 254885 2013-08-25 19:37:15Z dumbbell $
27 */
28
29 #include <drm/drmP.h>
30 #include <uapi_drm/radeon_drm.h>
31 #include "radeon.h"
32
33 #include "atom.h"
34
35 #ifdef PM_TODO
36 #include <linux/pm_runtime.h>
37 #endif
38 #include <drm/drm_crtc_helper.h>
39 #include <drm/drm_plane_helper.h>
40 #include <drm/drm_edid.h>
41 #include <linux/err.h>
42
43 #include <linux/gcd.h>
44
45 static void avivo_crtc_load_lut(struct drm_crtc *crtc)
46 {
47 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
48 struct drm_device *dev = crtc->dev;
49 struct radeon_device *rdev = dev->dev_private;
50 int i;
51
52 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
53 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
54
55 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
56 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
57 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
58
59 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
60 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
61 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
62
63 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
64 WREG32(AVIVO_DC_LUT_RW_MODE, 0);
65 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
66
67 WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
68 for (i = 0; i < 256; i++) {
69 WREG32(AVIVO_DC_LUT_30_COLOR,
70 (radeon_crtc->lut_r[i] << 20) |
71 (radeon_crtc->lut_g[i] << 10) |
72 (radeon_crtc->lut_b[i] << 0));
73 }
74
75 /* Only change bit 0 of LUT_SEL, other bits are set elsewhere */
76 WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id, ~1);
77 }
78
79 static void dce4_crtc_load_lut(struct drm_crtc *crtc)
80 {
81 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
82 struct drm_device *dev = crtc->dev;
83 struct radeon_device *rdev = dev->dev_private;
84 int i;
85
86 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
87 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
88
89 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
90 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
91 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
92
93 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
94 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
95 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
96
97 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
98 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
99
100 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
101 for (i = 0; i < 256; i++) {
102 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
103 (radeon_crtc->lut_r[i] << 20) |
104 (radeon_crtc->lut_g[i] << 10) |
105 (radeon_crtc->lut_b[i] << 0));
106 }
107 }
108
109 static void dce5_crtc_load_lut(struct drm_crtc *crtc)
110 {
111 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
112 struct drm_device *dev = crtc->dev;
113 struct radeon_device *rdev = dev->dev_private;
114 int i;
115
116 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
117
118 WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
119 (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |
120 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));
121 WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,
122 NI_GRPH_PRESCALE_BYPASS);
123 WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,
124 NI_OVL_PRESCALE_BYPASS);
125 WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,
126 (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) |
127 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)));
128
129 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
130
131 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
132 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
133 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
134
135 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
136 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
137 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
138
139 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
140 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
141
142 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
143 for (i = 0; i < 256; i++) {
144 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
145 (radeon_crtc->lut_r[i] << 20) |
146 (radeon_crtc->lut_g[i] << 10) |
147 (radeon_crtc->lut_b[i] << 0));
148 }
149
150 WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,
151 (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
152 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
153 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
154 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)));
155 WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,
156 (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) |
157 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)));
158 WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,
159 (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) |
160 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)));
161 WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
162 (NI_OUTPUT_CSC_GRPH_MODE(NI_OUTPUT_CSC_BYPASS) |
163 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));
164 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
165 WREG32(0x6940 + radeon_crtc->crtc_offset, 0);
166 if (ASIC_IS_DCE8(rdev)) {
167 /* XXX this only needs to be programmed once per crtc at startup,
168 * not sure where the best place for it is
169 */
170 WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset,
171 CIK_CURSOR_ALPHA_BLND_ENA);
172 }
173 }
174
175 static void legacy_crtc_load_lut(struct drm_crtc *crtc)
176 {
177 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
178 struct drm_device *dev = crtc->dev;
179 struct radeon_device *rdev = dev->dev_private;
180 int i;
181 uint32_t dac2_cntl;
182
183 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
184 if (radeon_crtc->crtc_id == 0)
185 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
186 else
187 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
188 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
189
190 WREG8(RADEON_PALETTE_INDEX, 0);
191 for (i = 0; i < 256; i++) {
192 WREG32(RADEON_PALETTE_30_DATA,
193 (radeon_crtc->lut_r[i] << 20) |
194 (radeon_crtc->lut_g[i] << 10) |
195 (radeon_crtc->lut_b[i] << 0));
196 }
197 }
198
199 void radeon_crtc_load_lut(struct drm_crtc *crtc)
200 {
201 struct drm_device *dev = crtc->dev;
202 struct radeon_device *rdev = dev->dev_private;
203
204 if (!crtc->enabled)
205 return;
206
207 if (ASIC_IS_DCE5(rdev))
208 dce5_crtc_load_lut(crtc);
209 else if (ASIC_IS_DCE4(rdev))
210 dce4_crtc_load_lut(crtc);
211 else if (ASIC_IS_AVIVO(rdev))
212 avivo_crtc_load_lut(crtc);
213 else
214 legacy_crtc_load_lut(crtc);
215 }
216
217 /** Sets the color ramps on behalf of fbcon */
218 void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
219 u16 blue, int regno)
220 {
221 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
222
223 radeon_crtc->lut_r[regno] = red >> 6;
224 radeon_crtc->lut_g[regno] = green >> 6;
225 radeon_crtc->lut_b[regno] = blue >> 6;
226 }
227
228 /** Gets the color ramps on behalf of fbcon */
229 void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
230 u16 *blue, int regno)
231 {
232 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
233
234 *red = radeon_crtc->lut_r[regno] << 6;
235 *green = radeon_crtc->lut_g[regno] << 6;
236 *blue = radeon_crtc->lut_b[regno] << 6;
237 }
238
239 static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
240 u16 *blue, uint32_t start, uint32_t size)
241 {
242 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
243 int end = (start + size > 256) ? 256 : start + size, i;
244
245 /* userspace palettes are always correct as is */
246 for (i = start; i < end; i++) {
247 radeon_crtc->lut_r[i] = red[i] >> 6;
248 radeon_crtc->lut_g[i] = green[i] >> 6;
249 radeon_crtc->lut_b[i] = blue[i] >> 6;
250 }
251 radeon_crtc_load_lut(crtc);
252 }
253
254 static void radeon_crtc_destroy(struct drm_crtc *crtc)
255 {
256 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
257
258 drm_crtc_cleanup(crtc);
259 destroy_workqueue(radeon_crtc->flip_queue);
260 kfree(radeon_crtc);
261 }
262
263 /**
264 * radeon_unpin_work_func - unpin old buffer object
265 *
266 * @__work - kernel work item
267 *
268 * Unpin the old frame buffer object outside of the interrupt handler
269 */
270 static void radeon_unpin_work_func(struct work_struct *__work)
271 {
272 struct radeon_flip_work *work =
273 container_of(__work, struct radeon_flip_work, unpin_work);
274 int r;
275
276 /* unpin of the old buffer */
277 r = radeon_bo_reserve(work->old_rbo, false);
278 if (likely(r == 0)) {
279 r = radeon_bo_unpin(work->old_rbo);
280 if (unlikely(r != 0)) {
281 DRM_ERROR("failed to unpin buffer after flip\n");
282 }
283 radeon_bo_unreserve(work->old_rbo);
284 } else
285 DRM_ERROR("failed to reserve buffer after flip\n");
286
287 drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
288 kfree(work);
289 }
290
291 void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id)
292 {
293 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
294 u32 update_pending;
295 int vpos, hpos;
296
297 /* can happen during initialization */
298 if (radeon_crtc == NULL)
299 return;
300
301 /* Skip the pageflip completion check below (based on polling) on
302 * asics which reliably support hw pageflip completion irqs. pflip
303 * irqs are a reliable and race-free method of handling pageflip
304 * completion detection. A use_pflipirq module parameter < 2 allows
305 * to override this in case of asics with faulty pflip irqs.
306 * A module parameter of 0 would only use this polling based path,
307 * a parameter of 1 would use pflip irq only as a backup to this
308 * path, as in Linux 3.16.
309 */
310 if ((radeon_use_pflipirq == 2) && ASIC_IS_DCE4(rdev))
311 return;
312
313 lockmgr(&rdev->ddev->event_lock, LK_EXCLUSIVE);
314 if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) {
315 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != "
316 "RADEON_FLIP_SUBMITTED(%d)\n",
317 radeon_crtc->flip_status,
318 RADEON_FLIP_SUBMITTED);
319 lockmgr(&rdev->ddev->event_lock, LK_RELEASE);
320 return;
321 }
322
323 update_pending = radeon_page_flip_pending(rdev, crtc_id);
324
325 /* Has the pageflip already completed in crtc, or is it certain
326 * to complete in this vblank?
327 */
328 if (update_pending &&
329 (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id, 0,
330 &vpos, &hpos, NULL, NULL,
331 &rdev->mode_info.crtcs[crtc_id]->base.hwmode)) &&
332 ((vpos >= (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100) ||
333 (vpos < 0 && !ASIC_IS_AVIVO(rdev)))) {
334 /* crtc didn't flip in this target vblank interval,
335 * but flip is pending in crtc. Based on the current
336 * scanout position we know that the current frame is
337 * (nearly) complete and the flip will (likely)
338 * complete before the start of the next frame.
339 */
340 update_pending = 0;
341 }
342 lockmgr(&rdev->ddev->event_lock, LK_RELEASE);
343 if (!update_pending)
344 radeon_crtc_handle_flip(rdev, crtc_id);
345 }
346
347 /**
348 * radeon_crtc_handle_flip - page flip completed
349 *
350 * @rdev: radeon device pointer
351 * @crtc_id: crtc number this event is for
352 *
353 * Called when we are sure that a page flip for this crtc is completed.
354 */
355 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
356 {
357 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
358 struct radeon_flip_work *work;
359
360 /* this can happen at init */
361 if (radeon_crtc == NULL)
362 return;
363
364 lockmgr(&rdev->ddev->event_lock, LK_EXCLUSIVE);
365 work = radeon_crtc->flip_work;
366 if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) {
367 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != "
368 "RADEON_FLIP_SUBMITTED(%d)\n",
369 radeon_crtc->flip_status,
370 RADEON_FLIP_SUBMITTED);
371 lockmgr(&rdev->ddev->event_lock, LK_RELEASE);
372 return;
373 }
374
375 /* Pageflip completed. Clean up. */
376 radeon_crtc->flip_status = RADEON_FLIP_NONE;
377 radeon_crtc->flip_work = NULL;
378
379 /* wakeup userspace */
380 if (work->event)
381 drm_send_vblank_event(rdev->ddev, crtc_id, work->event);
382
383 lockmgr(&rdev->ddev->event_lock, LK_RELEASE);
384
385 drm_vblank_put(rdev->ddev, radeon_crtc->crtc_id);
386 radeon_irq_kms_pflip_irq_put(rdev, work->crtc_id);
387 queue_work(radeon_crtc->flip_queue, &work->unpin_work);
388 }
389
390 /**
391 * radeon_flip_work_func - page flip framebuffer
392 *
393 * @work - kernel work item
394 *
395 * Wait for the buffer object to become idle and do the actual page flip
396 */
397 static void radeon_flip_work_func(struct work_struct *__work)
398 {
399 struct radeon_flip_work *work =
400 container_of(__work, struct radeon_flip_work, flip_work);
401 struct radeon_device *rdev = work->rdev;
402 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[work->crtc_id];
403
404 struct drm_crtc *crtc = &radeon_crtc->base;
405 int r;
406
407 lockmgr(&rdev->exclusive_lock, LK_EXCLUSIVE);
408 if (work->fence) {
409 r = radeon_fence_wait(work->fence, false);
410 if (r == -EDEADLK) {
411 lockmgr(&rdev->exclusive_lock, LK_RELEASE);
412 do {
413 r = radeon_gpu_reset(rdev);
414 } while (r == -EAGAIN);
415 lockmgr(&rdev->exclusive_lock, LK_EXCLUSIVE);
416 }
417 if (r)
418 DRM_ERROR("failed to wait on page flip fence (%d)!\n", r);
419
420 /* We continue with the page flip even if we failed to wait on
421 * the fence, otherwise the DRM core and userspace will be
422 * confused about which BO the CRTC is scanning out
423 */
424
425 radeon_fence_unref(&work->fence);
426 }
427
428 /* We borrow the event spin lock for protecting flip_status */
429 lockmgr(&crtc->dev->event_lock, LK_EXCLUSIVE);
430
431 /* set the proper interrupt */
432 radeon_irq_kms_pflip_irq_get(rdev, radeon_crtc->crtc_id);
433
434 /* do the flip (mmio) */
435 radeon_page_flip(rdev, radeon_crtc->crtc_id, work->base);
436
437 radeon_crtc->flip_status = RADEON_FLIP_SUBMITTED;
438 lockmgr(&crtc->dev->event_lock, LK_RELEASE);
439 lockmgr(&rdev->exclusive_lock, LK_RELEASE);
440 }
441
442 static int radeon_crtc_page_flip(struct drm_crtc *crtc,
443 struct drm_framebuffer *fb,
444 struct drm_pending_vblank_event *event,
445 uint32_t page_flip_flags)
446 {
447 struct drm_device *dev = crtc->dev;
448 struct radeon_device *rdev = dev->dev_private;
449 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
450 struct radeon_framebuffer *old_radeon_fb;
451 struct radeon_framebuffer *new_radeon_fb;
452 struct drm_gem_object *obj;
453 struct radeon_flip_work *work;
454 struct radeon_bo *new_rbo;
455 uint32_t tiling_flags, pitch_pixels;
456 uint64_t base;
457 int r;
458
459 work = kzalloc(sizeof *work, GFP_KERNEL);
460 if (work == NULL)
461 return -ENOMEM;
462
463 INIT_WORK(&work->flip_work, radeon_flip_work_func);
464 INIT_WORK(&work->unpin_work, radeon_unpin_work_func);
465
466 work->rdev = rdev;
467 work->crtc_id = radeon_crtc->crtc_id;
468 work->event = event;
469
470 /* schedule unpin of the old buffer */
471 old_radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
472 obj = old_radeon_fb->obj;
473
474 /* take a reference to the old object */
475 drm_gem_object_reference(obj);
476 work->old_rbo = gem_to_radeon_bo(obj);
477
478 new_radeon_fb = to_radeon_framebuffer(fb);
479 obj = new_radeon_fb->obj;
480 new_rbo = gem_to_radeon_bo(obj);
481
482 lockmgr(&new_rbo->tbo.bdev->fence_lock, LK_EXCLUSIVE);
483 if (new_rbo->tbo.sync_obj)
484 work->fence = radeon_fence_ref(new_rbo->tbo.sync_obj);
485 lockmgr(&new_rbo->tbo.bdev->fence_lock, LK_RELEASE);
486
487 /* pin the new buffer */
488 DRM_DEBUG_DRIVER("flip-ioctl() cur_rbo = %p, new_rbo = %p\n",
489 work->old_rbo, new_rbo);
490
491 r = radeon_bo_reserve(new_rbo, false);
492 if (unlikely(r != 0)) {
493 DRM_ERROR("failed to reserve new rbo buffer before flip\n");
494 goto cleanup;
495 }
496 /* Only 27 bit offset for legacy CRTC */
497 r = radeon_bo_pin_restricted(new_rbo, RADEON_GEM_DOMAIN_VRAM,
498 ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, (u64 *)&base);
499 if (unlikely(r != 0)) {
500 radeon_bo_unreserve(new_rbo);
501 r = -EINVAL;
502 DRM_ERROR("failed to pin new rbo buffer before flip\n");
503 goto cleanup;
504 }
505 radeon_bo_get_tiling_flags(new_rbo, &tiling_flags, NULL);
506 radeon_bo_unreserve(new_rbo);
507
508 if (!ASIC_IS_AVIVO(rdev)) {
509 /* crtc offset is from display base addr not FB location */
510 base -= radeon_crtc->legacy_display_base_addr;
511 pitch_pixels = fb->pitches[0] / (fb->bits_per_pixel / 8);
512
513 if (tiling_flags & RADEON_TILING_MACRO) {
514 if (ASIC_IS_R300(rdev)) {
515 base &= ~0x7ff;
516 } else {
517 int byteshift = fb->bits_per_pixel >> 4;
518 int tile_addr = (((crtc->y >> 3) * pitch_pixels + crtc->x) >> (8 - byteshift)) << 11;
519 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8);
520 }
521 } else {
522 int offset = crtc->y * pitch_pixels + crtc->x;
523 switch (fb->bits_per_pixel) {
524 case 8:
525 default:
526 offset *= 1;
527 break;
528 case 15:
529 case 16:
530 offset *= 2;
531 break;
532 case 24:
533 offset *= 3;
534 break;
535 case 32:
536 offset *= 4;
537 break;
538 }
539 base += offset;
540 }
541 base &= ~7;
542 }
543 work->base = base;
544
545 r = drm_vblank_get(crtc->dev, radeon_crtc->crtc_id);
546 if (r) {
547 DRM_ERROR("failed to get vblank before flip\n");
548 goto pflip_cleanup;
549 }
550
551 /* We borrow the event spin lock for protecting flip_work */
552 lockmgr(&crtc->dev->event_lock, LK_EXCLUSIVE);
553
554 if (radeon_crtc->flip_status != RADEON_FLIP_NONE) {
555 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
556 lockmgr(&crtc->dev->event_lock, LK_RELEASE);
557 r = -EBUSY;
558 goto vblank_cleanup;
559 }
560 radeon_crtc->flip_status = RADEON_FLIP_PENDING;
561 radeon_crtc->flip_work = work;
562
563 /* update crtc fb */
564 crtc->primary->fb = fb;
565
566 lockmgr(&crtc->dev->event_lock, LK_RELEASE);
567
568 queue_work(radeon_crtc->flip_queue, &work->flip_work);
569 return 0;
570
571 vblank_cleanup:
572 drm_vblank_put(crtc->dev, radeon_crtc->crtc_id);
573
574 pflip_cleanup:
575 if (unlikely(radeon_bo_reserve(new_rbo, false) != 0)) {
576 DRM_ERROR("failed to reserve new rbo in error path\n");
577 goto cleanup;
578 }
579 if (unlikely(radeon_bo_unpin(new_rbo) != 0)) {
580 DRM_ERROR("failed to unpin new rbo in error path\n");
581 }
582 radeon_bo_unreserve(new_rbo);
583
584 cleanup:
585 drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
586 radeon_fence_unref(&work->fence);
587 kfree(work);
588
589 return r;
590 }
591
592 static int
593 radeon_crtc_set_config(struct drm_mode_set *set)
594 {
595 struct drm_device *dev;
596 struct radeon_device *rdev;
597 struct drm_crtc *crtc;
598 bool active = false;
599 int ret;
600
601 if (!set || !set->crtc)
602 return -EINVAL;
603
604 dev = set->crtc->dev;
605
606 #ifdef PM_TODO
607 ret = pm_runtime_get_sync(dev->dev);
608 if (ret < 0)
609 return ret;
610 #endif
611
612 ret = drm_crtc_helper_set_config(set);
613
614 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
615 if (crtc->enabled)
616 active = true;
617
618 #ifdef PM_TODO
619 pm_runtime_mark_last_busy(dev->dev);
620 #endif
621
622 rdev = dev->dev_private;
623 /* if we have active crtcs and we don't have a power ref,
624 take the current one */
625 if (active && !rdev->have_disp_power_ref) {
626 rdev->have_disp_power_ref = true;
627 return ret;
628 }
629 /* if we have no active crtcs, then drop the power ref
630 we got before */
631 if (!active && rdev->have_disp_power_ref) {
632 #ifdef PM_TODO
633 pm_runtime_put_autosuspend(dev->dev);
634 #endif
635 rdev->have_disp_power_ref = false;
636 }
637
638 /* drop the power reference we got coming in here */
639 #ifdef PM_TODO
640 pm_runtime_put_autosuspend(dev->dev);
641 #endif
642 return ret;
643 }
644 static const struct drm_crtc_funcs radeon_crtc_funcs = {
645 .cursor_set = radeon_crtc_cursor_set,
646 .cursor_move = radeon_crtc_cursor_move,
647 .gamma_set = radeon_crtc_gamma_set,
648 .set_config = radeon_crtc_set_config,
649 .destroy = radeon_crtc_destroy,
650 .page_flip = radeon_crtc_page_flip,
651 };
652
653 static void radeon_crtc_init(struct drm_device *dev, int index)
654 {
655 struct radeon_device *rdev = dev->dev_private;
656 struct radeon_crtc *radeon_crtc;
657 int i;
658
659 radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
660 if (radeon_crtc == NULL)
661 return;
662
663 drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
664
665 drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
666 radeon_crtc->crtc_id = index;
667 radeon_crtc->flip_queue = create_singlethread_workqueue("radeon-crtc");
668 rdev->mode_info.crtcs[index] = radeon_crtc;
669
670 if (rdev->family >= CHIP_BONAIRE) {
671 radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
672 radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
673 } else {
674 radeon_crtc->max_cursor_width = CURSOR_WIDTH;
675 radeon_crtc->max_cursor_height = CURSOR_HEIGHT;
676 }
677 dev->mode_config.cursor_width = radeon_crtc->max_cursor_width;
678 dev->mode_config.cursor_height = radeon_crtc->max_cursor_height;
679
680 #if 0
681 radeon_crtc->mode_set.crtc = &radeon_crtc->base;
682 radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
683 radeon_crtc->mode_set.num_connectors = 0;
684 #endif
685
686 for (i = 0; i < 256; i++) {
687 radeon_crtc->lut_r[i] = i << 2;
688 radeon_crtc->lut_g[i] = i << 2;
689 radeon_crtc->lut_b[i] = i << 2;
690 }
691
692 if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
693 radeon_atombios_init_crtc(dev, radeon_crtc);
694 else
695 radeon_legacy_init_crtc(dev, radeon_crtc);
696 }
697
698 static const char *encoder_names[38] = {
699 "NONE",
700 "INTERNAL_LVDS",
701 "INTERNAL_TMDS1",
702 "INTERNAL_TMDS2",
703 "INTERNAL_DAC1",
704 "INTERNAL_DAC2",
705 "INTERNAL_SDVOA",
706 "INTERNAL_SDVOB",
707 "SI170B",
708 "CH7303",
709 "CH7301",
710 "INTERNAL_DVO1",
711 "EXTERNAL_SDVOA",
712 "EXTERNAL_SDVOB",
713 "TITFP513",
714 "INTERNAL_LVTM1",
715 "VT1623",
716 "HDMI_SI1930",
717 "HDMI_INTERNAL",
718 "INTERNAL_KLDSCP_TMDS1",
719 "INTERNAL_KLDSCP_DVO1",
720 "INTERNAL_KLDSCP_DAC1",
721 "INTERNAL_KLDSCP_DAC2",
722 "SI178",
723 "MVPU_FPGA",
724 "INTERNAL_DDI",
725 "VT1625",
726 "HDMI_SI1932",
727 "DP_AN9801",
728 "DP_DP501",
729 "INTERNAL_UNIPHY",
730 "INTERNAL_KLDSCP_LVTMA",
731 "INTERNAL_UNIPHY1",
732 "INTERNAL_UNIPHY2",
733 "NUTMEG",
734 "TRAVIS",
735 "INTERNAL_VCE",
736 "INTERNAL_UNIPHY3",
737 };
738
739 static const char *hpd_names[6] = {
740 "HPD1",
741 "HPD2",
742 "HPD3",
743 "HPD4",
744 "HPD5",
745 "HPD6",
746 };
747
748 static void radeon_print_display_setup(struct drm_device *dev)
749 {
750 struct drm_connector *connector;
751 struct radeon_connector *radeon_connector;
752 struct drm_encoder *encoder;
753 struct radeon_encoder *radeon_encoder;
754 uint32_t devices;
755 int i = 0;
756
757 DRM_INFO("Radeon Display Connectors\n");
758 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
759 radeon_connector = to_radeon_connector(connector);
760 DRM_INFO("Connector %d:\n", i);
761 DRM_INFO(" %s\n", connector->name);
762 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
763 DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]);
764 if (radeon_connector->ddc_bus) {
765 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
766 radeon_connector->ddc_bus->rec.mask_clk_reg,
767 radeon_connector->ddc_bus->rec.mask_data_reg,
768 radeon_connector->ddc_bus->rec.a_clk_reg,
769 radeon_connector->ddc_bus->rec.a_data_reg,
770 radeon_connector->ddc_bus->rec.en_clk_reg,
771 radeon_connector->ddc_bus->rec.en_data_reg,
772 radeon_connector->ddc_bus->rec.y_clk_reg,
773 radeon_connector->ddc_bus->rec.y_data_reg);
774 if (radeon_connector->router.ddc_valid)
775 DRM_INFO(" DDC Router 0x%x/0x%x\n",
776 radeon_connector->router.ddc_mux_control_pin,
777 radeon_connector->router.ddc_mux_state);
778 if (radeon_connector->router.cd_valid)
779 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n",
780 radeon_connector->router.cd_mux_control_pin,
781 radeon_connector->router.cd_mux_state);
782 } else {
783 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
784 connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
785 connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
786 connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
787 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
788 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
789 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
790 }
791 DRM_INFO(" Encoders:\n");
792 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
793 radeon_encoder = to_radeon_encoder(encoder);
794 devices = radeon_encoder->devices & radeon_connector->devices;
795 if (devices) {
796 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
797 DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
798 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
799 DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
800 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
801 DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
802 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
803 DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
804 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
805 DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
806 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
807 DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
808 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
809 DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
810 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
811 DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
812 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
813 DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
814 if (devices & ATOM_DEVICE_TV1_SUPPORT)
815 DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
816 if (devices & ATOM_DEVICE_CV_SUPPORT)
817 DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
818 }
819 }
820 i++;
821 }
822 }
823
824 static bool radeon_setup_enc_conn(struct drm_device *dev)
825 {
826 struct radeon_device *rdev = dev->dev_private;
827 bool ret = false;
828
829 if (rdev->bios) {
830 if (rdev->is_atom_bios) {
831 ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
832 if (ret == false)
833 ret = radeon_get_atom_connector_info_from_object_table(dev);
834 } else {
835 ret = radeon_get_legacy_connector_info_from_bios(dev);
836 if (ret == false)
837 ret = radeon_get_legacy_connector_info_from_table(dev);
838 }
839 } else {
840 if (!ASIC_IS_AVIVO(rdev))
841 ret = radeon_get_legacy_connector_info_from_table(dev);
842 }
843 if (ret) {
844 radeon_setup_encoder_clones(dev);
845 radeon_print_display_setup(dev);
846 }
847
848 return ret;
849 }
850
851 /* avivo */
852
853 /**
854 * avivo_reduce_ratio - fractional number reduction
855 *
856 * @nom: nominator
857 * @den: denominator
858 * @nom_min: minimum value for nominator
859 * @den_min: minimum value for denominator
860 *
861 * Find the greatest common divisor and apply it on both nominator and
862 * denominator, but make nominator and denominator are at least as large
863 * as their minimum values.
864 */
865 static void avivo_reduce_ratio(unsigned *nom, unsigned *den,
866 unsigned nom_min, unsigned den_min)
867 {
868 unsigned tmp;
869
870 /* reduce the numbers to a simpler ratio */
871 tmp = gcd64(*nom, *den);
872 *nom /= tmp;
873 *den /= tmp;
874
875 /* make sure nominator is large enough */
876 if (*nom < nom_min) {
877 tmp = DIV_ROUND_UP(nom_min, *nom);
878 *nom *= tmp;
879 *den *= tmp;
880 }
881
882 /* make sure the denominator is large enough */
883 if (*den < den_min) {
884 tmp = DIV_ROUND_UP(den_min, *den);
885 *nom *= tmp;
886 *den *= tmp;
887 }
888 }
889
890 /**
891 * avivo_get_fb_ref_div - feedback and ref divider calculation
892 *
893 * @nom: nominator
894 * @den: denominator
895 * @post_div: post divider
896 * @fb_div_max: feedback divider maximum
897 * @ref_div_max: reference divider maximum
898 * @fb_div: resulting feedback divider
899 * @ref_div: resulting reference divider
900 *
901 * Calculate feedback and reference divider for a given post divider. Makes
902 * sure we stay within the limits.
903 */
904 static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div,
905 unsigned fb_div_max, unsigned ref_div_max,
906 unsigned *fb_div, unsigned *ref_div)
907 {
908 /* limit reference * post divider to a maximum */
909 ref_div_max = max(min(100 / post_div, ref_div_max), 1u);
910
911 /* get matching reference and feedback divider */
912 *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max);
913 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den);
914
915 /* limit fb divider to its maximum */
916 if (*fb_div > fb_div_max) {
917 *ref_div = DIV_ROUND_CLOSEST(*ref_div * fb_div_max, *fb_div);
918 *fb_div = fb_div_max;
919 }
920 }
921
922 /**
923 * radeon_compute_pll_avivo - compute PLL paramaters
924 *
925 * @pll: information about the PLL
926 * @dot_clock_p: resulting pixel clock
927 * fb_div_p: resulting feedback divider
928 * frac_fb_div_p: fractional part of the feedback divider
929 * ref_div_p: resulting reference divider
930 * post_div_p: resulting reference divider
931 *
932 * Try to calculate the PLL parameters to generate the given frequency:
933 * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div)
934 */
935 void radeon_compute_pll_avivo(struct radeon_pll *pll,
936 u32 freq,
937 u32 *dot_clock_p,
938 u32 *fb_div_p,
939 u32 *frac_fb_div_p,
940 u32 *ref_div_p,
941 u32 *post_div_p)
942 {
943 unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ?
944 freq : freq / 10;
945
946 unsigned fb_div_min, fb_div_max, fb_div;
947 unsigned post_div_min, post_div_max, post_div;
948 unsigned ref_div_min, ref_div_max, ref_div;
949 unsigned post_div_best, diff_best;
950 unsigned nom, den;
951
952 /* determine allowed feedback divider range */
953 fb_div_min = pll->min_feedback_div;
954 fb_div_max = pll->max_feedback_div;
955
956 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
957 fb_div_min *= 10;
958 fb_div_max *= 10;
959 }
960
961 /* determine allowed ref divider range */
962 if (pll->flags & RADEON_PLL_USE_REF_DIV)
963 ref_div_min = pll->reference_div;
964 else
965 ref_div_min = pll->min_ref_div;
966
967 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV &&
968 pll->flags & RADEON_PLL_USE_REF_DIV)
969 ref_div_max = pll->reference_div;
970 else
971 ref_div_max = pll->max_ref_div;
972
973 /* determine allowed post divider range */
974 if (pll->flags & RADEON_PLL_USE_POST_DIV) {
975 post_div_min = pll->post_div;
976 post_div_max = pll->post_div;
977 } else {
978 unsigned vco_min, vco_max;
979
980 if (pll->flags & RADEON_PLL_IS_LCD) {
981 vco_min = pll->lcd_pll_out_min;
982 vco_max = pll->lcd_pll_out_max;
983 } else {
984 vco_min = pll->pll_out_min;
985 vco_max = pll->pll_out_max;
986 }
987
988 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
989 vco_min *= 10;
990 vco_max *= 10;
991 }
992
993 post_div_min = vco_min / target_clock;
994 if ((target_clock * post_div_min) < vco_min)
995 ++post_div_min;
996 if (post_div_min < pll->min_post_div)
997 post_div_min = pll->min_post_div;
998
999 post_div_max = vco_max / target_clock;
1000 if ((target_clock * post_div_max) > vco_max)
1001 --post_div_max;
1002 if (post_div_max > pll->max_post_div)
1003 post_div_max = pll->max_post_div;
1004 }
1005
1006 /* represent the searched ratio as fractional number */
1007 nom = target_clock;
1008 den = pll->reference_freq;
1009
1010 /* reduce the numbers to a simpler ratio */
1011 avivo_reduce_ratio(&nom, &den, fb_div_min, post_div_min);
1012
1013 /* now search for a post divider */
1014 if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
1015 post_div_best = post_div_min;
1016 else
1017 post_div_best = post_div_max;
1018 diff_best = ~0;
1019
1020 for (post_div = post_div_min; post_div <= post_div_max; ++post_div) {
1021 unsigned diff;
1022 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max,
1023 ref_div_max, &fb_div, &ref_div);
1024 diff = abs(target_clock - (pll->reference_freq * fb_div) /
1025 (ref_div * post_div));
1026
1027 if (diff < diff_best || (diff == diff_best &&
1028 !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) {
1029
1030 post_div_best = post_div;
1031 diff_best = diff;
1032 }
1033 }
1034 post_div = post_div_best;
1035
1036 /* get the feedback and reference divider for the optimal value */
1037 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, ref_div_max,
1038 &fb_div, &ref_div);
1039
1040 /* reduce the numbers to a simpler ratio once more */
1041 /* this also makes sure that the reference divider is large enough */
1042 avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min);
1043
1044 /* avoid high jitter with small fractional dividers */
1045 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) {
1046 fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 50);
1047 if (fb_div < fb_div_min) {
1048 unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div);
1049 fb_div *= tmp;
1050 ref_div *= tmp;
1051 }
1052 }
1053
1054 /* and finally save the result */
1055 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1056 *fb_div_p = fb_div / 10;
1057 *frac_fb_div_p = fb_div % 10;
1058 } else {
1059 *fb_div_p = fb_div;
1060 *frac_fb_div_p = 0;
1061 }
1062
1063 *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) +
1064 (pll->reference_freq * *frac_fb_div_p)) /
1065 (ref_div * post_div * 10);
1066 *ref_div_p = ref_div;
1067 *post_div_p = post_div;
1068
1069 DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1070 freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p,
1071 ref_div, post_div);
1072 }
1073
1074 /* pre-avivo */
1075 static inline uint32_t radeon_div(uint64_t n, uint32_t d)
1076 {
1077 uint64_t mod;
1078
1079 n += d / 2;
1080
1081 mod = do_div(n, d);
1082 return n;
1083 }
1084
1085 void radeon_compute_pll_legacy(struct radeon_pll *pll,
1086 uint64_t freq,
1087 uint32_t *dot_clock_p,
1088 uint32_t *fb_div_p,
1089 uint32_t *frac_fb_div_p,
1090 uint32_t *ref_div_p,
1091 uint32_t *post_div_p)
1092 {
1093 uint32_t min_ref_div = pll->min_ref_div;
1094 uint32_t max_ref_div = pll->max_ref_div;
1095 uint32_t min_post_div = pll->min_post_div;
1096 uint32_t max_post_div = pll->max_post_div;
1097 uint32_t min_fractional_feed_div = 0;
1098 uint32_t max_fractional_feed_div = 0;
1099 uint32_t best_vco = pll->best_vco;
1100 uint32_t best_post_div = 1;
1101 uint32_t best_ref_div = 1;
1102 uint32_t best_feedback_div = 1;
1103 uint32_t best_frac_feedback_div = 0;
1104 uint32_t best_freq = -1;
1105 uint32_t best_error = 0xffffffff;
1106 uint32_t best_vco_diff = 1;
1107 uint32_t post_div;
1108 u32 pll_out_min, pll_out_max;
1109
1110 DRM_DEBUG_KMS("PLL freq %ju %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
1111 freq = freq * 1000;
1112
1113 if (pll->flags & RADEON_PLL_IS_LCD) {
1114 pll_out_min = pll->lcd_pll_out_min;
1115 pll_out_max = pll->lcd_pll_out_max;
1116 } else {
1117 pll_out_min = pll->pll_out_min;
1118 pll_out_max = pll->pll_out_max;
1119 }
1120
1121 if (pll_out_min > 64800)
1122 pll_out_min = 64800;
1123
1124 if (pll->flags & RADEON_PLL_USE_REF_DIV)
1125 min_ref_div = max_ref_div = pll->reference_div;
1126 else {
1127 while (min_ref_div < max_ref_div-1) {
1128 uint32_t mid = (min_ref_div + max_ref_div) / 2;
1129 uint32_t pll_in = pll->reference_freq / mid;
1130 if (pll_in < pll->pll_in_min)
1131 max_ref_div = mid;
1132 else if (pll_in > pll->pll_in_max)
1133 min_ref_div = mid;
1134 else
1135 break;
1136 }
1137 }
1138
1139 if (pll->flags & RADEON_PLL_USE_POST_DIV)
1140 min_post_div = max_post_div = pll->post_div;
1141
1142 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1143 min_fractional_feed_div = pll->min_frac_feedback_div;
1144 max_fractional_feed_div = pll->max_frac_feedback_div;
1145 }
1146
1147 for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
1148 uint32_t ref_div;
1149
1150 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
1151 continue;
1152
1153 /* legacy radeons only have a few post_divs */
1154 if (pll->flags & RADEON_PLL_LEGACY) {
1155 if ((post_div == 5) ||
1156 (post_div == 7) ||
1157 (post_div == 9) ||
1158 (post_div == 10) ||
1159 (post_div == 11) ||
1160 (post_div == 13) ||
1161 (post_div == 14) ||
1162 (post_div == 15))
1163 continue;
1164 }
1165
1166 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
1167 uint32_t feedback_div, current_freq = 0, error, vco_diff;
1168 uint32_t pll_in = pll->reference_freq / ref_div;
1169 uint32_t min_feed_div = pll->min_feedback_div;
1170 uint32_t max_feed_div = pll->max_feedback_div + 1;
1171
1172 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
1173 continue;
1174
1175 while (min_feed_div < max_feed_div) {
1176 uint32_t vco;
1177 uint32_t min_frac_feed_div = min_fractional_feed_div;
1178 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
1179 uint32_t frac_feedback_div;
1180 uint64_t tmp;
1181
1182 feedback_div = (min_feed_div + max_feed_div) / 2;
1183
1184 tmp = (uint64_t)pll->reference_freq * feedback_div;
1185 vco = radeon_div(tmp, ref_div);
1186
1187 if (vco < pll_out_min) {
1188 min_feed_div = feedback_div + 1;
1189 continue;
1190 } else if (vco > pll_out_max) {
1191 max_feed_div = feedback_div;
1192 continue;
1193 }
1194
1195 while (min_frac_feed_div < max_frac_feed_div) {
1196 frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
1197 tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
1198 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
1199 current_freq = radeon_div(tmp, ref_div * post_div);
1200
1201 if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
1202 if (freq < current_freq)
1203 error = 0xffffffff;
1204 else
1205 error = freq - current_freq;
1206 } else
1207 error = abs(current_freq - freq);
1208 vco_diff = abs(vco - best_vco);
1209
1210 if ((best_vco == 0 && error < best_error) ||
1211 (best_vco != 0 &&
1212 ((best_error > 100 && error < best_error - 100) ||
1213 (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
1214 best_post_div = post_div;
1215 best_ref_div = ref_div;
1216 best_feedback_div = feedback_div;
1217 best_frac_feedback_div = frac_feedback_div;
1218 best_freq = current_freq;
1219 best_error = error;
1220 best_vco_diff = vco_diff;
1221 } else if (current_freq == freq) {
1222 if (best_freq == -1) {
1223 best_post_div = post_div;
1224 best_ref_div = ref_div;
1225 best_feedback_div = feedback_div;
1226 best_frac_feedback_div = frac_feedback_div;
1227 best_freq = current_freq;
1228 best_error = error;
1229 best_vco_diff = vco_diff;
1230 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
1231 ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
1232 ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
1233 ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
1234 ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
1235 ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
1236 best_post_div = post_div;
1237 best_ref_div = ref_div;
1238 best_feedback_div = feedback_div;
1239 best_frac_feedback_div = frac_feedback_div;
1240 best_freq = current_freq;
1241 best_error = error;
1242 best_vco_diff = vco_diff;
1243 }
1244 }
1245 if (current_freq < freq)
1246 min_frac_feed_div = frac_feedback_div + 1;
1247 else
1248 max_frac_feed_div = frac_feedback_div;
1249 }
1250 if (current_freq < freq)
1251 min_feed_div = feedback_div + 1;
1252 else
1253 max_feed_div = feedback_div;
1254 }
1255 }
1256 }
1257
1258 *dot_clock_p = best_freq / 10000;
1259 *fb_div_p = best_feedback_div;
1260 *frac_fb_div_p = best_frac_feedback_div;
1261 *ref_div_p = best_ref_div;
1262 *post_div_p = best_post_div;
1263 DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1264 (long long)freq,
1265 best_freq / 1000, best_feedback_div, best_frac_feedback_div,
1266 best_ref_div, best_post_div);
1267
1268 }
1269
1270 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
1271 {
1272 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1273
1274 if (radeon_fb->obj) {
1275 drm_gem_object_unreference_unlocked(radeon_fb->obj);
1276 }
1277 drm_framebuffer_cleanup(fb);
1278 kfree(radeon_fb);
1279 }
1280
1281 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
1282 struct drm_file *file_priv,
1283 unsigned int *handle)
1284 {
1285 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1286
1287 return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
1288 }
1289
1290 static const struct drm_framebuffer_funcs radeon_fb_funcs = {
1291 .destroy = radeon_user_framebuffer_destroy,
1292 .create_handle = radeon_user_framebuffer_create_handle,
1293 };
1294
1295 int
1296 radeon_framebuffer_init(struct drm_device *dev,
1297 struct radeon_framebuffer *rfb,
1298 const struct drm_mode_fb_cmd2 *mode_cmd,
1299 struct drm_gem_object *obj)
1300 {
1301 int ret;
1302 rfb->obj = obj;
1303 drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);
1304 ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs);
1305 if (ret) {
1306 rfb->obj = NULL;
1307 return ret;
1308 }
1309 return 0;
1310 }
1311
1312 static struct drm_framebuffer *
1313 radeon_user_framebuffer_create(struct drm_device *dev,
1314 struct drm_file *file_priv,
1315 const struct drm_mode_fb_cmd2 *mode_cmd)
1316 {
1317 struct drm_gem_object *obj;
1318 struct radeon_framebuffer *radeon_fb;
1319 int ret;
1320
1321 obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]);
1322 if (obj == NULL) {
1323 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
1324 "can't create framebuffer\n", mode_cmd->handles[0]);
1325 return ERR_PTR(-ENOENT);
1326 }
1327
1328 radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
1329 if (radeon_fb == NULL) {
1330 drm_gem_object_unreference_unlocked(obj);
1331 return ERR_PTR(-ENOMEM);
1332 }
1333
1334 ret = radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj);
1335 if (ret) {
1336 kfree(radeon_fb);
1337 drm_gem_object_unreference_unlocked(obj);
1338 return ERR_PTR(ret);
1339 }
1340
1341 return &radeon_fb->base;
1342 }
1343
1344 static void radeon_output_poll_changed(struct drm_device *dev)
1345 {
1346 struct radeon_device *rdev = dev->dev_private;
1347 radeon_fb_output_poll_changed(rdev);
1348 }
1349
1350 static const struct drm_mode_config_funcs radeon_mode_funcs = {
1351 .fb_create = radeon_user_framebuffer_create,
1352 .output_poll_changed = radeon_output_poll_changed
1353 };
1354
1355 static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
1356 { { 0, "driver" },
1357 { 1, "bios" },
1358 };
1359
1360 static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
1361 { { TV_STD_NTSC, "ntsc" },
1362 { TV_STD_PAL, "pal" },
1363 { TV_STD_PAL_M, "pal-m" },
1364 { TV_STD_PAL_60, "pal-60" },
1365 { TV_STD_NTSC_J, "ntsc-j" },
1366 { TV_STD_SCART_PAL, "scart-pal" },
1367 { TV_STD_PAL_CN, "pal-cn" },
1368 { TV_STD_SECAM, "secam" },
1369 };
1370
1371 static struct drm_prop_enum_list radeon_underscan_enum_list[] =
1372 { { UNDERSCAN_OFF, "off" },
1373 { UNDERSCAN_ON, "on" },
1374 { UNDERSCAN_AUTO, "auto" },
1375 };
1376
1377 static struct drm_prop_enum_list radeon_audio_enum_list[] =
1378 { { RADEON_AUDIO_DISABLE, "off" },
1379 { RADEON_AUDIO_ENABLE, "on" },
1380 { RADEON_AUDIO_AUTO, "auto" },
1381 };
1382
1383 /* XXX support different dither options? spatial, temporal, both, etc. */
1384 static struct drm_prop_enum_list radeon_dither_enum_list[] =
1385 { { RADEON_FMT_DITHER_DISABLE, "off" },
1386 { RADEON_FMT_DITHER_ENABLE, "on" },
1387 };
1388
1389 static int radeon_modeset_create_props(struct radeon_device *rdev)
1390 {
1391 int sz;
1392
1393 if (rdev->is_atom_bios) {
1394 rdev->mode_info.coherent_mode_property =
1395 drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1);
1396 if (!rdev->mode_info.coherent_mode_property)
1397 return -ENOMEM;
1398 }
1399
1400 if (!ASIC_IS_AVIVO(rdev)) {
1401 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
1402 rdev->mode_info.tmds_pll_property =
1403 drm_property_create_enum(rdev->ddev, 0,
1404 "tmds_pll",
1405 radeon_tmds_pll_enum_list, sz);
1406 }
1407
1408 rdev->mode_info.load_detect_property =
1409 drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1);
1410 if (!rdev->mode_info.load_detect_property)
1411 return -ENOMEM;
1412
1413 drm_mode_create_scaling_mode_property(rdev->ddev);
1414
1415 sz = ARRAY_SIZE(radeon_tv_std_enum_list);
1416 rdev->mode_info.tv_std_property =
1417 drm_property_create_enum(rdev->ddev, 0,
1418 "tv standard",
1419 radeon_tv_std_enum_list, sz);
1420
1421 sz = ARRAY_SIZE(radeon_underscan_enum_list);
1422 rdev->mode_info.underscan_property =
1423 drm_property_create_enum(rdev->ddev, 0,
1424 "underscan",
1425 radeon_underscan_enum_list, sz);
1426
1427 rdev->mode_info.underscan_hborder_property =
1428 drm_property_create_range(rdev->ddev, 0,
1429 "underscan hborder", 0, 128);
1430 if (!rdev->mode_info.underscan_hborder_property)
1431 return -ENOMEM;
1432
1433 rdev->mode_info.underscan_vborder_property =
1434 drm_property_create_range(rdev->ddev, 0,
1435 "underscan vborder", 0, 128);
1436 if (!rdev->mode_info.underscan_vborder_property)
1437 return -ENOMEM;
1438
1439 sz = ARRAY_SIZE(radeon_audio_enum_list);
1440 rdev->mode_info.audio_property =
1441 drm_property_create_enum(rdev->ddev, 0,
1442 "audio",
1443 radeon_audio_enum_list, sz);
1444
1445 sz = ARRAY_SIZE(radeon_dither_enum_list);
1446 rdev->mode_info.dither_property =
1447 drm_property_create_enum(rdev->ddev, 0,
1448 "dither",
1449 radeon_dither_enum_list, sz);
1450
1451 return 0;
1452 }
1453
1454 void radeon_update_display_priority(struct radeon_device *rdev)
1455 {
1456 /* adjustment options for the display watermarks */
1457 if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
1458 /* set display priority to high for r3xx, rv515 chips
1459 * this avoids flickering due to underflow to the
1460 * display controllers during heavy acceleration.
1461 * Don't force high on rs4xx igp chips as it seems to
1462 * affect the sound card. See kernel bug 15982.
1463 */
1464 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
1465 !(rdev->flags & RADEON_IS_IGP))
1466 rdev->disp_priority = 2;
1467 else
1468 rdev->disp_priority = 0;
1469 } else
1470 rdev->disp_priority = radeon_disp_priority;
1471
1472 }
1473
1474 /*
1475 * Allocate hdmi structs and determine register offsets
1476 */
1477 static void radeon_afmt_init(struct radeon_device *rdev)
1478 {
1479 int i;
1480
1481 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++)
1482 rdev->mode_info.afmt[i] = NULL;
1483
1484 if (ASIC_IS_NODCE(rdev)) {
1485 /* nothing to do */
1486 } else if (ASIC_IS_DCE4(rdev)) {
1487 static uint32_t eg_offsets[] = {
1488 EVERGREEN_CRTC0_REGISTER_OFFSET,
1489 EVERGREEN_CRTC1_REGISTER_OFFSET,
1490 EVERGREEN_CRTC2_REGISTER_OFFSET,
1491 EVERGREEN_CRTC3_REGISTER_OFFSET,
1492 EVERGREEN_CRTC4_REGISTER_OFFSET,
1493 EVERGREEN_CRTC5_REGISTER_OFFSET,
1494 0x13830 - 0x7030,
1495 };
1496 int num_afmt;
1497
1498 /* DCE8 has 7 audio blocks tied to DIG encoders */
1499 /* DCE6 has 6 audio blocks tied to DIG encoders */
1500 /* DCE4/5 has 6 audio blocks tied to DIG encoders */
1501 /* DCE4.1 has 2 audio blocks tied to DIG encoders */
1502 if (ASIC_IS_DCE8(rdev))
1503 num_afmt = 7;
1504 else if (ASIC_IS_DCE6(rdev))
1505 num_afmt = 6;
1506 else if (ASIC_IS_DCE5(rdev))
1507 num_afmt = 6;
1508 else if (ASIC_IS_DCE41(rdev))
1509 num_afmt = 2;
1510 else /* DCE4 */
1511 num_afmt = 6;
1512
1513 BUG_ON(num_afmt > ARRAY_SIZE(eg_offsets));
1514 for (i = 0; i < num_afmt; i++) {
1515 rdev->mode_info.afmt[i] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1516 if (rdev->mode_info.afmt[i]) {
1517 rdev->mode_info.afmt[i]->offset = eg_offsets[i];
1518 rdev->mode_info.afmt[i]->id = i;
1519 }
1520 }
1521 } else if (ASIC_IS_DCE3(rdev)) {
1522 /* DCE3.x has 2 audio blocks tied to DIG encoders */
1523 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1524 if (rdev->mode_info.afmt[0]) {
1525 rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0;
1526 rdev->mode_info.afmt[0]->id = 0;
1527 }
1528 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1529 if (rdev->mode_info.afmt[1]) {
1530 rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1;
1531 rdev->mode_info.afmt[1]->id = 1;
1532 }
1533 } else if (ASIC_IS_DCE2(rdev)) {
1534 /* DCE2 has at least 1 routable audio block */
1535 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1536 if (rdev->mode_info.afmt[0]) {
1537 rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0;
1538 rdev->mode_info.afmt[0]->id = 0;
1539 }
1540 /* r6xx has 2 routable audio blocks */
1541 if (rdev->family >= CHIP_R600) {
1542 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1543 if (rdev->mode_info.afmt[1]) {
1544 rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1;
1545 rdev->mode_info.afmt[1]->id = 1;
1546 }
1547 }
1548 }
1549 }
1550
1551 static void radeon_afmt_fini(struct radeon_device *rdev)
1552 {
1553 int i;
1554
1555 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) {
1556 kfree(rdev->mode_info.afmt[i]);
1557 rdev->mode_info.afmt[i] = NULL;
1558 }
1559 }
1560
1561 int radeon_modeset_init(struct radeon_device *rdev)
1562 {
1563 int i;
1564 int ret;
1565
1566 drm_mode_config_init(rdev->ddev);
1567 rdev->mode_info.mode_config_initialized = true;
1568
1569 rdev->ddev->mode_config.funcs = &radeon_mode_funcs;
1570
1571 if (ASIC_IS_DCE5(rdev)) {
1572 rdev->ddev->mode_config.max_width = 16384;
1573 rdev->ddev->mode_config.max_height = 16384;
1574 } else if (ASIC_IS_AVIVO(rdev)) {
1575 rdev->ddev->mode_config.max_width = 8192;
1576 rdev->ddev->mode_config.max_height = 8192;
1577 } else {
1578 rdev->ddev->mode_config.max_width = 4096;
1579 rdev->ddev->mode_config.max_height = 4096;
1580 }
1581
1582 rdev->ddev->mode_config.preferred_depth = 24;
1583 rdev->ddev->mode_config.prefer_shadow = 1;
1584
1585 rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
1586
1587 ret = radeon_modeset_create_props(rdev);
1588 if (ret) {
1589 return ret;
1590 }
1591
1592 /* init i2c buses */
1593 radeon_i2c_init(rdev);
1594
1595 /* check combios for a valid hardcoded EDID - Sun servers */
1596 if (!rdev->is_atom_bios) {
1597 /* check for hardcoded EDID in BIOS */
1598 radeon_combios_check_hardcoded_edid(rdev);
1599 }
1600
1601 /* allocate crtcs */
1602 for (i = 0; i < rdev->num_crtc; i++) {
1603 radeon_crtc_init(rdev->ddev, i);
1604 }
1605
1606 /* okay we should have all the bios connectors */
1607 ret = radeon_setup_enc_conn(rdev->ddev);
1608 if (!ret) {
1609 return ret;
1610 }
1611
1612 /* init dig PHYs, disp eng pll */
1613 if (rdev->is_atom_bios) {
1614 radeon_atom_encoder_init(rdev);
1615 radeon_atom_disp_eng_pll_init(rdev);
1616 }
1617
1618 /* initialize hpd */
1619 radeon_hpd_init(rdev);
1620
1621 /* setup afmt */
1622 radeon_afmt_init(rdev);
1623
1624 radeon_fbdev_init(rdev);
1625 drm_kms_helper_poll_init(rdev->ddev);
1626
1627 if (rdev->pm.dpm_enabled) {
1628 /* do dpm late init */
1629 ret = radeon_pm_late_init(rdev);
1630 if (ret) {
1631 rdev->pm.dpm_enabled = false;
1632 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
1633 }
1634 /* set the dpm state for PX since there won't be
1635 * a modeset to call this.
1636 */
1637 radeon_pm_compute_clocks(rdev);
1638 }
1639
1640 return 0;
1641 }
1642
1643 void radeon_modeset_fini(struct radeon_device *rdev)
1644 {
1645 radeon_fbdev_fini(rdev);
1646 kfree(rdev->mode_info.bios_hardcoded_edid);
1647
1648 if (rdev->mode_info.mode_config_initialized) {
1649 radeon_afmt_fini(rdev);
1650 drm_kms_helper_poll_fini(rdev->ddev);
1651 radeon_hpd_fini(rdev);
1652 DRM_UNLOCK(rdev->ddev); /* Work around lock recursion. dumbbell@ */
1653 drm_mode_config_cleanup(rdev->ddev);
1654 DRM_LOCK(rdev->ddev);
1655 rdev->mode_info.mode_config_initialized = false;
1656 }
1657 /* free i2c buses */
1658 radeon_i2c_fini(rdev);
1659 }
1660
1661 static bool is_hdtv_mode(const struct drm_display_mode *mode)
1662 {
1663 /* try and guess if this is a tv or a monitor */
1664 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1665 (mode->vdisplay == 576) || /* 576p */
1666 (mode->vdisplay == 720) || /* 720p */
1667 (mode->vdisplay == 1080)) /* 1080p */
1668 return true;
1669 else
1670 return false;
1671 }
1672
1673 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1674 const struct drm_display_mode *mode,
1675 struct drm_display_mode *adjusted_mode)
1676 {
1677 struct drm_device *dev = crtc->dev;
1678 struct radeon_device *rdev = dev->dev_private;
1679 struct drm_encoder *encoder;
1680 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1681 struct radeon_encoder *radeon_encoder;
1682 struct drm_connector *connector;
1683 struct radeon_connector *radeon_connector;
1684 bool first = true;
1685 u32 src_v = 1, dst_v = 1;
1686 u32 src_h = 1, dst_h = 1;
1687
1688 radeon_crtc->h_border = 0;
1689 radeon_crtc->v_border = 0;
1690
1691 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1692 if (encoder->crtc != crtc)
1693 continue;
1694 radeon_encoder = to_radeon_encoder(encoder);
1695 connector = radeon_get_connector_for_encoder(encoder);
1696 radeon_connector = to_radeon_connector(connector);
1697
1698 if (first) {
1699 /* set scaling */
1700 if (radeon_encoder->rmx_type == RMX_OFF)
1701 radeon_crtc->rmx_type = RMX_OFF;
1702 else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
1703 mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1704 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1705 else
1706 radeon_crtc->rmx_type = RMX_OFF;
1707 /* copy native mode */
1708 memcpy(&radeon_crtc->native_mode,
1709 &radeon_encoder->native_mode,
1710 sizeof(struct drm_display_mode));
1711 src_v = crtc->mode.vdisplay;
1712 dst_v = radeon_crtc->native_mode.vdisplay;
1713 src_h = crtc->mode.hdisplay;
1714 dst_h = radeon_crtc->native_mode.hdisplay;
1715
1716 /* fix up for overscan on hdmi */
1717 if (ASIC_IS_AVIVO(rdev) &&
1718 (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1719 ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1720 ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
1721 drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
1722 is_hdtv_mode(mode)))) {
1723 if (radeon_encoder->underscan_hborder != 0)
1724 radeon_crtc->h_border = radeon_encoder->underscan_hborder;
1725 else
1726 radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1727 if (radeon_encoder->underscan_vborder != 0)
1728 radeon_crtc->v_border = radeon_encoder->underscan_vborder;
1729 else
1730 radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
1731 radeon_crtc->rmx_type = RMX_FULL;
1732 src_v = crtc->mode.vdisplay;
1733 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
1734 src_h = crtc->mode.hdisplay;
1735 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
1736 }
1737 first = false;
1738 } else {
1739 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1740 /* WARNING: Right now this can't happen but
1741 * in the future we need to check that scaling
1742 * are consistent across different encoder
1743 * (ie all encoder can work with the same
1744 * scaling).
1745 */
1746 DRM_ERROR("Scaling not consistent across encoder.\n");
1747 return false;
1748 }
1749 }
1750 }
1751 if (radeon_crtc->rmx_type != RMX_OFF) {
1752 fixed20_12 a, b;
1753 a.full = dfixed_const(src_v);
1754 b.full = dfixed_const(dst_v);
1755 radeon_crtc->vsc.full = dfixed_div(a, b);
1756 a.full = dfixed_const(src_h);
1757 b.full = dfixed_const(dst_h);
1758 radeon_crtc->hsc.full = dfixed_div(a, b);
1759 } else {
1760 radeon_crtc->vsc.full = dfixed_const(1);
1761 radeon_crtc->hsc.full = dfixed_const(1);
1762 }
1763 return true;
1764 }
1765
1766 /*
1767 * Retrieve current video scanout position of crtc on a given gpu, and
1768 * an optional accurate timestamp of when query happened.
1769 *
1770 * \param dev Device to query.
1771 * \param crtc Crtc to query.
1772 * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
1773 * \param *vpos Location where vertical scanout position should be stored.
1774 * \param *hpos Location where horizontal scanout position should go.
1775 * \param *stime Target location for timestamp taken immediately before
1776 * scanout position query. Can be NULL to skip timestamp.
1777 * \param *etime Target location for timestamp taken immediately after
1778 * scanout position query. Can be NULL to skip timestamp.
1779 *
1780 * Returns vpos as a positive number while in active scanout area.
1781 * Returns vpos as a negative number inside vblank, counting the number
1782 * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1783 * until start of active scanout / end of vblank."
1784 *
1785 * \return Flags, or'ed together as follows:
1786 *
1787 * DRM_SCANOUTPOS_VALID = Query successful.
1788 * DRM_SCANOUTPOS_INVBL = Inside vblank.
1789 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1790 * this flag means that returned position may be offset by a constant but
1791 * unknown small number of scanlines wrt. real scanout position.
1792 *
1793 */
1794 int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, unsigned int flags,
1795 int *vpos, int *hpos, ktime_t *stime, ktime_t *etime,
1796 const struct drm_display_mode *mode)
1797 {
1798 u32 stat_crtc = 0, vbl = 0, position = 0;
1799 int vbl_start, vbl_end, vtotal, ret = 0;
1800 bool in_vbl = true;
1801
1802 struct radeon_device *rdev = dev->dev_private;
1803
1804 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
1805
1806 /* Get optional system timestamp before query. */
1807 if (stime)
1808 *stime = ktime_get();
1809
1810 if (ASIC_IS_DCE4(rdev)) {
1811 if (crtc == 0) {
1812 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1813 EVERGREEN_CRTC0_REGISTER_OFFSET);
1814 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1815 EVERGREEN_CRTC0_REGISTER_OFFSET);
1816 ret |= DRM_SCANOUTPOS_VALID;
1817 }
1818 if (crtc == 1) {
1819 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1820 EVERGREEN_CRTC1_REGISTER_OFFSET);
1821 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1822 EVERGREEN_CRTC1_REGISTER_OFFSET);
1823 ret |= DRM_SCANOUTPOS_VALID;
1824 }
1825 if (crtc == 2) {
1826 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1827 EVERGREEN_CRTC2_REGISTER_OFFSET);
1828 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1829 EVERGREEN_CRTC2_REGISTER_OFFSET);
1830 ret |= DRM_SCANOUTPOS_VALID;
1831 }
1832 if (crtc == 3) {
1833 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1834 EVERGREEN_CRTC3_REGISTER_OFFSET);
1835 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1836 EVERGREEN_CRTC3_REGISTER_OFFSET);
1837 ret |= DRM_SCANOUTPOS_VALID;
1838 }
1839 if (crtc == 4) {
1840 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1841 EVERGREEN_CRTC4_REGISTER_OFFSET);
1842 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1843 EVERGREEN_CRTC4_REGISTER_OFFSET);
1844 ret |= DRM_SCANOUTPOS_VALID;
1845 }
1846 if (crtc == 5) {
1847 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1848 EVERGREEN_CRTC5_REGISTER_OFFSET);
1849 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1850 EVERGREEN_CRTC5_REGISTER_OFFSET);
1851 ret |= DRM_SCANOUTPOS_VALID;
1852 }
1853 } else if (ASIC_IS_AVIVO(rdev)) {
1854 if (crtc == 0) {
1855 vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
1856 position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
1857 ret |= DRM_SCANOUTPOS_VALID;
1858 }
1859 if (crtc == 1) {
1860 vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
1861 position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
1862 ret |= DRM_SCANOUTPOS_VALID;
1863 }
1864 } else {
1865 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
1866 if (crtc == 0) {
1867 /* Assume vbl_end == 0, get vbl_start from
1868 * upper 16 bits.
1869 */
1870 vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &
1871 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1872 /* Only retrieve vpos from upper 16 bits, set hpos == 0. */
1873 position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1874 stat_crtc = RREG32(RADEON_CRTC_STATUS);
1875 if (!(stat_crtc & 1))
1876 in_vbl = false;
1877
1878 ret |= DRM_SCANOUTPOS_VALID;
1879 }
1880 if (crtc == 1) {
1881 vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
1882 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1883 position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1884 stat_crtc = RREG32(RADEON_CRTC2_STATUS);
1885 if (!(stat_crtc & 1))
1886 in_vbl = false;
1887
1888 ret |= DRM_SCANOUTPOS_VALID;
1889 }
1890 }
1891
1892 /* Get optional system timestamp after query. */
1893 if (etime)
1894 *etime = ktime_get();
1895
1896 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
1897
1898 /* Decode into vertical and horizontal scanout position. */
1899 *vpos = position & 0x1fff;
1900 *hpos = (position >> 16) & 0x1fff;
1901
1902 /* Valid vblank area boundaries from gpu retrieved? */
1903 if (vbl > 0) {
1904 /* Yes: Decode. */
1905 ret |= DRM_SCANOUTPOS_ACCURATE;
1906 vbl_start = vbl & 0x1fff;
1907 vbl_end = (vbl >> 16) & 0x1fff;
1908 }
1909 else {
1910 /* No: Fake something reasonable which gives at least ok results. */
1911 vbl_start = mode->crtc_vdisplay;
1912 vbl_end = 0;
1913 }
1914
1915 /* Test scanout position against vblank region. */
1916 if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1917 in_vbl = false;
1918
1919 /* Check if inside vblank area and apply corrective offsets:
1920 * vpos will then be >=0 in video scanout area, but negative
1921 * within vblank area, counting down the number of lines until
1922 * start of scanout.
1923 */
1924
1925 /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1926 if (in_vbl && (*vpos >= vbl_start)) {
1927 vtotal = mode->crtc_vtotal;
1928 *vpos = *vpos - vtotal;
1929 }
1930
1931 /* Correct for shifted end of vbl at vbl_end. */
1932 *vpos = *vpos - vbl_end;
1933
1934 /* In vblank? */
1935 if (in_vbl)
1936 ret |= DRM_SCANOUTPOS_IN_VBLANK;
1937
1938 /* Is vpos outside nominal vblank area, but less than
1939 * 1/100 of a frame height away from start of vblank?
1940 * If so, assume this isn't a massively delayed vblank
1941 * interrupt, but a vblank interrupt that fired a few
1942 * microseconds before true start of vblank. Compensate
1943 * by adding a full frame duration to the final timestamp.
1944 * Happens, e.g., on ATI R500, R600.
1945 *
1946 * We only do this if DRM_CALLED_FROM_VBLIRQ.
1947 */
1948 if ((flags & DRM_CALLED_FROM_VBLIRQ) && !in_vbl) {
1949 vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
1950 vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
1951
1952 if (vbl_start - *vpos < vtotal / 100) {
1953 *vpos -= vtotal;
1954
1955 /* Signal this correction as "applied". */
1956 ret |= 0x8;
1957 }
1958 }
1959
1960 return ret;
1961 }
DragonFly BSD