2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
26 * $FreeBSD: head/sys/dev/drm2/radeon/radeon_atombios.c 254885 2013-08-25 19:37:15Z dumbbell $
30 #include <uapi_drm/radeon_drm.h>
32 #include "radeon_asic.h"
35 #include "atom-bits.h"
37 union atom_supported_devices
{
38 struct _ATOM_SUPPORTED_DEVICES_INFO info
;
39 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2
;
40 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1
;
43 static void radeon_lookup_i2c_gpio_quirks(struct radeon_device
*rdev
,
44 ATOM_GPIO_I2C_ASSIGMENT
*gpio
,
47 /* r4xx mask is technically not used by the hw, so patch in the legacy mask bits */
48 if ((rdev
->family
== CHIP_R420
) ||
49 (rdev
->family
== CHIP_R423
) ||
50 (rdev
->family
== CHIP_RV410
)) {
51 if ((le16_to_cpu(gpio
->usClkMaskRegisterIndex
) == 0x0018) ||
52 (le16_to_cpu(gpio
->usClkMaskRegisterIndex
) == 0x0019) ||
53 (le16_to_cpu(gpio
->usClkMaskRegisterIndex
) == 0x001a)) {
54 gpio
->ucClkMaskShift
= 0x19;
55 gpio
->ucDataMaskShift
= 0x18;
59 /* some evergreen boards have bad data for this entry */
60 if (ASIC_IS_DCE4(rdev
)) {
62 (le16_to_cpu(gpio
->usClkMaskRegisterIndex
) == 0x1936) &&
63 (gpio
->sucI2cId
.ucAccess
== 0)) {
64 gpio
->sucI2cId
.ucAccess
= 0x97;
65 gpio
->ucDataMaskShift
= 8;
66 gpio
->ucDataEnShift
= 8;
67 gpio
->ucDataY_Shift
= 8;
68 gpio
->ucDataA_Shift
= 8;
72 /* some DCE3 boards have bad data for this entry */
73 if (ASIC_IS_DCE3(rdev
)) {
75 (le16_to_cpu(gpio
->usClkMaskRegisterIndex
) == 0x1fda) &&
76 (gpio
->sucI2cId
.ucAccess
== 0x94))
77 gpio
->sucI2cId
.ucAccess
= 0x14;
81 static struct radeon_i2c_bus_rec
radeon_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT
*gpio
)
83 struct radeon_i2c_bus_rec i2c
;
85 memset(&i2c
, 0, sizeof(struct radeon_i2c_bus_rec
));
87 i2c
.mask_clk_reg
= le16_to_cpu(gpio
->usClkMaskRegisterIndex
) * 4;
88 i2c
.mask_data_reg
= le16_to_cpu(gpio
->usDataMaskRegisterIndex
) * 4;
89 i2c
.en_clk_reg
= le16_to_cpu(gpio
->usClkEnRegisterIndex
) * 4;
90 i2c
.en_data_reg
= le16_to_cpu(gpio
->usDataEnRegisterIndex
) * 4;
91 i2c
.y_clk_reg
= le16_to_cpu(gpio
->usClkY_RegisterIndex
) * 4;
92 i2c
.y_data_reg
= le16_to_cpu(gpio
->usDataY_RegisterIndex
) * 4;
93 i2c
.a_clk_reg
= le16_to_cpu(gpio
->usClkA_RegisterIndex
) * 4;
94 i2c
.a_data_reg
= le16_to_cpu(gpio
->usDataA_RegisterIndex
) * 4;
95 i2c
.mask_clk_mask
= (1 << gpio
->ucClkMaskShift
);
96 i2c
.mask_data_mask
= (1 << gpio
->ucDataMaskShift
);
97 i2c
.en_clk_mask
= (1 << gpio
->ucClkEnShift
);
98 i2c
.en_data_mask
= (1 << gpio
->ucDataEnShift
);
99 i2c
.y_clk_mask
= (1 << gpio
->ucClkY_Shift
);
100 i2c
.y_data_mask
= (1 << gpio
->ucDataY_Shift
);
101 i2c
.a_clk_mask
= (1 << gpio
->ucClkA_Shift
);
102 i2c
.a_data_mask
= (1 << gpio
->ucDataA_Shift
);
104 if (gpio
->sucI2cId
.sbfAccess
.bfHW_Capable
)
105 i2c
.hw_capable
= true;
107 i2c
.hw_capable
= false;
109 if (gpio
->sucI2cId
.ucAccess
== 0xa0)
114 i2c
.i2c_id
= gpio
->sucI2cId
.ucAccess
;
116 if (i2c
.mask_clk_reg
)
124 static struct radeon_i2c_bus_rec
radeon_lookup_i2c_gpio(struct radeon_device
*rdev
,
127 struct atom_context
*ctx
= rdev
->mode_info
.atom_context
;
128 ATOM_GPIO_I2C_ASSIGMENT
*gpio
;
129 struct radeon_i2c_bus_rec i2c
;
130 int index
= GetIndexIntoMasterTable(DATA
, GPIO_I2C_Info
);
131 struct _ATOM_GPIO_I2C_INFO
*i2c_info
;
132 uint16_t data_offset
, size
;
135 memset(&i2c
, 0, sizeof(struct radeon_i2c_bus_rec
));
138 if (atom_parse_data_header(ctx
, index
, &size
, NULL
, NULL
, &data_offset
)) {
139 i2c_info
= (struct _ATOM_GPIO_I2C_INFO
*)((char *)ctx
->bios
+ data_offset
);
141 num_indices
= (size
- sizeof(ATOM_COMMON_TABLE_HEADER
)) /
142 sizeof(ATOM_GPIO_I2C_ASSIGMENT
);
144 gpio
= &i2c_info
->asGPIO_Info
[0];
145 for (i
= 0; i
< num_indices
; i
++) {
147 radeon_lookup_i2c_gpio_quirks(rdev
, gpio
, i
);
149 if (gpio
->sucI2cId
.ucAccess
== id
) {
150 i2c
= radeon_get_bus_rec_for_i2c_gpio(gpio
);
153 gpio
= (ATOM_GPIO_I2C_ASSIGMENT
*)
154 ((u8
*)gpio
+ sizeof(ATOM_GPIO_I2C_ASSIGMENT
));
161 void radeon_atombios_i2c_init(struct radeon_device
*rdev
)
163 struct atom_context
*ctx
= rdev
->mode_info
.atom_context
;
164 ATOM_GPIO_I2C_ASSIGMENT
*gpio
;
165 struct radeon_i2c_bus_rec i2c
;
166 int index
= GetIndexIntoMasterTable(DATA
, GPIO_I2C_Info
);
167 struct _ATOM_GPIO_I2C_INFO
*i2c_info
;
168 uint16_t data_offset
, size
;
172 if (atom_parse_data_header(ctx
, index
, &size
, NULL
, NULL
, &data_offset
)) {
173 i2c_info
= (struct _ATOM_GPIO_I2C_INFO
*)((char *)ctx
->bios
+ data_offset
);
175 num_indices
= (size
- sizeof(ATOM_COMMON_TABLE_HEADER
)) /
176 sizeof(ATOM_GPIO_I2C_ASSIGMENT
);
178 gpio
= &i2c_info
->asGPIO_Info
[0];
179 for (i
= 0; i
< num_indices
; i
++) {
180 radeon_lookup_i2c_gpio_quirks(rdev
, gpio
, i
);
182 i2c
= radeon_get_bus_rec_for_i2c_gpio(gpio
);
185 ksprintf(stmp
, "0x%x", i2c
.i2c_id
);
186 rdev
->i2c_bus
[i
] = radeon_i2c_create(rdev
->ddev
, &i2c
, stmp
);
188 gpio
= (ATOM_GPIO_I2C_ASSIGMENT
*)
189 ((u8
*)gpio
+ sizeof(ATOM_GPIO_I2C_ASSIGMENT
));
194 static struct radeon_gpio_rec
radeon_lookup_gpio(struct radeon_device
*rdev
,
197 struct atom_context
*ctx
= rdev
->mode_info
.atom_context
;
198 struct radeon_gpio_rec gpio
;
199 int index
= GetIndexIntoMasterTable(DATA
, GPIO_Pin_LUT
);
200 struct _ATOM_GPIO_PIN_LUT
*gpio_info
;
201 ATOM_GPIO_PIN_ASSIGNMENT
*pin
;
202 u16 data_offset
, size
;
205 memset(&gpio
, 0, sizeof(struct radeon_gpio_rec
));
208 if (atom_parse_data_header(ctx
, index
, &size
, NULL
, NULL
, &data_offset
)) {
209 gpio_info
= (struct _ATOM_GPIO_PIN_LUT
*)((char *)ctx
->bios
+ data_offset
);
211 num_indices
= (size
- sizeof(ATOM_COMMON_TABLE_HEADER
)) /
212 sizeof(ATOM_GPIO_PIN_ASSIGNMENT
);
214 pin
= gpio_info
->asGPIO_Pin
;
215 for (i
= 0; i
< num_indices
; i
++) {
216 if (id
== pin
->ucGPIO_ID
) {
217 gpio
.id
= pin
->ucGPIO_ID
;
218 gpio
.reg
= le16_to_cpu(pin
->usGpioPin_AIndex
) * 4;
219 gpio
.mask
= (1 << pin
->ucGpioPinBitShift
);
223 pin
= (ATOM_GPIO_PIN_ASSIGNMENT
*)
224 ((u8
*)pin
+ sizeof(ATOM_GPIO_PIN_ASSIGNMENT
));
231 static struct radeon_hpd
radeon_atom_get_hpd_info_from_gpio(struct radeon_device
*rdev
,
232 struct radeon_gpio_rec
*gpio
)
234 struct radeon_hpd hpd
;
237 memset(&hpd
, 0, sizeof(struct radeon_hpd
));
239 if (ASIC_IS_DCE6(rdev
))
240 reg
= SI_DC_GPIO_HPD_A
;
241 else if (ASIC_IS_DCE4(rdev
))
242 reg
= EVERGREEN_DC_GPIO_HPD_A
;
244 reg
= AVIVO_DC_GPIO_HPD_A
;
247 if (gpio
->reg
== reg
) {
250 hpd
.hpd
= RADEON_HPD_1
;
253 hpd
.hpd
= RADEON_HPD_2
;
256 hpd
.hpd
= RADEON_HPD_3
;
259 hpd
.hpd
= RADEON_HPD_4
;
262 hpd
.hpd
= RADEON_HPD_5
;
265 hpd
.hpd
= RADEON_HPD_6
;
268 hpd
.hpd
= RADEON_HPD_NONE
;
272 hpd
.hpd
= RADEON_HPD_NONE
;
276 static bool radeon_atom_apply_quirks(struct drm_device
*dev
,
277 uint32_t supported_device
,
279 struct radeon_i2c_bus_rec
*i2c_bus
,
281 struct radeon_hpd
*hpd
)
284 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
285 if ((dev
->pdev
->device
== 0x791e) &&
286 (dev
->pdev
->subsystem_vendor
== 0x1043) &&
287 (dev
->pdev
->subsystem_device
== 0x826d)) {
288 if ((*connector_type
== DRM_MODE_CONNECTOR_HDMIA
) &&
289 (supported_device
== ATOM_DEVICE_DFP3_SUPPORT
))
290 *connector_type
= DRM_MODE_CONNECTOR_DVID
;
293 /* Asrock RS600 board lists the DVI port as HDMI */
294 if ((dev
->pdev
->device
== 0x7941) &&
295 (dev
->pdev
->subsystem_vendor
== 0x1849) &&
296 (dev
->pdev
->subsystem_device
== 0x7941)) {
297 if ((*connector_type
== DRM_MODE_CONNECTOR_HDMIA
) &&
298 (supported_device
== ATOM_DEVICE_DFP3_SUPPORT
))
299 *connector_type
= DRM_MODE_CONNECTOR_DVID
;
302 /* MSI K9A2GM V2/V3 board has no HDMI or DVI */
303 if ((dev
->pdev
->device
== 0x796e) &&
304 (dev
->pdev
->subsystem_vendor
== 0x1462) &&
305 (dev
->pdev
->subsystem_device
== 0x7302)) {
306 if ((supported_device
== ATOM_DEVICE_DFP2_SUPPORT
) ||
307 (supported_device
== ATOM_DEVICE_DFP3_SUPPORT
))
311 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
312 if ((dev
->pdev
->device
== 0x7941) &&
313 (dev
->pdev
->subsystem_vendor
== 0x147b) &&
314 (dev
->pdev
->subsystem_device
== 0x2412)) {
315 if (*connector_type
== DRM_MODE_CONNECTOR_DVII
)
319 /* Falcon NW laptop lists vga ddc line for LVDS */
320 if ((dev
->pdev
->device
== 0x5653) &&
321 (dev
->pdev
->subsystem_vendor
== 0x1462) &&
322 (dev
->pdev
->subsystem_device
== 0x0291)) {
323 if (*connector_type
== DRM_MODE_CONNECTOR_LVDS
) {
324 i2c_bus
->valid
= false;
329 /* HIS X1300 is DVI+VGA, not DVI+DVI */
330 if ((dev
->pdev
->device
== 0x7146) &&
331 (dev
->pdev
->subsystem_vendor
== 0x17af) &&
332 (dev
->pdev
->subsystem_device
== 0x2058)) {
333 if (supported_device
== ATOM_DEVICE_DFP1_SUPPORT
)
337 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
338 if ((dev
->pdev
->device
== 0x7142) &&
339 (dev
->pdev
->subsystem_vendor
== 0x1458) &&
340 (dev
->pdev
->subsystem_device
== 0x2134)) {
341 if (supported_device
== ATOM_DEVICE_DFP1_SUPPORT
)
347 if ((dev
->pdev
->device
== 0x71C5) &&
348 (dev
->pdev
->subsystem_vendor
== 0x106b) &&
349 (dev
->pdev
->subsystem_device
== 0x0080)) {
350 if ((supported_device
== ATOM_DEVICE_CRT1_SUPPORT
) ||
351 (supported_device
== ATOM_DEVICE_DFP2_SUPPORT
))
353 if (supported_device
== ATOM_DEVICE_CRT2_SUPPORT
)
357 /* mac rv630, rv730, others */
358 if ((supported_device
== ATOM_DEVICE_TV1_SUPPORT
) &&
359 (*connector_type
== DRM_MODE_CONNECTOR_DVII
)) {
360 *connector_type
= DRM_MODE_CONNECTOR_9PinDIN
;
361 *line_mux
= CONNECTOR_7PIN_DIN_ENUM_ID1
;
364 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
365 if ((dev
->pdev
->device
== 0x9598) &&
366 (dev
->pdev
->subsystem_vendor
== 0x1043) &&
367 (dev
->pdev
->subsystem_device
== 0x01da)) {
368 if (*connector_type
== DRM_MODE_CONNECTOR_HDMIA
) {
369 *connector_type
= DRM_MODE_CONNECTOR_DVII
;
373 /* ASUS HD 3600 board lists the DVI port as HDMI */
374 if ((dev
->pdev
->device
== 0x9598) &&
375 (dev
->pdev
->subsystem_vendor
== 0x1043) &&
376 (dev
->pdev
->subsystem_device
== 0x01e4)) {
377 if (*connector_type
== DRM_MODE_CONNECTOR_HDMIA
) {
378 *connector_type
= DRM_MODE_CONNECTOR_DVII
;
382 /* ASUS HD 3450 board lists the DVI port as HDMI */
383 if ((dev
->pdev
->device
== 0x95C5) &&
384 (dev
->pdev
->subsystem_vendor
== 0x1043) &&
385 (dev
->pdev
->subsystem_device
== 0x01e2)) {
386 if (*connector_type
== DRM_MODE_CONNECTOR_HDMIA
) {
387 *connector_type
= DRM_MODE_CONNECTOR_DVII
;
391 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
392 * HDMI + VGA reporting as HDMI
394 if (*connector_type
== DRM_MODE_CONNECTOR_HDMIA
) {
395 if (supported_device
& (ATOM_DEVICE_CRT_SUPPORT
)) {
396 *connector_type
= DRM_MODE_CONNECTOR_VGA
;
401 /* Acer laptop (Acer TravelMate 5730/5730G) has an HDMI port
402 * on the laptop and a DVI port on the docking station and
403 * both share the same encoder, hpd pin, and ddc line.
404 * So while the bios table is technically correct,
405 * we drop the DVI port here since xrandr has no concept of
406 * encoders and will try and drive both connectors
407 * with different crtcs which isn't possible on the hardware
408 * side and leaves no crtcs for LVDS or VGA.
410 if (((dev
->pdev
->device
== 0x95c4) || (dev
->pdev
->device
== 0x9591)) &&
411 (dev
->pdev
->subsystem_vendor
== 0x1025) &&
412 (dev
->pdev
->subsystem_device
== 0x013c)) {
413 if ((*connector_type
== DRM_MODE_CONNECTOR_DVII
) &&
414 (supported_device
== ATOM_DEVICE_DFP1_SUPPORT
)) {
415 /* actually it's a DVI-D port not DVI-I */
416 *connector_type
= DRM_MODE_CONNECTOR_DVID
;
421 /* XFX Pine Group device rv730 reports no VGA DDC lines
422 * even though they are wired up to record 0x93
424 if ((dev
->pdev
->device
== 0x9498) &&
425 (dev
->pdev
->subsystem_vendor
== 0x1682) &&
426 (dev
->pdev
->subsystem_device
== 0x2452) &&
427 (i2c_bus
->valid
== false) &&
428 !(supported_device
& (ATOM_DEVICE_TV_SUPPORT
| ATOM_DEVICE_CV_SUPPORT
))) {
429 struct radeon_device
*rdev
= dev
->dev_private
;
430 *i2c_bus
= radeon_lookup_i2c_gpio(rdev
, 0x93);
433 /* Fujitsu D3003-S2 board lists DVI-I as DVI-D and VGA */
434 if (((dev
->pdev
->device
== 0x9802) || (dev
->pdev
->device
== 0x9806)) &&
435 (dev
->pdev
->subsystem_vendor
== 0x1734) &&
436 (dev
->pdev
->subsystem_device
== 0x11bd)) {
437 if (*connector_type
== DRM_MODE_CONNECTOR_VGA
) {
438 *connector_type
= DRM_MODE_CONNECTOR_DVII
;
440 } else if (*connector_type
== DRM_MODE_CONNECTOR_DVID
) {
441 *connector_type
= DRM_MODE_CONNECTOR_DVII
;
445 /* Fujitsu D3003-S2 board lists DVI-I as DVI-I and VGA */
446 if ((dev
->pdev
->device
== 0x9805) &&
447 (dev
->pdev
->subsystem_vendor
== 0x1734) &&
448 (dev
->pdev
->subsystem_device
== 0x11bd)) {
449 if (*connector_type
== DRM_MODE_CONNECTOR_VGA
)
456 static const int supported_devices_connector_convert
[] = {
457 DRM_MODE_CONNECTOR_Unknown
,
458 DRM_MODE_CONNECTOR_VGA
,
459 DRM_MODE_CONNECTOR_DVII
,
460 DRM_MODE_CONNECTOR_DVID
,
461 DRM_MODE_CONNECTOR_DVIA
,
462 DRM_MODE_CONNECTOR_SVIDEO
,
463 DRM_MODE_CONNECTOR_Composite
,
464 DRM_MODE_CONNECTOR_LVDS
,
465 DRM_MODE_CONNECTOR_Unknown
,
466 DRM_MODE_CONNECTOR_Unknown
,
467 DRM_MODE_CONNECTOR_HDMIA
,
468 DRM_MODE_CONNECTOR_HDMIB
,
469 DRM_MODE_CONNECTOR_Unknown
,
470 DRM_MODE_CONNECTOR_Unknown
,
471 DRM_MODE_CONNECTOR_9PinDIN
,
472 DRM_MODE_CONNECTOR_DisplayPort
475 static const uint16_t supported_devices_connector_object_id_convert
[] = {
476 CONNECTOR_OBJECT_ID_NONE
,
477 CONNECTOR_OBJECT_ID_VGA
,
478 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I
, /* not all boards support DL */
479 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D
, /* not all boards support DL */
480 CONNECTOR_OBJECT_ID_VGA
, /* technically DVI-A */
481 CONNECTOR_OBJECT_ID_COMPOSITE
,
482 CONNECTOR_OBJECT_ID_SVIDEO
,
483 CONNECTOR_OBJECT_ID_LVDS
,
484 CONNECTOR_OBJECT_ID_9PIN_DIN
,
485 CONNECTOR_OBJECT_ID_9PIN_DIN
,
486 CONNECTOR_OBJECT_ID_DISPLAYPORT
,
487 CONNECTOR_OBJECT_ID_HDMI_TYPE_A
,
488 CONNECTOR_OBJECT_ID_HDMI_TYPE_B
,
489 CONNECTOR_OBJECT_ID_SVIDEO
492 static const int object_connector_convert
[] = {
493 DRM_MODE_CONNECTOR_Unknown
,
494 DRM_MODE_CONNECTOR_DVII
,
495 DRM_MODE_CONNECTOR_DVII
,
496 DRM_MODE_CONNECTOR_DVID
,
497 DRM_MODE_CONNECTOR_DVID
,
498 DRM_MODE_CONNECTOR_VGA
,
499 DRM_MODE_CONNECTOR_Composite
,
500 DRM_MODE_CONNECTOR_SVIDEO
,
501 DRM_MODE_CONNECTOR_Unknown
,
502 DRM_MODE_CONNECTOR_Unknown
,
503 DRM_MODE_CONNECTOR_9PinDIN
,
504 DRM_MODE_CONNECTOR_Unknown
,
505 DRM_MODE_CONNECTOR_HDMIA
,
506 DRM_MODE_CONNECTOR_HDMIB
,
507 DRM_MODE_CONNECTOR_LVDS
,
508 DRM_MODE_CONNECTOR_9PinDIN
,
509 DRM_MODE_CONNECTOR_Unknown
,
510 DRM_MODE_CONNECTOR_Unknown
,
511 DRM_MODE_CONNECTOR_Unknown
,
512 DRM_MODE_CONNECTOR_DisplayPort
,
513 DRM_MODE_CONNECTOR_eDP
,
514 DRM_MODE_CONNECTOR_Unknown
517 bool radeon_get_atom_connector_info_from_object_table(struct drm_device
*dev
)
519 struct radeon_device
*rdev
= dev
->dev_private
;
520 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
521 struct atom_context
*ctx
= mode_info
->atom_context
;
522 int index
= GetIndexIntoMasterTable(DATA
, Object_Header
);
523 u16 size
, data_offset
;
525 ATOM_CONNECTOR_OBJECT_TABLE
*con_obj
;
526 ATOM_ENCODER_OBJECT_TABLE
*enc_obj
;
527 ATOM_OBJECT_TABLE
*router_obj
;
528 ATOM_DISPLAY_OBJECT_PATH_TABLE
*path_obj
;
529 ATOM_OBJECT_HEADER
*obj_header
;
530 int i
, j
, k
, path_size
, device_support
;
532 u16 igp_lane_info
, conn_id
, connector_object_id
;
533 struct radeon_i2c_bus_rec ddc_bus
;
534 struct radeon_router router
;
535 struct radeon_gpio_rec gpio
;
536 struct radeon_hpd hpd
;
538 if (!atom_parse_data_header(ctx
, index
, &size
, &frev
, &crev
, &data_offset
))
544 obj_header
= (ATOM_OBJECT_HEADER
*) ((char *)ctx
->bios
+ data_offset
);
545 path_obj
= (ATOM_DISPLAY_OBJECT_PATH_TABLE
*)
546 ((char *)ctx
->bios
+ data_offset
+
547 le16_to_cpu(obj_header
->usDisplayPathTableOffset
));
548 con_obj
= (ATOM_CONNECTOR_OBJECT_TABLE
*)
549 ((char *)ctx
->bios
+ data_offset
+
550 le16_to_cpu(obj_header
->usConnectorObjectTableOffset
));
551 enc_obj
= (ATOM_ENCODER_OBJECT_TABLE
*)
552 ((char *)ctx
->bios
+ data_offset
+
553 le16_to_cpu(obj_header
->usEncoderObjectTableOffset
));
554 router_obj
= (ATOM_OBJECT_TABLE
*)
555 ((char *)ctx
->bios
+ data_offset
+
556 le16_to_cpu(obj_header
->usRouterObjectTableOffset
));
557 device_support
= le16_to_cpu(obj_header
->usDeviceSupport
);
560 for (i
= 0; i
< path_obj
->ucNumOfDispPath
; i
++) {
561 uint8_t *addr
= (uint8_t *) path_obj
->asDispPath
;
562 ATOM_DISPLAY_OBJECT_PATH
*path
;
564 path
= (ATOM_DISPLAY_OBJECT_PATH
*) addr
;
565 path_size
+= le16_to_cpu(path
->usSize
);
567 if (device_support
& le16_to_cpu(path
->usDeviceTag
)) {
568 uint8_t con_obj_id
, con_obj_num
, con_obj_type
;
571 (le16_to_cpu(path
->usConnObjectId
) & OBJECT_ID_MASK
)
574 (le16_to_cpu(path
->usConnObjectId
) & ENUM_ID_MASK
)
577 (le16_to_cpu(path
->usConnObjectId
) &
578 OBJECT_TYPE_MASK
) >> OBJECT_TYPE_SHIFT
;
580 /* TODO CV support */
581 if (le16_to_cpu(path
->usDeviceTag
) ==
582 ATOM_DEVICE_CV_SUPPORT
)
586 if ((rdev
->flags
& RADEON_IS_IGP
) &&
588 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR
)) {
589 uint16_t igp_offset
= 0;
590 ATOM_INTEGRATED_SYSTEM_INFO_V2
*igp_obj
;
593 GetIndexIntoMasterTable(DATA
,
594 IntegratedSystemInfo
);
596 if (atom_parse_data_header(ctx
, index
, &size
, &frev
,
597 &crev
, &igp_offset
)) {
601 (ATOM_INTEGRATED_SYSTEM_INFO_V2
602 *) ((char *)ctx
->bios
+ igp_offset
);
605 uint32_t slot_config
, ct
;
607 if (con_obj_num
== 1)
616 ct
= (slot_config
>> 16) & 0xff;
618 object_connector_convert
620 connector_object_id
= ct
;
622 slot_config
& 0xffff;
630 object_connector_convert
[con_obj_id
];
631 connector_object_id
= con_obj_id
;
636 object_connector_convert
[con_obj_id
];
637 connector_object_id
= con_obj_id
;
640 if (connector_type
== DRM_MODE_CONNECTOR_Unknown
)
643 router
.ddc_valid
= false;
644 router
.cd_valid
= false;
645 for (j
= 0; j
< ((le16_to_cpu(path
->usSize
) - 8) / 2); j
++) {
646 uint8_t grph_obj_id
, grph_obj_num
, grph_obj_type
;
649 (le16_to_cpu(path
->usGraphicObjIds
[j
]) &
650 OBJECT_ID_MASK
) >> OBJECT_ID_SHIFT
;
652 (le16_to_cpu(path
->usGraphicObjIds
[j
]) &
653 ENUM_ID_MASK
) >> ENUM_ID_SHIFT
;
655 (le16_to_cpu(path
->usGraphicObjIds
[j
]) &
656 OBJECT_TYPE_MASK
) >> OBJECT_TYPE_SHIFT
;
658 if (grph_obj_type
== GRAPH_OBJECT_TYPE_ENCODER
) {
659 for (k
= 0; k
< enc_obj
->ucNumberOfObjects
; k
++) {
660 u16 encoder_obj
= le16_to_cpu(enc_obj
->asObjects
[k
].usObjectID
);
661 if (le16_to_cpu(path
->usGraphicObjIds
[j
]) == encoder_obj
) {
662 ATOM_COMMON_RECORD_HEADER
*record
= (ATOM_COMMON_RECORD_HEADER
*)
663 ((char *)ctx
->bios
+ data_offset
+
664 le16_to_cpu(enc_obj
->asObjects
[k
].usRecordOffset
));
665 ATOM_ENCODER_CAP_RECORD
*cap_record
;
668 while (record
->ucRecordSize
> 0 &&
669 record
->ucRecordType
> 0 &&
670 record
->ucRecordType
<= ATOM_MAX_OBJECT_RECORD_NUMBER
) {
671 switch (record
->ucRecordType
) {
672 case ATOM_ENCODER_CAP_RECORD_TYPE
:
673 cap_record
=(ATOM_ENCODER_CAP_RECORD
*)
675 caps
= le16_to_cpu(cap_record
->usEncoderCap
);
678 record
= (ATOM_COMMON_RECORD_HEADER
*)
679 ((char *)record
+ record
->ucRecordSize
);
681 radeon_add_atom_encoder(dev
,
689 } else if (grph_obj_type
== GRAPH_OBJECT_TYPE_ROUTER
) {
690 for (k
= 0; k
< router_obj
->ucNumberOfObjects
; k
++) {
691 u16 router_obj_id
= le16_to_cpu(router_obj
->asObjects
[k
].usObjectID
);
692 if (le16_to_cpu(path
->usGraphicObjIds
[j
]) == router_obj_id
) {
693 ATOM_COMMON_RECORD_HEADER
*record
= (ATOM_COMMON_RECORD_HEADER
*)
694 ((char *)ctx
->bios
+ data_offset
+
695 le16_to_cpu(router_obj
->asObjects
[k
].usRecordOffset
));
696 ATOM_I2C_RECORD
*i2c_record
;
697 ATOM_I2C_ID_CONFIG_ACCESS
*i2c_config
;
698 ATOM_ROUTER_DDC_PATH_SELECT_RECORD
*ddc_path
;
699 ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD
*cd_path
;
700 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT
*router_src_dst_table
=
701 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT
*)
702 ((char *)ctx
->bios
+ data_offset
+
703 le16_to_cpu(router_obj
->asObjects
[k
].usSrcDstTableOffset
));
704 u8
*num_dst_objs
= (u8
*)
705 ((u8
*)router_src_dst_table
+ 1 +
706 (router_src_dst_table
->ucNumberOfSrc
* 2));
707 u16
*dst_objs
= (u16
*)(num_dst_objs
+ 1);
710 router
.router_id
= router_obj_id
;
711 for (enum_id
= 0; enum_id
< (*num_dst_objs
); enum_id
++) {
712 if (le16_to_cpu(path
->usConnObjectId
) ==
713 le16_to_cpu(dst_objs
[enum_id
]))
717 while (record
->ucRecordSize
> 0 &&
718 record
->ucRecordType
> 0 &&
719 record
->ucRecordType
<= ATOM_MAX_OBJECT_RECORD_NUMBER
) {
720 switch (record
->ucRecordType
) {
721 case ATOM_I2C_RECORD_TYPE
:
726 (ATOM_I2C_ID_CONFIG_ACCESS
*)
727 &i2c_record
->sucI2cId
;
729 radeon_lookup_i2c_gpio(rdev
,
732 router
.i2c_addr
= i2c_record
->ucI2CAddr
>> 1;
734 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE
:
735 ddc_path
= (ATOM_ROUTER_DDC_PATH_SELECT_RECORD
*)
737 router
.ddc_valid
= true;
738 router
.ddc_mux_type
= ddc_path
->ucMuxType
;
739 router
.ddc_mux_control_pin
= ddc_path
->ucMuxControlPin
;
740 router
.ddc_mux_state
= ddc_path
->ucMuxState
[enum_id
];
742 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE
:
743 cd_path
= (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD
*)
745 router
.cd_valid
= true;
746 router
.cd_mux_type
= cd_path
->ucMuxType
;
747 router
.cd_mux_control_pin
= cd_path
->ucMuxControlPin
;
748 router
.cd_mux_state
= cd_path
->ucMuxState
[enum_id
];
751 record
= (ATOM_COMMON_RECORD_HEADER
*)
752 ((char *)record
+ record
->ucRecordSize
);
759 /* look up gpio for ddc, hpd */
760 ddc_bus
.valid
= false;
761 hpd
.hpd
= RADEON_HPD_NONE
;
762 if ((le16_to_cpu(path
->usDeviceTag
) &
763 (ATOM_DEVICE_TV_SUPPORT
| ATOM_DEVICE_CV_SUPPORT
)) == 0) {
764 for (j
= 0; j
< con_obj
->ucNumberOfObjects
; j
++) {
765 if (le16_to_cpu(path
->usConnObjectId
) ==
766 le16_to_cpu(con_obj
->asObjects
[j
].
768 ATOM_COMMON_RECORD_HEADER
770 (ATOM_COMMON_RECORD_HEADER
772 ((char *)ctx
->bios
+ data_offset
+
773 le16_to_cpu(con_obj
->
776 ATOM_I2C_RECORD
*i2c_record
;
777 ATOM_HPD_INT_RECORD
*hpd_record
;
778 ATOM_I2C_ID_CONFIG_ACCESS
*i2c_config
;
780 while (record
->ucRecordSize
> 0 &&
781 record
->ucRecordType
> 0 &&
782 record
->ucRecordType
<= ATOM_MAX_OBJECT_RECORD_NUMBER
) {
783 switch (record
->ucRecordType
) {
784 case ATOM_I2C_RECORD_TYPE
:
789 (ATOM_I2C_ID_CONFIG_ACCESS
*)
790 &i2c_record
->sucI2cId
;
791 ddc_bus
= radeon_lookup_i2c_gpio(rdev
,
795 case ATOM_HPD_INT_RECORD_TYPE
:
797 (ATOM_HPD_INT_RECORD
*)
799 gpio
= radeon_lookup_gpio(rdev
,
800 hpd_record
->ucHPDIntGPIOID
);
801 hpd
= radeon_atom_get_hpd_info_from_gpio(rdev
, &gpio
);
802 hpd
.plugged_state
= hpd_record
->ucPlugged_PinState
;
806 (ATOM_COMMON_RECORD_HEADER
817 /* needed for aux chan transactions */
818 ddc_bus
.hpd
= hpd
.hpd
;
820 conn_id
= le16_to_cpu(path
->usConnObjectId
);
822 if (!radeon_atom_apply_quirks
823 (dev
, le16_to_cpu(path
->usDeviceTag
), &connector_type
,
824 &ddc_bus
, &conn_id
, &hpd
))
827 radeon_add_atom_connector(dev
,
831 connector_type
, &ddc_bus
,
840 radeon_link_encoder_connector(dev
);
845 static uint16_t atombios_get_connector_object_id(struct drm_device
*dev
,
849 struct radeon_device
*rdev
= dev
->dev_private
;
851 if (rdev
->flags
& RADEON_IS_IGP
) {
852 return supported_devices_connector_object_id_convert
854 } else if (((connector_type
== DRM_MODE_CONNECTOR_DVII
) ||
855 (connector_type
== DRM_MODE_CONNECTOR_DVID
)) &&
856 (devices
& ATOM_DEVICE_DFP2_SUPPORT
)) {
857 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
858 struct atom_context
*ctx
= mode_info
->atom_context
;
859 int index
= GetIndexIntoMasterTable(DATA
, XTMDS_Info
);
860 uint16_t size
, data_offset
;
862 ATOM_XTMDS_INFO
*xtmds
;
864 if (atom_parse_data_header(ctx
, index
, &size
, &frev
, &crev
, &data_offset
)) {
865 xtmds
= (ATOM_XTMDS_INFO
*)((char *)ctx
->bios
+ data_offset
);
867 if (xtmds
->ucSupportedLink
& ATOM_XTMDS_SUPPORTED_DUALLINK
) {
868 if (connector_type
== DRM_MODE_CONNECTOR_DVII
)
869 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I
;
871 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D
;
873 if (connector_type
== DRM_MODE_CONNECTOR_DVII
)
874 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I
;
876 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D
;
879 return supported_devices_connector_object_id_convert
882 return supported_devices_connector_object_id_convert
887 struct bios_connector
{
892 struct radeon_i2c_bus_rec ddc_bus
;
893 struct radeon_hpd hpd
;
896 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
900 struct radeon_device
*rdev
= dev
->dev_private
;
901 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
902 struct atom_context
*ctx
= mode_info
->atom_context
;
903 int index
= GetIndexIntoMasterTable(DATA
, SupportedDevicesInfo
);
904 uint16_t size
, data_offset
;
906 uint16_t device_support
;
908 union atom_supported_devices
*supported_devices
;
909 int i
, j
, max_device
;
910 struct bios_connector
*bios_connectors
;
911 size_t bc_size
= sizeof(*bios_connectors
) * ATOM_MAX_SUPPORTED_DEVICE
;
912 struct radeon_router router
;
914 router
.ddc_valid
= false;
915 router
.cd_valid
= false;
917 bios_connectors
= kzalloc(bc_size
, GFP_KERNEL
);
918 if (!bios_connectors
)
921 if (!atom_parse_data_header(ctx
, index
, &size
, &frev
, &crev
,
923 kfree(bios_connectors
);
928 (union atom_supported_devices
*)((char *)ctx
->bios
+ data_offset
);
930 device_support
= le16_to_cpu(supported_devices
->info
.usDeviceSupport
);
933 max_device
= ATOM_MAX_SUPPORTED_DEVICE
;
935 max_device
= ATOM_MAX_SUPPORTED_DEVICE_INFO
;
937 for (i
= 0; i
< max_device
; i
++) {
938 ATOM_CONNECTOR_INFO_I2C ci
=
939 supported_devices
->info
.asConnInfo
[i
];
941 bios_connectors
[i
].valid
= false;
943 if (!(device_support
& (1 << i
))) {
947 if (i
== ATOM_DEVICE_CV_INDEX
) {
948 DRM_DEBUG_KMS("Skipping Component Video\n");
952 bios_connectors
[i
].connector_type
=
953 supported_devices_connector_convert
[ci
.sucConnectorInfo
.
957 if (bios_connectors
[i
].connector_type
==
958 DRM_MODE_CONNECTOR_Unknown
)
961 dac
= ci
.sucConnectorInfo
.sbfAccess
.bfAssociatedDAC
;
963 bios_connectors
[i
].line_mux
=
964 ci
.sucI2cId
.ucAccess
;
966 /* give tv unique connector ids */
967 if (i
== ATOM_DEVICE_TV1_INDEX
) {
968 bios_connectors
[i
].ddc_bus
.valid
= false;
969 bios_connectors
[i
].line_mux
= 50;
970 } else if (i
== ATOM_DEVICE_TV2_INDEX
) {
971 bios_connectors
[i
].ddc_bus
.valid
= false;
972 bios_connectors
[i
].line_mux
= 51;
973 } else if (i
== ATOM_DEVICE_CV_INDEX
) {
974 bios_connectors
[i
].ddc_bus
.valid
= false;
975 bios_connectors
[i
].line_mux
= 52;
977 bios_connectors
[i
].ddc_bus
=
978 radeon_lookup_i2c_gpio(rdev
,
979 bios_connectors
[i
].line_mux
);
981 if ((crev
> 1) && (frev
> 1)) {
982 u8 isb
= supported_devices
->info_2d1
.asIntSrcInfo
[i
].ucIntSrcBitmap
;
985 bios_connectors
[i
].hpd
.hpd
= RADEON_HPD_1
;
988 bios_connectors
[i
].hpd
.hpd
= RADEON_HPD_2
;
991 bios_connectors
[i
].hpd
.hpd
= RADEON_HPD_NONE
;
995 if (i
== ATOM_DEVICE_DFP1_INDEX
)
996 bios_connectors
[i
].hpd
.hpd
= RADEON_HPD_1
;
997 else if (i
== ATOM_DEVICE_DFP2_INDEX
)
998 bios_connectors
[i
].hpd
.hpd
= RADEON_HPD_2
;
1000 bios_connectors
[i
].hpd
.hpd
= RADEON_HPD_NONE
;
1003 /* Always set the connector type to VGA for CRT1/CRT2. if they are
1004 * shared with a DVI port, we'll pick up the DVI connector when we
1005 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
1007 if (i
== ATOM_DEVICE_CRT1_INDEX
|| i
== ATOM_DEVICE_CRT2_INDEX
)
1008 bios_connectors
[i
].connector_type
=
1009 DRM_MODE_CONNECTOR_VGA
;
1011 if (!radeon_atom_apply_quirks
1012 (dev
, (1 << i
), &bios_connectors
[i
].connector_type
,
1013 &bios_connectors
[i
].ddc_bus
, &bios_connectors
[i
].line_mux
,
1014 &bios_connectors
[i
].hpd
))
1017 bios_connectors
[i
].valid
= true;
1018 bios_connectors
[i
].devices
= (1 << i
);
1020 if (ASIC_IS_AVIVO(rdev
) || radeon_r4xx_atom
)
1021 radeon_add_atom_encoder(dev
,
1022 radeon_get_encoder_enum(dev
,
1028 radeon_add_legacy_encoder(dev
,
1029 radeon_get_encoder_enum(dev
,
1035 /* combine shared connectors */
1036 for (i
= 0; i
< max_device
; i
++) {
1037 if (bios_connectors
[i
].valid
) {
1038 for (j
= 0; j
< max_device
; j
++) {
1039 if (bios_connectors
[j
].valid
&& (i
!= j
)) {
1040 if (bios_connectors
[i
].line_mux
==
1041 bios_connectors
[j
].line_mux
) {
1042 /* make sure not to combine LVDS */
1043 if (bios_connectors
[i
].devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
1044 bios_connectors
[i
].line_mux
= 53;
1045 bios_connectors
[i
].ddc_bus
.valid
= false;
1048 if (bios_connectors
[j
].devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
1049 bios_connectors
[j
].line_mux
= 53;
1050 bios_connectors
[j
].ddc_bus
.valid
= false;
1053 /* combine analog and digital for DVI-I */
1054 if (((bios_connectors
[i
].devices
& (ATOM_DEVICE_DFP_SUPPORT
)) &&
1055 (bios_connectors
[j
].devices
& (ATOM_DEVICE_CRT_SUPPORT
))) ||
1056 ((bios_connectors
[j
].devices
& (ATOM_DEVICE_DFP_SUPPORT
)) &&
1057 (bios_connectors
[i
].devices
& (ATOM_DEVICE_CRT_SUPPORT
)))) {
1058 bios_connectors
[i
].devices
|=
1059 bios_connectors
[j
].devices
;
1060 bios_connectors
[i
].connector_type
=
1061 DRM_MODE_CONNECTOR_DVII
;
1062 if (bios_connectors
[j
].devices
& (ATOM_DEVICE_DFP_SUPPORT
))
1063 bios_connectors
[i
].hpd
=
1064 bios_connectors
[j
].hpd
;
1065 bios_connectors
[j
].valid
= false;
1073 /* add the connectors */
1074 for (i
= 0; i
< max_device
; i
++) {
1075 if (bios_connectors
[i
].valid
) {
1076 uint16_t connector_object_id
=
1077 atombios_get_connector_object_id(dev
,
1078 bios_connectors
[i
].connector_type
,
1079 bios_connectors
[i
].devices
);
1080 radeon_add_atom_connector(dev
,
1081 bios_connectors
[i
].line_mux
,
1082 bios_connectors
[i
].devices
,
1085 &bios_connectors
[i
].ddc_bus
,
1087 connector_object_id
,
1088 &bios_connectors
[i
].hpd
,
1093 radeon_link_encoder_connector(dev
);
1095 kfree(bios_connectors
);
1099 union firmware_info
{
1100 ATOM_FIRMWARE_INFO info
;
1101 ATOM_FIRMWARE_INFO_V1_2 info_12
;
1102 ATOM_FIRMWARE_INFO_V1_3 info_13
;
1103 ATOM_FIRMWARE_INFO_V1_4 info_14
;
1104 ATOM_FIRMWARE_INFO_V2_1 info_21
;
1105 ATOM_FIRMWARE_INFO_V2_2 info_22
;
1108 bool radeon_atom_get_clock_info(struct drm_device
*dev
)
1110 struct radeon_device
*rdev
= dev
->dev_private
;
1111 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1112 int index
= GetIndexIntoMasterTable(DATA
, FirmwareInfo
);
1113 union firmware_info
*firmware_info
;
1115 struct radeon_pll
*p1pll
= &rdev
->clock
.p1pll
;
1116 struct radeon_pll
*p2pll
= &rdev
->clock
.p2pll
;
1117 struct radeon_pll
*dcpll
= &rdev
->clock
.dcpll
;
1118 struct radeon_pll
*spll
= &rdev
->clock
.spll
;
1119 struct radeon_pll
*mpll
= &rdev
->clock
.mpll
;
1120 uint16_t data_offset
;
1122 if (atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
1123 &frev
, &crev
, &data_offset
)) {
1125 (union firmware_info
*)((char *)mode_info
->atom_context
->bios
+
1128 p1pll
->reference_freq
=
1129 le16_to_cpu(firmware_info
->info
.usReferenceClock
);
1130 p1pll
->reference_div
= 0;
1133 p1pll
->pll_out_min
=
1134 le16_to_cpu(firmware_info
->info
.usMinPixelClockPLL_Output
);
1136 p1pll
->pll_out_min
=
1137 le32_to_cpu(firmware_info
->info_12
.ulMinPixelClockPLL_Output
);
1138 p1pll
->pll_out_max
=
1139 le32_to_cpu(firmware_info
->info
.ulMaxPixelClockPLL_Output
);
1142 p1pll
->lcd_pll_out_min
=
1143 le16_to_cpu(firmware_info
->info_14
.usLcdMinPixelClockPLL_Output
) * 100;
1144 if (p1pll
->lcd_pll_out_min
== 0)
1145 p1pll
->lcd_pll_out_min
= p1pll
->pll_out_min
;
1146 p1pll
->lcd_pll_out_max
=
1147 le16_to_cpu(firmware_info
->info_14
.usLcdMaxPixelClockPLL_Output
) * 100;
1148 if (p1pll
->lcd_pll_out_max
== 0)
1149 p1pll
->lcd_pll_out_max
= p1pll
->pll_out_max
;
1151 p1pll
->lcd_pll_out_min
= p1pll
->pll_out_min
;
1152 p1pll
->lcd_pll_out_max
= p1pll
->pll_out_max
;
1155 if (p1pll
->pll_out_min
== 0) {
1156 if (ASIC_IS_AVIVO(rdev
))
1157 p1pll
->pll_out_min
= 64800;
1159 p1pll
->pll_out_min
= 20000;
1163 le16_to_cpu(firmware_info
->info
.usMinPixelClockPLL_Input
);
1165 le16_to_cpu(firmware_info
->info
.usMaxPixelClockPLL_Input
);
1170 if (ASIC_IS_DCE4(rdev
))
1171 spll
->reference_freq
=
1172 le16_to_cpu(firmware_info
->info_21
.usCoreReferenceClock
);
1174 spll
->reference_freq
=
1175 le16_to_cpu(firmware_info
->info
.usReferenceClock
);
1176 spll
->reference_div
= 0;
1179 le16_to_cpu(firmware_info
->info
.usMinEngineClockPLL_Output
);
1181 le32_to_cpu(firmware_info
->info
.ulMaxEngineClockPLL_Output
);
1184 if (spll
->pll_out_min
== 0) {
1185 if (ASIC_IS_AVIVO(rdev
))
1186 spll
->pll_out_min
= 64800;
1188 spll
->pll_out_min
= 20000;
1192 le16_to_cpu(firmware_info
->info
.usMinEngineClockPLL_Input
);
1194 le16_to_cpu(firmware_info
->info
.usMaxEngineClockPLL_Input
);
1197 if (ASIC_IS_DCE4(rdev
))
1198 mpll
->reference_freq
=
1199 le16_to_cpu(firmware_info
->info_21
.usMemoryReferenceClock
);
1201 mpll
->reference_freq
=
1202 le16_to_cpu(firmware_info
->info
.usReferenceClock
);
1203 mpll
->reference_div
= 0;
1206 le16_to_cpu(firmware_info
->info
.usMinMemoryClockPLL_Output
);
1208 le32_to_cpu(firmware_info
->info
.ulMaxMemoryClockPLL_Output
);
1211 if (mpll
->pll_out_min
== 0) {
1212 if (ASIC_IS_AVIVO(rdev
))
1213 mpll
->pll_out_min
= 64800;
1215 mpll
->pll_out_min
= 20000;
1219 le16_to_cpu(firmware_info
->info
.usMinMemoryClockPLL_Input
);
1221 le16_to_cpu(firmware_info
->info
.usMaxMemoryClockPLL_Input
);
1223 rdev
->clock
.default_sclk
=
1224 le32_to_cpu(firmware_info
->info
.ulDefaultEngineClock
);
1225 rdev
->clock
.default_mclk
=
1226 le32_to_cpu(firmware_info
->info
.ulDefaultMemoryClock
);
1228 if (ASIC_IS_DCE4(rdev
)) {
1229 rdev
->clock
.default_dispclk
=
1230 le32_to_cpu(firmware_info
->info_21
.ulDefaultDispEngineClkFreq
);
1231 if (rdev
->clock
.default_dispclk
== 0) {
1232 if (ASIC_IS_DCE6(rdev
))
1233 rdev
->clock
.default_dispclk
= 60000; /* 600 Mhz */
1234 else if (ASIC_IS_DCE5(rdev
))
1235 rdev
->clock
.default_dispclk
= 54000; /* 540 Mhz */
1237 rdev
->clock
.default_dispclk
= 60000; /* 600 Mhz */
1239 /* set a reasonable default for DP */
1240 if (ASIC_IS_DCE6(rdev
) && (rdev
->clock
.default_dispclk
< 53900)) {
1241 DRM_INFO("Changing default dispclk from %dMhz to 600Mhz\n",
1242 rdev
->clock
.default_dispclk
/ 100);
1243 rdev
->clock
.default_dispclk
= 60000;
1245 rdev
->clock
.dp_extclk
=
1246 le16_to_cpu(firmware_info
->info_21
.usUniphyDPModeExtClkFreq
);
1247 rdev
->clock
.current_dispclk
= rdev
->clock
.default_dispclk
;
1251 rdev
->clock
.max_pixel_clock
= le16_to_cpu(firmware_info
->info
.usMaxPixelClock
);
1252 if (rdev
->clock
.max_pixel_clock
== 0)
1253 rdev
->clock
.max_pixel_clock
= 40000;
1255 /* not technically a clock, but... */
1256 rdev
->mode_info
.firmware_flags
=
1257 le16_to_cpu(firmware_info
->info
.usFirmwareCapability
.susAccess
);
1266 struct _ATOM_INTEGRATED_SYSTEM_INFO info
;
1267 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2
;
1268 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6
;
1269 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7
;
1270 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8
;
1273 bool radeon_atombios_sideport_present(struct radeon_device
*rdev
)
1275 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1276 int index
= GetIndexIntoMasterTable(DATA
, IntegratedSystemInfo
);
1277 union igp_info
*igp_info
;
1281 /* sideport is AMD only */
1282 if (rdev
->family
== CHIP_RS600
)
1285 if (atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
1286 &frev
, &crev
, &data_offset
)) {
1287 igp_info
= (union igp_info
*)((char *)mode_info
->atom_context
->bios
+
1291 if (le32_to_cpu(igp_info
->info
.ulBootUpMemoryClock
))
1295 if (le32_to_cpu(igp_info
->info_2
.ulBootUpSidePortClock
))
1299 DRM_ERROR("Unsupported IGP table: %d %d\n", frev
, crev
);
1306 bool radeon_atombios_get_tmds_info(struct radeon_encoder
*encoder
,
1307 struct radeon_encoder_int_tmds
*tmds
)
1309 struct drm_device
*dev
= encoder
->base
.dev
;
1310 struct radeon_device
*rdev
= dev
->dev_private
;
1311 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1312 int index
= GetIndexIntoMasterTable(DATA
, TMDS_Info
);
1313 uint16_t data_offset
;
1314 struct _ATOM_TMDS_INFO
*tmds_info
;
1319 if (atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
1320 &frev
, &crev
, &data_offset
)) {
1322 (struct _ATOM_TMDS_INFO
*)((char *)mode_info
->atom_context
->bios
+
1325 maxfreq
= le16_to_cpu(tmds_info
->usMaxFrequency
);
1326 for (i
= 0; i
< 4; i
++) {
1327 tmds
->tmds_pll
[i
].freq
=
1328 le16_to_cpu(tmds_info
->asMiscInfo
[i
].usFrequency
);
1329 tmds
->tmds_pll
[i
].value
=
1330 tmds_info
->asMiscInfo
[i
].ucPLL_ChargePump
& 0x3f;
1331 tmds
->tmds_pll
[i
].value
|=
1332 (tmds_info
->asMiscInfo
[i
].
1333 ucPLL_VCO_Gain
& 0x3f) << 6;
1334 tmds
->tmds_pll
[i
].value
|=
1335 (tmds_info
->asMiscInfo
[i
].
1336 ucPLL_DutyCycle
& 0xf) << 12;
1337 tmds
->tmds_pll
[i
].value
|=
1338 (tmds_info
->asMiscInfo
[i
].
1339 ucPLL_VoltageSwing
& 0xf) << 16;
1341 DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
1342 tmds
->tmds_pll
[i
].freq
,
1343 tmds
->tmds_pll
[i
].value
);
1345 if (maxfreq
== tmds
->tmds_pll
[i
].freq
) {
1346 tmds
->tmds_pll
[i
].freq
= 0xffffffff;
1355 bool radeon_atombios_get_ppll_ss_info(struct radeon_device
*rdev
,
1356 struct radeon_atom_ss
*ss
,
1359 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1360 int index
= GetIndexIntoMasterTable(DATA
, PPLL_SS_Info
);
1361 uint16_t data_offset
, size
;
1362 struct _ATOM_SPREAD_SPECTRUM_INFO
*ss_info
;
1363 struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT
*ss_assign
;
1367 memset(ss
, 0, sizeof(struct radeon_atom_ss
));
1368 if (atom_parse_data_header(mode_info
->atom_context
, index
, &size
,
1369 &frev
, &crev
, &data_offset
)) {
1371 (struct _ATOM_SPREAD_SPECTRUM_INFO
*)((char *)mode_info
->atom_context
->bios
+ data_offset
);
1373 num_indices
= (size
- sizeof(ATOM_COMMON_TABLE_HEADER
)) /
1374 sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT
);
1375 ss_assign
= (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT
*)
1376 ((u8
*)&ss_info
->asSS_Info
[0]);
1377 for (i
= 0; i
< num_indices
; i
++) {
1378 if (ss_assign
->ucSS_Id
== id
) {
1380 le16_to_cpu(ss_assign
->usSpreadSpectrumPercentage
);
1381 ss
->type
= ss_assign
->ucSpreadSpectrumType
;
1382 ss
->step
= ss_assign
->ucSS_Step
;
1383 ss
->delay
= ss_assign
->ucSS_Delay
;
1384 ss
->range
= ss_assign
->ucSS_Range
;
1385 ss
->refdiv
= ss_assign
->ucRecommendedRef_Div
;
1388 ss_assign
= (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT
*)
1389 ((u8
*)ss_assign
+ sizeof(struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT
));
1395 static void radeon_atombios_get_igp_ss_overrides(struct radeon_device
*rdev
,
1396 struct radeon_atom_ss
*ss
,
1399 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1400 int index
= GetIndexIntoMasterTable(DATA
, IntegratedSystemInfo
);
1401 u16 data_offset
, size
;
1402 union igp_info
*igp_info
;
1404 u16 percentage
= 0, rate
= 0;
1406 /* get any igp specific overrides */
1407 if (atom_parse_data_header(mode_info
->atom_context
, index
, &size
,
1408 &frev
, &crev
, &data_offset
)) {
1409 igp_info
= (union igp_info
*)
1410 ((char *)mode_info
->atom_context
->bios
+ data_offset
);
1414 case ASIC_INTERNAL_SS_ON_TMDS
:
1415 percentage
= le16_to_cpu(igp_info
->info_6
.usDVISSPercentage
);
1416 rate
= le16_to_cpu(igp_info
->info_6
.usDVISSpreadRateIn10Hz
);
1418 case ASIC_INTERNAL_SS_ON_HDMI
:
1419 percentage
= le16_to_cpu(igp_info
->info_6
.usHDMISSPercentage
);
1420 rate
= le16_to_cpu(igp_info
->info_6
.usHDMISSpreadRateIn10Hz
);
1422 case ASIC_INTERNAL_SS_ON_LVDS
:
1423 percentage
= le16_to_cpu(igp_info
->info_6
.usLvdsSSPercentage
);
1424 rate
= le16_to_cpu(igp_info
->info_6
.usLvdsSSpreadRateIn10Hz
);
1430 case ASIC_INTERNAL_SS_ON_TMDS
:
1431 percentage
= le16_to_cpu(igp_info
->info_7
.usDVISSPercentage
);
1432 rate
= le16_to_cpu(igp_info
->info_7
.usDVISSpreadRateIn10Hz
);
1434 case ASIC_INTERNAL_SS_ON_HDMI
:
1435 percentage
= le16_to_cpu(igp_info
->info_7
.usHDMISSPercentage
);
1436 rate
= le16_to_cpu(igp_info
->info_7
.usHDMISSpreadRateIn10Hz
);
1438 case ASIC_INTERNAL_SS_ON_LVDS
:
1439 percentage
= le16_to_cpu(igp_info
->info_7
.usLvdsSSPercentage
);
1440 rate
= le16_to_cpu(igp_info
->info_7
.usLvdsSSpreadRateIn10Hz
);
1446 case ASIC_INTERNAL_SS_ON_TMDS
:
1447 percentage
= le16_to_cpu(igp_info
->info_8
.usDVISSPercentage
);
1448 rate
= le16_to_cpu(igp_info
->info_8
.usDVISSpreadRateIn10Hz
);
1450 case ASIC_INTERNAL_SS_ON_HDMI
:
1451 percentage
= le16_to_cpu(igp_info
->info_8
.usHDMISSPercentage
);
1452 rate
= le16_to_cpu(igp_info
->info_8
.usHDMISSpreadRateIn10Hz
);
1454 case ASIC_INTERNAL_SS_ON_LVDS
:
1455 percentage
= le16_to_cpu(igp_info
->info_8
.usLvdsSSPercentage
);
1456 rate
= le16_to_cpu(igp_info
->info_8
.usLvdsSSpreadRateIn10Hz
);
1461 DRM_ERROR("Unsupported IGP table: %d %d\n", frev
, crev
);
1465 ss
->percentage
= percentage
;
1471 union asic_ss_info
{
1472 struct _ATOM_ASIC_INTERNAL_SS_INFO info
;
1473 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2
;
1474 struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3
;
1477 union asic_ss_assignment
{
1478 struct _ATOM_ASIC_SS_ASSIGNMENT v1
;
1479 struct _ATOM_ASIC_SS_ASSIGNMENT_V2 v2
;
1480 struct _ATOM_ASIC_SS_ASSIGNMENT_V3 v3
;
1483 bool radeon_atombios_get_asic_ss_info(struct radeon_device
*rdev
,
1484 struct radeon_atom_ss
*ss
,
1487 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1488 int index
= GetIndexIntoMasterTable(DATA
, ASIC_InternalSS_Info
);
1489 uint16_t data_offset
, size
;
1490 union asic_ss_info
*ss_info
;
1491 union asic_ss_assignment
*ss_assign
;
1495 if (id
== ASIC_INTERNAL_MEMORY_SS
) {
1496 if (!(rdev
->mode_info
.firmware_flags
& ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT
))
1499 if (id
== ASIC_INTERNAL_ENGINE_SS
) {
1500 if (!(rdev
->mode_info
.firmware_flags
& ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT
))
1504 memset(ss
, 0, sizeof(struct radeon_atom_ss
));
1505 if (atom_parse_data_header(mode_info
->atom_context
, index
, &size
,
1506 &frev
, &crev
, &data_offset
)) {
1509 (union asic_ss_info
*)((char *)mode_info
->atom_context
->bios
+ data_offset
);
1513 num_indices
= (size
- sizeof(ATOM_COMMON_TABLE_HEADER
)) /
1514 sizeof(ATOM_ASIC_SS_ASSIGNMENT
);
1516 ss_assign
= (union asic_ss_assignment
*)((u8
*)&ss_info
->info
.asSpreadSpectrum
[0]);
1517 for (i
= 0; i
< num_indices
; i
++) {
1518 if ((ss_assign
->v1
.ucClockIndication
== id
) &&
1519 (clock
<= le32_to_cpu(ss_assign
->v1
.ulTargetClockRange
))) {
1521 le16_to_cpu(ss_assign
->v1
.usSpreadSpectrumPercentage
);
1522 ss
->type
= ss_assign
->v1
.ucSpreadSpectrumMode
;
1523 ss
->rate
= le16_to_cpu(ss_assign
->v1
.usSpreadRateInKhz
);
1524 ss
->percentage_divider
= 100;
1527 ss_assign
= (union asic_ss_assignment
*)
1528 ((u8
*)ss_assign
+ sizeof(ATOM_ASIC_SS_ASSIGNMENT
));
1532 num_indices
= (size
- sizeof(ATOM_COMMON_TABLE_HEADER
)) /
1533 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2
);
1534 ss_assign
= (union asic_ss_assignment
*)((u8
*)&ss_info
->info_2
.asSpreadSpectrum
[0]);
1535 for (i
= 0; i
< num_indices
; i
++) {
1536 if ((ss_assign
->v2
.ucClockIndication
== id
) &&
1537 (clock
<= le32_to_cpu(ss_assign
->v2
.ulTargetClockRange
))) {
1539 le16_to_cpu(ss_assign
->v2
.usSpreadSpectrumPercentage
);
1540 ss
->type
= ss_assign
->v2
.ucSpreadSpectrumMode
;
1541 ss
->rate
= le16_to_cpu(ss_assign
->v2
.usSpreadRateIn10Hz
);
1542 ss
->percentage_divider
= 100;
1544 ((id
== ASIC_INTERNAL_ENGINE_SS
) ||
1545 (id
== ASIC_INTERNAL_MEMORY_SS
)))
1549 ss_assign
= (union asic_ss_assignment
*)
1550 ((u8
*)ss_assign
+ sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2
));
1554 num_indices
= (size
- sizeof(ATOM_COMMON_TABLE_HEADER
)) /
1555 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3
);
1556 ss_assign
= (union asic_ss_assignment
*)((u8
*)&ss_info
->info_3
.asSpreadSpectrum
[0]);
1557 for (i
= 0; i
< num_indices
; i
++) {
1558 if ((ss_assign
->v3
.ucClockIndication
== id
) &&
1559 (clock
<= le32_to_cpu(ss_assign
->v3
.ulTargetClockRange
))) {
1561 le16_to_cpu(ss_assign
->v3
.usSpreadSpectrumPercentage
);
1562 ss
->type
= ss_assign
->v3
.ucSpreadSpectrumMode
;
1563 ss
->rate
= le16_to_cpu(ss_assign
->v3
.usSpreadRateIn10Hz
);
1564 if (ss_assign
->v3
.ucSpreadSpectrumMode
&
1565 SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK
)
1566 ss
->percentage_divider
= 1000;
1568 ss
->percentage_divider
= 100;
1569 if ((id
== ASIC_INTERNAL_ENGINE_SS
) ||
1570 (id
== ASIC_INTERNAL_MEMORY_SS
))
1572 if (rdev
->flags
& RADEON_IS_IGP
)
1573 radeon_atombios_get_igp_ss_overrides(rdev
, ss
, id
);
1576 ss_assign
= (union asic_ss_assignment
*)
1577 ((u8
*)ss_assign
+ sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3
));
1581 DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev
, crev
);
1590 struct _ATOM_LVDS_INFO info
;
1591 struct _ATOM_LVDS_INFO_V12 info_12
;
1594 struct radeon_encoder_atom_dig
*radeon_atombios_get_lvds_info(struct
1598 struct drm_device
*dev
= encoder
->base
.dev
;
1599 struct radeon_device
*rdev
= dev
->dev_private
;
1600 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1601 int index
= GetIndexIntoMasterTable(DATA
, LVDS_Info
);
1602 uint16_t data_offset
, misc
;
1603 union lvds_info
*lvds_info
;
1605 struct radeon_encoder_atom_dig
*lvds
= NULL
;
1606 int encoder_enum
= (encoder
->encoder_enum
& ENUM_ID_MASK
) >> ENUM_ID_SHIFT
;
1608 if (atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
1609 &frev
, &crev
, &data_offset
)) {
1611 (union lvds_info
*)((char *)mode_info
->atom_context
->bios
+ data_offset
);
1613 kzalloc(sizeof(struct radeon_encoder_atom_dig
), GFP_KERNEL
);
1618 lvds
->native_mode
.clock
=
1619 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usPixClk
) * 10;
1620 lvds
->native_mode
.hdisplay
=
1621 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usHActive
);
1622 lvds
->native_mode
.vdisplay
=
1623 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usVActive
);
1624 lvds
->native_mode
.htotal
= lvds
->native_mode
.hdisplay
+
1625 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usHBlanking_Time
);
1626 lvds
->native_mode
.hsync_start
= lvds
->native_mode
.hdisplay
+
1627 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usHSyncOffset
);
1628 lvds
->native_mode
.hsync_end
= lvds
->native_mode
.hsync_start
+
1629 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usHSyncWidth
);
1630 lvds
->native_mode
.vtotal
= lvds
->native_mode
.vdisplay
+
1631 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usVBlanking_Time
);
1632 lvds
->native_mode
.vsync_start
= lvds
->native_mode
.vdisplay
+
1633 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usVSyncOffset
);
1634 lvds
->native_mode
.vsync_end
= lvds
->native_mode
.vsync_start
+
1635 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usVSyncWidth
);
1636 lvds
->panel_pwr_delay
=
1637 le16_to_cpu(lvds_info
->info
.usOffDelayInMs
);
1638 lvds
->lcd_misc
= lvds_info
->info
.ucLVDS_Misc
;
1640 misc
= le16_to_cpu(lvds_info
->info
.sLCDTiming
.susModeMiscInfo
.usAccess
);
1641 if (misc
& ATOM_VSYNC_POLARITY
)
1642 lvds
->native_mode
.flags
|= DRM_MODE_FLAG_NVSYNC
;
1643 if (misc
& ATOM_HSYNC_POLARITY
)
1644 lvds
->native_mode
.flags
|= DRM_MODE_FLAG_NHSYNC
;
1645 if (misc
& ATOM_COMPOSITESYNC
)
1646 lvds
->native_mode
.flags
|= DRM_MODE_FLAG_CSYNC
;
1647 if (misc
& ATOM_INTERLACE
)
1648 lvds
->native_mode
.flags
|= DRM_MODE_FLAG_INTERLACE
;
1649 if (misc
& ATOM_DOUBLE_CLOCK_MODE
)
1650 lvds
->native_mode
.flags
|= DRM_MODE_FLAG_DBLSCAN
;
1652 lvds
->native_mode
.width_mm
= le16_to_cpu(lvds_info
->info
.sLCDTiming
.usImageHSize
);
1653 lvds
->native_mode
.height_mm
= le16_to_cpu(lvds_info
->info
.sLCDTiming
.usImageVSize
);
1655 /* set crtc values */
1656 drm_mode_set_crtcinfo(&lvds
->native_mode
, CRTC_INTERLACE_HALVE_V
);
1658 lvds
->lcd_ss_id
= lvds_info
->info
.ucSS_Id
;
1660 encoder
->native_mode
= lvds
->native_mode
;
1662 if (encoder_enum
== 2)
1665 lvds
->linkb
= false;
1667 /* parse the lcd record table */
1668 if (le16_to_cpu(lvds_info
->info
.usModePatchTableOffset
)) {
1669 ATOM_FAKE_EDID_PATCH_RECORD
*fake_edid_record
;
1670 ATOM_PANEL_RESOLUTION_PATCH_RECORD
*panel_res_record
;
1671 bool bad_record
= false;
1674 if ((frev
== 1) && (crev
< 2))
1676 record
= (u8
*)((char *)mode_info
->atom_context
->bios
+
1677 le16_to_cpu(lvds_info
->info
.usModePatchTableOffset
));
1680 record
= (u8
*)((char *)mode_info
->atom_context
->bios
+
1682 le16_to_cpu(lvds_info
->info
.usModePatchTableOffset
));
1683 while (*record
!= ATOM_RECORD_END_TYPE
) {
1685 case LCD_MODE_PATCH_RECORD_MODE_TYPE
:
1686 record
+= sizeof(ATOM_PATCH_RECORD_MODE
);
1688 case LCD_RTS_RECORD_TYPE
:
1689 record
+= sizeof(ATOM_LCD_RTS_RECORD
);
1691 case LCD_CAP_RECORD_TYPE
:
1692 record
+= sizeof(ATOM_LCD_MODE_CONTROL_CAP
);
1694 case LCD_FAKE_EDID_PATCH_RECORD_TYPE
:
1695 fake_edid_record
= (ATOM_FAKE_EDID_PATCH_RECORD
*)record
;
1696 if (fake_edid_record
->ucFakeEDIDLength
) {
1699 max((int)EDID_LENGTH
, (int)fake_edid_record
->ucFakeEDIDLength
);
1700 edid
= kmalloc(edid_size
, M_DRM
, M_WAITOK
);
1702 memcpy((u8
*)edid
, (u8
*)&fake_edid_record
->ucFakeEDIDString
[0],
1703 fake_edid_record
->ucFakeEDIDLength
);
1705 if (drm_edid_is_valid(edid
)) {
1706 rdev
->mode_info
.bios_hardcoded_edid
= edid
;
1707 rdev
->mode_info
.bios_hardcoded_edid_size
= edid_size
;
1712 record
+= fake_edid_record
->ucFakeEDIDLength
?
1713 fake_edid_record
->ucFakeEDIDLength
+ 2 :
1714 sizeof(ATOM_FAKE_EDID_PATCH_RECORD
);
1716 case LCD_PANEL_RESOLUTION_RECORD_TYPE
:
1717 panel_res_record
= (ATOM_PANEL_RESOLUTION_PATCH_RECORD
*)record
;
1718 lvds
->native_mode
.width_mm
= panel_res_record
->usHSize
;
1719 lvds
->native_mode
.height_mm
= panel_res_record
->usVSize
;
1720 record
+= sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD
);
1723 DRM_ERROR("Bad LCD record %d\n", *record
);
1735 struct radeon_encoder_primary_dac
*
1736 radeon_atombios_get_primary_dac_info(struct radeon_encoder
*encoder
)
1738 struct drm_device
*dev
= encoder
->base
.dev
;
1739 struct radeon_device
*rdev
= dev
->dev_private
;
1740 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1741 int index
= GetIndexIntoMasterTable(DATA
, CompassionateData
);
1742 uint16_t data_offset
;
1743 struct _COMPASSIONATE_DATA
*dac_info
;
1746 struct radeon_encoder_primary_dac
*p_dac
= NULL
;
1748 if (atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
1749 &frev
, &crev
, &data_offset
)) {
1750 dac_info
= (struct _COMPASSIONATE_DATA
*)
1751 ((char *)mode_info
->atom_context
->bios
+ data_offset
);
1753 p_dac
= kzalloc(sizeof(struct radeon_encoder_primary_dac
), GFP_KERNEL
);
1758 bg
= dac_info
->ucDAC1_BG_Adjustment
;
1759 dac
= dac_info
->ucDAC1_DAC_Adjustment
;
1760 p_dac
->ps2_pdac_adj
= (bg
<< 8) | (dac
);
1766 bool radeon_atom_get_tv_timings(struct radeon_device
*rdev
, int index
,
1767 struct drm_display_mode
*mode
)
1769 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1770 ATOM_ANALOG_TV_INFO
*tv_info
;
1771 ATOM_ANALOG_TV_INFO_V1_2
*tv_info_v1_2
;
1772 ATOM_DTD_FORMAT
*dtd_timings
;
1773 int data_index
= GetIndexIntoMasterTable(DATA
, AnalogTV_Info
);
1775 u16 data_offset
, misc
;
1777 if (!atom_parse_data_header(mode_info
->atom_context
, data_index
, NULL
,
1778 &frev
, &crev
, &data_offset
))
1783 tv_info
= (ATOM_ANALOG_TV_INFO
*)((char *)mode_info
->atom_context
->bios
+ data_offset
);
1784 if (index
>= MAX_SUPPORTED_TV_TIMING
)
1787 mode
->crtc_htotal
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_H_Total
);
1788 mode
->crtc_hdisplay
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_H_Disp
);
1789 mode
->crtc_hsync_start
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_H_SyncStart
);
1790 mode
->crtc_hsync_end
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_H_SyncStart
) +
1791 le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_H_SyncWidth
);
1793 mode
->crtc_vtotal
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_V_Total
);
1794 mode
->crtc_vdisplay
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_V_Disp
);
1795 mode
->crtc_vsync_start
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_V_SyncStart
);
1796 mode
->crtc_vsync_end
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_V_SyncStart
) +
1797 le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_V_SyncWidth
);
1800 misc
= le16_to_cpu(tv_info
->aModeTimings
[index
].susModeMiscInfo
.usAccess
);
1801 if (misc
& ATOM_VSYNC_POLARITY
)
1802 mode
->flags
|= DRM_MODE_FLAG_NVSYNC
;
1803 if (misc
& ATOM_HSYNC_POLARITY
)
1804 mode
->flags
|= DRM_MODE_FLAG_NHSYNC
;
1805 if (misc
& ATOM_COMPOSITESYNC
)
1806 mode
->flags
|= DRM_MODE_FLAG_CSYNC
;
1807 if (misc
& ATOM_INTERLACE
)
1808 mode
->flags
|= DRM_MODE_FLAG_INTERLACE
;
1809 if (misc
& ATOM_DOUBLE_CLOCK_MODE
)
1810 mode
->flags
|= DRM_MODE_FLAG_DBLSCAN
;
1812 mode
->crtc_clock
= mode
->clock
=
1813 le16_to_cpu(tv_info
->aModeTimings
[index
].usPixelClock
) * 10;
1816 /* PAL timings appear to have wrong values for totals */
1817 mode
->crtc_htotal
-= 1;
1818 mode
->crtc_vtotal
-= 1;
1822 tv_info_v1_2
= (ATOM_ANALOG_TV_INFO_V1_2
*)((char *)mode_info
->atom_context
->bios
+ data_offset
);
1823 if (index
>= MAX_SUPPORTED_TV_TIMING_V1_2
)
1826 dtd_timings
= &tv_info_v1_2
->aModeTimings
[index
];
1827 mode
->crtc_htotal
= le16_to_cpu(dtd_timings
->usHActive
) +
1828 le16_to_cpu(dtd_timings
->usHBlanking_Time
);
1829 mode
->crtc_hdisplay
= le16_to_cpu(dtd_timings
->usHActive
);
1830 mode
->crtc_hsync_start
= le16_to_cpu(dtd_timings
->usHActive
) +
1831 le16_to_cpu(dtd_timings
->usHSyncOffset
);
1832 mode
->crtc_hsync_end
= mode
->crtc_hsync_start
+
1833 le16_to_cpu(dtd_timings
->usHSyncWidth
);
1835 mode
->crtc_vtotal
= le16_to_cpu(dtd_timings
->usVActive
) +
1836 le16_to_cpu(dtd_timings
->usVBlanking_Time
);
1837 mode
->crtc_vdisplay
= le16_to_cpu(dtd_timings
->usVActive
);
1838 mode
->crtc_vsync_start
= le16_to_cpu(dtd_timings
->usVActive
) +
1839 le16_to_cpu(dtd_timings
->usVSyncOffset
);
1840 mode
->crtc_vsync_end
= mode
->crtc_vsync_start
+
1841 le16_to_cpu(dtd_timings
->usVSyncWidth
);
1844 misc
= le16_to_cpu(dtd_timings
->susModeMiscInfo
.usAccess
);
1845 if (misc
& ATOM_VSYNC_POLARITY
)
1846 mode
->flags
|= DRM_MODE_FLAG_NVSYNC
;
1847 if (misc
& ATOM_HSYNC_POLARITY
)
1848 mode
->flags
|= DRM_MODE_FLAG_NHSYNC
;
1849 if (misc
& ATOM_COMPOSITESYNC
)
1850 mode
->flags
|= DRM_MODE_FLAG_CSYNC
;
1851 if (misc
& ATOM_INTERLACE
)
1852 mode
->flags
|= DRM_MODE_FLAG_INTERLACE
;
1853 if (misc
& ATOM_DOUBLE_CLOCK_MODE
)
1854 mode
->flags
|= DRM_MODE_FLAG_DBLSCAN
;
1856 mode
->crtc_clock
= mode
->clock
=
1857 le16_to_cpu(dtd_timings
->usPixClk
) * 10;
1864 radeon_atombios_get_tv_info(struct radeon_device
*rdev
)
1866 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1867 int index
= GetIndexIntoMasterTable(DATA
, AnalogTV_Info
);
1868 uint16_t data_offset
;
1870 struct _ATOM_ANALOG_TV_INFO
*tv_info
;
1871 enum radeon_tv_std tv_std
= TV_STD_NTSC
;
1873 if (atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
1874 &frev
, &crev
, &data_offset
)) {
1876 tv_info
= (struct _ATOM_ANALOG_TV_INFO
*)
1877 ((char *)mode_info
->atom_context
->bios
+ data_offset
);
1879 switch (tv_info
->ucTV_BootUpDefaultStandard
) {
1881 tv_std
= TV_STD_NTSC
;
1882 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
1885 tv_std
= TV_STD_NTSC_J
;
1886 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
1889 tv_std
= TV_STD_PAL
;
1890 DRM_DEBUG_KMS("Default TV standard: PAL\n");
1893 tv_std
= TV_STD_PAL_M
;
1894 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
1897 tv_std
= TV_STD_PAL_N
;
1898 DRM_DEBUG_KMS("Default TV standard: PAL-N\n");
1901 tv_std
= TV_STD_PAL_CN
;
1902 DRM_DEBUG_KMS("Default TV standard: PAL-CN\n");
1905 tv_std
= TV_STD_PAL_60
;
1906 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
1909 tv_std
= TV_STD_SECAM
;
1910 DRM_DEBUG_KMS("Default TV standard: SECAM\n");
1913 tv_std
= TV_STD_NTSC
;
1914 DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n");
1921 struct radeon_encoder_tv_dac
*
1922 radeon_atombios_get_tv_dac_info(struct radeon_encoder
*encoder
)
1924 struct drm_device
*dev
= encoder
->base
.dev
;
1925 struct radeon_device
*rdev
= dev
->dev_private
;
1926 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1927 int index
= GetIndexIntoMasterTable(DATA
, CompassionateData
);
1928 uint16_t data_offset
;
1929 struct _COMPASSIONATE_DATA
*dac_info
;
1932 struct radeon_encoder_tv_dac
*tv_dac
= NULL
;
1934 if (atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
1935 &frev
, &crev
, &data_offset
)) {
1937 dac_info
= (struct _COMPASSIONATE_DATA
*)
1938 ((char *)mode_info
->atom_context
->bios
+ data_offset
);
1940 tv_dac
= kzalloc(sizeof(struct radeon_encoder_tv_dac
), GFP_KERNEL
);
1945 bg
= dac_info
->ucDAC2_CRT2_BG_Adjustment
;
1946 dac
= dac_info
->ucDAC2_CRT2_DAC_Adjustment
;
1947 tv_dac
->ps2_tvdac_adj
= (bg
<< 16) | (dac
<< 20);
1949 bg
= dac_info
->ucDAC2_PAL_BG_Adjustment
;
1950 dac
= dac_info
->ucDAC2_PAL_DAC_Adjustment
;
1951 tv_dac
->pal_tvdac_adj
= (bg
<< 16) | (dac
<< 20);
1953 bg
= dac_info
->ucDAC2_NTSC_BG_Adjustment
;
1954 dac
= dac_info
->ucDAC2_NTSC_DAC_Adjustment
;
1955 tv_dac
->ntsc_tvdac_adj
= (bg
<< 16) | (dac
<< 20);
1957 tv_dac
->tv_std
= radeon_atombios_get_tv_info(rdev
);
1962 static const char *thermal_controller_names
[] = {
1973 static const char *pp_lib_thermal_controller_names
[] = {
1996 struct _ATOM_POWERPLAY_INFO info
;
1997 struct _ATOM_POWERPLAY_INFO_V2 info_2
;
1998 struct _ATOM_POWERPLAY_INFO_V3 info_3
;
1999 struct _ATOM_PPLIB_POWERPLAYTABLE pplib
;
2000 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2
;
2001 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3
;
2004 union pplib_clock_info
{
2005 struct _ATOM_PPLIB_R600_CLOCK_INFO r600
;
2006 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780
;
2007 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen
;
2008 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo
;
2009 struct _ATOM_PPLIB_SI_CLOCK_INFO si
;
2010 struct _ATOM_PPLIB_CI_CLOCK_INFO ci
;
2013 union pplib_power_state
{
2014 struct _ATOM_PPLIB_STATE v1
;
2015 struct _ATOM_PPLIB_STATE_V2 v2
;
2018 static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device
*rdev
,
2020 u32 misc
, u32 misc2
)
2022 rdev
->pm
.power_state
[state_index
].misc
= misc
;
2023 rdev
->pm
.power_state
[state_index
].misc2
= misc2
;
2024 /* order matters! */
2025 if (misc
& ATOM_PM_MISCINFO_POWER_SAVING_MODE
)
2026 rdev
->pm
.power_state
[state_index
].type
=
2027 POWER_STATE_TYPE_POWERSAVE
;
2028 if (misc
& ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE
)
2029 rdev
->pm
.power_state
[state_index
].type
=
2030 POWER_STATE_TYPE_BATTERY
;
2031 if (misc
& ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE
)
2032 rdev
->pm
.power_state
[state_index
].type
=
2033 POWER_STATE_TYPE_BATTERY
;
2034 if (misc
& ATOM_PM_MISCINFO_LOAD_BALANCE_EN
)
2035 rdev
->pm
.power_state
[state_index
].type
=
2036 POWER_STATE_TYPE_BALANCED
;
2037 if (misc
& ATOM_PM_MISCINFO_3D_ACCELERATION_EN
) {
2038 rdev
->pm
.power_state
[state_index
].type
=
2039 POWER_STATE_TYPE_PERFORMANCE
;
2040 rdev
->pm
.power_state
[state_index
].flags
&=
2041 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
;
2043 if (misc2
& ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE
)
2044 rdev
->pm
.power_state
[state_index
].type
=
2045 POWER_STATE_TYPE_BALANCED
;
2046 if (misc
& ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE
) {
2047 rdev
->pm
.power_state
[state_index
].type
=
2048 POWER_STATE_TYPE_DEFAULT
;
2049 rdev
->pm
.default_power_state_index
= state_index
;
2050 rdev
->pm
.power_state
[state_index
].default_clock_mode
=
2051 &rdev
->pm
.power_state
[state_index
].clock_info
[0];
2052 } else if (state_index
== 0) {
2053 rdev
->pm
.power_state
[state_index
].clock_info
[0].flags
|=
2054 RADEON_PM_MODE_NO_DISPLAY
;
2058 static int radeon_atombios_parse_power_table_1_3(struct radeon_device
*rdev
)
2060 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
2061 u32 misc
, misc2
= 0;
2062 int num_modes
= 0, i
;
2063 int state_index
= 0;
2064 struct radeon_i2c_bus_rec i2c_bus
;
2065 union power_info
*power_info
;
2066 int index
= GetIndexIntoMasterTable(DATA
, PowerPlayInfo
);
2070 if (!atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
2071 &frev
, &crev
, &data_offset
))
2073 power_info
= (union power_info
*)((char *)mode_info
->atom_context
->bios
+ data_offset
);
2075 /* add the i2c bus for thermal/fan chip */
2076 if ((power_info
->info
.ucOverdriveThermalController
> 0) &&
2077 (power_info
->info
.ucOverdriveThermalController
< ARRAY_SIZE(thermal_controller_names
))) {
2078 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2079 thermal_controller_names
[power_info
->info
.ucOverdriveThermalController
],
2080 power_info
->info
.ucOverdriveControllerAddress
>> 1);
2081 i2c_bus
= radeon_lookup_i2c_gpio(rdev
, power_info
->info
.ucOverdriveI2cLine
);
2082 rdev
->pm
.i2c_bus
= radeon_i2c_lookup(rdev
, &i2c_bus
);
2084 if (rdev
->pm
.i2c_bus
) {
2085 struct i2c_board_info info
= { };
2086 const char *name
= thermal_controller_names
[power_info
->info
.
2087 ucOverdriveThermalController
];
2088 info
.addr
= power_info
->info
.ucOverdriveControllerAddress
>> 1;
2089 strlcpy(info
.type
, name
, sizeof(info
.type
));
2090 i2c_new_device(&rdev
->pm
.i2c_bus
->adapter
, &info
);
2092 #endif /* DUMBBELL_WIP */
2094 num_modes
= power_info
->info
.ucNumOfPowerModeEntries
;
2095 if (num_modes
> ATOM_MAX_NUMBEROF_POWER_BLOCK
)
2096 num_modes
= ATOM_MAX_NUMBEROF_POWER_BLOCK
;
2099 rdev
->pm
.power_state
= kzalloc(sizeof(struct radeon_power_state
) * num_modes
, GFP_KERNEL
);
2100 if (!rdev
->pm
.power_state
)
2102 /* last mode is usually default, array is low to high */
2103 for (i
= 0; i
< num_modes
; i
++) {
2104 rdev
->pm
.power_state
[state_index
].clock_info
=
2105 kzalloc(sizeof(struct radeon_pm_clock_info
) * 1, GFP_KERNEL
);
2106 if (!rdev
->pm
.power_state
[state_index
].clock_info
)
2108 rdev
->pm
.power_state
[state_index
].num_clock_modes
= 1;
2109 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
= VOLTAGE_NONE
;
2112 rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
=
2113 le16_to_cpu(power_info
->info
.asPowerPlayInfo
[i
].usMemoryClock
);
2114 rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
=
2115 le16_to_cpu(power_info
->info
.asPowerPlayInfo
[i
].usEngineClock
);
2116 /* skip invalid modes */
2117 if ((rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
== 0) ||
2118 (rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
== 0))
2120 rdev
->pm
.power_state
[state_index
].pcie_lanes
=
2121 power_info
->info
.asPowerPlayInfo
[i
].ucNumPciELanes
;
2122 misc
= le32_to_cpu(power_info
->info
.asPowerPlayInfo
[i
].ulMiscInfo
);
2123 if ((misc
& ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT
) ||
2124 (misc
& ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH
)) {
2125 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
=
2127 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.gpio
=
2128 radeon_lookup_gpio(rdev
,
2129 power_info
->info
.asPowerPlayInfo
[i
].ucVoltageDropIndex
);
2130 if (misc
& ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH
)
2131 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.active_high
=
2134 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.active_high
=
2136 } else if (misc
& ATOM_PM_MISCINFO_PROGRAM_VOLTAGE
) {
2137 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
=
2139 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.vddc_id
=
2140 power_info
->info
.asPowerPlayInfo
[i
].ucVoltageDropIndex
;
2142 rdev
->pm
.power_state
[state_index
].flags
= RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
;
2143 radeon_atombios_parse_misc_flags_1_3(rdev
, state_index
, misc
, 0);
2147 rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
=
2148 le32_to_cpu(power_info
->info_2
.asPowerPlayInfo
[i
].ulMemoryClock
);
2149 rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
=
2150 le32_to_cpu(power_info
->info_2
.asPowerPlayInfo
[i
].ulEngineClock
);
2151 /* skip invalid modes */
2152 if ((rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
== 0) ||
2153 (rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
== 0))
2155 rdev
->pm
.power_state
[state_index
].pcie_lanes
=
2156 power_info
->info_2
.asPowerPlayInfo
[i
].ucNumPciELanes
;
2157 misc
= le32_to_cpu(power_info
->info_2
.asPowerPlayInfo
[i
].ulMiscInfo
);
2158 misc2
= le32_to_cpu(power_info
->info_2
.asPowerPlayInfo
[i
].ulMiscInfo2
);
2159 if ((misc
& ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT
) ||
2160 (misc
& ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH
)) {
2161 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
=
2163 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.gpio
=
2164 radeon_lookup_gpio(rdev
,
2165 power_info
->info_2
.asPowerPlayInfo
[i
].ucVoltageDropIndex
);
2166 if (misc
& ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH
)
2167 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.active_high
=
2170 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.active_high
=
2172 } else if (misc
& ATOM_PM_MISCINFO_PROGRAM_VOLTAGE
) {
2173 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
=
2175 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.vddc_id
=
2176 power_info
->info_2
.asPowerPlayInfo
[i
].ucVoltageDropIndex
;
2178 rdev
->pm
.power_state
[state_index
].flags
= RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
;
2179 radeon_atombios_parse_misc_flags_1_3(rdev
, state_index
, misc
, misc2
);
2183 rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
=
2184 le32_to_cpu(power_info
->info_3
.asPowerPlayInfo
[i
].ulMemoryClock
);
2185 rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
=
2186 le32_to_cpu(power_info
->info_3
.asPowerPlayInfo
[i
].ulEngineClock
);
2187 /* skip invalid modes */
2188 if ((rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
== 0) ||
2189 (rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
== 0))
2191 rdev
->pm
.power_state
[state_index
].pcie_lanes
=
2192 power_info
->info_3
.asPowerPlayInfo
[i
].ucNumPciELanes
;
2193 misc
= le32_to_cpu(power_info
->info_3
.asPowerPlayInfo
[i
].ulMiscInfo
);
2194 misc2
= le32_to_cpu(power_info
->info_3
.asPowerPlayInfo
[i
].ulMiscInfo2
);
2195 if ((misc
& ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT
) ||
2196 (misc
& ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH
)) {
2197 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
=
2199 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.gpio
=
2200 radeon_lookup_gpio(rdev
,
2201 power_info
->info_3
.asPowerPlayInfo
[i
].ucVoltageDropIndex
);
2202 if (misc
& ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH
)
2203 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.active_high
=
2206 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.active_high
=
2208 } else if (misc
& ATOM_PM_MISCINFO_PROGRAM_VOLTAGE
) {
2209 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
=
2211 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.vddc_id
=
2212 power_info
->info_3
.asPowerPlayInfo
[i
].ucVoltageDropIndex
;
2213 if (misc2
& ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN
) {
2214 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.vddci_enabled
=
2216 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.vddci_id
=
2217 power_info
->info_3
.asPowerPlayInfo
[i
].ucVDDCI_VoltageDropIndex
;
2220 rdev
->pm
.power_state
[state_index
].flags
= RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
;
2221 radeon_atombios_parse_misc_flags_1_3(rdev
, state_index
, misc
, misc2
);
2226 /* last mode is usually default */
2227 if (rdev
->pm
.default_power_state_index
== -1) {
2228 rdev
->pm
.power_state
[state_index
- 1].type
=
2229 POWER_STATE_TYPE_DEFAULT
;
2230 rdev
->pm
.default_power_state_index
= state_index
- 1;
2231 rdev
->pm
.power_state
[state_index
- 1].default_clock_mode
=
2232 &rdev
->pm
.power_state
[state_index
- 1].clock_info
[0];
2233 rdev
->pm
.power_state
[state_index
].flags
&=
2234 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
;
2235 rdev
->pm
.power_state
[state_index
].misc
= 0;
2236 rdev
->pm
.power_state
[state_index
].misc2
= 0;
2241 static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device
*rdev
,
2242 ATOM_PPLIB_THERMALCONTROLLER
*controller
)
2244 struct radeon_i2c_bus_rec i2c_bus
;
2246 /* add the i2c bus for thermal/fan chip */
2247 if (controller
->ucType
> 0) {
2248 if (controller
->ucType
== ATOM_PP_THERMALCONTROLLER_RV6xx
) {
2249 DRM_INFO("Internal thermal controller %s fan control\n",
2250 (controller
->ucFanParameters
&
2251 ATOM_PP_FANPARAMETERS_NOFAN
) ? "without" : "with");
2252 rdev
->pm
.int_thermal_type
= THERMAL_TYPE_RV6XX
;
2253 } else if (controller
->ucType
== ATOM_PP_THERMALCONTROLLER_RV770
) {
2254 DRM_INFO("Internal thermal controller %s fan control\n",
2255 (controller
->ucFanParameters
&
2256 ATOM_PP_FANPARAMETERS_NOFAN
) ? "without" : "with");
2257 rdev
->pm
.int_thermal_type
= THERMAL_TYPE_RV770
;
2258 } else if (controller
->ucType
== ATOM_PP_THERMALCONTROLLER_EVERGREEN
) {
2259 DRM_INFO("Internal thermal controller %s fan control\n",
2260 (controller
->ucFanParameters
&
2261 ATOM_PP_FANPARAMETERS_NOFAN
) ? "without" : "with");
2262 rdev
->pm
.int_thermal_type
= THERMAL_TYPE_EVERGREEN
;
2263 } else if (controller
->ucType
== ATOM_PP_THERMALCONTROLLER_SUMO
) {
2264 DRM_INFO("Internal thermal controller %s fan control\n",
2265 (controller
->ucFanParameters
&
2266 ATOM_PP_FANPARAMETERS_NOFAN
) ? "without" : "with");
2267 rdev
->pm
.int_thermal_type
= THERMAL_TYPE_SUMO
;
2268 } else if (controller
->ucType
== ATOM_PP_THERMALCONTROLLER_NISLANDS
) {
2269 DRM_INFO("Internal thermal controller %s fan control\n",
2270 (controller
->ucFanParameters
&
2271 ATOM_PP_FANPARAMETERS_NOFAN
) ? "without" : "with");
2272 rdev
->pm
.int_thermal_type
= THERMAL_TYPE_NI
;
2273 } else if (controller
->ucType
== ATOM_PP_THERMALCONTROLLER_SISLANDS
) {
2274 DRM_INFO("Internal thermal controller %s fan control\n",
2275 (controller
->ucFanParameters
&
2276 ATOM_PP_FANPARAMETERS_NOFAN
) ? "without" : "with");
2277 rdev
->pm
.int_thermal_type
= THERMAL_TYPE_SI
;
2278 } else if (controller
->ucType
== ATOM_PP_THERMALCONTROLLER_CISLANDS
) {
2279 DRM_INFO("Internal thermal controller %s fan control\n",
2280 (controller
->ucFanParameters
&
2281 ATOM_PP_FANPARAMETERS_NOFAN
) ? "without" : "with");
2282 rdev
->pm
.int_thermal_type
= THERMAL_TYPE_CI
;
2283 } else if (controller
->ucType
== ATOM_PP_THERMALCONTROLLER_KAVERI
) {
2284 DRM_INFO("Internal thermal controller %s fan control\n",
2285 (controller
->ucFanParameters
&
2286 ATOM_PP_FANPARAMETERS_NOFAN
) ? "without" : "with");
2287 rdev
->pm
.int_thermal_type
= THERMAL_TYPE_KV
;
2288 } else if (controller
->ucType
==
2289 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO
) {
2290 DRM_INFO("External GPIO thermal controller %s fan control\n",
2291 (controller
->ucFanParameters
&
2292 ATOM_PP_FANPARAMETERS_NOFAN
) ? "without" : "with");
2293 rdev
->pm
.int_thermal_type
= THERMAL_TYPE_EXTERNAL_GPIO
;
2294 } else if (controller
->ucType
==
2295 ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL
) {
2296 DRM_INFO("ADT7473 with internal thermal controller %s fan control\n",
2297 (controller
->ucFanParameters
&
2298 ATOM_PP_FANPARAMETERS_NOFAN
) ? "without" : "with");
2299 rdev
->pm
.int_thermal_type
= THERMAL_TYPE_ADT7473_WITH_INTERNAL
;
2300 } else if (controller
->ucType
==
2301 ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL
) {
2302 DRM_INFO("EMC2103 with internal thermal controller %s fan control\n",
2303 (controller
->ucFanParameters
&
2304 ATOM_PP_FANPARAMETERS_NOFAN
) ? "without" : "with");
2305 rdev
->pm
.int_thermal_type
= THERMAL_TYPE_EMC2103_WITH_INTERNAL
;
2306 } else if (controller
->ucType
< ARRAY_SIZE(pp_lib_thermal_controller_names
)) {
2307 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
2308 pp_lib_thermal_controller_names
[controller
->ucType
],
2309 controller
->ucI2cAddress
>> 1,
2310 (controller
->ucFanParameters
&
2311 ATOM_PP_FANPARAMETERS_NOFAN
) ? "without" : "with");
2312 i2c_bus
= radeon_lookup_i2c_gpio(rdev
, controller
->ucI2cLine
);
2313 rdev
->pm
.i2c_bus
= radeon_i2c_lookup(rdev
, &i2c_bus
);
2315 if (rdev
->pm
.i2c_bus
) {
2316 struct i2c_board_info info
= { };
2317 const char *name
= pp_lib_thermal_controller_names
[controller
->ucType
];
2318 info
.addr
= controller
->ucI2cAddress
>> 1;
2319 strlcpy(info
.type
, name
, sizeof(info
.type
));
2320 i2c_new_device(&rdev
->pm
.i2c_bus
->adapter
, &info
);
2322 #endif /* DUMBBELL_WIP */
2324 DRM_INFO("Unknown thermal controller type %d at 0x%02x %s fan control\n",
2326 controller
->ucI2cAddress
>> 1,
2327 (controller
->ucFanParameters
&
2328 ATOM_PP_FANPARAMETERS_NOFAN
) ? "without" : "with");
2333 void radeon_atombios_get_default_voltages(struct radeon_device
*rdev
,
2334 u16
*vddc
, u16
*vddci
, u16
*mvdd
)
2336 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
2337 int index
= GetIndexIntoMasterTable(DATA
, FirmwareInfo
);
2340 union firmware_info
*firmware_info
;
2346 if (atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
2347 &frev
, &crev
, &data_offset
)) {
2349 (union firmware_info
*)((char *)mode_info
->atom_context
->bios
+
2351 *vddc
= le16_to_cpu(firmware_info
->info_14
.usBootUpVDDCVoltage
);
2352 if ((frev
== 2) && (crev
>= 2)) {
2353 *vddci
= le16_to_cpu(firmware_info
->info_22
.usBootUpVDDCIVoltage
);
2354 *mvdd
= le16_to_cpu(firmware_info
->info_22
.usBootUpMVDDCVoltage
);
2359 static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device
*rdev
,
2360 int state_index
, int mode_index
,
2361 struct _ATOM_PPLIB_NONCLOCK_INFO
*non_clock_info
)
2364 u32 misc
= le32_to_cpu(non_clock_info
->ulCapsAndSettings
);
2365 u32 misc2
= le16_to_cpu(non_clock_info
->usClassification
);
2366 u16 vddc
, vddci
, mvdd
;
2368 radeon_atombios_get_default_voltages(rdev
, &vddc
, &vddci
, &mvdd
);
2370 rdev
->pm
.power_state
[state_index
].misc
= misc
;
2371 rdev
->pm
.power_state
[state_index
].misc2
= misc2
;
2372 rdev
->pm
.power_state
[state_index
].pcie_lanes
=
2373 ((misc
& ATOM_PPLIB_PCIE_LINK_WIDTH_MASK
) >>
2374 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT
) + 1;
2375 switch (misc2
& ATOM_PPLIB_CLASSIFICATION_UI_MASK
) {
2376 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY
:
2377 rdev
->pm
.power_state
[state_index
].type
=
2378 POWER_STATE_TYPE_BATTERY
;
2380 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED
:
2381 rdev
->pm
.power_state
[state_index
].type
=
2382 POWER_STATE_TYPE_BALANCED
;
2384 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE
:
2385 rdev
->pm
.power_state
[state_index
].type
=
2386 POWER_STATE_TYPE_PERFORMANCE
;
2388 case ATOM_PPLIB_CLASSIFICATION_UI_NONE
:
2389 if (misc2
& ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE
)
2390 rdev
->pm
.power_state
[state_index
].type
=
2391 POWER_STATE_TYPE_PERFORMANCE
;
2394 rdev
->pm
.power_state
[state_index
].flags
= 0;
2395 if (misc
& ATOM_PPLIB_SINGLE_DISPLAY_ONLY
)
2396 rdev
->pm
.power_state
[state_index
].flags
|=
2397 RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
;
2398 if (misc2
& ATOM_PPLIB_CLASSIFICATION_BOOT
) {
2399 rdev
->pm
.power_state
[state_index
].type
=
2400 POWER_STATE_TYPE_DEFAULT
;
2401 rdev
->pm
.default_power_state_index
= state_index
;
2402 rdev
->pm
.power_state
[state_index
].default_clock_mode
=
2403 &rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
- 1];
2404 if ((rdev
->family
>= CHIP_BARTS
) && !(rdev
->flags
& RADEON_IS_IGP
)) {
2405 /* NI chips post without MC ucode, so default clocks are strobe mode only */
2406 rdev
->pm
.default_sclk
= rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
;
2407 rdev
->pm
.default_mclk
= rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
;
2408 rdev
->pm
.default_vddc
= rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.voltage
;
2409 rdev
->pm
.default_vddci
= rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.vddci
;
2413 if (ASIC_IS_DCE4(rdev
))
2414 radeon_atom_get_max_voltage(rdev
,
2415 SET_VOLTAGE_TYPE_ASIC_VDDCI
,
2417 /* patch the table values with the default sclk/mclk from firmware info */
2418 for (j
= 0; j
< mode_index
; j
++) {
2419 rdev
->pm
.power_state
[state_index
].clock_info
[j
].mclk
=
2420 rdev
->clock
.default_mclk
;
2421 rdev
->pm
.power_state
[state_index
].clock_info
[j
].sclk
=
2422 rdev
->clock
.default_sclk
;
2424 rdev
->pm
.power_state
[state_index
].clock_info
[j
].voltage
.voltage
=
2427 rdev
->pm
.power_state
[state_index
].clock_info
[j
].voltage
.vddci
=
2434 static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device
*rdev
,
2435 int state_index
, int mode_index
,
2436 union pplib_clock_info
*clock_info
)
2441 if (rdev
->flags
& RADEON_IS_IGP
) {
2442 if (rdev
->family
>= CHIP_PALM
) {
2443 sclk
= le16_to_cpu(clock_info
->sumo
.usEngineClockLow
);
2444 sclk
|= clock_info
->sumo
.ucEngineClockHigh
<< 16;
2445 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].sclk
= sclk
;
2447 sclk
= le16_to_cpu(clock_info
->rs780
.usLowEngineClockLow
);
2448 sclk
|= clock_info
->rs780
.ucLowEngineClockHigh
<< 16;
2449 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].sclk
= sclk
;
2451 } else if (rdev
->family
>= CHIP_BONAIRE
) {
2452 sclk
= le16_to_cpu(clock_info
->ci
.usEngineClockLow
);
2453 sclk
|= clock_info
->ci
.ucEngineClockHigh
<< 16;
2454 mclk
= le16_to_cpu(clock_info
->ci
.usMemoryClockLow
);
2455 mclk
|= clock_info
->ci
.ucMemoryClockHigh
<< 16;
2456 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].mclk
= mclk
;
2457 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].sclk
= sclk
;
2458 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].voltage
.type
=
2460 } else if (rdev
->family
>= CHIP_TAHITI
) {
2461 sclk
= le16_to_cpu(clock_info
->si
.usEngineClockLow
);
2462 sclk
|= clock_info
->si
.ucEngineClockHigh
<< 16;
2463 mclk
= le16_to_cpu(clock_info
->si
.usMemoryClockLow
);
2464 mclk
|= clock_info
->si
.ucMemoryClockHigh
<< 16;
2465 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].mclk
= mclk
;
2466 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].sclk
= sclk
;
2467 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].voltage
.type
=
2469 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].voltage
.voltage
=
2470 le16_to_cpu(clock_info
->si
.usVDDC
);
2471 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].voltage
.vddci
=
2472 le16_to_cpu(clock_info
->si
.usVDDCI
);
2473 } else if (rdev
->family
>= CHIP_CEDAR
) {
2474 sclk
= le16_to_cpu(clock_info
->evergreen
.usEngineClockLow
);
2475 sclk
|= clock_info
->evergreen
.ucEngineClockHigh
<< 16;
2476 mclk
= le16_to_cpu(clock_info
->evergreen
.usMemoryClockLow
);
2477 mclk
|= clock_info
->evergreen
.ucMemoryClockHigh
<< 16;
2478 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].mclk
= mclk
;
2479 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].sclk
= sclk
;
2480 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].voltage
.type
=
2482 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].voltage
.voltage
=
2483 le16_to_cpu(clock_info
->evergreen
.usVDDC
);
2484 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].voltage
.vddci
=
2485 le16_to_cpu(clock_info
->evergreen
.usVDDCI
);
2487 sclk
= le16_to_cpu(clock_info
->r600
.usEngineClockLow
);
2488 sclk
|= clock_info
->r600
.ucEngineClockHigh
<< 16;
2489 mclk
= le16_to_cpu(clock_info
->r600
.usMemoryClockLow
);
2490 mclk
|= clock_info
->r600
.ucMemoryClockHigh
<< 16;
2491 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].mclk
= mclk
;
2492 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].sclk
= sclk
;
2493 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].voltage
.type
=
2495 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].voltage
.voltage
=
2496 le16_to_cpu(clock_info
->r600
.usVDDC
);
2499 /* patch up vddc if necessary */
2500 switch (rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].voltage
.voltage
) {
2501 case ATOM_VIRTUAL_VOLTAGE_ID0
:
2502 case ATOM_VIRTUAL_VOLTAGE_ID1
:
2503 case ATOM_VIRTUAL_VOLTAGE_ID2
:
2504 case ATOM_VIRTUAL_VOLTAGE_ID3
:
2505 case ATOM_VIRTUAL_VOLTAGE_ID4
:
2506 case ATOM_VIRTUAL_VOLTAGE_ID5
:
2507 case ATOM_VIRTUAL_VOLTAGE_ID6
:
2508 case ATOM_VIRTUAL_VOLTAGE_ID7
:
2509 if (radeon_atom_get_max_vddc(rdev
, VOLTAGE_TYPE_VDDC
,
2510 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].voltage
.voltage
,
2512 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].voltage
.voltage
= vddc
;
2518 if (rdev
->flags
& RADEON_IS_IGP
) {
2519 /* skip invalid modes */
2520 if (rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].sclk
== 0)
2523 /* skip invalid modes */
2524 if ((rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].mclk
== 0) ||
2525 (rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].sclk
== 0))
2531 static int radeon_atombios_parse_power_table_4_5(struct radeon_device
*rdev
)
2533 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
2534 struct _ATOM_PPLIB_NONCLOCK_INFO
*non_clock_info
;
2535 union pplib_power_state
*power_state
;
2537 int state_index
= 0, mode_index
= 0;
2538 union pplib_clock_info
*clock_info
;
2540 union power_info
*power_info
;
2541 int index
= GetIndexIntoMasterTable(DATA
, PowerPlayInfo
);
2545 if (!atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
2546 &frev
, &crev
, &data_offset
))
2548 power_info
= (union power_info
*)((char *)mode_info
->atom_context
->bios
+ data_offset
);
2550 radeon_atombios_add_pplib_thermal_controller(rdev
, &power_info
->pplib
.sThermalController
);
2551 if (power_info
->pplib
.ucNumStates
== 0)
2553 rdev
->pm
.power_state
= kzalloc(sizeof(struct radeon_power_state
) *
2554 power_info
->pplib
.ucNumStates
, GFP_KERNEL
);
2555 if (!rdev
->pm
.power_state
)
2557 /* first mode is usually default, followed by low to high */
2558 for (i
= 0; i
< power_info
->pplib
.ucNumStates
; i
++) {
2560 power_state
= (union pplib_power_state
*)
2561 ((char *)mode_info
->atom_context
->bios
+ data_offset
+
2562 le16_to_cpu(power_info
->pplib
.usStateArrayOffset
) +
2563 i
* power_info
->pplib
.ucStateEntrySize
);
2564 non_clock_info
= (struct _ATOM_PPLIB_NONCLOCK_INFO
*)
2565 ((char *)mode_info
->atom_context
->bios
+ data_offset
+
2566 le16_to_cpu(power_info
->pplib
.usNonClockInfoArrayOffset
) +
2567 (power_state
->v1
.ucNonClockStateIndex
*
2568 power_info
->pplib
.ucNonClockSize
));
2569 rdev
->pm
.power_state
[i
].clock_info
= kzalloc(sizeof(struct radeon_pm_clock_info
) *
2570 ((power_info
->pplib
.ucStateEntrySize
- 1) ?
2571 (power_info
->pplib
.ucStateEntrySize
- 1) : 1),
2573 if (!rdev
->pm
.power_state
[i
].clock_info
)
2575 if (power_info
->pplib
.ucStateEntrySize
- 1) {
2576 for (j
= 0; j
< (power_info
->pplib
.ucStateEntrySize
- 1); j
++) {
2577 clock_info
= (union pplib_clock_info
*)
2578 ((char *)mode_info
->atom_context
->bios
+ data_offset
+
2579 le16_to_cpu(power_info
->pplib
.usClockInfoArrayOffset
) +
2580 (power_state
->v1
.ucClockStateIndices
[j
] *
2581 power_info
->pplib
.ucClockInfoSize
));
2582 valid
= radeon_atombios_parse_pplib_clock_info(rdev
,
2583 state_index
, mode_index
,
2589 rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
=
2590 rdev
->clock
.default_mclk
;
2591 rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
=
2592 rdev
->clock
.default_sclk
;
2595 rdev
->pm
.power_state
[state_index
].num_clock_modes
= mode_index
;
2597 radeon_atombios_parse_pplib_non_clock_info(rdev
, state_index
, mode_index
,
2602 /* if multiple clock modes, mark the lowest as no display */
2603 for (i
= 0; i
< state_index
; i
++) {
2604 if (rdev
->pm
.power_state
[i
].num_clock_modes
> 1)
2605 rdev
->pm
.power_state
[i
].clock_info
[0].flags
|=
2606 RADEON_PM_MODE_NO_DISPLAY
;
2608 /* first mode is usually default */
2609 if (rdev
->pm
.default_power_state_index
== -1) {
2610 rdev
->pm
.power_state
[0].type
=
2611 POWER_STATE_TYPE_DEFAULT
;
2612 rdev
->pm
.default_power_state_index
= 0;
2613 rdev
->pm
.power_state
[0].default_clock_mode
=
2614 &rdev
->pm
.power_state
[0].clock_info
[0];
2619 static int radeon_atombios_parse_power_table_6(struct radeon_device
*rdev
)
2621 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
2622 struct _ATOM_PPLIB_NONCLOCK_INFO
*non_clock_info
;
2623 union pplib_power_state
*power_state
;
2624 int i
, j
, non_clock_array_index
, clock_array_index
;
2625 int state_index
= 0, mode_index
= 0;
2626 union pplib_clock_info
*clock_info
;
2627 struct _StateArray
*state_array
;
2628 struct _ClockInfoArray
*clock_info_array
;
2629 struct _NonClockInfoArray
*non_clock_info_array
;
2631 union power_info
*power_info
;
2632 int index
= GetIndexIntoMasterTable(DATA
, PowerPlayInfo
);
2635 u8
*power_state_offset
;
2637 if (!atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
2638 &frev
, &crev
, &data_offset
))
2640 power_info
= (union power_info
*)((char *)mode_info
->atom_context
->bios
+ data_offset
);
2642 radeon_atombios_add_pplib_thermal_controller(rdev
, &power_info
->pplib
.sThermalController
);
2643 state_array
= (struct _StateArray
*)
2644 ((char *)mode_info
->atom_context
->bios
+ data_offset
+
2645 le16_to_cpu(power_info
->pplib
.usStateArrayOffset
));
2646 clock_info_array
= (struct _ClockInfoArray
*)
2647 ((char *)mode_info
->atom_context
->bios
+ data_offset
+
2648 le16_to_cpu(power_info
->pplib
.usClockInfoArrayOffset
));
2649 non_clock_info_array
= (struct _NonClockInfoArray
*)
2650 ((char *)mode_info
->atom_context
->bios
+ data_offset
+
2651 le16_to_cpu(power_info
->pplib
.usNonClockInfoArrayOffset
));
2652 if (state_array
->ucNumEntries
== 0)
2654 rdev
->pm
.power_state
= kzalloc(sizeof(struct radeon_power_state
) *
2655 state_array
->ucNumEntries
, GFP_KERNEL
);
2656 if (!rdev
->pm
.power_state
)
2658 power_state_offset
= (u8
*)state_array
->states
;
2659 for (i
= 0; i
< state_array
->ucNumEntries
; i
++) {
2661 power_state
= (union pplib_power_state
*)power_state_offset
;
2662 non_clock_array_index
= power_state
->v2
.nonClockInfoIndex
;
2663 non_clock_info
= (struct _ATOM_PPLIB_NONCLOCK_INFO
*)
2664 &non_clock_info_array
->nonClockInfo
[non_clock_array_index
];
2665 rdev
->pm
.power_state
[i
].clock_info
= kzalloc(sizeof(struct radeon_pm_clock_info
) *
2666 (power_state
->v2
.ucNumDPMLevels
?
2667 power_state
->v2
.ucNumDPMLevels
: 1),
2669 if (!rdev
->pm
.power_state
[i
].clock_info
)
2671 if (power_state
->v2
.ucNumDPMLevels
) {
2672 for (j
= 0; j
< power_state
->v2
.ucNumDPMLevels
; j
++) {
2673 clock_array_index
= power_state
->v2
.clockInfoIndex
[j
];
2674 clock_info
= (union pplib_clock_info
*)
2675 &clock_info_array
->clockInfo
[clock_array_index
* clock_info_array
->ucEntrySize
];
2676 valid
= radeon_atombios_parse_pplib_clock_info(rdev
,
2677 state_index
, mode_index
,
2683 rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
=
2684 rdev
->clock
.default_mclk
;
2685 rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
=
2686 rdev
->clock
.default_sclk
;
2689 rdev
->pm
.power_state
[state_index
].num_clock_modes
= mode_index
;
2691 radeon_atombios_parse_pplib_non_clock_info(rdev
, state_index
, mode_index
,
2695 power_state_offset
+= 2 + power_state
->v2
.ucNumDPMLevels
;
2697 /* if multiple clock modes, mark the lowest as no display */
2698 for (i
= 0; i
< state_index
; i
++) {
2699 if (rdev
->pm
.power_state
[i
].num_clock_modes
> 1)
2700 rdev
->pm
.power_state
[i
].clock_info
[0].flags
|=
2701 RADEON_PM_MODE_NO_DISPLAY
;
2703 /* first mode is usually default */
2704 if (rdev
->pm
.default_power_state_index
== -1) {
2705 rdev
->pm
.power_state
[0].type
=
2706 POWER_STATE_TYPE_DEFAULT
;
2707 rdev
->pm
.default_power_state_index
= 0;
2708 rdev
->pm
.power_state
[0].default_clock_mode
=
2709 &rdev
->pm
.power_state
[0].clock_info
[0];
2714 void radeon_atombios_get_power_modes(struct radeon_device
*rdev
)
2716 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
2717 int index
= GetIndexIntoMasterTable(DATA
, PowerPlayInfo
);
2720 int state_index
= 0;
2722 rdev
->pm
.default_power_state_index
= -1;
2724 if (atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
2725 &frev
, &crev
, &data_offset
)) {
2730 state_index
= radeon_atombios_parse_power_table_1_3(rdev
);
2734 state_index
= radeon_atombios_parse_power_table_4_5(rdev
);
2737 state_index
= radeon_atombios_parse_power_table_6(rdev
);
2744 if (state_index
== 0) {
2745 rdev
->pm
.power_state
= kzalloc(sizeof(struct radeon_power_state
), GFP_KERNEL
);
2746 if (rdev
->pm
.power_state
) {
2747 rdev
->pm
.power_state
[0].clock_info
=
2748 kzalloc(sizeof(struct radeon_pm_clock_info
) * 1, GFP_KERNEL
);
2749 if (rdev
->pm
.power_state
[0].clock_info
) {
2750 /* add the default mode */
2751 rdev
->pm
.power_state
[state_index
].type
=
2752 POWER_STATE_TYPE_DEFAULT
;
2753 rdev
->pm
.power_state
[state_index
].num_clock_modes
= 1;
2754 rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
= rdev
->clock
.default_mclk
;
2755 rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
= rdev
->clock
.default_sclk
;
2756 rdev
->pm
.power_state
[state_index
].default_clock_mode
=
2757 &rdev
->pm
.power_state
[state_index
].clock_info
[0];
2758 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
= VOLTAGE_NONE
;
2759 rdev
->pm
.power_state
[state_index
].pcie_lanes
= 16;
2760 rdev
->pm
.default_power_state_index
= state_index
;
2761 rdev
->pm
.power_state
[state_index
].flags
= 0;
2767 rdev
->pm
.num_power_states
= state_index
;
2769 rdev
->pm
.current_power_state_index
= rdev
->pm
.default_power_state_index
;
2770 rdev
->pm
.current_clock_mode_index
= 0;
2771 if (rdev
->pm
.default_power_state_index
>= 0)
2772 rdev
->pm
.current_vddc
=
2773 rdev
->pm
.power_state
[rdev
->pm
.default_power_state_index
].clock_info
[0].voltage
.voltage
;
2775 rdev
->pm
.current_vddc
= 0;
2778 union get_clock_dividers
{
2779 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1
;
2780 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 v2
;
2781 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3
;
2782 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4
;
2783 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5
;
2784 struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 v6_in
;
2785 struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 v6_out
;
2788 int radeon_atom_get_clock_dividers(struct radeon_device
*rdev
,
2792 struct atom_clock_dividers
*dividers
)
2794 union get_clock_dividers args
;
2795 int index
= GetIndexIntoMasterTable(COMMAND
, ComputeMemoryEnginePLL
);
2798 memset(&args
, 0, sizeof(args
));
2799 memset(dividers
, 0, sizeof(struct atom_clock_dividers
));
2801 if (!atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
))
2807 args
.v1
.ucAction
= clock_type
;
2808 args
.v1
.ulClock
= cpu_to_le32(clock
); /* 10 khz */
2810 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
2812 dividers
->post_div
= args
.v1
.ucPostDiv
;
2813 dividers
->fb_div
= args
.v1
.ucFbDiv
;
2814 dividers
->enable_post_div
= true;
2819 /* r6xx, r7xx, evergreen, ni, si */
2820 if (rdev
->family
<= CHIP_RV770
) {
2821 args
.v2
.ucAction
= clock_type
;
2822 args
.v2
.ulClock
= cpu_to_le32(clock
); /* 10 khz */
2824 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
2826 dividers
->post_div
= args
.v2
.ucPostDiv
;
2827 dividers
->fb_div
= le16_to_cpu(args
.v2
.usFbDiv
);
2828 dividers
->ref_div
= args
.v2
.ucAction
;
2829 if (rdev
->family
== CHIP_RV770
) {
2830 dividers
->enable_post_div
= (le32_to_cpu(args
.v2
.ulClock
) & (1 << 24)) ?
2832 dividers
->vco_mode
= (le32_to_cpu(args
.v2
.ulClock
) & (1 << 25)) ? 1 : 0;
2834 dividers
->enable_post_div
= (dividers
->fb_div
& 1) ? true : false;
2836 if (clock_type
== COMPUTE_ENGINE_PLL_PARAM
) {
2837 args
.v3
.ulClockParams
= cpu_to_le32((clock_type
<< 24) | clock
);
2839 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
2841 dividers
->post_div
= args
.v3
.ucPostDiv
;
2842 dividers
->enable_post_div
= (args
.v3
.ucCntlFlag
&
2843 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN
) ? true : false;
2844 dividers
->enable_dithen
= (args
.v3
.ucCntlFlag
&
2845 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE
) ? false : true;
2846 dividers
->whole_fb_div
= le16_to_cpu(args
.v3
.ulFbDiv
.usFbDiv
);
2847 dividers
->frac_fb_div
= le16_to_cpu(args
.v3
.ulFbDiv
.usFbDivFrac
);
2848 dividers
->ref_div
= args
.v3
.ucRefDiv
;
2849 dividers
->vco_mode
= (args
.v3
.ucCntlFlag
&
2850 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE
) ? 1 : 0;
2852 /* for SI we use ComputeMemoryClockParam for memory plls */
2853 if (rdev
->family
>= CHIP_TAHITI
)
2855 args
.v5
.ulClockParams
= cpu_to_le32((clock_type
<< 24) | clock
);
2857 args
.v5
.ucInputFlag
= ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN
;
2859 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
2861 dividers
->post_div
= args
.v5
.ucPostDiv
;
2862 dividers
->enable_post_div
= (args
.v5
.ucCntlFlag
&
2863 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN
) ? true : false;
2864 dividers
->enable_dithen
= (args
.v5
.ucCntlFlag
&
2865 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE
) ? false : true;
2866 dividers
->whole_fb_div
= le16_to_cpu(args
.v5
.ulFbDiv
.usFbDiv
);
2867 dividers
->frac_fb_div
= le16_to_cpu(args
.v5
.ulFbDiv
.usFbDivFrac
);
2868 dividers
->ref_div
= args
.v5
.ucRefDiv
;
2869 dividers
->vco_mode
= (args
.v5
.ucCntlFlag
&
2870 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE
) ? 1 : 0;
2876 args
.v4
.ulClock
= cpu_to_le32(clock
); /* 10 khz */
2878 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
2880 dividers
->post_divider
= dividers
->post_div
= args
.v4
.ucPostDiv
;
2881 dividers
->real_clock
= le32_to_cpu(args
.v4
.ulClock
);
2885 /* COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, COMPUTE_GPUCLK_INPUT_FLAG_SCLK */
2886 args
.v6_in
.ulClock
.ulComputeClockFlag
= clock_type
;
2887 args
.v6_in
.ulClock
.ulClockFreq
= cpu_to_le32(clock
); /* 10 khz */
2889 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
2891 dividers
->whole_fb_div
= le16_to_cpu(args
.v6_out
.ulFbDiv
.usFbDiv
);
2892 dividers
->frac_fb_div
= le16_to_cpu(args
.v6_out
.ulFbDiv
.usFbDivFrac
);
2893 dividers
->ref_div
= args
.v6_out
.ucPllRefDiv
;
2894 dividers
->post_div
= args
.v6_out
.ucPllPostDiv
;
2895 dividers
->flags
= args
.v6_out
.ucPllCntlFlag
;
2896 dividers
->real_clock
= le32_to_cpu(args
.v6_out
.ulClock
.ulClock
);
2897 dividers
->post_divider
= args
.v6_out
.ulClock
.ucPostDiv
;
2905 int radeon_atom_get_memory_pll_dividers(struct radeon_device
*rdev
,
2908 struct atom_mpll_param
*mpll_param
)
2910 COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 args
;
2911 int index
= GetIndexIntoMasterTable(COMMAND
, ComputeMemoryClockParam
);
2914 memset(&args
, 0, sizeof(args
));
2915 memset(mpll_param
, 0, sizeof(struct atom_mpll_param
));
2917 if (!atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
))
2925 args
.ulClock
= cpu_to_le32(clock
); /* 10 khz */
2926 args
.ucInputFlag
= 0;
2928 args
.ucInputFlag
|= MPLL_INPUT_FLAG_STROBE_MODE_EN
;
2930 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
2932 mpll_param
->clkfrac
= le16_to_cpu(args
.ulFbDiv
.usFbDivFrac
);
2933 mpll_param
->clkf
= le16_to_cpu(args
.ulFbDiv
.usFbDiv
);
2934 mpll_param
->post_div
= args
.ucPostDiv
;
2935 mpll_param
->dll_speed
= args
.ucDllSpeed
;
2936 mpll_param
->bwcntl
= args
.ucBWCntl
;
2937 mpll_param
->vco_mode
=
2938 (args
.ucPllCntlFlag
& MPLL_CNTL_FLAG_VCO_MODE_MASK
);
2939 mpll_param
->yclk_sel
=
2940 (args
.ucPllCntlFlag
& MPLL_CNTL_FLAG_BYPASS_DQ_PLL
) ? 1 : 0;
2942 (args
.ucPllCntlFlag
& MPLL_CNTL_FLAG_QDR_ENABLE
) ? 1 : 0;
2943 mpll_param
->half_rate
=
2944 (args
.ucPllCntlFlag
& MPLL_CNTL_FLAG_AD_HALF_RATE
) ? 1 : 0;
2956 void radeon_atom_set_clock_gating(struct radeon_device
*rdev
, int enable
)
2958 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args
;
2959 int index
= GetIndexIntoMasterTable(COMMAND
, DynamicClockGating
);
2961 args
.ucEnable
= enable
;
2963 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
2966 uint32_t radeon_atom_get_engine_clock(struct radeon_device
*rdev
)
2968 GET_ENGINE_CLOCK_PS_ALLOCATION args
;
2969 int index
= GetIndexIntoMasterTable(COMMAND
, GetEngineClock
);
2971 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
2972 return le32_to_cpu(args
.ulReturnEngineClock
);
2975 uint32_t radeon_atom_get_memory_clock(struct radeon_device
*rdev
)
2977 GET_MEMORY_CLOCK_PS_ALLOCATION args
;
2978 int index
= GetIndexIntoMasterTable(COMMAND
, GetMemoryClock
);
2980 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
2981 return le32_to_cpu(args
.ulReturnMemoryClock
);
2984 void radeon_atom_set_engine_clock(struct radeon_device
*rdev
,
2987 SET_ENGINE_CLOCK_PS_ALLOCATION args
;
2988 int index
= GetIndexIntoMasterTable(COMMAND
, SetEngineClock
);
2990 args
.ulTargetEngineClock
= cpu_to_le32(eng_clock
); /* 10 khz */
2992 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
2995 void radeon_atom_set_memory_clock(struct radeon_device
*rdev
,
2998 SET_MEMORY_CLOCK_PS_ALLOCATION args
;
2999 int index
= GetIndexIntoMasterTable(COMMAND
, SetMemoryClock
);
3001 if (rdev
->flags
& RADEON_IS_IGP
)
3004 args
.ulTargetMemoryClock
= cpu_to_le32(mem_clock
); /* 10 khz */
3006 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
3009 void radeon_atom_set_engine_dram_timings(struct radeon_device
*rdev
,
3010 u32 eng_clock
, u32 mem_clock
)
3012 SET_ENGINE_CLOCK_PS_ALLOCATION args
;
3013 int index
= GetIndexIntoMasterTable(COMMAND
, DynamicMemorySettings
);
3016 memset(&args
, 0, sizeof(args
));
3018 tmp
= eng_clock
& SET_CLOCK_FREQ_MASK
;
3019 tmp
|= (COMPUTE_ENGINE_PLL_PARAM
<< 24);
3021 args
.ulTargetEngineClock
= cpu_to_le32(tmp
);
3023 args
.sReserved
.ulClock
= cpu_to_le32(mem_clock
& SET_CLOCK_FREQ_MASK
);
3025 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
3028 void radeon_atom_update_memory_dll(struct radeon_device
*rdev
,
3032 int index
= GetIndexIntoMasterTable(COMMAND
, DynamicMemorySettings
);
3034 args
= cpu_to_le32(mem_clock
); /* 10 khz */
3036 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
3039 void radeon_atom_set_ac_timing(struct radeon_device
*rdev
,
3042 SET_MEMORY_CLOCK_PS_ALLOCATION args
;
3043 int index
= GetIndexIntoMasterTable(COMMAND
, DynamicMemorySettings
);
3044 u32 tmp
= mem_clock
| (COMPUTE_MEMORY_PLL_PARAM
<< 24);
3046 args
.ulTargetMemoryClock
= cpu_to_le32(tmp
); /* 10 khz */
3048 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
3052 struct _SET_VOLTAGE_PS_ALLOCATION alloc
;
3053 struct _SET_VOLTAGE_PARAMETERS v1
;
3054 struct _SET_VOLTAGE_PARAMETERS_V2 v2
;
3055 struct _SET_VOLTAGE_PARAMETERS_V1_3 v3
;
3058 void radeon_atom_set_voltage(struct radeon_device
*rdev
, u16 voltage_level
, u8 voltage_type
)
3060 union set_voltage args
;
3061 int index
= GetIndexIntoMasterTable(COMMAND
, SetVoltage
);
3062 u8 frev
, crev
, volt_index
= voltage_level
;
3064 if (!atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
))
3067 /* 0xff01 is a flag rather then an actual voltage */
3068 if (voltage_level
== 0xff01)
3073 args
.v1
.ucVoltageType
= voltage_type
;
3074 args
.v1
.ucVoltageMode
= SET_ASIC_VOLTAGE_MODE_ALL_SOURCE
;
3075 args
.v1
.ucVoltageIndex
= volt_index
;
3078 args
.v2
.ucVoltageType
= voltage_type
;
3079 args
.v2
.ucVoltageMode
= SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE
;
3080 args
.v2
.usVoltageLevel
= cpu_to_le16(voltage_level
);
3083 args
.v3
.ucVoltageType
= voltage_type
;
3084 args
.v3
.ucVoltageMode
= ATOM_SET_VOLTAGE
;
3085 args
.v3
.usVoltageLevel
= cpu_to_le16(voltage_level
);
3088 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
3092 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
3095 int radeon_atom_get_max_vddc(struct radeon_device
*rdev
, u8 voltage_type
,
3096 u16 voltage_id
, u16
*voltage
)
3098 union set_voltage args
;
3099 int index
= GetIndexIntoMasterTable(COMMAND
, SetVoltage
);
3102 if (!atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
))
3109 args
.v2
.ucVoltageType
= SET_VOLTAGE_GET_MAX_VOLTAGE
;
3110 args
.v2
.ucVoltageMode
= 0;
3111 args
.v2
.usVoltageLevel
= 0;
3113 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
3115 *voltage
= le16_to_cpu(args
.v2
.usVoltageLevel
);
3118 args
.v3
.ucVoltageType
= voltage_type
;
3119 args
.v3
.ucVoltageMode
= ATOM_GET_VOLTAGE_LEVEL
;
3120 args
.v3
.usVoltageLevel
= cpu_to_le16(voltage_id
);
3122 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
3124 *voltage
= le16_to_cpu(args
.v3
.usVoltageLevel
);
3127 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
3134 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device
*rdev
,
3138 return radeon_atom_get_max_vddc(rdev
, VOLTAGE_TYPE_VDDC
, leakage_idx
, voltage
);
3141 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device
*rdev
,
3144 union set_voltage args
;
3145 int index
= GetIndexIntoMasterTable(COMMAND
, SetVoltage
);
3148 if (!atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
))
3154 args
.v3
.ucVoltageType
= 0;
3155 args
.v3
.ucVoltageMode
= ATOM_GET_LEAKAGE_ID
;
3156 args
.v3
.usVoltageLevel
= 0;
3158 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
3160 *leakage_id
= le16_to_cpu(args
.v3
.usVoltageLevel
);
3163 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
3170 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device
*rdev
,
3171 u16
*vddc
, u16
*vddci
,
3172 u16 virtual_voltage_id
,
3173 u16 vbios_voltage_id
)
3175 int index
= GetIndexIntoMasterTable(DATA
, ASIC_ProfilingInfo
);
3177 u16 data_offset
, size
;
3179 ATOM_ASIC_PROFILING_INFO_V2_1
*profile
;
3180 u16
*leakage_bin
, *vddc_id_buf
, *vddc_buf
, *vddci_id_buf
, *vddci_buf
;
3185 if (!atom_parse_data_header(rdev
->mode_info
.atom_context
, index
, &size
,
3186 &frev
, &crev
, &data_offset
))
3189 profile
= (ATOM_ASIC_PROFILING_INFO_V2_1
*)
3190 (rdev
->mode_info
.atom_context
->bios
+ data_offset
);
3198 if (size
< sizeof(ATOM_ASIC_PROFILING_INFO_V2_1
))
3200 leakage_bin
= (u16
*)
3201 (rdev
->mode_info
.atom_context
->bios
+ data_offset
+
3202 le16_to_cpu(profile
->usLeakageBinArrayOffset
));
3203 vddc_id_buf
= (u16
*)
3204 (rdev
->mode_info
.atom_context
->bios
+ data_offset
+
3205 le16_to_cpu(profile
->usElbVDDC_IdArrayOffset
));
3207 (rdev
->mode_info
.atom_context
->bios
+ data_offset
+
3208 le16_to_cpu(profile
->usElbVDDC_LevelArrayOffset
));
3209 vddci_id_buf
= (u16
*)
3210 (rdev
->mode_info
.atom_context
->bios
+ data_offset
+
3211 le16_to_cpu(profile
->usElbVDDCI_IdArrayOffset
));
3213 (rdev
->mode_info
.atom_context
->bios
+ data_offset
+
3214 le16_to_cpu(profile
->usElbVDDCI_LevelArrayOffset
));
3216 if (profile
->ucElbVDDC_Num
> 0) {
3217 for (i
= 0; i
< profile
->ucElbVDDC_Num
; i
++) {
3218 if (vddc_id_buf
[i
] == virtual_voltage_id
) {
3219 for (j
= 0; j
< profile
->ucLeakageBinNum
; j
++) {
3220 if (vbios_voltage_id
<= leakage_bin
[j
]) {
3221 *vddc
= vddc_buf
[j
* profile
->ucElbVDDC_Num
+ i
];
3229 if (profile
->ucElbVDDCI_Num
> 0) {
3230 for (i
= 0; i
< profile
->ucElbVDDCI_Num
; i
++) {
3231 if (vddci_id_buf
[i
] == virtual_voltage_id
) {
3232 for (j
= 0; j
< profile
->ucLeakageBinNum
; j
++) {
3233 if (vbios_voltage_id
<= leakage_bin
[j
]) {
3234 *vddci
= vddci_buf
[j
* profile
->ucElbVDDCI_Num
+ i
];
3244 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
3249 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
3256 union get_voltage_info
{
3257 struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 in
;
3258 struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 evv_out
;
3261 int radeon_atom_get_voltage_evv(struct radeon_device
*rdev
,
3262 u16 virtual_voltage_id
,
3265 int index
= GetIndexIntoMasterTable(COMMAND
, GetVoltageInfo
);
3267 u32 count
= rdev
->pm
.dpm
.dyn_state
.vddc_dependency_on_sclk
.count
;
3268 union get_voltage_info args
;
3270 for (entry_id
= 0; entry_id
< count
; entry_id
++) {
3271 if (rdev
->pm
.dpm
.dyn_state
.vddc_dependency_on_sclk
.entries
[entry_id
].v
==
3276 if (entry_id
>= count
)
3279 args
.in
.ucVoltageType
= VOLTAGE_TYPE_VDDC
;
3280 args
.in
.ucVoltageMode
= ATOM_GET_VOLTAGE_EVV_VOLTAGE
;
3281 args
.in
.ulSCLKFreq
=
3282 cpu_to_le32(rdev
->pm
.dpm
.dyn_state
.vddc_dependency_on_sclk
.entries
[entry_id
].clk
);
3284 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
3286 *voltage
= le16_to_cpu(args
.evv_out
.usVoltageLevel
);
3291 int radeon_atom_get_voltage_gpio_settings(struct radeon_device
*rdev
,
3292 u16 voltage_level
, u8 voltage_type
,
3293 u32
*gpio_value
, u32
*gpio_mask
)
3295 union set_voltage args
;
3296 int index
= GetIndexIntoMasterTable(COMMAND
, SetVoltage
);
3299 if (!atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
))
3306 args
.v2
.ucVoltageType
= voltage_type
;
3307 args
.v2
.ucVoltageMode
= SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK
;
3308 args
.v2
.usVoltageLevel
= cpu_to_le16(voltage_level
);
3310 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
3312 *gpio_mask
= le32_to_cpu(*(u32
*)&args
.v2
);
3314 args
.v2
.ucVoltageType
= voltage_type
;
3315 args
.v2
.ucVoltageMode
= SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL
;
3316 args
.v2
.usVoltageLevel
= cpu_to_le16(voltage_level
);
3318 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
3320 *gpio_value
= le32_to_cpu(*(u32
*)&args
.v2
);
3323 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
3330 union voltage_object_info
{
3331 struct _ATOM_VOLTAGE_OBJECT_INFO v1
;
3332 struct _ATOM_VOLTAGE_OBJECT_INFO_V2 v2
;
3333 struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3
;
3336 union voltage_object
{
3337 struct _ATOM_VOLTAGE_OBJECT v1
;
3338 struct _ATOM_VOLTAGE_OBJECT_V2 v2
;
3339 union _ATOM_VOLTAGE_OBJECT_V3 v3
;
3342 static ATOM_VOLTAGE_OBJECT
*atom_lookup_voltage_object_v1(ATOM_VOLTAGE_OBJECT_INFO
*v1
,
3345 u32 size
= le16_to_cpu(v1
->sHeader
.usStructureSize
);
3346 u32 offset
= offsetof(ATOM_VOLTAGE_OBJECT_INFO
, asVoltageObj
[0]);
3347 u8
*start
= (u8
*)v1
;
3349 while (offset
< size
) {
3350 ATOM_VOLTAGE_OBJECT
*vo
= (ATOM_VOLTAGE_OBJECT
*)(start
+ offset
);
3351 if (vo
->ucVoltageType
== voltage_type
)
3353 offset
+= offsetof(ATOM_VOLTAGE_OBJECT
, asFormula
.ucVIDAdjustEntries
) +
3354 vo
->asFormula
.ucNumOfVoltageEntries
;
3359 static ATOM_VOLTAGE_OBJECT_V2
*atom_lookup_voltage_object_v2(ATOM_VOLTAGE_OBJECT_INFO_V2
*v2
,
3362 u32 size
= le16_to_cpu(v2
->sHeader
.usStructureSize
);
3363 u32 offset
= offsetof(ATOM_VOLTAGE_OBJECT_INFO_V2
, asVoltageObj
[0]);
3364 u8
*start
= (u8
*)v2
;
3366 while (offset
< size
) {
3367 ATOM_VOLTAGE_OBJECT_V2
*vo
= (ATOM_VOLTAGE_OBJECT_V2
*)(start
+ offset
);
3368 if (vo
->ucVoltageType
== voltage_type
)
3370 offset
+= offsetof(ATOM_VOLTAGE_OBJECT_V2
, asFormula
.asVIDAdjustEntries
) +
3371 (vo
->asFormula
.ucNumOfVoltageEntries
* sizeof(VOLTAGE_LUT_ENTRY
));
3376 static ATOM_VOLTAGE_OBJECT_V3
*atom_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1
*v3
,
3377 u8 voltage_type
, u8 voltage_mode
)
3379 u32 size
= le16_to_cpu(v3
->sHeader
.usStructureSize
);
3380 u32 offset
= offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1
, asVoltageObj
[0]);
3381 u8
*start
= (u8
*)v3
;
3383 while (offset
< size
) {
3384 ATOM_VOLTAGE_OBJECT_V3
*vo
= (ATOM_VOLTAGE_OBJECT_V3
*)(start
+ offset
);
3385 if ((vo
->asGpioVoltageObj
.sHeader
.ucVoltageType
== voltage_type
) &&
3386 (vo
->asGpioVoltageObj
.sHeader
.ucVoltageMode
== voltage_mode
))
3388 offset
+= le16_to_cpu(vo
->asGpioVoltageObj
.sHeader
.usSize
);
3394 radeon_atom_is_voltage_gpio(struct radeon_device
*rdev
,
3395 u8 voltage_type
, u8 voltage_mode
)
3397 int index
= GetIndexIntoMasterTable(DATA
, VoltageObjectInfo
);
3399 u16 data_offset
, size
;
3400 union voltage_object_info
*voltage_info
;
3401 union voltage_object
*voltage_object
= NULL
;
3403 if (atom_parse_data_header(rdev
->mode_info
.atom_context
, index
, &size
,
3404 &frev
, &crev
, &data_offset
)) {
3405 voltage_info
= (union voltage_object_info
*)
3406 ((uint8_t*)rdev
->mode_info
.atom_context
->bios
+ data_offset
);
3413 voltage_object
= (union voltage_object
*)
3414 atom_lookup_voltage_object_v1(&voltage_info
->v1
, voltage_type
);
3415 if (voltage_object
&&
3416 (voltage_object
->v1
.asControl
.ucVoltageControlId
== VOLTAGE_CONTROLLED_BY_GPIO
))
3420 voltage_object
= (union voltage_object
*)
3421 atom_lookup_voltage_object_v2(&voltage_info
->v2
, voltage_type
);
3422 if (voltage_object
&&
3423 (voltage_object
->v2
.asControl
.ucVoltageControlId
== VOLTAGE_CONTROLLED_BY_GPIO
))
3427 DRM_ERROR("unknown voltage object table\n");
3434 if (atom_lookup_voltage_object_v3(&voltage_info
->v3
,
3435 voltage_type
, voltage_mode
))
3439 DRM_ERROR("unknown voltage object table\n");
3444 DRM_ERROR("unknown voltage object table\n");
3452 int radeon_atom_get_svi2_info(struct radeon_device
*rdev
,
3454 u8
*svd_gpio_id
, u8
*svc_gpio_id
)
3456 int index
= GetIndexIntoMasterTable(DATA
, VoltageObjectInfo
);
3458 u16 data_offset
, size
;
3459 union voltage_object_info
*voltage_info
;
3460 union voltage_object
*voltage_object
= NULL
;
3462 if (atom_parse_data_header(rdev
->mode_info
.atom_context
, index
, &size
,
3463 &frev
, &crev
, &data_offset
)) {
3464 voltage_info
= (union voltage_object_info
*)
3465 ((uint8_t*)rdev
->mode_info
.atom_context
->bios
+ data_offset
);
3471 voltage_object
= (union voltage_object
*)
3472 atom_lookup_voltage_object_v3(&voltage_info
->v3
,
3475 if (voltage_object
) {
3476 *svd_gpio_id
= voltage_object
->v3
.asSVID2Obj
.ucSVDGpioId
;
3477 *svc_gpio_id
= voltage_object
->v3
.asSVID2Obj
.ucSVCGpioId
;
3483 DRM_ERROR("unknown voltage object table\n");
3488 DRM_ERROR("unknown voltage object table\n");
3496 int radeon_atom_get_max_voltage(struct radeon_device
*rdev
,
3497 u8 voltage_type
, u16
*max_voltage
)
3499 int index
= GetIndexIntoMasterTable(DATA
, VoltageObjectInfo
);
3501 u16 data_offset
, size
;
3502 union voltage_object_info
*voltage_info
;
3503 union voltage_object
*voltage_object
= NULL
;
3505 if (atom_parse_data_header(rdev
->mode_info
.atom_context
, index
, &size
,
3506 &frev
, &crev
, &data_offset
)) {
3507 voltage_info
= (union voltage_object_info
*)
3508 ((uint8_t*)rdev
->mode_info
.atom_context
->bios
+ data_offset
);
3512 voltage_object
= (union voltage_object
*)
3513 atom_lookup_voltage_object_v1(&voltage_info
->v1
, voltage_type
);
3514 if (voltage_object
) {
3515 ATOM_VOLTAGE_FORMULA
*formula
=
3516 &voltage_object
->v1
.asFormula
;
3517 if (formula
->ucFlag
& 1)
3519 le16_to_cpu(formula
->usVoltageBaseLevel
) +
3520 formula
->ucNumOfVoltageEntries
/ 2 *
3521 le16_to_cpu(formula
->usVoltageStep
);
3524 le16_to_cpu(formula
->usVoltageBaseLevel
) +
3525 (formula
->ucNumOfVoltageEntries
- 1) *
3526 le16_to_cpu(formula
->usVoltageStep
);
3531 voltage_object
= (union voltage_object
*)
3532 atom_lookup_voltage_object_v2(&voltage_info
->v2
, voltage_type
);
3533 if (voltage_object
) {
3534 ATOM_VOLTAGE_FORMULA_V2
*formula
=
3535 &voltage_object
->v2
.asFormula
;
3536 if (formula
->ucNumOfVoltageEntries
) {
3537 VOLTAGE_LUT_ENTRY
*lut
= (VOLTAGE_LUT_ENTRY
*)
3538 ((u8
*)&formula
->asVIDAdjustEntries
[0] +
3539 (sizeof(VOLTAGE_LUT_ENTRY
) * (formula
->ucNumOfVoltageEntries
- 1)));
3541 le16_to_cpu(lut
->usVoltageValue
);
3547 DRM_ERROR("unknown voltage object table\n");
3555 int radeon_atom_get_min_voltage(struct radeon_device
*rdev
,
3556 u8 voltage_type
, u16
*min_voltage
)
3558 int index
= GetIndexIntoMasterTable(DATA
, VoltageObjectInfo
);
3560 u16 data_offset
, size
;
3561 union voltage_object_info
*voltage_info
;
3562 union voltage_object
*voltage_object
= NULL
;
3564 if (atom_parse_data_header(rdev
->mode_info
.atom_context
, index
, &size
,
3565 &frev
, &crev
, &data_offset
)) {
3566 voltage_info
= (union voltage_object_info
*)
3567 ((uint8_t*)rdev
->mode_info
.atom_context
->bios
+ data_offset
);
3571 voltage_object
= (union voltage_object
*)
3572 atom_lookup_voltage_object_v1(&voltage_info
->v1
, voltage_type
);
3573 if (voltage_object
) {
3574 ATOM_VOLTAGE_FORMULA
*formula
=
3575 &voltage_object
->v1
.asFormula
;
3577 le16_to_cpu(formula
->usVoltageBaseLevel
);
3582 voltage_object
= (union voltage_object
*)
3583 atom_lookup_voltage_object_v2(&voltage_info
->v2
, voltage_type
);
3584 if (voltage_object
) {
3585 ATOM_VOLTAGE_FORMULA_V2
*formula
=
3586 &voltage_object
->v2
.asFormula
;
3587 if (formula
->ucNumOfVoltageEntries
) {
3589 le16_to_cpu(formula
->asVIDAdjustEntries
[
3597 DRM_ERROR("unknown voltage object table\n");
3605 int radeon_atom_get_voltage_step(struct radeon_device
*rdev
,
3606 u8 voltage_type
, u16
*voltage_step
)
3608 int index
= GetIndexIntoMasterTable(DATA
, VoltageObjectInfo
);
3610 u16 data_offset
, size
;
3611 union voltage_object_info
*voltage_info
;
3612 union voltage_object
*voltage_object
= NULL
;
3614 if (atom_parse_data_header(rdev
->mode_info
.atom_context
, index
, &size
,
3615 &frev
, &crev
, &data_offset
)) {
3616 voltage_info
= (union voltage_object_info
*)
3617 ((uint8_t*)rdev
->mode_info
.atom_context
->bios
+ data_offset
);
3621 voltage_object
= (union voltage_object
*)
3622 atom_lookup_voltage_object_v1(&voltage_info
->v1
, voltage_type
);
3623 if (voltage_object
) {
3624 ATOM_VOLTAGE_FORMULA
*formula
=
3625 &voltage_object
->v1
.asFormula
;
3626 if (formula
->ucFlag
& 1)
3628 (le16_to_cpu(formula
->usVoltageStep
) + 1) / 2;
3631 le16_to_cpu(formula
->usVoltageStep
);
3638 DRM_ERROR("unknown voltage object table\n");
3646 int radeon_atom_round_to_true_voltage(struct radeon_device
*rdev
,
3648 u16 nominal_voltage
,
3651 u16 min_voltage
, max_voltage
, voltage_step
;
3653 if (radeon_atom_get_max_voltage(rdev
, voltage_type
, &max_voltage
))
3655 if (radeon_atom_get_min_voltage(rdev
, voltage_type
, &min_voltage
))
3657 if (radeon_atom_get_voltage_step(rdev
, voltage_type
, &voltage_step
))
3660 if (nominal_voltage
<= min_voltage
)
3661 *true_voltage
= min_voltage
;
3662 else if (nominal_voltage
>= max_voltage
)
3663 *true_voltage
= max_voltage
;
3665 *true_voltage
= min_voltage
+
3666 ((nominal_voltage
- min_voltage
) / voltage_step
) *
3672 int radeon_atom_get_voltage_table(struct radeon_device
*rdev
,
3673 u8 voltage_type
, u8 voltage_mode
,
3674 struct atom_voltage_table
*voltage_table
)
3676 int index
= GetIndexIntoMasterTable(DATA
, VoltageObjectInfo
);
3678 u16 data_offset
, size
;
3680 union voltage_object_info
*voltage_info
;
3681 union voltage_object
*voltage_object
= NULL
;
3683 if (atom_parse_data_header(rdev
->mode_info
.atom_context
, index
, &size
,
3684 &frev
, &crev
, &data_offset
)) {
3685 voltage_info
= (union voltage_object_info
*)
3686 ((uint8_t*)rdev
->mode_info
.atom_context
->bios
+ data_offset
);
3693 DRM_ERROR("old table version %d, %d\n", frev
, crev
);
3696 voltage_object
= (union voltage_object
*)
3697 atom_lookup_voltage_object_v2(&voltage_info
->v2
, voltage_type
);
3698 if (voltage_object
) {
3699 ATOM_VOLTAGE_FORMULA_V2
*formula
=
3700 &voltage_object
->v2
.asFormula
;
3701 VOLTAGE_LUT_ENTRY
*lut
;
3702 if (formula
->ucNumOfVoltageEntries
> MAX_VOLTAGE_ENTRIES
)
3704 lut
= &formula
->asVIDAdjustEntries
[0];
3705 for (i
= 0; i
< formula
->ucNumOfVoltageEntries
; i
++) {
3706 voltage_table
->entries
[i
].value
=
3707 le16_to_cpu(lut
->usVoltageValue
);
3708 ret
= radeon_atom_get_voltage_gpio_settings(rdev
,
3709 voltage_table
->entries
[i
].value
,
3711 &voltage_table
->entries
[i
].smio_low
,
3712 &voltage_table
->mask_low
);
3715 lut
= (VOLTAGE_LUT_ENTRY
*)
3716 ((u8
*)lut
+ sizeof(VOLTAGE_LUT_ENTRY
));
3718 voltage_table
->count
= formula
->ucNumOfVoltageEntries
;
3723 DRM_ERROR("unknown voltage object table\n");
3730 voltage_object
= (union voltage_object
*)
3731 atom_lookup_voltage_object_v3(&voltage_info
->v3
,
3732 voltage_type
, voltage_mode
);
3733 if (voltage_object
) {
3734 ATOM_GPIO_VOLTAGE_OBJECT_V3
*gpio
=
3735 &voltage_object
->v3
.asGpioVoltageObj
;
3736 VOLTAGE_LUT_ENTRY_V2
*lut
;
3737 if (gpio
->ucGpioEntryNum
> MAX_VOLTAGE_ENTRIES
)
3739 lut
= &gpio
->asVolGpioLut
[0];
3740 for (i
= 0; i
< gpio
->ucGpioEntryNum
; i
++) {
3741 voltage_table
->entries
[i
].value
=
3742 le16_to_cpu(lut
->usVoltageValue
);
3743 voltage_table
->entries
[i
].smio_low
=
3744 le32_to_cpu(lut
->ulVoltageId
);
3745 lut
= (VOLTAGE_LUT_ENTRY_V2
*)
3746 ((u8
*)lut
+ sizeof(VOLTAGE_LUT_ENTRY_V2
));
3748 voltage_table
->mask_low
= le32_to_cpu(gpio
->ulGpioMaskVal
);
3749 voltage_table
->count
= gpio
->ucGpioEntryNum
;
3750 voltage_table
->phase_delay
= gpio
->ucPhaseDelay
;
3755 DRM_ERROR("unknown voltage object table\n");
3760 DRM_ERROR("unknown voltage object table\n");
3768 struct _ATOM_VRAM_INFO_V3 v1_3
;
3769 struct _ATOM_VRAM_INFO_V4 v1_4
;
3770 struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1
;
3773 int radeon_atom_get_memory_info(struct radeon_device
*rdev
,
3774 u8 module_index
, struct atom_memory_info
*mem_info
)
3776 int index
= GetIndexIntoMasterTable(DATA
, VRAM_Info
);
3778 u16 data_offset
, size
;
3779 union vram_info
*vram_info
;
3781 memset(mem_info
, 0, sizeof(struct atom_memory_info
));
3783 if (atom_parse_data_header(rdev
->mode_info
.atom_context
, index
, &size
,
3784 &frev
, &crev
, &data_offset
)) {
3785 vram_info
= (union vram_info
*)
3786 ((uint8_t*)rdev
->mode_info
.atom_context
->bios
+ data_offset
);
3792 if (module_index
< vram_info
->v1_3
.ucNumOfVRAMModule
) {
3793 ATOM_VRAM_MODULE_V3
*vram_module
=
3794 (ATOM_VRAM_MODULE_V3
*)vram_info
->v1_3
.aVramInfo
;
3796 for (i
= 0; i
< module_index
; i
++) {
3797 if (le16_to_cpu(vram_module
->usSize
) == 0)
3799 vram_module
= (ATOM_VRAM_MODULE_V3
*)
3800 ((u8
*)vram_module
+ le16_to_cpu(vram_module
->usSize
));
3802 mem_info
->mem_vendor
= vram_module
->asMemory
.ucMemoryVenderID
& 0xf;
3803 mem_info
->mem_type
= vram_module
->asMemory
.ucMemoryType
& 0xf0;
3808 /* r7xx, evergreen */
3809 if (module_index
< vram_info
->v1_4
.ucNumOfVRAMModule
) {
3810 ATOM_VRAM_MODULE_V4
*vram_module
=
3811 (ATOM_VRAM_MODULE_V4
*)vram_info
->v1_4
.aVramInfo
;
3813 for (i
= 0; i
< module_index
; i
++) {
3814 if (le16_to_cpu(vram_module
->usModuleSize
) == 0)
3816 vram_module
= (ATOM_VRAM_MODULE_V4
*)
3817 ((u8
*)vram_module
+ le16_to_cpu(vram_module
->usModuleSize
));
3819 mem_info
->mem_vendor
= vram_module
->ucMemoryVenderID
& 0xf;
3820 mem_info
->mem_type
= vram_module
->ucMemoryType
& 0xf0;
3825 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
3833 if (module_index
< vram_info
->v2_1
.ucNumOfVRAMModule
) {
3834 ATOM_VRAM_MODULE_V7
*vram_module
=
3835 (ATOM_VRAM_MODULE_V7
*)vram_info
->v2_1
.aVramInfo
;
3837 for (i
= 0; i
< module_index
; i
++) {
3838 if (le16_to_cpu(vram_module
->usModuleSize
) == 0)
3840 vram_module
= (ATOM_VRAM_MODULE_V7
*)
3841 ((u8
*)vram_module
+ le16_to_cpu(vram_module
->usModuleSize
));
3843 mem_info
->mem_vendor
= vram_module
->ucMemoryVenderID
& 0xf;
3844 mem_info
->mem_type
= vram_module
->ucMemoryType
& 0xf0;
3849 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
3854 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
3862 int radeon_atom_get_mclk_range_table(struct radeon_device
*rdev
,
3863 bool gddr5
, u8 module_index
,
3864 struct atom_memory_clock_range_table
*mclk_range_table
)
3866 int index
= GetIndexIntoMasterTable(DATA
, VRAM_Info
);
3868 u16 data_offset
, size
;
3869 union vram_info
*vram_info
;
3870 u32 mem_timing_size
= gddr5
?
3871 sizeof(ATOM_MEMORY_TIMING_FORMAT_V2
) : sizeof(ATOM_MEMORY_TIMING_FORMAT
);
3873 memset(mclk_range_table
, 0, sizeof(struct atom_memory_clock_range_table
));
3875 if (atom_parse_data_header(rdev
->mode_info
.atom_context
, index
, &size
,
3876 &frev
, &crev
, &data_offset
)) {
3877 vram_info
= (union vram_info
*)
3878 ((uint8_t*)rdev
->mode_info
.atom_context
->bios
+ data_offset
);
3883 DRM_ERROR("old table version %d, %d\n", frev
, crev
);
3886 /* r7xx, evergreen */
3887 if (module_index
< vram_info
->v1_4
.ucNumOfVRAMModule
) {
3888 ATOM_VRAM_MODULE_V4
*vram_module
=
3889 (ATOM_VRAM_MODULE_V4
*)vram_info
->v1_4
.aVramInfo
;
3890 ATOM_MEMORY_TIMING_FORMAT
*format
;
3892 for (i
= 0; i
< module_index
; i
++) {
3893 if (le16_to_cpu(vram_module
->usModuleSize
) == 0)
3895 vram_module
= (ATOM_VRAM_MODULE_V4
*)
3896 ((u8
*)vram_module
+ le16_to_cpu(vram_module
->usModuleSize
));
3898 mclk_range_table
->num_entries
= (u8
)
3899 ((le16_to_cpu(vram_module
->usModuleSize
) - offsetof(ATOM_VRAM_MODULE_V4
, asMemTiming
)) /
3901 format
= &vram_module
->asMemTiming
[0];
3902 for (i
= 0; i
< mclk_range_table
->num_entries
; i
++) {
3903 mclk_range_table
->mclk
[i
] = le32_to_cpu(format
->ulClkRange
);
3904 format
= (ATOM_MEMORY_TIMING_FORMAT
*)
3905 ((u8
*)format
+ mem_timing_size
);
3911 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
3916 DRM_ERROR("new table version %d, %d\n", frev
, crev
);
3919 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
3927 #define MEM_ID_MASK 0xff000000
3928 #define MEM_ID_SHIFT 24
3929 #define CLOCK_RANGE_MASK 0x00ffffff
3930 #define CLOCK_RANGE_SHIFT 0
3931 #define LOW_NIBBLE_MASK 0xf
3932 #define DATA_EQU_PREV 0
3933 #define DATA_FROM_TABLE 4
3935 int radeon_atom_init_mc_reg_table(struct radeon_device
*rdev
,
3937 struct atom_mc_reg_table
*reg_table
)
3939 int index
= GetIndexIntoMasterTable(DATA
, VRAM_Info
);
3940 u8 frev
, crev
, num_entries
, t_mem_id
, num_ranges
= 0;
3942 u16 data_offset
, size
;
3943 union vram_info
*vram_info
;
3945 memset(reg_table
, 0, sizeof(struct atom_mc_reg_table
));
3947 if (atom_parse_data_header(rdev
->mode_info
.atom_context
, index
, &size
,
3948 &frev
, &crev
, &data_offset
)) {
3949 vram_info
= (union vram_info
*)
3950 ((uint8_t*)rdev
->mode_info
.atom_context
->bios
+ data_offset
);
3953 DRM_ERROR("old table version %d, %d\n", frev
, crev
);
3958 if (module_index
< vram_info
->v2_1
.ucNumOfVRAMModule
) {
3959 ATOM_INIT_REG_BLOCK
*reg_block
=
3960 (ATOM_INIT_REG_BLOCK
*)
3961 ((u8
*)vram_info
+ le16_to_cpu(vram_info
->v2_1
.usMemClkPatchTblOffset
));
3962 ATOM_MEMORY_SETTING_DATA_BLOCK
*reg_data
=
3963 (ATOM_MEMORY_SETTING_DATA_BLOCK
*)
3964 ((u8
*)reg_block
+ (2 * sizeof(u16
)) +
3965 le16_to_cpu(reg_block
->usRegIndexTblSize
));
3966 ATOM_INIT_REG_INDEX_FORMAT
*format
= ®_block
->asRegIndexBuf
[0];
3967 num_entries
= (u8
)((le16_to_cpu(reg_block
->usRegIndexTblSize
)) /
3968 sizeof(ATOM_INIT_REG_INDEX_FORMAT
)) - 1;
3969 if (num_entries
> VBIOS_MC_REGISTER_ARRAY_SIZE
)
3971 while (i
< num_entries
) {
3972 if (format
->ucPreRegDataLength
& ACCESS_PLACEHOLDER
)
3974 reg_table
->mc_reg_address
[i
].s1
=
3975 (u16
)(le16_to_cpu(format
->usRegIndex
));
3976 reg_table
->mc_reg_address
[i
].pre_reg_data
=
3977 (u8
)(format
->ucPreRegDataLength
);
3979 format
= (ATOM_INIT_REG_INDEX_FORMAT
*)
3980 ((u8
*)format
+ sizeof(ATOM_INIT_REG_INDEX_FORMAT
));
3982 reg_table
->last
= i
;
3983 while ((le32_to_cpu(*(u32
*)reg_data
) != END_OF_REG_DATA_BLOCK
) &&
3984 (num_ranges
< VBIOS_MAX_AC_TIMING_ENTRIES
)) {
3985 t_mem_id
= (u8
)((le32_to_cpu(*(u32
*)reg_data
) & MEM_ID_MASK
)
3987 if (module_index
== t_mem_id
) {
3988 reg_table
->mc_reg_table_entry
[num_ranges
].mclk_max
=
3989 (u32
)((le32_to_cpu(*(u32
*)reg_data
) & CLOCK_RANGE_MASK
)
3990 >> CLOCK_RANGE_SHIFT
);
3991 for (i
= 0, j
= 1; i
< reg_table
->last
; i
++) {
3992 if ((reg_table
->mc_reg_address
[i
].pre_reg_data
& LOW_NIBBLE_MASK
) == DATA_FROM_TABLE
) {
3993 reg_table
->mc_reg_table_entry
[num_ranges
].mc_data
[i
] =
3994 (u32
)le32_to_cpu(*((u32
*)reg_data
+ j
));
3996 } else if ((reg_table
->mc_reg_address
[i
].pre_reg_data
& LOW_NIBBLE_MASK
) == DATA_EQU_PREV
) {
3997 reg_table
->mc_reg_table_entry
[num_ranges
].mc_data
[i
] =
3998 reg_table
->mc_reg_table_entry
[num_ranges
].mc_data
[i
- 1];
4003 reg_data
= (ATOM_MEMORY_SETTING_DATA_BLOCK
*)
4004 ((u8
*)reg_data
+ le16_to_cpu(reg_block
->usRegDataBlkSize
));
4006 if (le32_to_cpu(*(u32
*)reg_data
) != END_OF_REG_DATA_BLOCK
)
4008 reg_table
->num_entries
= num_ranges
;
4013 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
4018 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
4026 void radeon_atom_initialize_bios_scratch_regs(struct drm_device
*dev
)
4028 struct radeon_device
*rdev
= dev
->dev_private
;
4029 uint32_t bios_2_scratch
, bios_6_scratch
;
4031 if (rdev
->family
>= CHIP_R600
) {
4032 bios_2_scratch
= RREG32(R600_BIOS_2_SCRATCH
);
4033 bios_6_scratch
= RREG32(R600_BIOS_6_SCRATCH
);
4035 bios_2_scratch
= RREG32(RADEON_BIOS_2_SCRATCH
);
4036 bios_6_scratch
= RREG32(RADEON_BIOS_6_SCRATCH
);
4039 /* let the bios control the backlight */
4040 bios_2_scratch
&= ~ATOM_S2_VRI_BRIGHT_ENABLE
;
4042 /* tell the bios not to handle mode switching */
4043 bios_6_scratch
|= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH
;
4045 /* clear the vbios dpms state */
4046 if (ASIC_IS_DCE4(rdev
))
4047 bios_2_scratch
&= ~ATOM_S2_DEVICE_DPMS_STATE
;
4049 if (rdev
->family
>= CHIP_R600
) {
4050 WREG32(R600_BIOS_2_SCRATCH
, bios_2_scratch
);
4051 WREG32(R600_BIOS_6_SCRATCH
, bios_6_scratch
);
4053 WREG32(RADEON_BIOS_2_SCRATCH
, bios_2_scratch
);
4054 WREG32(RADEON_BIOS_6_SCRATCH
, bios_6_scratch
);
4059 void radeon_save_bios_scratch_regs(struct radeon_device
*rdev
)
4061 uint32_t scratch_reg
;
4064 if (rdev
->family
>= CHIP_R600
)
4065 scratch_reg
= R600_BIOS_0_SCRATCH
;
4067 scratch_reg
= RADEON_BIOS_0_SCRATCH
;
4069 for (i
= 0; i
< RADEON_BIOS_NUM_SCRATCH
; i
++)
4070 rdev
->bios_scratch
[i
] = RREG32(scratch_reg
+ (i
* 4));
4073 void radeon_restore_bios_scratch_regs(struct radeon_device
*rdev
)
4075 uint32_t scratch_reg
;
4078 if (rdev
->family
>= CHIP_R600
)
4079 scratch_reg
= R600_BIOS_0_SCRATCH
;
4081 scratch_reg
= RADEON_BIOS_0_SCRATCH
;
4083 for (i
= 0; i
< RADEON_BIOS_NUM_SCRATCH
; i
++)
4084 WREG32(scratch_reg
+ (i
* 4), rdev
->bios_scratch
[i
]);
4087 void radeon_atom_output_lock(struct drm_encoder
*encoder
, bool lock
)
4089 struct drm_device
*dev
= encoder
->dev
;
4090 struct radeon_device
*rdev
= dev
->dev_private
;
4091 uint32_t bios_6_scratch
;
4093 if (rdev
->family
>= CHIP_R600
)
4094 bios_6_scratch
= RREG32(R600_BIOS_6_SCRATCH
);
4096 bios_6_scratch
= RREG32(RADEON_BIOS_6_SCRATCH
);
4099 bios_6_scratch
|= ATOM_S6_CRITICAL_STATE
;
4100 bios_6_scratch
&= ~ATOM_S6_ACC_MODE
;
4102 bios_6_scratch
&= ~ATOM_S6_CRITICAL_STATE
;
4103 bios_6_scratch
|= ATOM_S6_ACC_MODE
;
4106 if (rdev
->family
>= CHIP_R600
)
4107 WREG32(R600_BIOS_6_SCRATCH
, bios_6_scratch
);
4109 WREG32(RADEON_BIOS_6_SCRATCH
, bios_6_scratch
);
4112 /* at some point we may want to break this out into individual functions */
4114 radeon_atombios_connected_scratch_regs(struct drm_connector
*connector
,
4115 struct drm_encoder
*encoder
,
4118 struct drm_device
*dev
= connector
->dev
;
4119 struct radeon_device
*rdev
= dev
->dev_private
;
4120 struct radeon_connector
*radeon_connector
=
4121 to_radeon_connector(connector
);
4122 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
4123 uint32_t bios_0_scratch
, bios_3_scratch
, bios_6_scratch
;
4125 if (rdev
->family
>= CHIP_R600
) {
4126 bios_0_scratch
= RREG32(R600_BIOS_0_SCRATCH
);
4127 bios_3_scratch
= RREG32(R600_BIOS_3_SCRATCH
);
4128 bios_6_scratch
= RREG32(R600_BIOS_6_SCRATCH
);
4130 bios_0_scratch
= RREG32(RADEON_BIOS_0_SCRATCH
);
4131 bios_3_scratch
= RREG32(RADEON_BIOS_3_SCRATCH
);
4132 bios_6_scratch
= RREG32(RADEON_BIOS_6_SCRATCH
);
4135 if ((radeon_encoder
->devices
& ATOM_DEVICE_TV1_SUPPORT
) &&
4136 (radeon_connector
->devices
& ATOM_DEVICE_TV1_SUPPORT
)) {
4138 DRM_DEBUG_KMS("TV1 connected\n");
4139 bios_3_scratch
|= ATOM_S3_TV1_ACTIVE
;
4140 bios_6_scratch
|= ATOM_S6_ACC_REQ_TV1
;
4142 DRM_DEBUG_KMS("TV1 disconnected\n");
4143 bios_0_scratch
&= ~ATOM_S0_TV1_MASK
;
4144 bios_3_scratch
&= ~ATOM_S3_TV1_ACTIVE
;
4145 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_TV1
;
4148 if ((radeon_encoder
->devices
& ATOM_DEVICE_CV_SUPPORT
) &&
4149 (radeon_connector
->devices
& ATOM_DEVICE_CV_SUPPORT
)) {
4151 DRM_DEBUG_KMS("CV connected\n");
4152 bios_3_scratch
|= ATOM_S3_CV_ACTIVE
;
4153 bios_6_scratch
|= ATOM_S6_ACC_REQ_CV
;
4155 DRM_DEBUG_KMS("CV disconnected\n");
4156 bios_0_scratch
&= ~ATOM_S0_CV_MASK
;
4157 bios_3_scratch
&= ~ATOM_S3_CV_ACTIVE
;
4158 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_CV
;
4161 if ((radeon_encoder
->devices
& ATOM_DEVICE_LCD1_SUPPORT
) &&
4162 (radeon_connector
->devices
& ATOM_DEVICE_LCD1_SUPPORT
)) {
4164 DRM_DEBUG_KMS("LCD1 connected\n");
4165 bios_0_scratch
|= ATOM_S0_LCD1
;
4166 bios_3_scratch
|= ATOM_S3_LCD1_ACTIVE
;
4167 bios_6_scratch
|= ATOM_S6_ACC_REQ_LCD1
;
4169 DRM_DEBUG_KMS("LCD1 disconnected\n");
4170 bios_0_scratch
&= ~ATOM_S0_LCD1
;
4171 bios_3_scratch
&= ~ATOM_S3_LCD1_ACTIVE
;
4172 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_LCD1
;
4175 if ((radeon_encoder
->devices
& ATOM_DEVICE_CRT1_SUPPORT
) &&
4176 (radeon_connector
->devices
& ATOM_DEVICE_CRT1_SUPPORT
)) {
4178 DRM_DEBUG_KMS("CRT1 connected\n");
4179 bios_0_scratch
|= ATOM_S0_CRT1_COLOR
;
4180 bios_3_scratch
|= ATOM_S3_CRT1_ACTIVE
;
4181 bios_6_scratch
|= ATOM_S6_ACC_REQ_CRT1
;
4183 DRM_DEBUG_KMS("CRT1 disconnected\n");
4184 bios_0_scratch
&= ~ATOM_S0_CRT1_MASK
;
4185 bios_3_scratch
&= ~ATOM_S3_CRT1_ACTIVE
;
4186 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_CRT1
;
4189 if ((radeon_encoder
->devices
& ATOM_DEVICE_CRT2_SUPPORT
) &&
4190 (radeon_connector
->devices
& ATOM_DEVICE_CRT2_SUPPORT
)) {
4192 DRM_DEBUG_KMS("CRT2 connected\n");
4193 bios_0_scratch
|= ATOM_S0_CRT2_COLOR
;
4194 bios_3_scratch
|= ATOM_S3_CRT2_ACTIVE
;
4195 bios_6_scratch
|= ATOM_S6_ACC_REQ_CRT2
;
4197 DRM_DEBUG_KMS("CRT2 disconnected\n");
4198 bios_0_scratch
&= ~ATOM_S0_CRT2_MASK
;
4199 bios_3_scratch
&= ~ATOM_S3_CRT2_ACTIVE
;
4200 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_CRT2
;
4203 if ((radeon_encoder
->devices
& ATOM_DEVICE_DFP1_SUPPORT
) &&
4204 (radeon_connector
->devices
& ATOM_DEVICE_DFP1_SUPPORT
)) {
4206 DRM_DEBUG_KMS("DFP1 connected\n");
4207 bios_0_scratch
|= ATOM_S0_DFP1
;
4208 bios_3_scratch
|= ATOM_S3_DFP1_ACTIVE
;
4209 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP1
;
4211 DRM_DEBUG_KMS("DFP1 disconnected\n");
4212 bios_0_scratch
&= ~ATOM_S0_DFP1
;
4213 bios_3_scratch
&= ~ATOM_S3_DFP1_ACTIVE
;
4214 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP1
;
4217 if ((radeon_encoder
->devices
& ATOM_DEVICE_DFP2_SUPPORT
) &&
4218 (radeon_connector
->devices
& ATOM_DEVICE_DFP2_SUPPORT
)) {
4220 DRM_DEBUG_KMS("DFP2 connected\n");
4221 bios_0_scratch
|= ATOM_S0_DFP2
;
4222 bios_3_scratch
|= ATOM_S3_DFP2_ACTIVE
;
4223 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP2
;
4225 DRM_DEBUG_KMS("DFP2 disconnected\n");
4226 bios_0_scratch
&= ~ATOM_S0_DFP2
;
4227 bios_3_scratch
&= ~ATOM_S3_DFP2_ACTIVE
;
4228 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP2
;
4231 if ((radeon_encoder
->devices
& ATOM_DEVICE_DFP3_SUPPORT
) &&
4232 (radeon_connector
->devices
& ATOM_DEVICE_DFP3_SUPPORT
)) {
4234 DRM_DEBUG_KMS("DFP3 connected\n");
4235 bios_0_scratch
|= ATOM_S0_DFP3
;
4236 bios_3_scratch
|= ATOM_S3_DFP3_ACTIVE
;
4237 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP3
;
4239 DRM_DEBUG_KMS("DFP3 disconnected\n");
4240 bios_0_scratch
&= ~ATOM_S0_DFP3
;
4241 bios_3_scratch
&= ~ATOM_S3_DFP3_ACTIVE
;
4242 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP3
;
4245 if ((radeon_encoder
->devices
& ATOM_DEVICE_DFP4_SUPPORT
) &&
4246 (radeon_connector
->devices
& ATOM_DEVICE_DFP4_SUPPORT
)) {
4248 DRM_DEBUG_KMS("DFP4 connected\n");
4249 bios_0_scratch
|= ATOM_S0_DFP4
;
4250 bios_3_scratch
|= ATOM_S3_DFP4_ACTIVE
;
4251 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP4
;
4253 DRM_DEBUG_KMS("DFP4 disconnected\n");
4254 bios_0_scratch
&= ~ATOM_S0_DFP4
;
4255 bios_3_scratch
&= ~ATOM_S3_DFP4_ACTIVE
;
4256 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP4
;
4259 if ((radeon_encoder
->devices
& ATOM_DEVICE_DFP5_SUPPORT
) &&
4260 (radeon_connector
->devices
& ATOM_DEVICE_DFP5_SUPPORT
)) {
4262 DRM_DEBUG_KMS("DFP5 connected\n");
4263 bios_0_scratch
|= ATOM_S0_DFP5
;
4264 bios_3_scratch
|= ATOM_S3_DFP5_ACTIVE
;
4265 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP5
;
4267 DRM_DEBUG_KMS("DFP5 disconnected\n");
4268 bios_0_scratch
&= ~ATOM_S0_DFP5
;
4269 bios_3_scratch
&= ~ATOM_S3_DFP5_ACTIVE
;
4270 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP5
;
4273 if ((radeon_encoder
->devices
& ATOM_DEVICE_DFP6_SUPPORT
) &&
4274 (radeon_connector
->devices
& ATOM_DEVICE_DFP6_SUPPORT
)) {
4276 DRM_DEBUG_KMS("DFP6 connected\n");
4277 bios_0_scratch
|= ATOM_S0_DFP6
;
4278 bios_3_scratch
|= ATOM_S3_DFP6_ACTIVE
;
4279 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP6
;
4281 DRM_DEBUG_KMS("DFP6 disconnected\n");
4282 bios_0_scratch
&= ~ATOM_S0_DFP6
;
4283 bios_3_scratch
&= ~ATOM_S3_DFP6_ACTIVE
;
4284 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP6
;
4288 if (rdev
->family
>= CHIP_R600
) {
4289 WREG32(R600_BIOS_0_SCRATCH
, bios_0_scratch
);
4290 WREG32(R600_BIOS_3_SCRATCH
, bios_3_scratch
);
4291 WREG32(R600_BIOS_6_SCRATCH
, bios_6_scratch
);
4293 WREG32(RADEON_BIOS_0_SCRATCH
, bios_0_scratch
);
4294 WREG32(RADEON_BIOS_3_SCRATCH
, bios_3_scratch
);
4295 WREG32(RADEON_BIOS_6_SCRATCH
, bios_6_scratch
);
4300 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder
*encoder
, int crtc
)
4302 struct drm_device
*dev
= encoder
->dev
;
4303 struct radeon_device
*rdev
= dev
->dev_private
;
4304 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
4305 uint32_t bios_3_scratch
;
4307 if (ASIC_IS_DCE4(rdev
))
4310 if (rdev
->family
>= CHIP_R600
)
4311 bios_3_scratch
= RREG32(R600_BIOS_3_SCRATCH
);
4313 bios_3_scratch
= RREG32(RADEON_BIOS_3_SCRATCH
);
4315 if (radeon_encoder
->devices
& ATOM_DEVICE_TV1_SUPPORT
) {
4316 bios_3_scratch
&= ~ATOM_S3_TV1_CRTC_ACTIVE
;
4317 bios_3_scratch
|= (crtc
<< 18);
4319 if (radeon_encoder
->devices
& ATOM_DEVICE_CV_SUPPORT
) {
4320 bios_3_scratch
&= ~ATOM_S3_CV_CRTC_ACTIVE
;
4321 bios_3_scratch
|= (crtc
<< 24);
4323 if (radeon_encoder
->devices
& ATOM_DEVICE_CRT1_SUPPORT
) {
4324 bios_3_scratch
&= ~ATOM_S3_CRT1_CRTC_ACTIVE
;
4325 bios_3_scratch
|= (crtc
<< 16);
4327 if (radeon_encoder
->devices
& ATOM_DEVICE_CRT2_SUPPORT
) {
4328 bios_3_scratch
&= ~ATOM_S3_CRT2_CRTC_ACTIVE
;
4329 bios_3_scratch
|= (crtc
<< 20);
4331 if (radeon_encoder
->devices
& ATOM_DEVICE_LCD1_SUPPORT
) {
4332 bios_3_scratch
&= ~ATOM_S3_LCD1_CRTC_ACTIVE
;
4333 bios_3_scratch
|= (crtc
<< 17);
4335 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP1_SUPPORT
) {
4336 bios_3_scratch
&= ~ATOM_S3_DFP1_CRTC_ACTIVE
;
4337 bios_3_scratch
|= (crtc
<< 19);
4339 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP2_SUPPORT
) {
4340 bios_3_scratch
&= ~ATOM_S3_DFP2_CRTC_ACTIVE
;
4341 bios_3_scratch
|= (crtc
<< 23);
4343 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP3_SUPPORT
) {
4344 bios_3_scratch
&= ~ATOM_S3_DFP3_CRTC_ACTIVE
;
4345 bios_3_scratch
|= (crtc
<< 25);
4348 if (rdev
->family
>= CHIP_R600
)
4349 WREG32(R600_BIOS_3_SCRATCH
, bios_3_scratch
);
4351 WREG32(RADEON_BIOS_3_SCRATCH
, bios_3_scratch
);
4355 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder
*encoder
, bool on
)
4357 struct drm_device
*dev
= encoder
->dev
;
4358 struct radeon_device
*rdev
= dev
->dev_private
;
4359 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
4360 uint32_t bios_2_scratch
;
4362 if (ASIC_IS_DCE4(rdev
))
4365 if (rdev
->family
>= CHIP_R600
)
4366 bios_2_scratch
= RREG32(R600_BIOS_2_SCRATCH
);
4368 bios_2_scratch
= RREG32(RADEON_BIOS_2_SCRATCH
);
4370 if (radeon_encoder
->devices
& ATOM_DEVICE_TV1_SUPPORT
) {
4372 bios_2_scratch
&= ~ATOM_S2_TV1_DPMS_STATE
;
4374 bios_2_scratch
|= ATOM_S2_TV1_DPMS_STATE
;
4376 if (radeon_encoder
->devices
& ATOM_DEVICE_CV_SUPPORT
) {
4378 bios_2_scratch
&= ~ATOM_S2_CV_DPMS_STATE
;
4380 bios_2_scratch
|= ATOM_S2_CV_DPMS_STATE
;
4382 if (radeon_encoder
->devices
& ATOM_DEVICE_CRT1_SUPPORT
) {
4384 bios_2_scratch
&= ~ATOM_S2_CRT1_DPMS_STATE
;
4386 bios_2_scratch
|= ATOM_S2_CRT1_DPMS_STATE
;
4388 if (radeon_encoder
->devices
& ATOM_DEVICE_CRT2_SUPPORT
) {
4390 bios_2_scratch
&= ~ATOM_S2_CRT2_DPMS_STATE
;
4392 bios_2_scratch
|= ATOM_S2_CRT2_DPMS_STATE
;
4394 if (radeon_encoder
->devices
& ATOM_DEVICE_LCD1_SUPPORT
) {
4396 bios_2_scratch
&= ~ATOM_S2_LCD1_DPMS_STATE
;
4398 bios_2_scratch
|= ATOM_S2_LCD1_DPMS_STATE
;
4400 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP1_SUPPORT
) {
4402 bios_2_scratch
&= ~ATOM_S2_DFP1_DPMS_STATE
;
4404 bios_2_scratch
|= ATOM_S2_DFP1_DPMS_STATE
;
4406 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP2_SUPPORT
) {
4408 bios_2_scratch
&= ~ATOM_S2_DFP2_DPMS_STATE
;
4410 bios_2_scratch
|= ATOM_S2_DFP2_DPMS_STATE
;
4412 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP3_SUPPORT
) {
4414 bios_2_scratch
&= ~ATOM_S2_DFP3_DPMS_STATE
;
4416 bios_2_scratch
|= ATOM_S2_DFP3_DPMS_STATE
;
4418 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP4_SUPPORT
) {
4420 bios_2_scratch
&= ~ATOM_S2_DFP4_DPMS_STATE
;
4422 bios_2_scratch
|= ATOM_S2_DFP4_DPMS_STATE
;
4424 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP5_SUPPORT
) {
4426 bios_2_scratch
&= ~ATOM_S2_DFP5_DPMS_STATE
;
4428 bios_2_scratch
|= ATOM_S2_DFP5_DPMS_STATE
;
4431 if (rdev
->family
>= CHIP_R600
)
4432 WREG32(R600_BIOS_2_SCRATCH
, bios_2_scratch
);
4434 WREG32(RADEON_BIOS_2_SCRATCH
, bios_2_scratch
);