2 * Copyright 2011 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Alex Deucher
25 #include <linux/firmware.h>
30 #include "radeon_ucode.h"
33 static int ci_set_smc_sram_address(struct radeon_device
*rdev
,
34 u32 smc_address
, u32 limit
)
38 if ((smc_address
+ 3) > limit
)
41 WREG32(SMC_IND_INDEX_0
, smc_address
);
42 WREG32_P(SMC_IND_ACCESS_CNTL
, 0, ~AUTO_INCREMENT_IND_0
);
47 int ci_copy_bytes_to_smc(struct radeon_device
*rdev
,
48 u32 smc_start_address
,
49 const u8
*src
, u32 byte_count
, u32 limit
)
51 u32 data
, original_data
;
56 if (smc_start_address
& 3)
58 if ((smc_start_address
+ byte_count
) > limit
)
61 addr
= smc_start_address
;
63 spin_lock(&rdev
->smc_idx_lock
);
64 while (byte_count
>= 4) {
65 /* SMC address space is BE */
66 data
= (src
[0] << 24) | (src
[1] << 16) | (src
[2] << 8) | src
[3];
68 ret
= ci_set_smc_sram_address(rdev
, addr
, limit
);
72 WREG32(SMC_IND_DATA_0
, data
);
79 /* RMW for the final bytes */
83 ret
= ci_set_smc_sram_address(rdev
, addr
, limit
);
87 original_data
= RREG32(SMC_IND_DATA_0
);
89 extra_shift
= 8 * (4 - byte_count
);
91 while (byte_count
> 0) {
92 data
= (data
<< 8) + *src
++;
98 data
|= (original_data
& ~((~0UL) << extra_shift
));
100 ret
= ci_set_smc_sram_address(rdev
, addr
, limit
);
104 WREG32(SMC_IND_DATA_0
, data
);
108 spin_unlock(&rdev
->smc_idx_lock
);
113 void ci_start_smc(struct radeon_device
*rdev
)
115 u32 tmp
= RREG32_SMC(SMC_SYSCON_RESET_CNTL
);
118 WREG32_SMC(SMC_SYSCON_RESET_CNTL
, tmp
);
121 void ci_reset_smc(struct radeon_device
*rdev
)
123 u32 tmp
= RREG32_SMC(SMC_SYSCON_RESET_CNTL
);
126 WREG32_SMC(SMC_SYSCON_RESET_CNTL
, tmp
);
129 int ci_program_jump_on_start(struct radeon_device
*rdev
)
131 static u8 data
[] = { 0xE0, 0x00, 0x80, 0x40 };
133 return ci_copy_bytes_to_smc(rdev
, 0x0, data
, 4, sizeof(data
)+1);
136 void ci_stop_smc_clock(struct radeon_device
*rdev
)
138 u32 tmp
= RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0
);
142 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0
, tmp
);
145 void ci_start_smc_clock(struct radeon_device
*rdev
)
147 u32 tmp
= RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0
);
151 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0
, tmp
);
154 bool ci_is_smc_running(struct radeon_device
*rdev
)
156 u32 clk
= RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0
);
157 u32 pc_c
= RREG32_SMC(SMC_PC_C
);
159 if (!(clk
& CK_DISABLE
) && (0x20100 <= pc_c
))
165 PPSMC_Result
ci_send_msg_to_smc(struct radeon_device
*rdev
, PPSMC_Msg msg
)
170 if (!ci_is_smc_running(rdev
))
171 return PPSMC_Result_Failed
;
173 WREG32(SMC_MESSAGE_0
, msg
);
175 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
176 tmp
= RREG32(SMC_RESP_0
);
181 tmp
= RREG32(SMC_RESP_0
);
183 return (PPSMC_Result
)tmp
;
187 PPSMC_Result
ci_wait_for_smc_inactive(struct radeon_device
*rdev
)
192 if (!ci_is_smc_running(rdev
))
193 return PPSMC_Result_OK
;
195 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
196 tmp
= RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0
);
197 if ((tmp
& CKEN
) == 0)
202 return PPSMC_Result_OK
;
206 int ci_load_smc_ucode(struct radeon_device
*rdev
, u32 limit
)
208 u32 ucode_start_address
;
217 const struct smc_firmware_header_v1_0
*hdr
=
218 (const struct smc_firmware_header_v1_0
*)rdev
->smc_fw
->data
;
220 radeon_ucode_print_smc_hdr(&hdr
->header
);
222 ucode_start_address
= le32_to_cpu(hdr
->ucode_start_addr
);
223 ucode_size
= le32_to_cpu(hdr
->header
.ucode_size_bytes
);
225 ((const char *)rdev
->smc_fw
->data
+ le32_to_cpu(hdr
->header
.ucode_array_offset_bytes
));
227 switch (rdev
->family
) {
229 ucode_start_address
= BONAIRE_SMC_UCODE_START
;
230 ucode_size
= BONAIRE_SMC_UCODE_SIZE
;
233 ucode_start_address
= HAWAII_SMC_UCODE_START
;
234 ucode_size
= HAWAII_SMC_UCODE_SIZE
;
237 DRM_ERROR("unknown asic in smc ucode loader\n");
241 src
= (const u8
*)rdev
->smc_fw
->data
;
247 spin_lock(&rdev
->smc_idx_lock
);
248 WREG32(SMC_IND_INDEX_0
, ucode_start_address
);
249 WREG32_P(SMC_IND_ACCESS_CNTL
, AUTO_INCREMENT_IND_0
, ~AUTO_INCREMENT_IND_0
);
250 while (ucode_size
>= 4) {
251 /* SMC address space is BE */
252 data
= (src
[0] << 24) | (src
[1] << 16) | (src
[2] << 8) | src
[3];
254 WREG32(SMC_IND_DATA_0
, data
);
259 WREG32_P(SMC_IND_ACCESS_CNTL
, 0, ~AUTO_INCREMENT_IND_0
);
260 spin_unlock(&rdev
->smc_idx_lock
);
265 int ci_read_smc_sram_dword(struct radeon_device
*rdev
,
266 u32 smc_address
, u32
*value
, u32 limit
)
270 spin_lock(&rdev
->smc_idx_lock
);
271 ret
= ci_set_smc_sram_address(rdev
, smc_address
, limit
);
273 *value
= RREG32(SMC_IND_DATA_0
);
274 spin_unlock(&rdev
->smc_idx_lock
);
279 int ci_write_smc_sram_dword(struct radeon_device
*rdev
,
280 u32 smc_address
, u32 value
, u32 limit
)
284 spin_lock(&rdev
->smc_idx_lock
);
285 ret
= ci_set_smc_sram_address(rdev
, smc_address
, limit
);
287 WREG32(SMC_IND_DATA_0
, value
);
288 spin_unlock(&rdev
->smc_idx_lock
);