sys/dev/netif/ath/hal/ath_hal/ah_desc.h

   1 /*
   2  * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
   3  * Copyright (c) 2002-2008 Atheros Communications, Inc.
   4  *
   5  * Permission to use, copy, modify, and/or distribute this software for any
   6  * purpose with or without fee is hereby granted, provided that the above
   7  * copyright notice and this permission notice appear in all copies.
   8  *
   9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16  *
  17  * $Id: ah_desc.h,v 1.5 2008/11/10 04:08:00 sam Exp $
  18  */
  19
  20 #ifndef _DEV_ATH_DESC_H
  21 #define _DEV_ATH_DESC_H
  22
  23 #include "opt_ah.h"             /* NB: required for AH_SUPPORT_AR5416 */
  24 #define AH_SUPPORT_AR5416 1     /* XXX has to be 1 to compile */
  25
  26 /*
  27  * Transmit descriptor status.  This structure is filled
  28  * in only after the tx descriptor process method finds a
  29  * ``done'' descriptor; at which point it returns something
  30  * other than HAL_EINPROGRESS.
  31  *
  32  * Note that ts_antenna may not be valid for all h/w.  It
  33  * should be used only if non-zero.
  34  */
  35 struct ath_tx_status {
  36         uint16_t        ts_seqnum;      /* h/w assigned sequence number */
  37         uint16_t        ts_tstamp;      /* h/w assigned timestamp */
  38         uint8_t         ts_status;      /* frame status, 0 => xmit ok */
  39         uint8_t         ts_rate;        /* h/w transmit rate index */
  40 #define HAL_TXSTAT_ALTRATE      0x80    /* alternate xmit rate used */
  41         int8_t          ts_rssi;        /* tx ack RSSI */
  42         uint8_t         ts_shortretry;  /* # short retries */
  43         uint8_t         ts_longretry;   /* # long retries */
  44         uint8_t         ts_virtcol;     /* virtual collision count */
  45         uint8_t         ts_antenna;     /* antenna information */
  46         uint8_t         ts_finaltsi;    /* final transmit series index */
  47 #ifdef AH_SUPPORT_AR5416
  48                                         /* 802.11n status */
  49         uint8_t         ts_flags;       /* misc flags */
  50         int8_t          ts_rssi_ctl[3]; /* tx ack RSSI [ctl, chain 0-2] */
  51         int8_t          ts_rssi_ext[3]; /* tx ack RSSI [ext, chain 0-2] */
  52 /* #define ts_rssi ts_rssi_combined */
  53         uint32_t        ts_ba_low;      /* blockack bitmap low */
  54         uint32_t        ts_ba_high;     /* blockack bitmap high */
  55         uint32_t        ts_evm0;        /* evm bytes */
  56         uint32_t        ts_evm1;
  57         uint32_t        ts_evm2;
  58 #endif /* AH_SUPPORT_AR5416 */
  59 };
  60
  61 /* bits found in ts_status */
  62 #define HAL_TXERR_XRETRY        0x01    /* excessive retries */
  63 #define HAL_TXERR_FILT          0x02    /* blocked by tx filtering */
  64 #define HAL_TXERR_FIFO          0x04    /* fifo underrun */
  65 #define HAL_TXERR_XTXOP         0x08    /* txop exceeded */
  66 #define HAL_TXERR_TIMER_EXPIRED 0x10    /* Tx timer expired */
  67
  68 /* bits found in ts_flags */
  69 #define HAL_TX_BA               0x01    /* Block Ack seen */
  70 #define HAL_TX_AGGR             0x02    /* Aggregate */
  71 #define HAL_TX_DESC_CFG_ERR     0x10    /* Error in 20/40 desc config */
  72 #define HAL_TX_DATA_UNDERRUN    0x20    /* Tx buffer underrun */
  73 #define HAL_TX_DELIM_UNDERRUN   0x40    /* Tx delimiter underrun */
  74
  75 /*
  76  * Receive descriptor status.  This structure is filled
  77  * in only after the rx descriptor process method finds a
  78  * ``done'' descriptor; at which point it returns something
  79  * other than HAL_EINPROGRESS.
  80  *
  81  * If rx_status is zero, then the frame was received ok;
  82  * otherwise the error information is indicated and rs_phyerr
  83  * contains a phy error code if HAL_RXERR_PHY is set.  In general
  84  * the frame contents is undefined when an error occurred thought
  85  * for some errors (e.g. a decryption error), it may be meaningful.
  86  *
  87  * Note that the receive timestamp is expanded using the TSF to
  88  * at least 15 bits (regardless of what the h/w provides directly).
  89  * Newer hardware supports a full 32-bits; use HAL_CAP_32TSTAMP to
  90  * find out if the hardware is capable.
  91  *
  92  * rx_rssi is in units of dbm above the noise floor.  This value
  93  * is measured during the preamble and PLCP; i.e. with the initial
  94  * 4us of detection.  The noise floor is typically a consistent
  95  * -96dBm absolute power in a 20MHz channel.
  96  */
  97 struct ath_rx_status {
  98         uint16_t        rs_datalen;     /* rx frame length */
  99         uint8_t         rs_status;      /* rx status, 0 => recv ok */
 100         uint8_t         rs_phyerr;      /* phy error code */
 101         int8_t          rs_rssi;        /* rx frame RSSI (combined for 11n) */
 102         uint8_t         rs_keyix;       /* key cache index */
 103         uint8_t         rs_rate;        /* h/w receive rate index */
 104         uint8_t         rs_more;        /* more descriptors follow */
 105         uint32_t        rs_tstamp;      /* h/w assigned timestamp */
 106         uint32_t        rs_antenna;     /* antenna information */
 107 #ifdef AH_SUPPORT_AR5416
 108                                         /* 802.11n status */
 109         int8_t          rs_rssi_ctl[3]; /* rx frame RSSI [ctl, chain 0-2] */
 110         int8_t          rs_rssi_ext[3]; /* rx frame RSSI [ext, chain 0-2] */
 111         uint8_t         rs_isaggr;      /* is part of the aggregate */
 112         uint8_t         rs_moreaggr;    /* more frames in aggr to follow */
 113         uint8_t         rs_num_delims;  /* number of delims in aggr */
 114         uint8_t         rs_flags;       /* misc flags */
 115         uint32_t        rs_evm0;        /* evm bytes */
 116         uint32_t        rs_evm1;
 117         uint32_t        rs_evm2;
 118 #endif /* AH_SUPPORT_AR5416 */
 119 };
 120
 121 /* bits found in rs_status */
 122 #define HAL_RXERR_CRC           0x01    /* CRC error on frame */
 123 #define HAL_RXERR_PHY           0x02    /* PHY error, rs_phyerr is valid */
 124 #define HAL_RXERR_FIFO          0x04    /* fifo overrun */
 125 #define HAL_RXERR_DECRYPT       0x08    /* non-Michael decrypt error */
 126 #define HAL_RXERR_MIC           0x10    /* Michael MIC decrypt error */
 127
 128 /* bits found in rs_flags */
 129 #define HAL_RX_MORE             0x01    /* more descriptors follow */
 130 #define HAL_RX_MORE_AGGR        0x02    /* more frames in aggr */
 131 #define HAL_RX_GI               0x04    /* full gi */
 132 #define HAL_RX_2040             0x08    /* 40 Mhz */
 133 #define HAL_RX_DELIM_CRC_PRE    0x10    /* crc error in delimiter pre */
 134 #define HAL_RX_DELIM_CRC_POST   0x20    /* crc error in delim after */
 135 #define HAL_RX_DECRYPT_BUSY     0x40    /* decrypt was too slow */
 136 #define HAL_RX_HI_RX_CHAIN      0x80    /* SM power save: hi Rx chain control */
 137
 138 enum {
 139         HAL_PHYERR_UNDERRUN             = 0,    /* Transmit underrun */
 140         HAL_PHYERR_TIMING               = 1,    /* Timing error */
 141         HAL_PHYERR_PARITY               = 2,    /* Illegal parity */
 142         HAL_PHYERR_RATE                 = 3,    /* Illegal rate */
 143         HAL_PHYERR_LENGTH               = 4,    /* Illegal length */
 144         HAL_PHYERR_RADAR                = 5,    /* Radar detect */
 145         HAL_PHYERR_SERVICE              = 6,    /* Illegal service */
 146         HAL_PHYERR_TOR                  = 7,    /* Transmit override receive */
 147         /* NB: these are specific to the 5212 */
 148         HAL_PHYERR_OFDM_TIMING          = 17,   /* */
 149         HAL_PHYERR_OFDM_SIGNAL_PARITY   = 18,   /* */
 150         HAL_PHYERR_OFDM_RATE_ILLEGAL    = 19,   /* */
 151         HAL_PHYERR_OFDM_LENGTH_ILLEGAL  = 20,   /* */
 152         HAL_PHYERR_OFDM_POWER_DROP      = 21,   /* */
 153         HAL_PHYERR_OFDM_SERVICE         = 22,   /* */
 154         HAL_PHYERR_OFDM_RESTART         = 23,   /* */
 155         HAL_PHYERR_CCK_TIMING           = 25,   /* */
 156         HAL_PHYERR_CCK_HEADER_CRC       = 26,   /* */
 157         HAL_PHYERR_CCK_RATE_ILLEGAL     = 27,   /* */
 158         HAL_PHYERR_CCK_SERVICE          = 30,   /* */
 159         HAL_PHYERR_CCK_RESTART          = 31,   /* */
 160 };
 161
 162 /* value found in rs_keyix to mark invalid entries */
 163 #define HAL_RXKEYIX_INVALID     ((uint8_t) -1)
 164 /* value used to specify no encryption key for xmit */
 165 #define HAL_TXKEYIX_INVALID     ((u_int) -1)
 166
 167 /* XXX rs_antenna definitions */
 168
 169 /*
 170  * Definitions for the software frame/packet descriptors used by
 171  * the Atheros HAL.  This definition obscures hardware-specific
 172  * details from the driver.  Drivers are expected to fillin the
 173  * portions of a descriptor that are not opaque then use HAL calls
 174  * to complete the work.  Status for completed frames is returned
 175  * in a device-independent format.
 176  */
 177 #ifdef AH_SUPPORT_AR5416
 178 #define HAL_DESC_HW_SIZE        20
 179 #else
 180 #define HAL_DESC_HW_SIZE        4
 181 #endif /* AH_SUPPORT_AR5416 */
 182
 183 struct ath_desc {
 184         /*
 185          * The following definitions are passed directly
 186          * the hardware and managed by the HAL.  Drivers
 187          * should not touch those elements marked opaque.
 188          */
 189         uint32_t        ds_link;        /* phys address of next descriptor */
 190         uint32_t        ds_data;        /* phys address of data buffer */
 191         uint32_t        ds_ctl0;        /* opaque DMA control 0 */
 192         uint32_t        ds_ctl1;        /* opaque DMA control 1 */
 193         uint32_t        ds_hw[HAL_DESC_HW_SIZE];        /* opaque h/w region */
 194 };
 195
 196 struct ath_desc_status {
 197         union {
 198                 struct ath_tx_status tx;/* xmit status */
 199                 struct ath_rx_status rx;/* recv status */
 200         } ds_us;
 201 };
 202
 203 #define ds_txstat       ds_us.tx
 204 #define ds_rxstat       ds_us.rx
 205
 206 /* flags passed to tx descriptor setup methods */
 207 #define HAL_TXDESC_CLRDMASK     0x0001  /* clear destination filter mask */
 208 #define HAL_TXDESC_NOACK        0x0002  /* don't wait for ACK */
 209 #define HAL_TXDESC_RTSENA       0x0004  /* enable RTS */
 210 #define HAL_TXDESC_CTSENA       0x0008  /* enable CTS */
 211 #define HAL_TXDESC_INTREQ       0x0010  /* enable per-descriptor interrupt */
 212 #define HAL_TXDESC_VEOL         0x0020  /* mark virtual EOL */
 213 /* NB: this only affects frame, not any RTS/CTS */
 214 #define HAL_TXDESC_DURENA       0x0040  /* enable h/w write of duration field */
 215 #define HAL_TXDESC_EXT_ONLY     0x0080  /* send on ext channel only (11n) */
 216 #define HAL_TXDESC_EXT_AND_CTL  0x0100  /* send on ext + ctl channels (11n) */
 217 #define HAL_TXDESC_VMF          0x0200  /* virtual more frag */
 218
 219 /* flags passed to rx descriptor setup methods */
 220 #define HAL_RXDESC_INTREQ       0x0020  /* enable per-descriptor interrupt */
 221 #endif /* _DEV_ATH_DESC_H */