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NFE - Change default RX ring size from 128 -> 256, Adjust moderation timer.
[dragonfly.git] / sys / dev / disk / ata / ata-pci.c
blob085805f68563e52ab77a5daf49158d711ccf155b
1 /*-
2 * Copyright (c) 1998,1999,2000,2001,2002 Søren Schmidt <sos@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * $FreeBSD: src/sys/dev/ata/ata-pci.c,v 1.32.2.15 2003/06/06 13:27:05 fjoe Exp $
29 * $DragonFly: src/sys/dev/disk/ata/ata-pci.c,v 1.29 2007/05/01 00:05:16 dillon Exp $
30 */
31
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/kernel.h>
35 #include <sys/disk.h>
36 #include <sys/module.h>
37 #include <sys/bus.h>
38 #include <sys/buf.h>
39 #include <sys/malloc.h>
40 #include <sys/devicestat.h>
41 #include <sys/sysctl.h>
42 #include <sys/rman.h>
43
44 #include <machine/stdarg.h>
45 #include <machine/clock.h>
46
47 #include <bus/pci/pcivar.h>
48 #include <bus/pci/pcireg.h>
49 #include "ata-all.h"
50
51 /* device structures */
52 struct ata_pci_controller {
53 struct resource *bmio;
54 int bmaddr;
55 struct resource *irq;
56 int irqcnt;
57 };
58
59 /* misc defines */
60 #define IOMASK 0xfffffffc
61 #define GRANDPARENT(dev) device_get_parent(device_get_parent(dev))
62 #define ATA_MASTERDEV(dev) ((pci_get_progif(dev) & 0x80) && \
63 (pci_get_progif(dev) & 0x05) != 0x05)
64
65 int
66 ata_find_dev(device_t dev, u_int32_t devid, u_int32_t revid)
67 {
68 device_t *children;
69 int nchildren, i;
70
71 if (device_get_children(device_get_parent(dev), &children, &nchildren))
72 return 0;
73
74 for (i = 0; i < nchildren; i++) {
75 if (pci_get_devid(children[i]) == devid &&
76 pci_get_revid(children[i]) >= revid) {
77 kfree(children, M_TEMP);
78 return 1;
79 }
80 }
81 kfree(children, M_TEMP);
82 return 0;
83 }
84
85 static void
86 ata_via_southbridge_fixup(device_t dev)
87 {
88 device_t *children;
89 int nchildren, i;
90
91 if (device_get_children(device_get_parent(dev), &children, &nchildren))
92 return;
93
94 for (i = 0; i < nchildren; i++) {
95 if (pci_get_devid(children[i]) == 0x03051106 || /* VIA VT8363 */
96 pci_get_devid(children[i]) == 0x03911106 || /* VIA VT8371 */
97 pci_get_devid(children[i]) == 0x31021106 || /* VIA VT8662 */
98 pci_get_devid(children[i]) == 0x31121106) { /* VIA VT8361 */
99 u_int8_t reg76 = pci_read_config(children[i], 0x76, 1);
100
101 if ((reg76 & 0xf0) != 0xd0) {
102 device_printf(dev,
103 "Correcting VIA config for southbridge data corruption bug\n");
104 pci_write_config(children[i], 0x75, 0x80, 1);
105 pci_write_config(children[i], 0x76, (reg76 & 0x0f) | 0xd0, 1);
106 }
107 break;
108 }
109 }
110 kfree(children, M_TEMP);
111 }
112
113 static const char *
114 ata_pci_match(device_t dev)
115 {
116 if (pci_get_class(dev) != PCIC_STORAGE)
117 return NULL;
118
119 switch (pci_get_devid(dev)) {
120 /* supported chipsets */
121 case 0x12308086:
122 return "Intel PIIX ATA controller";
123
124 case 0x70108086:
125 return "Intel PIIX3 ATA controller";
126
127 case 0x71118086:
128 case 0x71998086:
129 case 0x84ca8086:
130 return "Intel PIIX4 ATA33 controller";
131
132 case 0x24218086:
133 return "Intel ICH0 ATA33 controller";
134
135 case 0x24118086:
136 case 0x76018086:
137 return "Intel ICH ATA66 controller";
138
139 case 0x244a8086:
140 case 0x244b8086:
141 return "Intel ICH2 ATA100 controller";
142
143 case 0x248a8086:
144 case 0x248b8086:
145 return "Intel ICH3 ATA100 controller";
146
147 case 0x24ca8086:
148 case 0x24cb8086:
149 return "Intel ICH4 ATA100 controller";
150
151 case 0x24d18086:
152 return "Intel ICH5 SATA150 controller";
153
154 case 0x24db8086:
155 return "Intel ICH5 ATA100 controller";
156
157 case 0x269e8086:
158 case 0x26808086:
159 return "Intel ICH6 SATA300 controller";
160
161 case 0x26518086:
162 return "Intel ICH6/W SATA150 controller";
163
164 case 0x26528086:
165 return "Intel ICH6R/RW SATA150 controller";
166
167 case 0x26538086:
168 return "Intel ICH6M SATA150 controller";
169
170 case 0x266f8086:
171 return "Intel ICH6R/RW ATA100 controller";
172
173 case 0x27df8086:
174 return "Intel ICH7 ATA controller";
175
176 case 0x27c48086:
177 return "Intel ICH7M SATA controller";
178
179 case 0x522910b9:
180 if (pci_get_revid(dev) >= 0xc4)
181 return "AcerLabs Aladdin ATA100 controller";
182 else if (pci_get_revid(dev) >= 0xc2)
183 return "AcerLabs Aladdin ATA66 controller";
184 else if (pci_get_revid(dev) >= 0x20)
185 return "AcerLabs Aladdin ATA33 controller";
186 else
187 return "AcerLabs Aladdin ATA controller";
188
189 case 0x05711106:
190 if (ata_find_dev(dev, 0x05861106, 0x02))
191 return "VIA 82C586 ATA33 controller";
192 if (ata_find_dev(dev, 0x05861106, 0))
193 return "VIA 82C586 ATA controller";
194 if (ata_find_dev(dev, 0x05961106, 0x12))
195 return "VIA 82C596 ATA66 controller";
196 if (ata_find_dev(dev, 0x05961106, 0))
197 return "VIA 82C596 ATA33 controller";
198 if (ata_find_dev(dev, 0x06861106, 0x40))
199 return "VIA 82C686 ATA100 controller";
200 if (ata_find_dev(dev, 0x06861106, 0x10))
201 return "VIA 82C686 ATA66 controller";
202 if (ata_find_dev(dev, 0x06861106, 0))
203 return "VIA 82C686 ATA33 controller";
204 if (ata_find_dev(dev, 0x82311106, 0))
205 return "VIA 8231 ATA100 controller";
206 if (ata_find_dev(dev, 0x30741106, 0) ||
207 ata_find_dev(dev, 0x31091106, 0))
208 return "VIA 8233 ATA100 controller";
209 if (ata_find_dev(dev, 0x31471106, 0))
210 return "VIA 8233 ATA133 controller";
211 if (ata_find_dev(dev, 0x31771106, 0))
212 return "VIA 8235 ATA133 controller";
213 if (ata_find_dev(dev, 0x31491106, 0))
214 return "VIA 8237 ATA133 controller";
215 return "VIA Apollo ATA controller";
216
217 case 0x31491106:
218 return "VIA 8237 SATA 150 controller";
219
220 case 0x55131039:
221 if (ata_find_dev(dev, 0x07461039, 0))
222 return "SiS 5591 ATA133 controller";
223 if (ata_find_dev(dev, 0x06301039, 0x30) ||
224 ata_find_dev(dev, 0x06331039, 0) ||
225 ata_find_dev(dev, 0x06351039, 0) ||
226 ata_find_dev(dev, 0x06401039, 0) ||
227 ata_find_dev(dev, 0x06451039, 0) ||
228 ata_find_dev(dev, 0x06461039, 0) ||
229 ata_find_dev(dev, 0x06481039, 0) ||
230 ata_find_dev(dev, 0x06501039, 0) ||
231 ata_find_dev(dev, 0x07301039, 0) ||
232 ata_find_dev(dev, 0x07331039, 0) ||
233 ata_find_dev(dev, 0x07351039, 0) ||
234 ata_find_dev(dev, 0x07401039, 0) ||
235 ata_find_dev(dev, 0x07451039, 0) ||
236 ata_find_dev(dev, 0x07501039, 0))
237 return "SiS 5591 ATA100 controller";
238 else if (ata_find_dev(dev, 0x05301039, 0) ||
239 ata_find_dev(dev, 0x05401039, 0) ||
240 ata_find_dev(dev, 0x06201039, 0) ||
241 ata_find_dev(dev, 0x06301039, 0))
242 return "SiS 5591 ATA66 controller";
243 else
244 return "SiS 5591 ATA33 controller";
245
246 case 0x35121095:
247 return "SiI 3512 SATA controller";
248
249 case 0x31121095:
250 return "SiI 3112 SATA controller";
251
252 case 0x31141095:
253 return "SiI 3114 SATA controller";
254
255 case 0x31241095:
256 return "SiI 3124 SATA controller";
257
258 case 0x06801095:
259 return "SiI 0680 ATA133 controller";
260
261 case 0x06491095:
262 return "CMD 649 ATA100 controller";
263
264 case 0x06481095:
265 return "CMD 648 ATA66 controller";
266
267 case 0x06461095:
268 return "CMD 646 ATA controller";
269
270 case 0xc6931080:
271 if (pci_get_subclass(dev) == PCIS_STORAGE_IDE)
272 return "Cypress 82C693 ATA controller";
273 return NULL;
274
275 case 0x01021078:
276 return "Cyrix 5530 ATA33 controller";
277
278 case 0x74091022:
279 return "AMD 756 ATA66 controller";
280
281 case 0x74111022:
282 return "AMD 766 ATA100 controller";
283
284 case 0x74411022:
285 return "AMD 768 ATA100 controller";
286
287 case 0x74691022:
288 return "AMD 8111 UltraATA/133 controller";
289
290 case 0x01bc10de:
291 return "nVIDIA nForce1 ATA100 controller";
292
293 case 0x006510de:
294 return "nVIDIA nForce2 ATA133 controller";
295
296 case 0x00d510de:
297 return "nVIDIA nForce3 ATA133 controller";
298
299 case 0x00e310de:
300 return "nVIDIA nForce3 PRO S1 controller";
301
302 case 0x00e510de:
303 return "nVIDIA nForce3 PRO controller";
304
305 case 0x02111166:
306 return "ServerWorks ROSB4 ATA33 controller";
307
308 case 0x02121166:
309 if (pci_get_revid(dev) >= 0x92)
310 return "ServerWorks CSB5 ATA100 controller";
311 else
312 return "ServerWorks CSB5 ATA66 controller";
313
314 case 0x02131166:
315 return "ServerWorks CSB6 ATA100 controller (channel 0+1)";
316
317 case 0x02171166:
318 return "ServerWorks CSB6 ATA66 controller (channel 2)";
319
320 case 0x4d33105a:
321 return "Promise ATA33 controller";
322
323 case 0x0d38105a:
324 case 0x4d38105a:
325 return "Promise ATA66 controller";
326
327 case 0x0d30105a:
328 case 0x4d30105a:
329 return "Promise ATA100 controller";
330
331 case 0x4d68105a:
332 case 0x6268105a:
333 if (pci_get_devid(GRANDPARENT(dev)) == 0x00221011 &&
334 pci_get_class(GRANDPARENT(dev)) == PCIC_BRIDGE) {
335 static long start = 0, end = 0;
336
337 /* we belive we are on a TX4, now do our (simple) magic */
338 if (pci_get_slot(dev) == 1) {
339 bus_get_resource(dev, SYS_RES_IRQ, 0, &start, &end);
340 return "Promise TX4 ATA100 controller (channel 0+1)";
341 }
342 else if (pci_get_slot(dev) == 2 && start && end) {
343 bus_set_resource(dev, SYS_RES_IRQ, 0, start, end);
344 start = end = 0;
345 return "Promise TX4 ATA100 controller (channel 2+3)";
346 }
347 else
348 start = end = 0;
349 }
350 return "Promise TX2 ATA100 controller";
351
352 case 0x4d69105a:
353 case 0x5275105a:
354 case 0x6269105a:
355 case 0x7275105a:
356 return "Promise TX2 ATA133 controller";
357
358 case 0x00041103:
359 switch (pci_get_revid(dev)) {
360 case 0x00:
361 case 0x01:
362 return "HighPoint HPT366 ATA66 controller";
363 case 0x02:
364 return "HighPoint HPT368 ATA66 controller";
365 case 0x03:
366 case 0x04:
367 return "HighPoint HPT370 ATA100 controller";
368 case 0x05:
369 return "HighPoint HPT372 ATA133 controller";
370 }
371 return NULL;
372
373 case 0x00051103:
374 switch (pci_get_revid(dev)) {
375 case 0x01:
376 case 0x02:
377 return "HighPoint HPT372 ATA133 controller";
378 }
379 return NULL;
380
381 case 0x00081103:
382 switch (pci_get_revid(dev)) {
383 case 0x07:
384 return "HighPoint HPT374 ATA133 controller";
385 }
386 return NULL;
387
388 case 0x000116ca:
389 return "Cenatek Rocket Drive controller";
390
391 /* unsupported but known chipsets, generic DMA only */
392 case 0x10001042:
393 case 0x10011042:
394 return "RZ 100? ATA controller !WARNING! buggy chip data loss possible";
395
396 case 0x06401095:
397 return "CMD 640 ATA controller !WARNING! buggy chip data loss possible";
398
399 /* unknown chipsets, try generic DMA if it seems possible */
400 default:
401 if (pci_get_class(dev) == PCIC_STORAGE &&
402 (pci_get_subclass(dev) == PCIS_STORAGE_IDE))
403 return "Generic PCI ATA controller";
404 }
405 return NULL;
406 }
407
408 static int
409 ata_pci_probe(device_t dev)
410 {
411 const char *desc = ata_pci_match(dev);
412
413 if (desc) {
414 device_set_desc(dev, desc);
415 device_set_async_attach(dev, TRUE);
416 return 0;
417 } else {
418 return ENXIO;
419 }
420 }
421
422 static int
423 ata_pci_add_child(device_t dev, int unit)
424 {
425 device_t child;
426
427 /* check if this is located at one of the std addresses */
428 if (ATA_MASTERDEV(dev)) {
429 if (!(child = device_add_child(dev, "ata", unit)))
430 return ENOMEM;
431 }
432 else {
433 if (!(child = device_add_child(dev, "ata", 2)))
434 return ENOMEM;
435 }
436 return 0;
437 }
438
439 static int
440 ata_pci_attach(device_t dev)
441 {
442 struct ata_pci_controller *controller = device_get_softc(dev);
443 u_int8_t class, subclass;
444 u_int32_t type, cmd;
445 int rid;
446 int flags;
447
448 /* set up vendor-specific stuff */
449 type = pci_get_devid(dev);
450 class = pci_get_class(dev);
451 subclass = pci_get_subclass(dev);
452 cmd = pci_read_config(dev, PCIR_COMMAND, 4);
453
454 if (!(cmd & PCIM_CMD_PORTEN)) {
455 device_printf(dev, "ATA channel disabled by BIOS\n");
456 return 0;
457 }
458
459 /* is busmastering supported ? */
460 if ((cmd & (PCIM_CMD_PORTEN | PCIM_CMD_BUSMASTEREN)) ==
461 (PCIM_CMD_PORTEN | PCIM_CMD_BUSMASTEREN)) {
462
463 /* is there a valid port range to connect to ? */
464 rid = 0x20;
465 controller->bmio = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
466 0, ~0, 1, RF_ACTIVE);
467 if (!controller->bmio)
468 device_printf(dev, "Busmastering DMA not configured\n");
469 }
470 else
471 device_printf(dev, "Busmastering DMA not supported\n");
472
473 /* do extra chipset specific setups */
474 flags = 0;
475
476 switch (type) {
477 case 0x522910b9: /* Aladdin need to activate the ATAPI FIFO */
478 pci_write_config(dev, 0x53,
479 (pci_read_config(dev, 0x53, 1) & ~0x01) | 0x02, 1);
480 break;
481
482 case 0x4d38105a: /* Promise 66 & 100 (before TX2) need the clock changed */
483 case 0x4d30105a:
484 case 0x0d30105a:
485 ATA_OUTB(controller->bmio, 0x11, ATA_INB(controller->bmio, 0x11)|0x0a);
486 /* FALLTHROUGH */
487
488 case 0x4d33105a: /* Promise (before TX2) need burst mode turned on */
489 ATA_OUTB(controller->bmio, 0x1f, ATA_INB(controller->bmio, 0x1f)|0x01);
490 break;
491
492 case 0x00041103: /* HighPoint HPT366/368/370/372 */
493 if (pci_get_revid(dev) < 2) { /* HPT 366 */
494 /* turn off interrupt prediction */
495 pci_write_config(dev, 0x51,
496 (pci_read_config(dev, 0x51, 1) & ~0x80), 1);
497 break;
498 }
499 if (pci_get_revid(dev) < 5) { /* HPT368/370 */
500 /* turn off interrupt prediction */
501 pci_write_config(dev, 0x51,
502 (pci_read_config(dev, 0x51, 1) & ~0x03), 1);
503 pci_write_config(dev, 0x55,
504 (pci_read_config(dev, 0x55, 1) & ~0x03), 1);
505
506 /* turn on interrupts */
507 pci_write_config(dev, 0x5a,
508 (pci_read_config(dev, 0x5a, 1) & ~0x10), 1);
509
510 /* set clocks etc */
511 pci_write_config(dev, 0x5b, 0x22, 1);
512 break;
513 }
514 /* FALLTHROUGH */
515
516 case 0x00051103: /* HighPoint HPT372 */
517 case 0x00081103: /* HighPoint HPT374 */
518 /* turn off interrupt prediction */
519 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x03), 1);
520 pci_write_config(dev, 0x55, (pci_read_config(dev, 0x55, 1) & ~0x03), 1);
521
522 /* turn on interrupts */
523 pci_write_config(dev, 0x5a, (pci_read_config(dev, 0x5a, 1) & ~0x10), 1);
524
525 /* set clocks etc */
526 pci_write_config(dev, 0x5b,
527 (pci_read_config(dev, 0x5b, 1) & 0x01) | 0x20, 1);
528 break;
529
530 case 0x05711106: /* VIA 82C586, '596, '686 default setup */
531 /* prepare for ATA-66 on the 82C686a and 82C596b */
532 if ((ata_find_dev(dev, 0x06861106, 0x10) &&
533 !ata_find_dev(dev, 0x06861106, 0x40)) ||
534 ata_find_dev(dev, 0x05961106, 0x12))
535 pci_write_config(dev, 0x50, 0x030b030b, 4);
536
537 /* the southbridge might need the data corruption fix */
538 if (ata_find_dev(dev, 0x06861106, 0x40) ||
539 ata_find_dev(dev, 0x82311106, 0x10))
540 ata_via_southbridge_fixup(dev);
541
542 /* set fifo configuration half'n'half */
543 pci_write_config(dev, 0x43,
544 (pci_read_config(dev, 0x43, 1) & 0x90) | 0x2a, 1);
545
546 /* set status register read retry */
547 pci_write_config(dev, 0x44, pci_read_config(dev, 0x44, 1) | 0x08, 1);
548
549 /* set DMA read & end-of-sector fifo flush */
550 pci_write_config(dev, 0x46,
551 (pci_read_config(dev, 0x46, 1) & 0x0c) | 0xf0, 1);
552
553 /* set sector size */
554 pci_write_config(dev, 0x60, DEV_BSIZE, 2);
555 pci_write_config(dev, 0x68, DEV_BSIZE, 2);
556 break;
557 case 0x74111022: /* AMD 766 default setup */
558 flags = 1; /* bugged */
559 /* fall through */
560 case 0x74091022: /* AMD 756 default setup */
561 case 0x74411022: /* AMD 768 default setup */
562 case 0x746d1022: /* AMD 8111 default setup */
563 if (flags) {
564 pci_write_config(dev, 0x41,
565 pci_read_config(dev, 0x41, 1) & 0x0f, 1);
566 } else {
567 pci_write_config(dev, 0x41,
568 pci_read_config(dev, 0x41, 1) | 0xf0, 1);
569 }
570 break;
571 case 0x01bc10de: /* NVIDIA nForce1 default setup */
572 case 0x006510de: /* NVIDIA nForce2 default setup */
573 flags = 1;
574 /* fall through */
575 case 0x00d510de: /* NVIDIA nForce3 default setup */
576 if (flags) {
577 pci_write_config(dev, 0x51,
578 pci_read_config(dev, 0x51, 1) & 0x0f, 1);
579 } else {
580 pci_write_config(dev, 0x51,
581 pci_read_config(dev, 0x51, 1) | 0xf0, 1);
582 }
583 break;
584
585 case 0x02111166: /* ServerWorks ROSB4 enable UDMA33 */
586 pci_write_config(dev, 0x64,
587 (pci_read_config(dev, 0x64, 4) & ~0x00002000) |
588 0x00004000, 4);
589 break;
590
591 case 0x02121166: /* ServerWorks CSB5 enable UDMA66/100 depending on rev */
592 pci_write_config(dev, 0x5a,
593 (pci_read_config(dev, 0x5a, 1) & ~0x40) |
594 (pci_get_revid(dev) >= 0x92) ? 0x03 : 0x02, 1);
595 break;
596
597 case 0x06801095: /* SiI 0680 set ATA reference clock speed */
598 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
599 pci_write_config(dev, 0x8a,
600 (pci_read_config(dev, 0x8a, 1) & 0x0F) | 0x10, 1);
601 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
602 device_printf(dev, "SiI 0680 could not set clock\n");
603 break;
604
605 case 0x06491095:
606 case 0x06481095:
607 case 0x06461095: /* CMD 646 enable interrupts, set DMA read mode */
608 pci_write_config(dev, 0x71, 0x01, 1);
609 break;
610
611 case 0x10001042: /* RZ 100? known bad, no DMA */
612 case 0x10011042:
613 case 0x06401095: /* CMD 640 known bad, no DMA */
614 controller->bmio = NULL;
615 device_printf(dev, "Busmastering DMA disabled\n");
616 }
617
618 if (controller->bmio) {
619 controller->bmaddr = rman_get_start(controller->bmio);
620 BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
621 SYS_RES_IOPORT, rid, controller->bmio);
622 controller->bmio = NULL;
623 }
624
625 /*
626 * the Cypress chip is a mess, it contains two ATA functions, but
627 * both channels are visible on the first one.
628 * simply ignore the second function for now, as the right
629 * solution (ignoring the second channel on the first function)
630 * doesn't work with the crappy ATA interrupt setup on the alpha.
631 */
632 if (pci_get_devid(dev) == 0xc6931080 && pci_get_function(dev) > 1)
633 return 0;
634
635 ata_pci_add_child(dev, 0);
636
637 if (ATA_MASTERDEV(dev) || pci_read_config(dev, 0x18, 4) & IOMASK)
638 ata_pci_add_child(dev, 1);
639
640 return bus_generic_attach(dev);
641 }
642
643 static int
644 ata_pci_intr(struct ata_channel *ch)
645 {
646 u_int8_t dmastat;
647
648 /*
649 * since we might share the IRQ with another device, and in some
650 * cases with our twin channel, we only want to process interrupts
651 * that we know this channel generated.
652 */
653 switch (ch->chiptype) {
654 case 0x00041103: /* HighPoint HPT366/368/370/372 */
655 case 0x00051103: /* HighPoint HPT372 */
656 case 0x00081103: /* HighPoint HPT374 */
657 if (((dmastat = ata_dmastatus(ch)) &
658 (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) != ATA_BMSTAT_INTERRUPT)
659 return 1;
660 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, dmastat | ATA_BMSTAT_INTERRUPT);
661 DELAY(1);
662 return 0;
663
664 case 0x06481095: /* CMD 648 */
665 case 0x06491095: /* CMD 649 */
666 if (!(pci_read_config(device_get_parent(ch->dev), 0x71, 1) &
667 (ch->unit ? 0x08 : 0x04)))
668 return 1;
669 #if !defined(NO_ATANG)
670 pci_write_config(device_get_parent(ch->dev), 0x71,
671 pci_read_config(device_get_parent(ch->dev), 0x71, 1) &
672 ~(ch->unit ? 0x04 : 0x08), 1);
673 break;
674 #endif
675
676 case 0x06801095: /* SiI 680 */
677 if (!(pci_read_config(device_get_parent(ch->dev),
678 (ch->unit ? 0xb1 : 0xa1), 1) & 0x08))
679 return 1;
680 break;
681
682 case 0x4d33105a: /* Promise Ultra/Fasttrak 33 */
683 case 0x0d38105a: /* Promise Fasttrak 66 */
684 case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */
685 case 0x0d30105a: /* Promise OEM ATA100 */
686 case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */
687 if (!(ATA_INL(ch->r_bmio, (ch->unit ? 0x14 : 0x1c)) &
688 (ch->unit ? 0x00004000 : 0x00000400)))
689 return 1;
690 break;
691
692 case 0x4d68105a: /* Promise TX2 ATA100 */
693 case 0x6268105a: /* Promise TX2 ATA100 */
694 case 0x4d69105a: /* Promise TX2 ATA133 */
695 case 0x5275105a: /* Promise TX2 ATA133 */
696 case 0x6269105a: /* Promise TX2 ATA133 */
697 case 0x7275105a: /* Promise TX2 ATA133 */
698 ATA_OUTB(ch->r_bmio, ATA_BMDEVSPEC_0, 0x0b);
699 if (!(ATA_INB(ch->r_bmio, ATA_BMDEVSPEC_1) & 0x20))
700 return 1;
701 break;
702
703 case 0x24d18086: /* Intel ICH5 SATA150 */
704 case 0x24db8086: /* Intel ICH5 ATA100 */
705 case 0x26518086: /* Intel ICH6 SATA150 */
706 case 0x26528086: /* Intel ICH6R SATA150 */
707 case 0x26808086: /* Intel ICH6R SATA150 */
708 case 0x260e8086: /* Intel ICH6 SATA300 */
709 dmastat = ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT);
710 if ((dmastat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
711 ATA_BMSTAT_INTERRUPT)
712 return 1;
713 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, dmastat &
714 ~(ATA_BMSTAT_DMA_SIMPLEX | ATA_BMSTAT_ERROR));
715 DELAY(1);
716 return 0;
717
718 }
719
720 if (ch->flags & ATA_DMA_ACTIVE) {
721 if (!((dmastat = ata_dmastatus(ch)) & ATA_BMSTAT_INTERRUPT))
722 return 1;
723 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, dmastat | ATA_BMSTAT_INTERRUPT);
724 DELAY(1);
725 }
726 return 0;
727 }
728
729 static int
730 ata_pci_print_child(device_t dev, device_t child)
731 {
732 struct ata_channel *ch = device_get_softc(child);
733 int retval = 0;
734
735 retval += bus_print_child_header(dev, child);
736 retval += kprintf(": at 0x%lx", rman_get_start(ch->r_io));
737
738 if (ATA_MASTERDEV(dev))
739 retval += kprintf(" irq %d", 14 + ch->unit);
740
741 retval += bus_print_child_footer(dev, child);
742
743 return retval;
744 }
745
746 static struct resource *
747 ata_pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
748 u_long start, u_long end, u_long count, u_int flags)
749 {
750 struct ata_pci_controller *controller = device_get_softc(dev);
751 struct resource *res = NULL;
752 int unit = ((struct ata_channel *)device_get_softc(child))->unit;
753 int myrid;
754
755 if (type == SYS_RES_IOPORT) {
756 switch (*rid) {
757 case ATA_IOADDR_RID:
758 if (ATA_MASTERDEV(dev)) {
759 myrid = 0;
760 start = (unit ? ATA_SECONDARY : ATA_PRIMARY);
761 end = start + ATA_IOSIZE - 1;
762 count = ATA_IOSIZE;
763 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
764 SYS_RES_IOPORT, &myrid,
765 start, end, count, flags);
766 }
767 else {
768 myrid = 0x10 + 8 * unit;
769 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
770 SYS_RES_IOPORT, &myrid,
771 start, end, count, flags);
772 }
773 break;
774
775 case ATA_ALTADDR_RID:
776 if (ATA_MASTERDEV(dev)) {
777 myrid = 0;
778 start = (unit ? ATA_SECONDARY : ATA_PRIMARY) + ATA_ALTOFFSET;
779 end = start + ATA_ALTIOSIZE - 1;
780 count = ATA_ALTIOSIZE;
781 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
782 SYS_RES_IOPORT, &myrid,
783 start, end, count, flags);
784 }
785 else {
786 myrid = 0x14 + 8 * unit;
787 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
788 SYS_RES_IOPORT, &myrid,
789 start, end, count, flags);
790 if (res) {
791 start = rman_get_start(res) + 2;
792 end = start + ATA_ALTIOSIZE - 1;
793 count = ATA_ALTIOSIZE;
794 BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
795 SYS_RES_IOPORT, myrid, res);
796 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
797 SYS_RES_IOPORT, &myrid,
798 start, end, count, flags);
799 }
800 }
801 break;
802
803 case ATA_BMADDR_RID:
804 if (controller->bmaddr) {
805 myrid = 0x20;
806 start = (unit == 0 ?
807 controller->bmaddr : controller->bmaddr+ATA_BMIOSIZE);
808 end = start + ATA_BMIOSIZE - 1;
809 count = ATA_BMIOSIZE;
810 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
811 SYS_RES_IOPORT, &myrid,
812 start, end, count, flags);
813 }
814 }
815 return res;
816 }
817
818 if (type == SYS_RES_IRQ && *rid == ATA_IRQ_RID) {
819 if (ATA_MASTERDEV(dev)) {
820 int irq = (unit == 0 ? 14 : 15);
821
822 return BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
823 SYS_RES_IRQ, rid, irq, irq, 1, flags);
824 }
825 else {
826 /* primary and secondary channels share interrupt, keep track */
827 if (!controller->irq)
828 controller->irq = BUS_ALLOC_RESOURCE(device_get_parent(dev),
829 dev, SYS_RES_IRQ,
830 rid, 0, ~0, 1, flags);
831 controller->irqcnt++;
832 return controller->irq;
833 }
834 }
835 return 0;
836 }
837
838 static int
839 ata_pci_release_resource(device_t dev, device_t child, int type, int rid,
840 struct resource *r)
841 {
842 struct ata_pci_controller *controller = device_get_softc(dev);
843 int unit = ((struct ata_channel *)device_get_softc(child))->unit;
844
845 if (type == SYS_RES_IOPORT) {
846 switch (rid) {
847 case ATA_IOADDR_RID:
848 if (ATA_MASTERDEV(dev))
849 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
850 SYS_RES_IOPORT, 0x0, r);
851 else
852 return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
853 SYS_RES_IOPORT, 0x10 + 8 * unit, r);
854 break;
855
856 case ATA_ALTADDR_RID:
857 if (ATA_MASTERDEV(dev))
858 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
859 SYS_RES_IOPORT, 0x0, r);
860 else
861 return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
862 SYS_RES_IOPORT, 0x14 + 8 * unit, r);
863 break;
864
865 case ATA_BMADDR_RID:
866 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
867 SYS_RES_IOPORT, 0x20, r);
868 default:
869 return ENOENT;
870 }
871 }
872 if (type == SYS_RES_IRQ) {
873 if (rid != ATA_IRQ_RID)
874 return ENOENT;
875
876 if (ATA_MASTERDEV(dev)) {
877 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
878 SYS_RES_IRQ, rid, r);
879 }
880 else {
881 /* primary and secondary channels share interrupt, keep track */
882 if (--controller->irqcnt)
883 return 0;
884 controller->irq = NULL;
885 return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
886 SYS_RES_IRQ, rid, r);
887 }
888 }
889 return EINVAL;
890 }
891
892 static int
893 ata_pci_setup_intr(device_t dev, device_t child, struct resource *irq,
894 int flags, driver_intr_t *intr, void *arg,
895 void **cookiep, lwkt_serialize_t serializer)
896 {
897 if (ATA_MASTERDEV(dev)) {
898 return BUS_SETUP_INTR(device_get_parent(dev), child, irq,
899 flags, intr, arg, cookiep, serializer);
900 }
901 else
902 return BUS_SETUP_INTR(device_get_parent(dev), dev, irq,
903 flags, intr, arg, cookiep, serializer);
904 }
905
906 static int
907 ata_pci_teardown_intr(device_t dev, device_t child, struct resource *irq,
908 void *cookie)
909 {
910 if (ATA_MASTERDEV(dev)) {
911 return BUS_TEARDOWN_INTR(device_get_parent(dev), child, irq, cookie);
912 }
913 else
914 return BUS_TEARDOWN_INTR(device_get_parent(dev), dev, irq, cookie);
915 }
916
917 static device_method_t ata_pci_methods[] = {
918 /* device interface */
919 DEVMETHOD(device_probe, ata_pci_probe),
920 DEVMETHOD(device_attach, ata_pci_attach),
921 DEVMETHOD(device_shutdown, bus_generic_shutdown),
922 DEVMETHOD(device_suspend, bus_generic_suspend),
923 DEVMETHOD(device_resume, bus_generic_resume),
924
925 /* bus methods */
926 DEVMETHOD(bus_print_child, ata_pci_print_child),
927 DEVMETHOD(bus_alloc_resource, ata_pci_alloc_resource),
928 DEVMETHOD(bus_release_resource, ata_pci_release_resource),
929 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
930 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
931 DEVMETHOD(bus_setup_intr, ata_pci_setup_intr),
932 DEVMETHOD(bus_teardown_intr, ata_pci_teardown_intr),
933 { 0, 0 }
934 };
935
936 static driver_t ata_pci_driver = {
937 "atapci",
938 ata_pci_methods,
939 sizeof(struct ata_pci_controller),
940 };
941
942 static devclass_t ata_pci_devclass;
943
944 DRIVER_MODULE(atapci, pci, ata_pci_driver, ata_pci_devclass, 0, 0);
945
946 static int
947 ata_pcisub_probe(device_t dev)
948 {
949 struct ata_channel *ch = device_get_softc(dev);
950 device_t *children;
951 int count, i;
952
953 /* find channel number on this controller */
954 device_get_children(device_get_parent(dev), &children, &count);
955 for (i = 0; i < count; i++) {
956 if (children[i] == dev)
957 ch->unit = i;
958 }
959 kfree(children, M_TEMP);
960 ch->chiptype = pci_get_devid(device_get_parent(dev));
961 ch->intr_func = ata_pci_intr;
962 return ata_probe(dev);
963 }
964
965 static device_method_t ata_pcisub_methods[] = {
966 /* device interface */
967 DEVMETHOD(device_probe, ata_pcisub_probe),
968 DEVMETHOD(device_attach, ata_attach),
969 DEVMETHOD(device_detach, ata_detach),
970 DEVMETHOD(device_resume, ata_resume),
971 DEVMETHOD(device_suspend, ata_suspend),
972 { 0, 0 }
973 };
974
975 static driver_t ata_pcisub_driver = {
976 "ata",
977 ata_pcisub_methods,
978 sizeof(struct ata_channel),
979 };
980
981 DRIVER_MODULE(ata, atapci, ata_pcisub_driver, ata_devclass, 0, 0);
DragonFly BSD