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NFE - Change default RX ring size from 128 -> 256, Adjust moderation timer.
[dragonfly.git] / sys / dev / disk / ata / ata-dma.c
blob8c5e453939bc8f799c0f74d6316bd3c691e88e9c
1 /*-
2 * Copyright (c) 1998,1999,2000,2001,2002 Søren Schmidt <sos@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * $FreeBSD: src/sys/dev/ata/ata-dma.c,v 1.35.2.31 2003/05/07 16:46:11 jhb Exp $
29 * $DragonFly: src/sys/dev/disk/ata/ata-dma.c,v 1.31 2006/12/12 19:01:31 dillon Exp $
30 */
31
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/ata.h>
35 #include <sys/buf.h>
36 #include <sys/malloc.h>
37 #include <sys/mpipe.h>
38 #include <sys/bus.h>
39 #include <sys/disk.h>
40 #include <sys/devicestat.h>
41 #include <sys/rman.h>
42
43 #include <vm/vm.h>
44 #include <vm/pmap.h>
45
46 #include <bus/pci/pcivar.h>
47 #include "ata-all.h"
48
49 /* prototypes */
50 static void cyrix_timing(struct ata_device *, int, int);
51 static void promise_timing(struct ata_device *, int, int);
52 static void hpt_timing(struct ata_device *, int, int);
53 static int hpt_cable80(struct ata_device *);
54
55 /* misc defines */
56 #define ATAPI_DEVICE(atadev) \
57 ((atadev->unit == ATA_MASTER && \
58 atadev->channel->devices & ATA_ATAPI_MASTER) || \
59 (atadev->unit == ATA_SLAVE && \
60 atadev->channel->devices & ATA_ATAPI_SLAVE))
61
62 int ata_dma_debug = 0;
63
64 int
65 ata_dmaalloc(struct ata_device *atadev, int flags)
66 {
67 struct ata_channel *ch = atadev->channel;
68
69 if (atadev->dmastate.dmatab != NULL)
70 return(0);
71
72 KKASSERT(ch->dma_mpipe.max_count != 0);
73 if (flags & M_RNOWAIT)
74 atadev->dmastate.dmatab = mpipe_alloc_nowait(&ch->dma_mpipe);
75 else
76 atadev->dmastate.dmatab = mpipe_alloc_waitok(&ch->dma_mpipe);
77
78 if (atadev->dmastate.dmatab != NULL) {
79 KKASSERT(((uintptr_t)atadev->dmastate.dmatab & PAGE_MASK) == 0);
80 return(0);
81 }
82 return(ENOBUFS);
83 }
84
85 void
86 ata_dmafree(struct ata_device *atadev)
87 {
88 struct ata_channel *ch = atadev->channel;
89
90 if (atadev->dmastate.dmatab) {
91 mpipe_free(&ch->dma_mpipe, atadev->dmastate.dmatab);
92 atadev->dmastate.dmatab = NULL;
93 }
94 }
95
96 void
97 ata_dmafreetags(struct ata_channel *ch)
98 {
99 }
100
101 static void
102 ata_dmacreate(struct ata_device *atadev, int apiomode, int mode)
103 {
104 atadev->mode = mode;
105 }
106
107 void
108 ata_dmainit(struct ata_device *atadev, int apiomode, int wdmamode, int udmamode)
109 {
110 device_t parent = device_get_parent(atadev->channel->dev);
111 int chiptype = atadev->channel->chiptype;
112 int chiprev = pci_get_revid(parent);
113 int channel = atadev->channel->unit;
114 int device = ATA_DEV(atadev->unit);
115 int devno = (channel << 1) + device;
116 int error;
117
118 /* set our most pessimistic default mode */
119 atadev->mode = ATA_PIO;
120
121 if (!atadev->channel->r_bmio)
122 return;
123
124 /* if simplex controller, only allow DMA on primary channel */
125 if (channel == 1) {
126 ATA_OUTB(atadev->channel->r_bmio, ATA_BMSTAT_PORT,
127 ATA_INB(atadev->channel->r_bmio, ATA_BMSTAT_PORT) &
128 (ATA_BMSTAT_DMA_MASTER | ATA_BMSTAT_DMA_SLAVE));
129 if (ATA_INB(atadev->channel->r_bmio, ATA_BMSTAT_PORT) &
130 ATA_BMSTAT_DMA_SIMPLEX) {
131 ata_prtdev(atadev, "simplex device, DMA on primary only\n");
132 return;
133 }
134 }
135
136 /* DMA engine address alignment is usually 1 word (2 bytes) */
137 atadev->channel->alignment = 0x1;
138
139 #if 1
140 if (udmamode > 2 && !atadev->param->hwres_cblid) {
141 ata_prtdev(atadev,"DMA limited to UDMA33, non-ATA66 cable or device\n");
142 udmamode = 2;
143 }
144 #endif
145 switch (chiptype) {
146
147 case 0x27df8086: /* Intel ICH7 ATA */
148 case 0x27c48086: /* Intel ICH7M SATA */
149 case 0x269e8086: /* Intel ICH6 SATA */
150 case 0x26808086: /* Intel ICH6 SATA */
151 case 0x266f8086: /* Intel ICH6 ATA */
152 case 0x26528086: /* Intel ICH6R/RW SATA */
153 case 0x26538086: /* Intel ICH6M SATA */
154 case 0x26518086: /* Intel ICH6/W SATA */
155 case 0x24db8086: /* Intel ICH5 */
156 case 0x24d18086: /* Intel ICH5 SATA */
157 case 0x24ca8086: /* Intel ICH4 mobile */
158 case 0x24cb8086: /* Intel ICH4 */
159 case 0x248a8086: /* Intel ICH3 mobile */
160 case 0x248b8086: /* Intel ICH3 */
161 case 0x244a8086: /* Intel ICH2 mobile */
162 case 0x244b8086: /* Intel ICH2 */
163 if (udmamode >= 5) {
164 int32_t mask48, new48;
165 int16_t word54;
166
167 word54 = pci_read_config(parent, 0x54, 2);
168 if (word54 & (0x10 << devno)) {
169 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
170 ATA_UDMA5, ATA_C_F_SETXFER,ATA_WAIT_READY);
171 if (bootverbose)
172 ata_prtdev(atadev, "%s setting UDMA5 on Intel chip\n",
173 (error) ? "failed" : "success");
174 if (!error) {
175 mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
176 new48 = (1 << devno) + (1 << (16 + (devno << 2)));
177 pci_write_config(parent, 0x48,
178 (pci_read_config(parent, 0x48, 4) &
179 ~mask48) | new48, 4);
180 pci_write_config(parent, 0x54, word54 | (0x1000<<devno), 2);
181 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
182 return;
183 }
184 }
185 }
186 /* make sure eventual ATA100 mode from the BIOS is disabled */
187 pci_write_config(parent, 0x54,
188 pci_read_config(parent, 0x54, 2) & ~(0x1000<<devno),2);
189 /* FALLTHROUGH */
190
191 case 0x24118086: /* Intel ICH */
192 case 0x76018086: /* Intel ICH */
193 if (udmamode >= 4) {
194 int32_t mask48, new48;
195 int16_t word54;
196
197 word54 = pci_read_config(parent, 0x54, 2);
198 if (word54 & (0x10 << devno)) {
199 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
200 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
201 if (bootverbose)
202 ata_prtdev(atadev, "%s setting UDMA4 on Intel chip\n",
203 (error) ? "failed" : "success");
204 if (!error) {
205 mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
206 new48 = (1 << devno) + (2 << (16 + (devno << 2)));
207 pci_write_config(parent, 0x48,
208 (pci_read_config(parent, 0x48, 4) &
209 ~mask48) | new48, 4);
210 pci_write_config(parent, 0x54, word54 | (1 << devno), 2);
211 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
212 return;
213 }
214 }
215 }
216 /* make sure eventual ATA66 mode from the BIOS is disabled */
217 pci_write_config(parent, 0x54,
218 pci_read_config(parent, 0x54, 2) & ~(1 << devno), 2);
219 /* FALLTHROUGH */
220
221 case 0x71118086: /* Intel PIIX4 */
222 case 0x84CA8086: /* Intel PIIX4 */
223 case 0x71998086: /* Intel PIIX4e */
224 case 0x24218086: /* Intel ICH0 */
225 if (udmamode >= 2) {
226 int32_t mask48, new48;
227
228 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
229 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
230 if (bootverbose)
231 ata_prtdev(atadev, "%s setting UDMA2 on Intel chip\n",
232 (error) ? "failed" : "success");
233 if (!error) {
234 mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
235 new48 = (1 << devno) + (2 << (16 + (devno << 2)));
236 pci_write_config(parent, 0x48,
237 (pci_read_config(parent, 0x48, 4) &
238 ~mask48) | new48, 4);
239 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
240 return;
241 }
242 }
243 /* make sure eventual ATA33 mode from the BIOS is disabled */
244 pci_write_config(parent, 0x48,
245 pci_read_config(parent, 0x48, 4) & ~(1 << devno), 4);
246 /* FALLTHROUGH */
247
248 case 0x70108086: /* Intel PIIX3 */
249 if (wdmamode >= 2 && apiomode >= 4) {
250 int32_t mask40, new40, mask44, new44;
251
252 /* if SITRE not set doit for both channels */
253 if (!((pci_read_config(parent,0x40,4)>>(channel<<8))&0x4000)) {
254 new40 = pci_read_config(parent, 0x40, 4);
255 new44 = pci_read_config(parent, 0x44, 4);
256 if (!(new40 & 0x00004000)) {
257 new44 &= ~0x0000000f;
258 new44 |= ((new40&0x00003000)>>10)|((new40&0x00000300)>>8);
259 }
260 if (!(new40 & 0x40000000)) {
261 new44 &= ~0x000000f0;
262 new44 |= ((new40&0x30000000)>>22)|((new40&0x03000000)>>20);
263 }
264 new40 |= 0x40004000;
265 pci_write_config(parent, 0x40, new40, 4);
266 pci_write_config(parent, 0x44, new44, 4);
267 }
268 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
269 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
270 if (bootverbose)
271 ata_prtdev(atadev, "%s setting WDMA2 on Intel chip\n",
272 (error) ? "failed" : "success");
273 if (!error) {
274 if (device == ATA_MASTER) {
275 mask40 = 0x0000330f;
276 new40 = 0x00002307;
277 mask44 = 0;
278 new44 = 0;
279 }
280 else {
281 mask40 = 0x000000f0;
282 new40 = 0x00000070;
283 mask44 = 0x0000000f;
284 new44 = 0x0000000b;
285 }
286 if (channel) {
287 mask40 <<= 16;
288 new40 <<= 16;
289 mask44 <<= 4;
290 new44 <<= 4;
291 }
292 pci_write_config(parent, 0x40,
293 (pci_read_config(parent, 0x40, 4) & ~mask40)|
294 new40, 4);
295 pci_write_config(parent, 0x44,
296 (pci_read_config(parent, 0x44, 4) & ~mask44)|
297 new44, 4);
298 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
299 return;
300 }
301 }
302 /* we could set PIO mode timings, but we assume the BIOS did that */
303 break;
304
305 case 0x12308086: /* Intel PIIX */
306 if (wdmamode >= 2 && apiomode >= 4) {
307 int32_t word40;
308
309 word40 = pci_read_config(parent, 0x40, 4);
310 word40 >>= channel * 16;
311
312 /* Check for timing config usable for DMA on controller */
313 if (!((word40 & 0x3300) == 0x2300 &&
314 ((word40 >> (device ? 4 : 0)) & 1) == 1))
315 break;
316
317 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
318 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
319 if (bootverbose)
320 ata_prtdev(atadev, "%s setting WDMA2 on Intel chip\n",
321 (error) ? "failed" : "success");
322 if (!error) {
323 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
324 return;
325 }
326 }
327 break;
328
329 case 0x522910b9: /* AcerLabs Aladdin IV/V */
330 /* the older Aladdin doesn't support ATAPI DMA on both master & slave */
331 if (chiprev < 0xc2 &&
332 atadev->channel->devices & ATA_ATAPI_MASTER &&
333 atadev->channel->devices & ATA_ATAPI_SLAVE) {
334 ata_prtdev(atadev, "two atapi devices on this channel, no DMA\n");
335 break;
336 }
337 #if !defined(NO_ATANG)
338 pci_write_config(parent, 0x58 + (channel << 2), 0x00310001, 4);
339 #endif
340 if (udmamode >= 5 && chiprev >= 0xc4) {
341 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
342 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
343 if (bootverbose)
344 ata_prtdev(atadev, "%s setting UDMA5 on Acer chip\n",
345 (error) ? "failed" : "success");
346 if (!error) {
347 int32_t word54 = pci_read_config(parent, 0x54, 4);
348
349 pci_write_config(parent, 0x4b,
350 pci_read_config(parent, 0x4b, 1) | 0x01, 1);
351 word54 &= ~(0x000f000f << (devno << 2));
352 word54 |= (0x000f0005 << (devno << 2));
353 pci_write_config(parent, 0x54, word54, 4);
354 pci_write_config(parent, 0x53,
355 pci_read_config(parent, 0x53, 1) | 0x03, 1);
356 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
357 return;
358 }
359 }
360 if (udmamode >= 4 && chiprev >= 0xc2) {
361 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
362 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
363 if (bootverbose)
364 ata_prtdev(atadev, "%s setting UDMA4 on Acer chip\n",
365 (error) ? "failed" : "success");
366 if (!error) {
367 int32_t word54 = pci_read_config(parent, 0x54, 4);
368
369 pci_write_config(parent, 0x4b,
370 pci_read_config(parent, 0x4b, 1) | 0x01, 1);
371 word54 &= ~(0x000f000f << (devno << 2));
372 word54 |= (0x00080005 << (devno << 2));
373 pci_write_config(parent, 0x54, word54, 4);
374 pci_write_config(parent, 0x53,
375 pci_read_config(parent, 0x53, 1) | 0x03, 1);
376 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
377 return;
378 }
379 }
380 if (udmamode >= 2 && chiprev >= 0x20) {
381 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
382 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
383 if (bootverbose)
384 ata_prtdev(atadev, "%s setting UDMA2 on Acer chip\n",
385 (error) ? "failed" : "success");
386 if (!error) {
387 int32_t word54 = pci_read_config(parent, 0x54, 4);
388
389 word54 &= ~(0x000f000f << (devno << 2));
390 word54 |= (0x000a0005 << (devno << 2));
391 pci_write_config(parent, 0x54, word54, 4);
392 pci_write_config(parent, 0x53,
393 pci_read_config(parent, 0x53, 1) | 0x03, 1);
394 atadev->channel->flags |= ATA_ATAPI_DMA_RO;
395 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
396 return;
397 }
398 }
399
400 /* make sure eventual UDMA mode from the BIOS is disabled */
401 pci_write_config(parent, 0x56, pci_read_config(parent, 0x56, 2) &
402 ~(0x0008 << (devno << 2)), 2);
403
404 if (wdmamode >= 2 && apiomode >= 4) {
405 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
406 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
407 if (bootverbose)
408 ata_prtdev(atadev, "%s setting WDMA2 on Acer chip\n",
409 (error) ? "failed" : "success");
410 if (!error) {
411 pci_write_config(parent, 0x53,
412 pci_read_config(parent, 0x53, 1) | 0x03, 1);
413 atadev->channel->flags |= ATA_ATAPI_DMA_RO;
414 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
415 return;
416 }
417 }
418 pci_write_config(parent, 0x53,
419 (pci_read_config(parent, 0x53, 1) & ~0x01) | 0x02, 1);
420 #if !defined(NO_ATANG)
421 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
422 ATA_PIO0 + apiomode,
423 ATA_C_F_SETXFER, ATA_WAIT_READY);
424 if (bootverbose)
425 ata_prtdev(atadev, "%s setting PIO%d on Acer chip\n",
426 (error) ? "failed" : "success",
427 (apiomode >= 0) ? apiomode : 0);
428 if (!error) {
429 int32_t word54 = pci_read_config(parent, 0x54, 4);
430 int32_t timing;
431
432 switch(ATA_PIO0 + apiomode) {
433 case ATA_PIO0: timing = 0x006d0003; break;
434 case ATA_PIO1: timing = 0x00580002; break;
435 case ATA_PIO2: timing = 0x00440001; break;
436 case ATA_PIO3: timing = 0x00330001; break;
437 case ATA_PIO4: timing = 0x00310001; break;
438 default: timing = 0x006d0003; break;
439 }
440 pci_write_config(parent, 0x58 + (channel << 2), timing, 4);
441 word54 &= ~(0x000f000f << (devno << 2));
442 word54 |= (0x00000004 << (devno << 2));
443 pci_write_config(parent, 0x54, word54, 4);
444 atadev->mode = ATA_PIO0 + apiomode;
445 return;
446 }
447 #endif
448 break;
449
450 case 0x31491106: /* VIA 8237 SATA part */
451 if (udmamode) {
452 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
453 ATA_UDMA + udmamode,
454 ATA_C_F_SETXFER, ATA_WAIT_READY);
455 if (bootverbose)
456 ata_prtdev(atadev, "%s setting UDMA%d on VIA chip\n",
457 (error) ? "failed" : "success", udmamode);
458 if (!error) {
459 ata_dmacreate(atadev, apiomode, ATA_UDMA + udmamode);
460 return;
461 }
462 }
463 /* we could set PIO mode timings, but we assume the BIOS did that */
464 break;
465
466 case 0x01bc10de: /* NVIDIA nForce1 */
467 case 0x006510de: /* NVIDIA nForce2 */
468 case 0x00d510de: /* NVIDIA nForce3 */
469 case 0x00e310de: /* NVIDIA nForce3 PRO S1 */
470 case 0x00e510de: /* NVIDIA nForce3 PRO */
471 case 0x74691022: /* AMD 8111 */
472 case 0x74411022: /* AMD 768 */
473 case 0x74111022: /* AMD 766 */
474 case 0x74091022: /* AMD 756 */
475 case 0x05711106: /* VIA 82C571, 82C586, 82C596, 82C686, 8231,8233,8235 */
476 {
477 int via_modes[][7] = {
478 { 0xc2, 0xc1, 0xc0, 0x00, 0x00, 0x00, 0x00 }, /* VIA ATA33 */
479 { 0xee, 0xec, 0xea, 0xe9, 0xe8, 0x00, 0x00 }, /* VIA ATA66 */
480 { 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0, 0x00 }, /* VIA ATA100 */
481 { 0xf7, 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0 }, /* VIA ATA133 */
482 { 0xc2, 0xc1, 0xc0, 0xc4, 0xc5, 0xc6, 0xc7 }}; /* AMD/NVIDIA */
483 int *reg_val = NULL;
484 int reg_off = 0x53;
485 char *chip = "VIA";
486
487 if (ata_find_dev(parent, 0x31471106, 0) || /* 8233a */
488 ata_find_dev(parent, 0x31771106, 0) || /* 8235 */
489 ata_find_dev(parent, 0x31491106, 0)) { /* 8237 */
490 udmamode = imin(udmamode, 6);
491 reg_val = via_modes[3];
492 }
493 else if (ata_find_dev(parent, 0x06861106, 0x40) || /* 82C686b */
494 ata_find_dev(parent, 0x82311106, 0) || /* 8231 */
495 ata_find_dev(parent, 0x30741106, 0) || /* 8233 */
496 ata_find_dev(parent, 0x31091106, 0)) { /* 8233c */
497 udmamode = imin(udmamode, 5);
498 reg_val = via_modes[2];
499 }
500 else if (ata_find_dev(parent, 0x06861106, 0x10) || /* 82C686a */
501 ata_find_dev(parent, 0x05961106, 0x12)) { /* 82C596b */
502 udmamode = imin(udmamode, 4);
503 reg_val = via_modes[1];
504 }
505 else if (ata_find_dev(parent, 0x06861106, 0)) { /* 82C686 */
506 udmamode = imin(udmamode, 2);
507 reg_val = via_modes[1];
508 }
509 else if (ata_find_dev(parent, 0x05961106, 0) || /* 82C596a */
510 ata_find_dev(parent, 0x05861106, 0x03)) { /* 82C586b */
511 udmamode = imin(udmamode, 2);
512 reg_val = via_modes[0];
513 }
514 else if (chiptype == 0x74691022 || /* AMD 8111 */
515 chiptype == 0x74411022 || /* AMD 768 */
516 chiptype == 0x74111022) { /* AMD 766 */
517 udmamode = imin(udmamode, 5);
518 reg_val = via_modes[4];
519 chip = "AMD";
520 }
521 else if (chiptype == 0x74091022) { /* AMD 756 */
522 udmamode = imin(udmamode, 4);
523 reg_val = via_modes[4];
524 chip = "AMD";
525 }
526 else if (chiptype == 0x01bc10de) { /* nForce1 */
527 udmamode = imin(udmamode, 5);
528 reg_val = via_modes[4];
529 #if !defined(NO_ATANG)
530 reg_off += 0x10;
531 #endif
532 chip = "nVIDIA";
533 }
534 else if (chiptype == 0x006510de || /* nForce2 */
535 chiptype == 0x00d510de || /* nForce3 */
536 chiptype == 0x00e310de || /* nForce3 PRO S1 */
537 chiptype == 0x00e510de) { /* nForce3 PRO */
538 udmamode = imin(udmamode, 6);
539 reg_val = via_modes[4];
540 #if !defined(NO_ATANG)
541 reg_off += 0x10;
542 #endif
543 chip = "nVIDIA";
544 }
545 else
546 udmamode = 0;
547
548 reg_off -= devno;
549
550 if (udmamode >= 6) {
551 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
552 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY);
553 if (bootverbose)
554 ata_prtdev(atadev, "%s setting UDMA6 on %s chip\n",
555 (error) ? "failed" : "success", chip);
556 if (!error) {
557 pci_write_config(parent, reg_off, reg_val[6], 1);
558 pci_write_config(parent, reg_off - 8, 0x20, 1);
559 ata_dmacreate(atadev, apiomode, ATA_UDMA6);
560 return;
561 }
562 }
563 if (udmamode >= 5) {
564 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
565 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
566 if (bootverbose)
567 ata_prtdev(atadev, "%s setting UDMA5 on %s chip\n",
568 (error) ? "failed" : "success", chip);
569 if (!error) {
570 pci_write_config(parent, reg_off, reg_val[5], 1);
571 pci_write_config(parent, reg_off - 8, 0x20, 1);
572 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
573 return;
574 }
575 }
576 if (udmamode >= 4) {
577 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
578 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
579 if (bootverbose)
580 ata_prtdev(atadev, "%s setting UDMA4 on %s chip\n",
581 (error) ? "failed" : "success", chip);
582 if (!error) {
583 pci_write_config(parent, reg_off, reg_val[4], 1);
584 pci_write_config(parent, reg_off - 8, 0x20, 1);
585 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
586 return;
587 }
588 }
589 if (udmamode >= 2) {
590 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
591 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
592 if (bootverbose)
593 ata_prtdev(atadev, "%s setting UDMA2 on %s chip\n",
594 (error) ? "failed" : "success", chip);
595 if (!error) {
596 pci_write_config(parent, reg_off, reg_val[2], 1);
597 pci_write_config(parent, reg_off - 8, 0x20, 1);
598 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
599 return;
600 }
601 }
602 if (wdmamode >= 2 && apiomode >= 4) {
603 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
604 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
605 if (bootverbose)
606 ata_prtdev(atadev, "%s setting WDMA2 on %s chip\n",
607 (error) ? "failed" : "success", chip);
608 if (!error) {
609 pci_write_config(parent, reg_off, 0x0b, 1);
610 pci_write_config(parent, reg_off - 8, 0x20, 1);
611 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
612 return;
613 }
614 }
615 pci_write_config(parent, reg_off, 0x8b, 1);
616 switch(apiomode) {
617 case 0:
618 pci_write_config(parent, reg_off - 8, 0xa8, 1);
619 break;
620 case 1:
621 pci_write_config(parent, reg_off - 8, 0x65, 1);
622 break;
623 case 2:
624 pci_write_config(parent, reg_off - 8, 0x42, 1);
625 break;
626 case 3:
627 pci_write_config(parent, reg_off - 8, 0x22, 1);
628 break;
629 case 4:
630 pci_write_config(parent, reg_off - 8, 0x20, 1);
631 break;
632 }
633 }
634 break;
635
636 case 0x55131039: /* SiS 5591 */
637 if (ata_find_dev(parent, 0x06301039, 0x30) || /* SiS 630 */
638 ata_find_dev(parent, 0x06331039, 0) || /* SiS 633 */
639 ata_find_dev(parent, 0x06351039, 0) || /* SiS 635 */
640 ata_find_dev(parent, 0x06401039, 0) || /* SiS 640 */
641 ata_find_dev(parent, 0x06451039, 0) || /* SiS 645 */
642 ata_find_dev(parent, 0x06461039, 0) || /* SiS 645DX */
643 ata_find_dev(parent, 0x06481039, 0) || /* SiS 648 */
644 ata_find_dev(parent, 0x06501039, 0) || /* SiS 650 */
645 ata_find_dev(parent, 0x07301039, 0) || /* SiS 730 */
646 ata_find_dev(parent, 0x07331039, 0) || /* SiS 733 */
647 ata_find_dev(parent, 0x07351039, 0) || /* SiS 735 */
648 ata_find_dev(parent, 0x07401039, 0) || /* SiS 740 */
649 ata_find_dev(parent, 0x07451039, 0) || /* SiS 745 */
650 ata_find_dev(parent, 0x07461039, 0) || /* SiS 746 */
651 ata_find_dev(parent, 0x07501039, 0)) { /* SiS 750 */
652 int8_t reg = 0x40 + (devno << 1);
653 int16_t val = pci_read_config(parent, reg, 2) & 0x0fff;
654
655 if (udmamode >= 5) {
656 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
657 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
658 if (bootverbose)
659 ata_prtdev(atadev, "%s setting UDMA5 on SiS chip\n",
660 (error) ? "failed" : "success");
661 if (!error) {
662 pci_write_config(parent, reg, val | 0x8000, 2);
663 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
664 return;
665 }
666 }
667 if (udmamode >= 4) {
668 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
669 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
670 if (bootverbose)
671 ata_prtdev(atadev, "%s setting UDMA4 on SiS chip\n",
672 (error) ? "failed" : "success");
673 if (!error) {
674 pci_write_config(parent, reg, val | 0x9000, 2);
675 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
676 return;
677 }
678 }
679 if (udmamode >= 2) {
680 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
681 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
682 if (bootverbose)
683 ata_prtdev(atadev, "%s setting UDMA2 on SiS chip\n",
684 (error) ? "failed" : "success");
685 if (!error) {
686 pci_write_config(parent, reg, val | 0xb000, 2);
687 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
688 return;
689 }
690 }
691 } else if (ata_find_dev(parent, 0x05301039, 0) || /* SiS 530 */
692 ata_find_dev(parent, 0x05401039, 0) || /* SiS 540 */
693 ata_find_dev(parent, 0x06201039, 0) || /* SiS 620 */
694 ata_find_dev(parent, 0x06301039, 0)) { /* SiS 630 */
695 int8_t reg = 0x40 + (devno << 1);
696 int16_t val = pci_read_config(parent, reg, 2) & 0x0fff;
697
698 if (udmamode >= 4) {
699 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
700 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
701 if (bootverbose)
702 ata_prtdev(atadev, "%s setting UDMA4 on SiS chip\n",
703 (error) ? "failed" : "success");
704 if (!error) {
705 pci_write_config(parent, reg, val | 0x9000, 2);
706 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
707 return;
708 }
709 }
710 if (udmamode >= 2) {
711 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
712 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
713 if (bootverbose)
714 ata_prtdev(atadev, "%s setting UDMA2 on SiS chip\n",
715 (error) ? "failed" : "success");
716 if (!error) {
717 pci_write_config(parent, reg, val | 0xa000, 2);
718 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
719 return;
720 }
721 }
722 } else if (udmamode >= 2 && chiprev > 0xc1) {
723 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
724 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
725 if (bootverbose)
726 ata_prtdev(atadev, "%s setting UDMA2 on SiS chip\n",
727 (error) ? "failed" : "success");
728 if (!error) {
729 pci_write_config(parent, 0x40 + (devno << 1), 0xa301, 2);
730 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
731 return;
732 }
733 }
734 if (wdmamode >=2 && apiomode >= 4) {
735 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
736 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
737 if (bootverbose)
738 ata_prtdev(atadev, "%s setting WDMA2 on SiS chip\n",
739 (error) ? "failed" : "success");
740 if (!error) {
741 pci_write_config(parent, 0x40 + (devno << 1), 0x0301, 2);
742 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
743 return;
744 }
745 }
746 /* we could set PIO mode timings, but we assume the BIOS did that */
747 break;
748
749 case 0x35121095: /* SiI 3512 SATA controller */
750 /* EXPERIMENTAL! Works with FN85 AMD 64 3200+ motherboard */
751 /* FALLTHROUGH */
752 case 0x31241095: /* SiI 3124 SATA controller */
753 case 0x31141095: /* SiI 3114 SATA controller */
754 case 0x31121095: /* SiI 3112 SATA controller */
755 case 0x06801095: /* SiI 0680 ATA133 controller */
756 {
757 u_int8_t ureg = 0xac + (device * 0x02) + (channel * 0x10);
758 u_int8_t uval = pci_read_config(parent, ureg, 1);
759 u_int8_t mreg = channel ? 0x84 : 0x80;
760 u_int8_t mask = device ? 0x30 : 0x03;
761 u_int8_t mode = pci_read_config(parent, mreg, 1);
762
763 /* enable UDMA mode */
764 pci_write_config(parent, mreg,
765 (mode & ~mask) | (device ? 0x30 : 0x03), 1);
766 if (udmamode >= 6) {
767 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
768 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY);
769 if (bootverbose)
770 ata_prtdev(atadev, "%s setting UDMA6 on SiI chip\n",
771 (error) ? "failed" : "success");
772 if (!error) {
773 pci_write_config(parent, ureg, (uval & ~0x3f) | 0x01, 1);
774 ata_dmacreate(atadev, apiomode, ATA_UDMA6);
775 return;
776 }
777 }
778 if (udmamode >= 5) {
779 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
780 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
781 if (bootverbose)
782 ata_prtdev(atadev, "%s setting UDMA5 on SiI chip\n",
783 (error) ? "failed" : "success");
784 if (!error) {
785 pci_write_config(parent, ureg, (uval & ~0x3f) | 0x02, 1);
786 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
787 return;
788 }
789 }
790 if (udmamode >= 4) {
791 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
792 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
793 if (bootverbose)
794 ata_prtdev(atadev, "%s setting UDMA4 on SiI chip\n",
795 (error) ? "failed" : "success");
796 if (!error) {
797 pci_write_config(parent, ureg, (uval & ~0x3f) | 0x03, 1);
798 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
799 return;
800 }
801 }
802 if (udmamode >= 2) {
803 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
804 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
805 if (bootverbose)
806 ata_prtdev(atadev, "%s setting UDMA2 on SiI chip\n",
807 (error) ? "failed" : "success");
808 if (!error) {
809 pci_write_config(parent, ureg, (uval & ~0x3f) | 0x07, 1);
810 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
811 return;
812 }
813 }
814
815 /* disable UDMA mode and enable WDMA mode */
816 pci_write_config(parent, mreg,
817 (mode & ~mask) | (device ? 0x20 : 0x02), 1);
818 if (wdmamode >= 2 && apiomode >= 4) {
819 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
820 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
821 if (bootverbose)
822 ata_prtdev(atadev, "%s setting WDMA2 on SiI chip\n",
823 (error) ? "failed" : "success");
824 if (!error) {
825 pci_write_config(parent, ureg - 0x4, 0x10c1, 2);
826 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
827 return;
828 }
829 }
830
831 /* restore PIO mode */
832 pci_write_config(parent, mreg, mode, 1);
833 }
834 /* we could set PIO mode timings, but we assume the BIOS did that */
835 break;
836
837 case 0x06491095: /* CMD 649 ATA100 controller */
838 if (udmamode >= 5) {
839 u_int8_t umode;
840
841 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
842 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
843 if (bootverbose)
844 ata_prtdev(atadev, "%s setting UDMA5 on CMD chip\n",
845 (error) ? "failed" : "success");
846 if (!error) {
847 umode = pci_read_config(parent, channel ? 0x7b : 0x73, 1);
848 umode &= ~(device ? 0xca : 0x35);
849 umode |= (device ? 0x0a : 0x05);
850 pci_write_config(parent, channel ? 0x7b : 0x73, umode, 1);
851 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
852 return;
853 }
854 }
855 /* FALLTHROUGH */
856
857 case 0x06481095: /* CMD 648 ATA66 controller */
858 if (udmamode >= 4) {
859 u_int8_t umode;
860
861 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
862 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
863 if (bootverbose)
864 ata_prtdev(atadev, "%s setting UDMA4 on CMD chip\n",
865 (error) ? "failed" : "success");
866 if (!error) {
867 umode = pci_read_config(parent, channel ? 0x7b : 0x73, 1);
868 umode &= ~(device ? 0xca : 0x35);
869 umode |= (device ? 0x4a : 0x15);
870 pci_write_config(parent, channel ? 0x7b : 0x73, umode, 1);
871 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
872 return;
873 }
874 }
875 if (udmamode >= 2) {
876 u_int8_t umode;
877
878 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
879 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
880 if (bootverbose)
881 ata_prtdev(atadev, "%s setting UDMA2 on CMD chip\n",
882 (error) ? "failed" : "success");
883 if (!error) {
884 umode = pci_read_config(parent, channel ? 0x7b : 0x73, 1);
885 umode &= ~(device ? 0xca : 0x35);
886 umode |= (device ? 0x42 : 0x11);
887 pci_write_config(parent, channel ? 0x7b : 0x73, umode, 1);
888 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
889 return;
890 }
891 }
892 /* make sure eventual UDMA mode from the BIOS is disabled */
893 pci_write_config(parent, channel ? 0x7b : 0x73,
894 pci_read_config(parent, channel ? 0x7b : 0x73, 1)&
895 #if !defined(NO_ATANG)
896 ~(device ? 0xca : 0x53), 1);
897 #else
898 ~(device ? 0xca : 0x35), 1);
899 #endif
900 /* FALLTHROUGH */
901
902 case 0x06461095: /* CMD 646 ATA controller */
903 if (wdmamode >= 2 && apiomode >= 4) {
904 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
905 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
906 if (bootverbose)
907 ata_prtdev(atadev, "%s setting WDMA2 on CMD chip\n",
908 error ? "failed" : "success");
909 if (!error) {
910 int32_t offset = (devno < 3) ? (devno << 1) : 7;
911
912 pci_write_config(parent, 0x54 + offset, 0x3f, 1);
913 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
914 return;
915 }
916 }
917 /* we could set PIO mode timings, but we assume the BIOS did that */
918 break;
919
920 case 0xc6931080: /* Cypress 82c693 ATA controller */
921 if (wdmamode >= 2 && apiomode >= 4) {
922 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
923 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
924 if (bootverbose)
925 ata_prtdev(atadev, "%s setting WDMA2 on Cypress chip\n",
926 error ? "failed" : "success");
927 if (!error) {
928 pci_write_config(atadev->channel->dev,
929 channel ? 0x4e:0x4c, 0x2020, 2);
930 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
931 return;
932 }
933 }
934 /* we could set PIO mode timings, but we assume the BIOS did that */
935 break;
936
937 case 0x01021078: /* Cyrix 5530 ATA33 controller */
938 atadev->channel->alignment = 0xf; /* DMA engine requires 16 byte alignment */
939 if (udmamode >= 2) {
940 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
941 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
942 if (bootverbose)
943 ata_prtdev(atadev, "%s setting UDMA2 on Cyrix chip\n",
944 (error) ? "failed" : "success");
945 if (!error) {
946 cyrix_timing(atadev, devno, ATA_UDMA2);
947 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
948 return;
949 }
950 }
951 if (wdmamode >= 2 && apiomode >= 4) {
952 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
953 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
954 if (bootverbose)
955 ata_prtdev(atadev, "%s setting WDMA2 on Cyrix chip\n",
956 (error) ? "failed" : "success");
957 if (!error) {
958 cyrix_timing(atadev, devno, ATA_WDMA2);
959 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
960 return;
961 }
962 }
963 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
964 ATA_PIO0 + apiomode, ATA_C_F_SETXFER,
965 ATA_WAIT_READY);
966 if (bootverbose)
967 ata_prtdev(atadev, "%s setting %s on Cyrix chip\n",
968 (error) ? "failed" : "success",
969 ata_mode2str(ATA_PIO0 + apiomode));
970 cyrix_timing(atadev, devno, ATA_PIO0 + apiomode);
971 atadev->mode = ATA_PIO0 + apiomode;
972 return;
973
974 #if !defined(NO_ATANG)
975 case 0x02131166: /* ServerWorks CSB6 ATA 100 controller (chan 0+1) */
976 #endif
977 case 0x02121166: /* ServerWorks CSB5 ATA66/100 controller */
978 #if !defined(NO_ATANG)
979 if (udmamode >= 5 && (chiptype == 0x02131166 ||
980 (chiptype == 0x02121166 &&
981 chiprev >= 0x92))) {
982 #else
983 if (udmamode >= 5 && chiprev >= 0x92) {
984 #endif
985 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
986 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
987 if (bootverbose)
988 ata_prtdev(atadev, "%s setting UDMA5 on ServerWorks chip\n",
989 (error) ? "failed" : "success");
990 if (!error) {
991 u_int16_t reg56;
992
993 pci_write_config(parent, 0x54,
994 pci_read_config(parent, 0x54, 1) |
995 (0x01 << devno), 1);
996 reg56 = pci_read_config(parent, 0x56, 2);
997 reg56 &= ~(0xf << (devno * 4));
998 reg56 |= (0x5 << (devno * 4));
999 pci_write_config(parent, 0x56, reg56, 2);
1000 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
1001 return;
1002 }
1003 }
1004 #if !defined(NO_ATANG)
1005 /* FALLTHROUGH */
1006 case 0x02171166: /* Server Works CSB6 ATA 66 controller chan 2 */
1007 #endif
1008 if (udmamode >= 4) {
1009 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1010 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
1011 if (bootverbose)
1012 ata_prtdev(atadev, "%s setting UDMA4 on ServerWorks chip\n",
1013 (error) ? "failed" : "success");
1014 if (!error) {
1015 u_int16_t reg56;
1016
1017 pci_write_config(parent, 0x54,
1018 pci_read_config(parent, 0x54, 1) |
1019 (0x01 << devno), 1);
1020 reg56 = pci_read_config(parent, 0x56, 2);
1021 reg56 &= ~(0xf << (devno * 4));
1022 reg56 |= (0x4 << (devno * 4));
1023 pci_write_config(parent, 0x56, reg56, 2);
1024 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
1025 return;
1026 }
1027 }
1028 /* FALLTHROUGH */
1029
1030 case 0x02111166: /* ServerWorks ROSB4 ATA33 controller */
1031 if (udmamode >= 2) {
1032 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1033 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1034 if (bootverbose)
1035 ata_prtdev(atadev, "%s setting UDMA2 on ServerWorks chip\n",
1036 (error) ? "failed" : "success");
1037 if (!error) {
1038 u_int16_t reg56;
1039
1040 pci_write_config(parent, 0x54,
1041 pci_read_config(parent, 0x54, 1) |
1042 (0x01 << devno), 1);
1043 reg56 = pci_read_config(parent, 0x56, 2);
1044 reg56 &= ~(0xf << (devno * 4));
1045 reg56 |= (0x2 << (devno * 4));
1046 pci_write_config(parent, 0x56, reg56, 2);
1047 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
1048 return;
1049 }
1050 }
1051 if (wdmamode >= 2 && apiomode >= 4) {
1052 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1053 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1054 if (bootverbose)
1055 ata_prtdev(atadev, "%s setting WDMA2 on ServerWorks chip\n",
1056 (error) ? "failed" : "success");
1057 if (!error) {
1058 int offset = devno ^ 0x01; /* (chan*2) + (dev==ATA_MASTER)*/
1059 int word44 = pci_read_config(parent, 0x44, 4);
1060
1061 pci_write_config(parent, 0x54,
1062 pci_read_config(parent, 0x54, 1) &
1063 ~(0x01 << devno), 1);
1064 word44 &= ~(0xff << (offset << 8));
1065 word44 |= (0x20 << (offset << 8));
1066 pci_write_config(parent, 0x44, 0x20, 4);
1067 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
1068 return;
1069 }
1070 }
1071 /* we could set PIO mode timings, but we assume the BIOS did that */
1072 break;
1073
1074 case 0x4d69105a: /* Promise TX2 ATA133 controllers */
1075 case 0x5275105a: /* Promise TX2 ATA133 controllers */
1076 case 0x6269105a: /* Promise TX2 ATA133 controllers */
1077 case 0x7275105a: /* Promise TX2 ATA133 controllers */
1078 ATA_OUTB(atadev->channel->r_bmio, ATA_BMDEVSPEC_0, 0x0b);
1079 if (udmamode >= 6 &&
1080 !(ATA_INB(atadev->channel->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) {
1081 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1082 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY);
1083 if (bootverbose)
1084 ata_prtdev(atadev, "%s setting UDMA6 on Promise chip\n",
1085 (error) ? "failed" : "success");
1086 if (!error) {
1087 ata_dmacreate(atadev, apiomode, ATA_UDMA6);
1088 return;
1089 }
1090 }
1091 /* FALLTHROUGH */
1092
1093 case 0x4d68105a: /* Promise TX2 ATA100 controllers */
1094 case 0x6268105a: /* Promise TX2 ATA100 controllers */
1095 ATA_OUTB(atadev->channel->r_bmio, ATA_BMDEVSPEC_0, 0x0b);
1096 if (udmamode >= 5 &&
1097 !(ATA_INB(atadev->channel->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) {
1098 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1099 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
1100 if (bootverbose)
1101 ata_prtdev(atadev, "%s setting UDMA5 on Promise chip\n",
1102 (error) ? "failed" : "success");
1103 if (!error) {
1104 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
1105 return;
1106 }
1107 }
1108 ATA_OUTB(atadev->channel->r_bmio, ATA_BMDEVSPEC_0, 0x0b);
1109 if (udmamode >= 4 &&
1110 !(ATA_INB(atadev->channel->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) {
1111 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1112 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
1113 if (bootverbose)
1114 ata_prtdev(atadev, "%s setting UDMA4 on Promise chip\n",
1115 (error) ? "failed" : "success");
1116 if (!error) {
1117 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
1118 return;
1119 }
1120 }
1121 if (udmamode >= 2) {
1122 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1123 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1124 if (bootverbose)
1125 ata_prtdev(atadev, "%s setting UDMA on Promise chip\n",
1126 (error) ? "failed" : "success");
1127 if (!error) {
1128 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
1129 return;
1130 }
1131 }
1132 if (wdmamode >= 2 && apiomode >= 4) {
1133 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1134 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1135 if (bootverbose)
1136 ata_prtdev(atadev, "%s setting WDMA2 on Promise chip\n",
1137 (error) ? "failed" : "success");
1138 if (!error) {
1139 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
1140 return;
1141 }
1142 }
1143 break;
1144
1145 case 0x0d30105a: /* Promise OEM ATA100 controllers */
1146 case 0x4d30105a: /* Promise Ultra/FastTrak 100 controllers */
1147 if (!ATAPI_DEVICE(atadev) && udmamode >= 5 &&
1148 !(pci_read_config(parent, 0x50, 2)&(channel ? 1<<11 : 1<<10))){
1149 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1150 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
1151 if (bootverbose)
1152 ata_prtdev(atadev, "%s setting UDMA5 on Promise chip\n",
1153 (error) ? "failed" : "success");
1154 if (!error) {
1155 promise_timing(atadev, devno, ATA_UDMA5);
1156 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
1157 return;
1158 }
1159 }
1160 /* FALLTHROUGH */
1161
1162 case 0x0d38105a: /* Promise FastTrak 66 controllers */
1163 case 0x4d38105a: /* Promise Ultra/FastTrak 66 controllers */
1164 if (!ATAPI_DEVICE(atadev) && udmamode >= 4 &&
1165 !(pci_read_config(parent, 0x50, 2)&(channel ? 1<<11 : 1<<10))){
1166 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1167 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
1168 if (bootverbose)
1169 ata_prtdev(atadev, "%s setting UDMA4 on Promise chip\n",
1170 (error) ? "failed" : "success");
1171 if (!error) {
1172 promise_timing(atadev, devno, ATA_UDMA4);
1173 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
1174 return;
1175 }
1176 }
1177 /* FALLTHROUGH */
1178
1179 case 0x4d33105a: /* Promise Ultra/FastTrak 33 controllers */
1180 if (!ATAPI_DEVICE(atadev) && udmamode >= 2) {
1181 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1182 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1183 if (bootverbose)
1184 ata_prtdev(atadev, "%s setting UDMA2 on Promise chip\n",
1185 (error) ? "failed" : "success");
1186 if (!error) {
1187 promise_timing(atadev, devno, ATA_UDMA2);
1188 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
1189 return;
1190 }
1191 }
1192 if (!ATAPI_DEVICE(atadev) && wdmamode >= 2 && apiomode >= 4) {
1193 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1194 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1195 if (bootverbose)
1196 ata_prtdev(atadev, "%s setting WDMA2 on Promise chip\n",
1197 (error) ? "failed" : "success");
1198 if (!error) {
1199 promise_timing(atadev, devno, ATA_WDMA2);
1200 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
1201 return;
1202 }
1203 }
1204 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1205 ATA_PIO0 + apiomode,
1206 ATA_C_F_SETXFER, ATA_WAIT_READY);
1207 if (bootverbose)
1208 ata_prtdev(atadev, "%s setting PIO%d on Promise chip\n",
1209 (error) ? "failed" : "success",
1210 (apiomode >= 0) ? apiomode : 0);
1211 promise_timing(atadev, devno, ATA_PIO0 + apiomode);
1212 atadev->mode = ATA_PIO0 + apiomode;
1213 return;
1214
1215 case 0x00041103: /* HighPoint HPT366/368/370/372 controllers */
1216 case 0x00051103: /* HighPoint HPT372 controllers */
1217 case 0x00081103: /* HighPoint HPT374 controllers */
1218 if (!ATAPI_DEVICE(atadev) && udmamode >= 6 && hpt_cable80(atadev) &&
1219 ((chiptype == 0x00041103 && chiprev >= 0x05) ||
1220 (chiptype == 0x00051103 && chiprev >= 0x01) ||
1221 (chiptype == 0x00081103 && chiprev >= 0x07))) {
1222 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1223 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY);
1224 if (bootverbose)
1225 ata_prtdev(atadev, "%s setting UDMA6 on HighPoint chip\n",
1226 (error) ? "failed" : "success");
1227 if (!error) {
1228 hpt_timing(atadev, devno, ATA_UDMA6);
1229 ata_dmacreate(atadev, apiomode, ATA_UDMA6);
1230 return;
1231 }
1232 }
1233 if (!ATAPI_DEVICE(atadev) && udmamode >= 5 && hpt_cable80(atadev) &&
1234 ((chiptype == 0x00041103 && chiprev >= 0x03) ||
1235 (chiptype == 0x00051103 && chiprev >= 0x01) ||
1236 (chiptype == 0x00081103 && chiprev >= 0x07))) {
1237 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1238 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
1239 if (bootverbose)
1240 ata_prtdev(atadev, "%s setting UDMA5 on HighPoint chip\n",
1241 (error) ? "failed" : "success");
1242 if (!error) {
1243 hpt_timing(atadev, devno, ATA_UDMA5);
1244 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
1245 return;
1246 }
1247 }
1248 if (!ATAPI_DEVICE(atadev) && udmamode >= 4 && hpt_cable80(atadev)) {
1249 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1250 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
1251 if (bootverbose)
1252 ata_prtdev(atadev, "%s setting UDMA4 on HighPoint chip\n",
1253 (error) ? "failed" : "success");
1254 if (!error) {
1255 hpt_timing(atadev, devno, ATA_UDMA4);
1256 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
1257 return;
1258 }
1259 }
1260 if (!ATAPI_DEVICE(atadev) && udmamode >= 2) {
1261 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1262 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1263 if (bootverbose)
1264 ata_prtdev(atadev, "%s setting UDMA2 on HighPoint chip\n",
1265 (error) ? "failed" : "success");
1266 if (!error) {
1267 hpt_timing(atadev, devno, ATA_UDMA2);
1268 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
1269 return;
1270 }
1271 }
1272 if (!ATAPI_DEVICE(atadev) && wdmamode >= 2 && apiomode >= 4) {
1273 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1274 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1275 if (bootverbose)
1276 ata_prtdev(atadev, "%s setting WDMA2 on HighPoint chip\n",
1277 (error) ? "failed" : "success");
1278 if (!error) {
1279 hpt_timing(atadev, devno, ATA_WDMA2);
1280 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
1281 return;
1282 }
1283 }
1284 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1285 ATA_PIO0 + apiomode,
1286 ATA_C_F_SETXFER, ATA_WAIT_READY);
1287 if (bootverbose)
1288 ata_prtdev(atadev, "%s setting PIO%d on HighPoint chip\n",
1289 (error) ? "failed" : "success",
1290 (apiomode >= 0) ? apiomode : 0);
1291 hpt_timing(atadev, devno, ATA_PIO0 + apiomode);
1292 atadev->mode = ATA_PIO0 + apiomode;
1293 return;
1294
1295 case 0x000116ca: /* Cenatek Rocket Drive controller */
1296 if (wdmamode >= 0 &&
1297 (ATA_INB(atadev->channel->r_bmio, ATA_BMSTAT_PORT) &
1298 (device ? ATA_BMSTAT_DMA_SLAVE : ATA_BMSTAT_DMA_MASTER)))
1299 ata_dmacreate(atadev, apiomode, ATA_DMA);
1300 else
1301 atadev->mode = ATA_PIO;
1302 return;
1303
1304 default: /* unknown controller chip */
1305 /* better not try generic DMA on ATAPI devices it almost never works */
1306 if (ATAPI_DEVICE(atadev))
1307 break;
1308
1309 /* if controller says its setup for DMA take the easy way out */
1310 /* the downside is we dont know what DMA mode we are in */
1311 if ((udmamode >= 0 || wdmamode >= 2) &&
1312 (ATA_INB(atadev->channel->r_bmio, ATA_BMSTAT_PORT) &
1313 (device ? ATA_BMSTAT_DMA_SLAVE : ATA_BMSTAT_DMA_MASTER))) {
1314 ata_dmacreate(atadev, apiomode, ATA_DMA);
1315 return;
1316 }
1317
1318 /* well, we have no support for this, but try anyways */
1319 if ((wdmamode >= 2 && apiomode >= 4) && atadev->channel->r_bmio) {
1320 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1321 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1322 if (bootverbose)
1323 ata_prtdev(atadev, "%s setting WDMA2 on generic chip\n",
1324 (error) ? "failed" : "success");
1325 if (!error) {
1326 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
1327 return;
1328 }
1329 }
1330 }
1331 error = ata_command(atadev, ATA_C_SETFEATURES, 0, ATA_PIO0 + apiomode,
1332 ATA_C_F_SETXFER, ATA_WAIT_READY);
1333 if (bootverbose)
1334 ata_prtdev(atadev, "%s setting PIO%d on generic chip\n",
1335 (error) ? "failed" : "success", apiomode < 0 ? 0 : apiomode);
1336 if (!error)
1337 atadev->mode = ATA_PIO0 + apiomode;
1338 else {
1339 if (bootverbose)
1340 ata_prtdev(atadev, "using PIO mode set by BIOS\n");
1341 atadev->mode = ATA_PIO;
1342 }
1343 }
1344
1345 int
1346 ata_dmasetup(struct ata_device *atadev, caddr_t data, int32_t count)
1347 {
1348 struct ata_channel *ch = atadev->channel;
1349 struct ata_dmastate *ds = &atadev->dmastate;
1350 u_int32_t dma_count, dma_base;
1351 int i = 0;
1352
1353 if (((uintptr_t)data & ch->alignment) || (count & ch->alignment)) {
1354 ata_prtdev(atadev, "non aligned DMA transfer attempted\n");
1355 return -1;
1356 }
1357
1358 if (!count) {
1359 ata_prtdev(atadev, "zero length DMA transfer attempted\n");
1360 return -1;
1361 }
1362
1363 dma_base = vtophys(data);
1364 dma_count = imin(count, (PAGE_SIZE - ((uintptr_t)data & PAGE_MASK)));
1365 data += dma_count;
1366 count -= dma_count;
1367
1368 while (count) {
1369 ds->dmatab[i].base = dma_base;
1370 ds->dmatab[i].count = (dma_count & 0xffff);
1371 i++;
1372 if (i >= ATA_DMA_ENTRIES) {
1373 ata_prtdev(atadev, "too many segments in DMA table\n");
1374 return -1;
1375 }
1376 dma_base = vtophys(data);
1377 dma_count = imin(count, PAGE_SIZE);
1378 data += imin(count, PAGE_SIZE);
1379 count -= imin(count, PAGE_SIZE);
1380 }
1381 ds->dmatab[i].base = dma_base;
1382 ds->dmatab[i].count = (dma_count & 0xffff) | ATA_DMA_EOT;
1383 return 0;
1384 }
1385
1386 int
1387 ata_dmastart(struct ata_device *atadev, caddr_t data, int32_t count, int dir)
1388 {
1389 struct ata_channel *ch = atadev->channel;
1390 struct ata_dmastate *ds = &atadev->dmastate;
1391
1392 ch->flags |= ATA_DMA_ACTIVE;
1393 ATA_OUTL(ch->r_bmio, ATA_BMDTP_PORT, vtophys(ds->dmatab));
1394 ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT, dir ? ATA_BMCMD_WRITE_READ : 0);
1395 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT,
1396 (ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) |
1397 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR)));
1398 ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT,
1399 ATA_INB(ch->r_bmio, ATA_BMCMD_PORT) | ATA_BMCMD_START_STOP);
1400 return(0);
1401 }
1402
1403 int
1404 ata_dmadone(struct ata_device *atadev)
1405 {
1406 struct ata_channel *ch;
1407 struct ata_dmastate *ds;
1408 int error;
1409
1410 ch = atadev->channel;
1411 ds = &atadev->dmastate;
1412
1413 ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT,
1414 ATA_INB(ch->r_bmio, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
1415 error = ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT);
1416 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT,
1417 error | ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR);
1418 ch->flags &= ~ATA_DMA_ACTIVE;
1419 ds->flags = 0;
1420 return error & ATA_BMSTAT_MASK;
1421 }
1422
1423 int
1424 ata_dmastatus(struct ata_channel *ch)
1425 {
1426 return ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
1427 }
1428
1429 static void
1430 cyrix_timing(struct ata_device *atadev, int devno, int mode)
1431 {
1432 u_int32_t reg20 = 0x0000e132;
1433 u_int32_t reg24 = 0x00017771;
1434
1435 switch (mode) {
1436 case ATA_PIO0: reg20 = 0x0000e132; break;
1437 case ATA_PIO1: reg20 = 0x00018121; break;
1438 case ATA_PIO2: reg20 = 0x00024020; break;
1439 case ATA_PIO3: reg20 = 0x00032010; break;
1440 case ATA_PIO4: reg20 = 0x00040010; break;
1441 case ATA_WDMA2: reg24 = 0x00002020; break;
1442 case ATA_UDMA2: reg24 = 0x00911030; break;
1443 }
1444 ATA_OUTL(atadev->channel->r_bmio, (devno << 3) + 0x20, reg20);
1445 ATA_OUTL(atadev->channel->r_bmio, (devno << 3) + 0x24, reg24);
1446 }
1447
1448 static void
1449 promise_timing(struct ata_device *atadev, int devno, int mode)
1450 {
1451 u_int32_t timing = 0;
1452 /* XXX: Endianess */
1453 struct promise_timing {
1454 u_int8_t pa:4;
1455 u_int8_t prefetch:1;
1456 u_int8_t iordy:1;
1457 u_int8_t errdy:1;
1458 u_int8_t syncin:1;
1459 u_int8_t pb:5;
1460 u_int8_t mb:3;
1461 u_int8_t mc:4;
1462 u_int8_t dmaw:1;
1463 u_int8_t dmar:1;
1464 u_int8_t iordyp:1;
1465 u_int8_t dmarqp:1;
1466 u_int8_t reserved:8;
1467 } *t = (struct promise_timing*)&timing;
1468
1469 t->iordy = 1; t->iordyp = 1;
1470 if (mode >= ATA_DMA) {
1471 t->prefetch = 1; t->errdy = 1; t->syncin = 1;
1472 }
1473
1474 switch (atadev->channel->chiptype) {
1475 case 0x4d33105a: /* Promise Ultra/Fasttrak 33 */
1476 switch (mode) {
1477 default:
1478 case ATA_PIO0: t->pa = 9; t->pb = 19; t->mb = 7; t->mc = 15; break;
1479 case ATA_PIO1: t->pa = 5; t->pb = 12; t->mb = 7; t->mc = 15; break;
1480 case ATA_PIO2: t->pa = 3; t->pb = 8; t->mb = 7; t->mc = 15; break;
1481 case ATA_PIO3: t->pa = 2; t->pb = 6; t->mb = 7; t->mc = 15; break;
1482 case ATA_PIO4: t->pa = 1; t->pb = 4; t->mb = 7; t->mc = 15; break;
1483 case ATA_WDMA2: t->pa = 3; t->pb = 7; t->mb = 3; t->mc = 3; break;
1484 case ATA_UDMA2: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break;
1485 }
1486 break;
1487
1488 case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */
1489 case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */
1490 case 0x0d30105a: /* Promise OEM ATA 100 */
1491 switch (mode) {
1492 default:
1493 case ATA_PIO0: t->pa = 15; t->pb = 31; t->mb = 7; t->mc = 15; break;
1494 case ATA_PIO1: t->pa = 10; t->pb = 24; t->mb = 7; t->mc = 15; break;
1495 case ATA_PIO2: t->pa = 6; t->pb = 16; t->mb = 7; t->mc = 15; break;
1496 case ATA_PIO3: t->pa = 4; t->pb = 12; t->mb = 7; t->mc = 15; break;
1497 case ATA_PIO4: t->pa = 2; t->pb = 8; t->mb = 7; t->mc = 15; break;
1498 case ATA_WDMA2: t->pa = 6; t->pb = 14; t->mb = 6; t->mc = 6; break;
1499 case ATA_UDMA2: t->pa = 6; t->pb = 14; t->mb = 2; t->mc = 2; break;
1500 case ATA_UDMA4: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break;
1501 case ATA_UDMA5: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break;
1502 }
1503 break;
1504 }
1505 pci_write_config(device_get_parent(atadev->channel->dev),
1506 0x60 + (devno<<2), timing, 4);
1507 }
1508
1509 static void
1510 hpt_timing(struct ata_device *atadev, int devno, int mode)
1511 {
1512 device_t parent = device_get_parent(atadev->channel->dev);
1513 u_int32_t chiptype = atadev->channel->chiptype;
1514 int chiprev = pci_get_revid(parent);
1515 u_int32_t timing;
1516
1517 if (chiptype == 0x00081103 && chiprev >= 0x07) {
1518 switch (mode) { /* HPT374 */
1519 case ATA_PIO0: timing = 0x0ac1f48a; break;
1520 case ATA_PIO1: timing = 0x0ac1f465; break;
1521 case ATA_PIO2: timing = 0x0a81f454; break;
1522 case ATA_PIO3: timing = 0x0a81f443; break;
1523 case ATA_PIO4: timing = 0x0a81f442; break;
1524 case ATA_WDMA2: timing = 0x22808242; break;
1525 case ATA_UDMA2: timing = 0x120c8242; break;
1526 case ATA_UDMA4: timing = 0x12ac8242; break;
1527 case ATA_UDMA5: timing = 0x12848242; break;
1528 case ATA_UDMA6: timing = 0x12808242; break;
1529 default: timing = 0x0d029d5e;
1530 }
1531 }
1532 else if ((chiptype == 0x00041103 && chiprev >= 0x05) ||
1533 (chiptype == 0x00051103 && chiprev >= 0x01)) {
1534 switch (mode) { /* HPT372 */
1535 case ATA_PIO0: timing = 0x0d029d5e; break;
1536 case ATA_PIO1: timing = 0x0d029d26; break;
1537 case ATA_PIO2: timing = 0x0c829ca6; break;
1538 case ATA_PIO3: timing = 0x0c829c84; break;
1539 case ATA_PIO4: timing = 0x0c829c62; break;
1540 case ATA_WDMA2: timing = 0x2c829262; break;
1541 case ATA_UDMA2: timing = 0x1c91dc62; break;
1542 case ATA_UDMA4: timing = 0x1c8ddc62; break;
1543 case ATA_UDMA5: timing = 0x1c6ddc62; break;
1544 case ATA_UDMA6: timing = 0x1c81dc62; break;
1545 default: timing = 0x0d029d5e;
1546 }
1547 }
1548 else if (chiptype == 0x00041103 && chiprev >= 0x03) {
1549 switch (mode) { /* HPT370 */
1550 case ATA_PIO0: timing = 0x06914e57; break;
1551 case ATA_PIO1: timing = 0x06914e43; break;
1552 case ATA_PIO2: timing = 0x06514e33; break;
1553 case ATA_PIO3: timing = 0x06514e22; break;
1554 case ATA_PIO4: timing = 0x06514e21; break;
1555 case ATA_WDMA2: timing = 0x26514e21; break;
1556 case ATA_UDMA2: timing = 0x16494e31; break;
1557 case ATA_UDMA4: timing = 0x16454e31; break;
1558 case ATA_UDMA5: timing = 0x16454e31; break;
1559 default: timing = 0x06514e57;
1560 }
1561 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4);
1562 }
1563 else { /* HPT36[68] */
1564 switch (pci_read_config(parent, 0x41 + (devno << 2), 1)) {
1565 case 0x85: /* 25Mhz */
1566 switch (mode) {
1567 case ATA_PIO0: timing = 0x40d08585; break;
1568 case ATA_PIO1: timing = 0x40d08572; break;
1569 case ATA_PIO2: timing = 0x40ca8542; break;
1570 case ATA_PIO3: timing = 0x40ca8532; break;
1571 case ATA_PIO4: timing = 0x40ca8521; break;
1572 case ATA_WDMA2: timing = 0x20ca8521; break;
1573 case ATA_UDMA2: timing = 0x10cf8521; break;
1574 case ATA_UDMA4: timing = 0x10c98521; break;
1575 default: timing = 0x01208585;
1576 }
1577 break;
1578 default:
1579 case 0xa7: /* 33MHz */
1580 switch (mode) {
1581 case ATA_PIO0: timing = 0x40d0a7aa; break;
1582 case ATA_PIO1: timing = 0x40d0a7a3; break;
1583 case ATA_PIO2: timing = 0x40d0a753; break;
1584 case ATA_PIO3: timing = 0x40c8a742; break;
1585 case ATA_PIO4: timing = 0x40c8a731; break;
1586 case ATA_WDMA2: timing = 0x20c8a731; break;
1587 case ATA_UDMA2: timing = 0x10caa731; break;
1588 case ATA_UDMA4: timing = 0x10c9a731; break;
1589 default: timing = 0x0120a7a7;
1590 }
1591 break;
1592 case 0xd9: /* 40Mhz */
1593 switch (mode) {
1594 case ATA_PIO0: timing = 0x4018d9d9; break;
1595 case ATA_PIO1: timing = 0x4010d9c7; break;
1596 case ATA_PIO2: timing = 0x4010d997; break;
1597 case ATA_PIO3: timing = 0x4010d974; break;
1598 case ATA_PIO4: timing = 0x4008d963; break;
1599 case ATA_WDMA2: timing = 0x2008d943; break;
1600 case ATA_UDMA2: timing = 0x100bd943; break;
1601 case ATA_UDMA4: timing = 0x100fd943; break;
1602 default: timing = 0x0120d9d9;
1603 }
1604 }
1605 }
1606 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4);
1607 }
1608
1609 static int
1610 hpt_cable80(struct ata_device *atadev)
1611 {
1612 device_t parent = device_get_parent(atadev->channel->dev);
1613 u_int8_t reg, val, res;
1614
1615 if (atadev->channel->chiptype == 0x00081103 && pci_get_function(parent) == 1) {
1616 reg = atadev->channel->unit ? 0x57 : 0x53;
1617 val = pci_read_config(parent, reg, 1);
1618 pci_write_config(parent, reg, val | 0x80, 1);
1619 }
1620 else {
1621 reg = 0x5b;
1622 val = pci_read_config(parent, reg, 1);
1623 pci_write_config(parent, reg, val & 0xfe, 1);
1624 }
1625 res = pci_read_config(parent, 0x5a, 1) & (atadev->channel->unit ? 0x01 : 0x02);
1626 pci_write_config(parent, reg, val, 1);
1627 return !res;
1628 }
DragonFly BSD