sys/dev/disk/ata/ata-all.h

   1 /*-
   2  * Copyright (c) 1998,1999,2000,2001,2002 Søren Schmidt <sos@FreeBSD.org>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer,
  10  *    without modification, immediately at the beginning of the file.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. The name of the author may not be used to endorse or promote products
  15  *    derived from this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * $FreeBSD: src/sys/dev/ata/ata-all.h,v 1.26.2.12 2003/01/30 07:19:59 sos Exp $
  29  * $DragonFly: src/sys/dev/disk/ata/ata-all.h,v 1.8 2006/10/12 04:02:37 y0netan1 Exp $
  30  */
  31
  32 #ifndef _SYS_MPIPE_H_
  33 #include <sys/mpipe.h>
  34 #endif
  35
  36 /* ATA register defines */
  37 #define ATA_DATA                        0x00    /* data register */
  38 #define ATA_ERROR                       0x01    /* (R) error register */
  39 #define         ATA_E_NM                0x02    /* no media */
  40 #define         ATA_E_ABORT             0x04    /* command aborted */
  41 #define         ATA_E_MCR               0x08    /* media change request */
  42 #define         ATA_E_IDNF              0x10    /* ID not found */
  43 #define         ATA_E_MC                0x20    /* media changed */
  44 #define         ATA_E_UNC               0x40    /* uncorrectable data */
  45 #define         ATA_E_ICRC              0x80    /* UDMA crc error */
  46
  47 #define ATA_FEATURE                     0x01    /* (W) feature register */
  48 #define         ATA_F_DMA               0x01    /* enable DMA */
  49 #define         ATA_F_OVL               0x02    /* enable overlap */
  50
  51 #define ATA_COUNT                       0x02    /* (W) sector count */
  52 #define ATA_IREASON                     0x02    /* (R) interrupt reason */
  53 #define         ATA_I_CMD               0x01    /* cmd (1) | data (0) */
  54 #define         ATA_I_IN                0x02    /* read (1) | write (0) */
  55 #define         ATA_I_RELEASE           0x04    /* released bus (1) */
  56 #define         ATA_I_TAGMASK           0xf8    /* tag mask */
  57
  58 #define ATA_SECTOR                      0x03    /* sector # */
  59 #define ATA_CYL_LSB                     0x04    /* cylinder# LSB */
  60 #define ATA_CYL_MSB                     0x05    /* cylinder# MSB */
  61 #define ATA_DRIVE                       0x06    /* Sector/Drive/Head register */
  62 #define         ATA_D_LBA               0x40    /* use LBA addressing */
  63 #define         ATA_D_IBM               0xa0    /* 512 byte sectors, ECC */
  64
  65 #define ATA_CMD                         0x07    /* command register */
  66 #define         ATA_C_NOP               0x00    /* NOP command */
  67 #define             ATA_C_F_FLUSHQUEUE  0x00    /* flush queued cmd's */
  68 #define             ATA_C_F_AUTOPOLL    0x01    /* start autopoll function */
  69 #define         ATA_C_ATAPI_RESET       0x08    /* reset ATAPI device */
  70 #define         ATA_C_READ              0x20    /* read command */
  71 #define         ATA_C_READ48            0x24    /* read command */
  72 #define         ATA_C_READ_DMA48        0x25    /* read w/DMA command */
  73 #define         ATA_C_READ_DMA_QUEUED48 0x26    /* read w/DMA QUEUED command */
  74 #define         ATA_C_READ_MUL48        0x29    /* read multi command */
  75 #define         ATA_C_WRITE             0x30    /* write command */
  76 #define         ATA_C_WRITE48           0x34    /* write command */
  77 #define         ATA_C_WRITE_DMA48       0x35    /* write w/DMA command */
  78 #define         ATA_C_WRITE_DMA_QUEUED48 0x36   /* write w/DMA QUEUED command */
  79 #define         ATA_C_WRITE_MUL48       0x39    /* write multi command */
  80 #define         ATA_C_PACKET_CMD        0xa0    /* packet command */
  81 #define         ATA_C_ATAPI_IDENTIFY    0xa1    /* get ATAPI params*/
  82 #define         ATA_C_SERVICE           0xa2    /* service command */
  83 #define         ATA_C_READ_MUL          0xc4    /* read multi command */
  84 #define         ATA_C_WRITE_MUL         0xc5    /* write multi command */
  85 #define         ATA_C_SET_MULTI         0xc6    /* set multi size command */
  86 #define         ATA_C_READ_DMA_QUEUED   0xc7    /* read w/DMA QUEUED command */
  87 #define         ATA_C_READ_DMA          0xc8    /* read w/DMA command */
  88 #define         ATA_C_WRITE_DMA         0xca    /* write w/DMA command */
  89 #define         ATA_C_WRITE_DMA_QUEUED  0xcc    /* write w/DMA QUEUED command */
  90 #define         ATA_C_SLEEP             0xe6    /* sleep command */
  91 #define         ATA_C_FLUSHCACHE        0xe7    /* flush cache to disk */
  92 #define         ATA_C_FLUSHCACHE48      0xea    /* flush cache to disk */
  93 #define         ATA_C_ATA_IDENTIFY      0xec    /* get ATA params */
  94 #define         ATA_C_SETFEATURES       0xef    /* features command */
  95 #define             ATA_C_F_SETXFER     0x03    /* set transfer mode */
  96 #define             ATA_C_F_ENAB_WCACHE 0x02    /* enable write cache */
  97 #define             ATA_C_F_DIS_WCACHE  0x82    /* disable write cache */
  98 #define             ATA_C_F_ENAB_RCACHE 0xaa    /* enable readahead cache */
  99 #define             ATA_C_F_DIS_RCACHE  0x55    /* disable readahead cache */
 100 #define             ATA_C_F_ENAB_RELIRQ 0x5d    /* enable release interrupt */
 101 #define             ATA_C_F_DIS_RELIRQ  0xdd    /* disable release interrupt */
 102 #define             ATA_C_F_ENAB_SRVIRQ 0x5e    /* enable service interrupt */
 103 #define             ATA_C_F_DIS_SRVIRQ  0xde    /* disable service interrupt */
 104
 105 #define ATA_STATUS                      0x07    /* status register */
 106 #define         ATA_S_ERROR             0x01    /* error */
 107 #define         ATA_S_INDEX             0x02    /* index */
 108 #define         ATA_S_CORR              0x04    /* data corrected */
 109 #define         ATA_S_DRQ               0x08    /* data request */
 110 #define         ATA_S_DSC               0x10    /* drive seek completed */
 111 #define         ATA_S_SERVICE           0x10    /* drive needs service */
 112 #define         ATA_S_DWF               0x20    /* drive write fault */
 113 #define         ATA_S_DMA               0x20    /* DMA ready */
 114 #define         ATA_S_READY             0x40    /* drive ready */
 115 #define         ATA_S_BUSY              0x80    /* busy */
 116
 117 #define ATA_ALTSTAT                     0x00    /* alternate status register */
 118 #define ATA_ALTOFFSET                   0x206   /* alternate registers offset */
 119 #define ATA_PCCARD_ALTOFFSET            0x0e    /* do for PCCARD devices */
 120 #define         ATA_A_IDS               0x02    /* disable interrupts */
 121 #define         ATA_A_RESET             0x04    /* RESET controller */
 122 #define         ATA_A_4BIT              0x08    /* 4 head bits */
 123
 124 /* misc defines */
 125 #define ATA_PRIMARY                     0x1f0
 126 #define ATA_SECONDARY                   0x170
 127 #define ATA_IOSIZE                      0x08
 128 #define ATA_ALTIOSIZE                   0x01
 129 #define ATA_BMIOSIZE                    0x08
 130 #define ATA_OP_FINISHED                 0x00
 131 #define ATA_OP_CONTINUES                0x01
 132 #define ATA_IOADDR_RID                  0
 133 #define ATA_ALTADDR_RID                 1
 134 #define ATA_BMADDR_RID                  2
 135 #define ATA_IRQ_RID                     0
 136 #define ATA_DEV(device)                 ((device == ATA_MASTER) ? 0 : 1)
 137
 138 /* busmaster DMA related defines */
 139 #define ATA_DMA_ENTRIES                 256
 140 #define ATA_DMA_EOT                     0x80000000
 141
 142 #define ATA_BMCMD_PORT                  0x00
 143 #define         ATA_BMCMD_START_STOP    0x01
 144 #define         ATA_BMCMD_WRITE_READ    0x08
 145
 146 #define ATA_BMDEVSPEC_0                 0x01
 147
 148 #define ATA_BMSTAT_PORT                 0x02
 149 #define         ATA_BMSTAT_ACTIVE       0x01
 150 #define         ATA_BMSTAT_ERROR        0x02
 151 #define         ATA_BMSTAT_INTERRUPT    0x04
 152 #define         ATA_BMSTAT_MASK         0x07
 153 #define         ATA_BMSTAT_DMA_MASTER   0x20
 154 #define         ATA_BMSTAT_DMA_SLAVE    0x40
 155 #define         ATA_BMSTAT_DMA_SIMPLEX  0x80
 156
 157 #define ATA_BMDEVSPEC_1                 0x03
 158 #define ATA_BMDTP_PORT                  0x04
 159
 160 /* structure for holding DMA address data */
 161 struct ata_dmaentry {
 162     u_int32_t base;
 163     u_int32_t count;
 164 };
 165
 166 struct ata_dmastate {
 167     bus_dma_tag_t       ddmatag;        /* data DMA tag */
 168     bus_dmamap_t        ddmamap;        /* data DMA map */
 169     bus_dma_tag_t       cdmatag;        /* control DMA tag */
 170     bus_dmamap_t        cdmamap;        /* control DMA map */
 171     struct ata_dmaentry *dmatab;        /* DMA transfer table */
 172     bus_addr_t          mdmatab;        /* bus address of dmatab */
 173     int                 flags;          /* debugging    */
 174 #define ATA_DS_ACTIVE   0x01            /* debugging */
 175 #define ATA_DS_READ     0x02            /* transaction is a read */
 176 };
 177
 178 /* structure describing an ATA/ATAPI device */
 179 struct ata_device {
 180     struct ata_channel          *channel;
 181     int                         unit;           /* unit number */
 182 #define ATA_MASTER                      0x00
 183 #define ATA_SLAVE                       0x10
 184
 185     char                        *name;          /* device name */
 186     struct ata_params           *param;         /* ata param structure */
 187     void                        *driver;        /* ptr to driver for device */
 188     int                         flags;
 189 #define         ATA_D_USE_CHS           0x0001
 190 #define         ATA_D_DETACHING         0x0002
 191 #define         ATA_D_MEDIA_CHANGED     0x0004
 192 #define         ATA_D_ENC_PRESENT       0x0008
 193
 194     int                         mode;           /* transfermode */
 195     int                         cmd;            /* last cmd executed */
 196     void                        *result;        /* misc data */
 197     struct ata_dmastate         dmastate;
 198 };
 199
 200 /* structure describing an ATA channel */
 201 struct ata_channel {
 202     struct device               *dev;           /* device handle */
 203     int                         unit;           /* channel number */
 204     struct resource             *r_io;          /* io addr resource handle */
 205     struct resource             *r_altio;       /* altio addr resource handle */
 206     struct resource             *r_bmio;        /* bmio addr resource handle */
 207     struct resource             *r_irq;         /* interrupt of this channel */
 208     void                        *ih;            /* interrupt handle */
 209     int (*intr_func)(struct ata_channel *);     /* interrupt function */
 210     u_int32_t                   chiptype;       /* pciid of controller chip */
 211     u_int32_t                   alignment;      /* dma engine min alignment */
 212     int                         flags;          /* controller flags */
 213 #define         ATA_NO_SLAVE            0x01
 214 #define         ATA_USE_16BIT           0x02
 215 #define         ATA_ATAPI_DMA_RO        0x04
 216 #define         ATA_QUEUED              0x08
 217 #define         ATA_DMA_ACTIVE          0x10
 218
 219     struct ata_device           device[2];      /* devices on this channel */
 220 #define         MASTER                  0x00
 221 #define         SLAVE                   0x01
 222
 223     int                         devices;        /* what is present */
 224 #define         ATA_ATA_MASTER          0x01
 225 #define         ATA_ATA_SLAVE           0x02
 226 #define         ATA_ATAPI_MASTER        0x04
 227 #define         ATA_ATAPI_SLAVE         0x08
 228
 229     u_int8_t                    status;         /* last controller status */
 230     u_int8_t                    error;          /* last controller error */
 231     int                         active;         /* active processing request */
 232 #define         ATA_IDLE                0x0000
 233 #define         ATA_IMMEDIATE           0x0001
 234 #define         ATA_WAIT_INTR           0x0002
 235 #define         ATA_WAIT_READY          0x0004
 236 #define         ATA_WAIT_MASK           0x0007
 237 #define         ATA_ACTIVE              0x0010
 238 #define         ATA_ACTIVE_ATA          0x0020
 239 #define         ATA_ACTIVE_ATAPI        0x0040
 240 #define         ATA_CONTROL             0x0080
 241
 242     TAILQ_HEAD(, ad_request)    ata_queue;      /* head of ATA queue */
 243     TAILQ_HEAD(, atapi_request) atapi_queue;    /* head of ATAPI queue */
 244     void                        *running;       /* currently running request */
 245     struct malloc_pipe          req_mpipe;      /* request allocations */
 246     struct malloc_pipe          dma_mpipe;      /* dma allocations */
 247 };
 248
 249 /* disk bay/enclosure related */
 250 #define         ATA_LED_OFF             0x00
 251 #define         ATA_LED_RED             0x01
 252 #define         ATA_LED_GREEN           0x02
 253 #define         ATA_LED_ORANGE          0x03
 254 #define         ATA_LED_MASK            0x03
 255
 256 /* externs */
 257 extern devclass_t ata_devclass;
 258 extern int      ata_mpipe_size;
 259
 260 /* public prototypes */
 261 int ata_probe(device_t);
 262 int ata_attach(device_t);
 263 int ata_detach(device_t);
 264 int ata_resume(device_t);
 265 int ata_suspend(device_t);
 266
 267 void ata_start(struct ata_channel *);
 268 void ata_reset(struct ata_channel *);
 269 int ata_reinit(struct ata_channel *);
 270 int ata_wait(struct ata_device *, u_int8_t);
 271 int ata_command(struct ata_device *, u_int8_t, u_int64_t, u_int16_t, u_int8_t, int);
 272 void ata_enclosure_leds(struct ata_device *, u_int8_t);
 273 void ata_enclosure_print(struct ata_device *);
 274 int ata_printf(struct ata_channel *, int, const char *, ...) __printflike(3, 4);
 275 int ata_prtdev(struct ata_device *, const char *, ...) __printflike(2, 3);
 276 void ata_set_name(struct ata_device *, char *, int);
 277 void ata_free_name(struct ata_device *);
 278 int ata_get_lun(u_int32_t *);
 279 int ata_test_lun(u_int32_t *, int);
 280 void ata_free_lun(u_int32_t *, int);
 281 char *ata_mode2str(int);
 282 int ata_pmode(struct ata_params *);
 283 int ata_wmode(struct ata_params *);
 284 int ata_umode(struct ata_params *);
 285 int ata_find_dev(device_t, u_int32_t, u_int32_t);
 286
 287 int ata_dmaalloc(struct ata_device *, int);
 288 void ata_dmafree(struct ata_device *);
 289 void ata_dmafreetags(struct ata_channel *);
 290 void ata_dmainit(struct ata_device *, int, int, int);
 291 int ata_dmasetup(struct ata_device *, caddr_t, int);
 292 int ata_dmastart(struct ata_device *, caddr_t, int32_t, int);
 293 int ata_dmastatus(struct ata_channel *);
 294 int ata_dmadone(struct ata_device *);
 295
 296 /* macros for locking a channel */
 297 #define ATA_LOCK_CH(ch, value)\
 298         (((ch)->active == ATA_IDLE) ? ((ch)->active = value) : 0)
 299
 300 #define ATA_SLEEPLOCK_CH(ch, value) {\
 301         while ((ch)->active != ATA_IDLE)\
 302             tsleep((caddr_t)&(ch), 0, "atalck", 1);\
 303         (ch)->active = value; }
 304
 305 #define ATA_FORCELOCK_CH(ch, value) \
 306         (ch)->active = value
 307
 308 #define ATA_UNLOCK_CH(ch) \
 309         (ch)->active = ATA_IDLE
 310
 311 /* macros to hide busspace uglyness */
 312 #define ATA_INB(res, offset) \
 313         bus_space_read_1(rman_get_bustag((res)), \
 314                          rman_get_bushandle((res)), (offset))
 315 #define ATA_INW(res, offset) \
 316         bus_space_read_2(rman_get_bustag((res)), \
 317                          rman_get_bushandle((res)), (offset))
 318 #define ATA_INL(res, offset) \
 319         bus_space_read_4(rman_get_bustag((res)), \
 320                          rman_get_bushandle((res)), (offset))
 321 #define ATA_INSW(res, offset, addr, count) \
 322         bus_space_read_multi_2(rman_get_bustag((res)), \
 323                                rman_get_bushandle((res)), \
 324                                (offset), (addr), (count))
 325 #define ATA_INSL(res, offset, addr, count) \
 326         bus_space_read_multi_4(rman_get_bustag((res)), \
 327                                rman_get_bushandle((res)), \
 328                                (offset), (addr), (count))
 329 #define ATA_OUTB(res, offset, value) \
 330         bus_space_write_1(rman_get_bustag((res)), \
 331                           rman_get_bushandle((res)), (offset), (value))
 332 #define ATA_OUTW(res, offset, value) \
 333         bus_space_write_2(rman_get_bustag((res)), \
 334                           rman_get_bushandle((res)), (offset), (value))
 335 #define ATA_OUTL(res, offset, value) \
 336         bus_space_write_4(rman_get_bustag((res)), \
 337                           rman_get_bushandle((res)), (offset), (value))
 338 #define ATA_OUTSW(res, offset, addr, count) \
 339         bus_space_write_multi_2(rman_get_bustag((res)), \
 340                                 rman_get_bushandle((res)), \
 341                                 (offset), (addr), (count))
 342 #define ATA_OUTSL(res, offset, addr, count) \
 343         bus_space_write_multi_4(rman_get_bustag((res)), \
 344                                 rman_get_bushandle((res)), \
 345                                 (offset), (addr), (count))