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NFE - Change default RX ring size from 128 -> 256, Adjust moderation timer.
[dragonfly.git] / sys / dev / disk / ahci / ahci.h
blob7d64a1af2fb211f4a785f1e616c288b483df307d
1 /*
2 * Copyright (c) 2006 David Gwynne <dlg@openbsd.org>
3 *
4 * Permission to use, copy, modify, and distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 *
16 * $OpenBSD: ahci.c,v 1.147 2009/02/16 21:19:07 miod Exp $
17 */
18
19 #if defined(__DragonFly__)
20 #include "ahci_dragonfly.h"
21 #else
22 #error "build for OS unknown"
23 #endif
24 #include "pmreg.h"
25 #include "atascsi.h"
26
27 /* change to AHCI_DEBUG for dmesg spam */
28 #define NO_AHCI_DEBUG
29
30 #ifdef AHCI_DEBUG
31 #define DPRINTF(m, f...) do { if ((ahcidebug & (m)) == (m)) kprintf(f); } \
32 while (0)
33 #define AHCI_D_TIMEOUT 0x00
34 #define AHCI_D_VERBOSE 0x01
35 #define AHCI_D_INTR 0x02
36 #define AHCI_D_XFER 0x08
37 int ahcidebug = AHCI_D_VERBOSE;
38 #else
39 #define DPRINTF(m, f...)
40 #endif
41
42 #define AHCI_PCI_ATI_SB600_MAGIC 0x40
43 #define AHCI_PCI_ATI_SB600_LOCKED 0x01
44
45 #define AHCI_REG_CAP 0x000 /* HBA Capabilities */
46 #define AHCI_REG_CAP_NP(_r) (((_r) & 0x1f)+1) /* Number of Ports */
47 #define AHCI_REG_CAP_SXS (1<<5) /* External SATA */
48 #define AHCI_REG_CAP_EMS (1<<6) /* Enclosure Mgmt */
49 #define AHCI_REG_CAP_CCCS (1<<7) /* Cmd Coalescing */
50 #define AHCI_REG_CAP_NCS(_r) ((((_r) & 0x1f00)>>8)+1) /* NCmds*/
51 #define AHCI_REG_CAP_PSC (1<<13) /* Partial State Capable */
52 #define AHCI_REG_CAP_SSC (1<<14) /* Slumber State Capable */
53 #define AHCI_REG_CAP_PMD (1<<15) /* PIO Multiple DRQ Block */
54 #define AHCI_REG_CAP_FBSS (1<<16) /* FIS-Based Switching */
55 #define AHCI_REG_CAP_SPM (1<<17) /* Port Multiplier */
56 #define AHCI_REG_CAP_SAM (1<<18) /* AHCI Only mode */
57 #define AHCI_REG_CAP_SNZO (1<<19) /* Non Zero DMA Offsets */
58 #define AHCI_REG_CAP_ISS (0xf<<20) /* Interface Speed Support */
59 #define AHCI_REG_CAP_ISS_G1 (0x1<<20) /* Gen 1 (1.5 Gbps) */
60 #define AHCI_REG_CAP_ISS_G1_2 (0x2<<20) /* Gen 1 and 2 (3 Gbps) */
61 #define AHCI_REG_CAP_SCLO (1<<24) /* Cmd List Override */
62 #define AHCI_REG_CAP_SAL (1<<25) /* Activity LED */
63 #define AHCI_REG_CAP_SALP (1<<26) /* Aggressive Link Pwr Mgmt */
64 #define AHCI_REG_CAP_SSS (1<<27) /* Staggered Spinup */
65 #define AHCI_REG_CAP_SMPS (1<<28) /* Mech Presence Switch */
66 #define AHCI_REG_CAP_SSNTF (1<<29) /* SNotification Register */
67 #define AHCI_REG_CAP_SNCQ (1<<30) /* Native Cmd Queuing */
68 #define AHCI_REG_CAP_S64A (1<<31) /* 64bit Addressing */
69 #define AHCI_FMT_CAP "\020" "\040S64A" "\037NCQ" "\036SSNTF" \
70 "\035SMPS" "\034SSS" "\033SALP" "\032SAL" \
71 "\031SCLO" "\024SNZO" "\023SAM" "\022SPM" \
72 "\021FBSS" "\020PMD" "\017SSC" "\016PSC" \
73 "\010CCCS" "\007EMS" "\006SXS"
74
75 #define AHCI_REG_GHC 0x004 /* Global HBA Control */
76 #define AHCI_REG_GHC_HR (1<<0) /* HBA Reset */
77 #define AHCI_REG_GHC_IE (1<<1) /* Interrupt Enable */
78 #define AHCI_REG_GHC_MRSM (1<<2) /* MSI Revert to Single Msg */
79 #define AHCI_REG_GHC_AE (1<<31) /* AHCI Enable */
80 #define AHCI_FMT_GHC "\020" "\040AE" "\003MRSM" "\002IE" "\001HR"
81
82 #define AHCI_REG_IS 0x008 /* Interrupt Status */
83 #define AHCI_REG_PI 0x00c /* Ports Implemented */
84
85 #define AHCI_REG_VS 0x010 /* AHCI Version */
86 #define AHCI_REG_VS_0_95 0x00000905 /* 0.95 */
87 #define AHCI_REG_VS_1_0 0x00010000 /* 1.0 */
88 #define AHCI_REG_VS_1_1 0x00010100 /* 1.1 */
89 #define AHCI_REG_VS_1_2 0x00010200 /* 1.2 */
90
91 #define AHCI_REG_CCC_CTL 0x014 /* Coalescing Control */
92 #define AHCI_REG_CCC_CTL_INT(_r) (((_r) & 0xf8) >> 3) /* CCC INT slot */
93
94 #define AHCI_REG_CCC_PORTS 0x018 /* Coalescing Ports */
95 #define AHCI_REG_EM_LOC 0x01c /* Enclosure Mgmt Location */
96 #define AHCI_REG_EM_CTL 0x020 /* Enclosure Mgmt Control */
97
98 #define AHCI_PORT_REGION(_p) (0x100 + ((_p) * 0x80))
99 #define AHCI_PORT_SIZE 0x80
100
101 #define AHCI_PREG_CLB 0x00 /* Cmd List Base Addr */
102 #define AHCI_PREG_CLBU 0x04 /* Cmd List Base Hi Addr */
103 #define AHCI_PREG_FB 0x08 /* FIS Base Addr */
104 #define AHCI_PREG_FBU 0x0c /* FIS Base Hi Addr */
105
106 #define AHCI_PREG_IS 0x10 /* Interrupt Status */
107 #define AHCI_PREG_IS_DHRS (1<<0) /* Device to Host FIS */
108 #define AHCI_PREG_IS_PSS (1<<1) /* PIO Setup FIS */
109 #define AHCI_PREG_IS_DSS (1<<2) /* DMA Setup FIS */
110 #define AHCI_PREG_IS_SDBS (1<<3) /* Set Device Bits FIS */
111 #define AHCI_PREG_IS_UFS (1<<4) /* Unknown FIS */
112 #define AHCI_PREG_IS_DPS (1<<5) /* Descriptor Processed */
113 #define AHCI_PREG_IS_PCS (1<<6) /* Port Change */
114 #define AHCI_PREG_IS_DMPS (1<<7) /* Device Mechanical Presence */
115 #define AHCI_PREG_IS_PRCS (1<<22) /* PhyRdy Change */
116 #define AHCI_PREG_IS_IPMS (1<<23) /* Incorrect Port Multiplier */
117 #define AHCI_PREG_IS_OFS (1<<24) /* Overflow */
118 #define AHCI_PREG_IS_INFS (1<<26) /* Interface Non-fatal Error */
119 #define AHCI_PREG_IS_IFS (1<<27) /* Interface Fatal Error */
120 #define AHCI_PREG_IS_HBDS (1<<28) /* Host Bus Data Error */
121 #define AHCI_PREG_IS_HBFS (1<<29) /* Host Bus Fatal Error */
122 #define AHCI_PREG_IS_TFES (1<<30) /* Task File Error */
123 #define AHCI_PREG_IS_CPDS (1<<31) /* Cold Presence Detect */
124 #define AHCI_PFMT_IS "\20" "\040CPDS" "\037TFES" "\036HBFS" \
125 "\035HBDS" "\034IFS" "\033INFS" "\031OFS" \
126 "\030IPMS" "\027PRCS" "\010DMPS" "\006DPS" \
127 "\007PCS" "\005UFS" "\004SDBS" "\003DSS" \
128 "\002PSS" "\001DHRS"
129
130 #define AHCI_PREG_IE 0x14 /* Interrupt Enable */
131 #define AHCI_PREG_IE_DHRE (1<<0) /* Device to Host FIS */
132 #define AHCI_PREG_IE_PSE (1<<1) /* PIO Setup FIS */
133 #define AHCI_PREG_IE_DSE (1<<2) /* DMA Setup FIS */
134 #define AHCI_PREG_IE_SDBE (1<<3) /* Set Device Bits FIS */
135 #define AHCI_PREG_IE_UFE (1<<4) /* Unknown FIS */
136 #define AHCI_PREG_IE_DPE (1<<5) /* Descriptor Processed */
137 #define AHCI_PREG_IE_PCE (1<<6) /* Port Change */
138 #define AHCI_PREG_IE_DMPE (1<<7) /* Device Mechanical Presence */
139 #define AHCI_PREG_IE_PRCE (1<<22) /* PhyRdy Change */
140 #define AHCI_PREG_IE_IPME (1<<23) /* Incorrect Port Multiplier */
141 #define AHCI_PREG_IE_OFE (1<<24) /* Overflow */
142 #define AHCI_PREG_IE_INFE (1<<26) /* Interface Non-fatal Error */
143 #define AHCI_PREG_IE_IFE (1<<27) /* Interface Fatal Error */
144 #define AHCI_PREG_IE_HBDE (1<<28) /* Host Bus Data Error */
145 #define AHCI_PREG_IE_HBFE (1<<29) /* Host Bus Fatal Error */
146 #define AHCI_PREG_IE_TFEE (1<<30) /* Task File Error */
147 #define AHCI_PREG_IE_CPDE (1<<31) /* Cold Presence Detect */
148 #define AHCI_PFMT_IE "\20" "\040CPDE" "\037TFEE" "\036HBFE" \
149 "\035HBDE" "\034IFE" "\033INFE" "\031OFE" \
150 "\030IPME" "\027PRCE" "\010DMPE" "\007PCE" \
151 "\006DPE" "\005UFE" "\004SDBE" "\003DSE" \
152 "\002PSE" "\001DHRE"
153
154 #define AHCI_PREG_CMD 0x18 /* Command and Status */
155 #define AHCI_PREG_CMD_ST (1<<0) /* Start */
156 #define AHCI_PREG_CMD_SUD (1<<1) /* Spin Up Device */
157 #define AHCI_PREG_CMD_POD (1<<2) /* Power On Device */
158 #define AHCI_PREG_CMD_CLO (1<<3) /* Command List Override */
159 #define AHCI_PREG_CMD_FRE (1<<4) /* FIS Receive Enable */
160 #define AHCI_PREG_CMD_CCS(_r) (((_r) >> 8) & 0x1f) /* Curr CmdSlot# */
161 #define AHCI_PREG_CMD_MPSS (1<<13) /* Mech Presence State */
162 #define AHCI_PREG_CMD_FR (1<<14) /* FIS Receive Running */
163 #define AHCI_PREG_CMD_CR (1<<15) /* Command List Running */
164 #define AHCI_PREG_CMD_CPS (1<<16) /* Cold Presence State */
165 #define AHCI_PREG_CMD_PMA (1<<17) /* Port Multiplier Attached */
166 #define AHCI_PREG_CMD_HPCP (1<<18) /* Hot Plug Capable */
167 #define AHCI_PREG_CMD_MPSP (1<<19) /* Mech Presence Switch */
168 #define AHCI_PREG_CMD_CPD (1<<20) /* Cold Presence Detection */
169 #define AHCI_PREG_CMD_ESP (1<<21) /* External SATA Port */
170 #define AHCI_PREG_CMD_ATAPI (1<<24) /* Device is ATAPI */
171 #define AHCI_PREG_CMD_DLAE (1<<25) /* Drv LED on ATAPI Enable */
172 #define AHCI_PREG_CMD_ALPE (1<<26) /* Aggro Pwr Mgmt Enable */
173 #define AHCI_PREG_CMD_ASP (1<<27) /* Aggro Slumber/Partial */
174 #define AHCI_PREG_CMD_ICC 0xf0000000 /* Interface Comm Ctrl */
175 #define AHCI_PREG_CMD_ICC_SLUMBER 0x60000000
176 #define AHCI_PREG_CMD_ICC_PARTIAL 0x20000000
177 #define AHCI_PREG_CMD_ICC_ACTIVE 0x10000000
178 #define AHCI_PREG_CMD_ICC_IDLE 0x00000000
179 #define AHCI_PFMT_CMD "\020" "\034ASP" "\033ALPE" "\032DLAE" \
180 "\031ATAPI" "\026ESP" "\025CPD" "\024MPSP" \
181 "\023HPCP" "\022PMA" "\021CPS" "\020CR" \
182 "\017FR" "\016MPSS" "\005FRE" "\004CLO" \
183 "\003POD" "\002SUD" "\001ST"
184
185 #define AHCI_PREG_TFD 0x20 /* Task File Data*/
186 #define AHCI_PREG_TFD_STS 0xff
187 #define AHCI_PREG_TFD_STS_ERR (1<<0)
188 #define AHCI_PREG_TFD_STS_DRQ (1<<3)
189 #define AHCI_PREG_TFD_STS_BSY (1<<7)
190 #define AHCI_PREG_TFD_ERR 0xff00
191
192 #define AHCI_PFMT_TFD_STS "\20" "\010BSY" "\004DRQ" "\001ERR"
193 #define AHCI_PREG_SIG 0x24 /* Signature */
194
195 #define AHCI_PREG_SSTS 0x28 /* SATA Status */
196 #define AHCI_PREG_SSTS_DET 0xf /* Device Detection */
197 #define AHCI_PREG_SSTS_DET_NONE 0x0
198 #define AHCI_PREG_SSTS_DET_DEV_NE 0x1
199 #define AHCI_PREG_SSTS_DET_DEV 0x3
200 #define AHCI_PREG_SSTS_DET_PHYOFFLINE 0x4
201 #define AHCI_PREG_SSTS_SPD 0xf0 /* Current Interface Speed */
202 #define AHCI_PREG_SSTS_SPD_NONE 0x00
203 #define AHCI_PREG_SSTS_SPD_GEN1 0x10
204 #define AHCI_PREG_SSTS_SPD_GEN2 0x20
205 #define AHCI_PREG_SSTS_IPM 0xf00 /* Interface Power Management */
206 #define AHCI_PREG_SSTS_IPM_NONE 0x000
207 #define AHCI_PREG_SSTS_IPM_ACTIVE 0x100
208 #define AHCI_PREG_SSTS_IPM_PARTIAL 0x200
209 #define AHCI_PREG_SSTS_IPM_SLUMBER 0x600
210
211 #define AHCI_PREG_SCTL 0x2c /* SATA Control */
212 #define AHCI_PREG_SCTL_DET 0xf /* Device Detection */
213 #define AHCI_PREG_SCTL_DET_NONE 0x0
214 #define AHCI_PREG_SCTL_DET_INIT 0x1
215 #define AHCI_PREG_SCTL_DET_DISABLE 0x4
216 #define AHCI_PREG_SCTL_SPD 0xf0 /* Speed Allowed */
217 #define AHCI_PREG_SCTL_SPD_ANY 0x00
218 #define AHCI_PREG_SCTL_SPD_GEN1 0x10
219 #define AHCI_PREG_SCTL_SPD_GEN2 0x20
220 #define AHCI_PREG_SCTL_IPM 0xf00 /* Interface Power Management */
221 #define AHCI_PREG_SCTL_IPM_NONE 0x000
222 #define AHCI_PREG_SCTL_IPM_NOPARTIAL 0x100
223 #define AHCI_PREG_SCTL_IPM_NOSLUMBER 0x200
224 #define AHCI_PREG_SCTL_IPM_DISABLED 0x300
225 #define AHCI_PREG_SCTL_SPM 0xf000 /* Select Power Management */
226 #define AHCI_PREG_SCTL_SPM_NONE 0x0000
227 #define AHCI_PREG_SCTL_SPM_NOPARTIAL 0x1000
228 #define AHCI_PREG_SCTL_SPM_NOSLUMBER 0x2000
229 #define AHCI_PREG_SCTL_SPM_DISABLED 0x3000
230 #define AHCI_PREG_SCTL_PMP 0xf0000 /* Set PM port for xmit FISes */
231 #define AHCI_PREG_SCTL_PMP_SHIFT 16
232
233 #define AHCI_PREG_SERR 0x30 /* SATA Error */
234 #define AHCI_PREG_SERR_ERR_I (1<<0) /* Recovered Data Integrity */
235 #define AHCI_PREG_SERR_ERR_M (1<<1) /* Recovered Communications */
236 #define AHCI_PREG_SERR_ERR_T (1<<8) /* Transient Data Integrity */
237 #define AHCI_PREG_SERR_ERR_C (1<<9) /* Persistent Comm/Data */
238 #define AHCI_PREG_SERR_ERR_P (1<<10) /* Protocol */
239 #define AHCI_PREG_SERR_ERR_E (1<<11) /* Internal */
240 #define AHCI_PREG_SERR_DIAG_N (1<<16) /* PhyRdy Change */
241 #define AHCI_PREG_SERR_DIAG_I (1<<17) /* Phy Internal Error */
242 #define AHCI_PREG_SERR_DIAG_W (1<<18) /* Comm Wake */
243 #define AHCI_PREG_SERR_DIAG_B (1<<19) /* 10B to 8B Decode Error */
244 #define AHCI_PREG_SERR_DIAG_D (1<<20) /* Disparity Error */
245 #define AHCI_PREG_SERR_DIAG_C (1<<21) /* CRC Error */
246 #define AHCI_PREG_SERR_DIAG_H (1<<22) /* Handshake Error */
247 #define AHCI_PREG_SERR_DIAG_S (1<<23) /* Link Sequence Error */
248 #define AHCI_PREG_SERR_DIAG_T (1<<24) /* Transport State Trans Err */
249 #define AHCI_PREG_SERR_DIAG_F (1<<25) /* Unknown FIS Type */
250 #define AHCI_PREG_SERR_DIAG_X (1<<26) /* Exchanged */
251
252 #define AHCI_PFMT_SERR "\020" \
253 "\033DIAG.X" "\032DIAG.F" "\031DIAG.T" "\030DIAG.S" \
254 "\027DIAG.H" "\026DIAG.C" "\025DIAG.D" "\024DIAG.B" \
255 "\023DIAG.W" "\022DIAG.I" "\021DIAG.N" \
256 "\014ERR.E" "\013ERR.P" "\012ERR.C" "\011ERR.T" \
257 "\002ERR.M" "\001ERR.I"
258
259 #define AHCI_PREG_SACT 0x34 /* SATA Active */
260 #define AHCI_PREG_CI 0x38 /* Command Issue */
261 #define AHCI_PREG_CI_ALL_SLOTS 0xffffffff
262 #define AHCI_PREG_SNTF 0x3c /* SNotification */
263
264 /*
265 * AHCI mapped structures
266 */
267 struct ahci_cmd_hdr {
268 u_int16_t flags;
269 #define AHCI_CMD_LIST_FLAG_CFL 0x001f /* Command FIS Length */
270 #define AHCI_CMD_LIST_FLAG_A (1<<5) /* ATAPI */
271 #define AHCI_CMD_LIST_FLAG_W (1<<6) /* Write */
272 #define AHCI_CMD_LIST_FLAG_P (1<<7) /* Prefetchable */
273 #define AHCI_CMD_LIST_FLAG_R (1<<8) /* Reset */
274 #define AHCI_CMD_LIST_FLAG_B (1<<9) /* BIST */
275 #define AHCI_CMD_LIST_FLAG_C (1<<10) /* Clear Busy upon R_OK */
276 #define AHCI_CMD_LIST_FLAG_PMP 0xf000 /* Port Multiplier Port */
277 #define AHCI_CMD_LIST_FLAG_PMP_SHIFT 12
278 u_int16_t prdtl; /* sgl len */
279
280 u_int32_t prdbc; /* transferred byte count */
281
282 u_int32_t ctba_lo;
283 u_int32_t ctba_hi;
284
285 u_int32_t reserved[4];
286 } __packed;
287
288 struct ahci_rfis {
289 u_int8_t dsfis[28];
290 u_int8_t reserved1[4];
291 u_int8_t psfis[24];
292 u_int8_t reserved2[8];
293 u_int8_t rfis[24];
294 u_int8_t reserved3[4];
295 u_int8_t sdbfis[4];
296 u_int8_t ufis[64];
297 u_int8_t reserved4[96];
298 } __packed;
299
300 struct ahci_prdt {
301 u_int32_t dba_lo;
302 u_int32_t dba_hi;
303 u_int32_t reserved;
304 u_int32_t flags;
305 #define AHCI_PRDT_FLAG_INTR (1<<31) /* interrupt on completion */
306 } __packed;
307
308 /*
309 * The base command table structure is 128 bytes. Each prdt is 16 bytes.
310 * We need to accomodate MAXPHYS (128K) which is at least 32 entries,
311 * plus one for page slop.
312 *
313 * Making the ahci_cmd_table 1024 bytes (a reasonable power of 2)
314 * thus requires MAX_PRDT to be set to 56.
315 */
316 #define AHCI_MAX_PRDT 56
317 #define AHCI_MAX_PMPORTS 16
318
319 #if MAXPHYS / PAGE_SIZE + 1 > AHCI_MAX_PRDT
320 #error "AHCI_MAX_PRDT is not big enough"
321 #endif
322
323 struct ahci_cmd_table {
324 u_int8_t cfis[64]; /* Command FIS */
325 u_int8_t acmd[16]; /* ATAPI Command */
326 u_int8_t reserved[48];
327
328 struct ahci_prdt prdt[AHCI_MAX_PRDT];
329 } __packed;
330
331 #define AHCI_MAX_PORTS 32
332
333 struct ahci_dmamem {
334 bus_dma_tag_t adm_tag;
335 bus_dmamap_t adm_map;
336 bus_dma_segment_t adm_seg;
337 bus_addr_t adm_busaddr;
338 caddr_t adm_kva;
339 };
340 #define AHCI_DMA_MAP(_adm) ((_adm)->adm_map)
341 #define AHCI_DMA_DVA(_adm) ((_adm)->adm_busaddr)
342 #define AHCI_DMA_KVA(_adm) ((void *)(_adm)->adm_kva)
343
344 struct ahci_softc;
345 struct ahci_port;
346 struct ahci_device;
347
348 struct ahci_ccb {
349 /* ATA xfer associated with this CCB. Must be 1st struct member. */
350 struct ata_xfer ccb_xa;
351 struct callout ccb_timeout;
352
353 int ccb_slot;
354 struct ahci_port *ccb_port;
355
356 bus_dmamap_t ccb_dmamap;
357 struct ahci_cmd_hdr *ccb_cmd_hdr;
358 struct ahci_cmd_table *ccb_cmd_table;
359
360 void (*ccb_done)(struct ahci_ccb *);
361
362 TAILQ_ENTRY(ahci_ccb) ccb_entry;
363 };
364
365 struct ahci_port {
366 struct ahci_softc *ap_sc;
367 bus_space_handle_t ap_ioh;
368
369 int ap_num;
370 int ap_pmcount;
371 int ap_flags;
372 #define AP_F_BUS_REGISTERED 0x0001
373 #define AP_F_CAM_ATTACHED 0x0002
374 #define AP_F_IN_RESET 0x0004
375 #define AP_F_SCAN_RUNNING 0x0008
376 #define AP_F_SCAN_REQUESTED 0x0010
377 #define AP_F_SCAN_COMPLETED 0x0020
378 #define AP_F_IGNORE_IFS 0x0040
379 #define AP_F_IFS_IGNORED 0x0080
380 #define AP_F_IFS_OCCURED 0x0100
381 #define AP_F_EXCLUSIVE_ACCESS 0x0200
382 #define AP_F_ERR_CCB_RESERVED 0x0400
383 int ap_signal; /* os per-port thread sig */
384 thread_t ap_thread; /* os per-port thread */
385 struct lock ap_lock; /* os per-port lock */
386 #define AP_SIGF_INIT 0x0001
387 #define AP_SIGF_TIMEOUT 0x0002
388 #define AP_SIGF_PORTINT 0x0004
389 #define AP_SIGF_THREAD_SYNC 0x0008
390 #define AP_SIGF_STOP 0x8000
391 struct cam_sim *ap_sim;
392
393 struct ahci_rfis *ap_rfis;
394 struct ahci_dmamem *ap_dmamem_rfis;
395
396 struct ahci_dmamem *ap_dmamem_cmd_list;
397 struct ahci_dmamem *ap_dmamem_cmd_table;
398
399 u_int32_t ap_active; /* active CI command bmask */
400 u_int32_t ap_active_cnt; /* active CI command count */
401 u_int32_t ap_sactive; /* active SACT command bmask */
402 u_int32_t ap_expired; /* deferred expired bmask */
403 u_int32_t ap_intmask; /* interrupts we care about */
404 struct ahci_ccb *ap_ccbs;
405 struct ahci_ccb *ap_err_ccb; /* always CCB SLOT 1 */
406 int ap_run_flags; /* used to check excl mode */
407
408 TAILQ_HEAD(, ahci_ccb) ap_ccb_free;
409 TAILQ_HEAD(, ahci_ccb) ap_ccb_pending;
410 struct lock ap_ccb_lock;
411
412 int ap_type; /* ATA_PORT_T_xxx */
413 int ap_probe; /* ATA_PROBE_xxx */
414 struct ata_port *ap_ata[AHCI_MAX_PMPORTS];
415
416 u_int32_t ap_state;
417 #define AP_S_NORMAL 0
418 #define AP_S_FATAL_ERROR 1
419
420 /* For error recovery. */
421 u_int32_t ap_err_saved_sactive;
422 u_int32_t ap_err_saved_active;
423 u_int32_t ap_err_saved_active_cnt;
424
425 u_int8_t *ap_err_scratch;
426
427 char ap_name[16];
428 };
429
430 #define PORTNAME(_ap) ((_ap)->ap_name)
431 #define ATANAME(_ap, _at) ((_at) ? (_at)->at_name : (_ap)->ap_name)
432
433 struct ahci_softc {
434 device_t sc_dev;
435 const struct ahci_device *sc_ad; /* special casing */
436
437 struct resource *sc_irq; /* bus resources */
438 struct resource *sc_regs; /* bus resources */
439 bus_space_tag_t sc_iot; /* split from sc_regs */
440 bus_space_handle_t sc_ioh; /* split from sc_regs */
441
442 int sc_rid_irq; /* saved bus RIDs */
443 int sc_rid_regs;
444 u_int32_t sc_cap; /* capabilities */
445 int sc_numports;
446 u_int32_t sc_portmask;
447
448 void *sc_irq_handle; /* installed irq vector */
449
450 bus_dma_tag_t sc_tag_rfis; /* bus DMA tags */
451 bus_dma_tag_t sc_tag_cmdh;
452 bus_dma_tag_t sc_tag_cmdt;
453 bus_dma_tag_t sc_tag_data;
454
455 int sc_flags;
456 #define AHCI_F_NO_NCQ (1<<0)
457 #define AHCI_F_IGN_FR (1<<1)
458 #define AHCI_F_INT_GOOD (1<<2)
459
460 u_int sc_ncmds;
461
462 struct ahci_port *sc_ports[AHCI_MAX_PORTS];
463
464 #ifdef AHCI_COALESCE
465 u_int32_t sc_ccc_mask;
466 u_int32_t sc_ccc_ports;
467 u_int32_t sc_ccc_ports_cur;
468 #endif
469 };
470 #define DEVNAME(_s) ((_s)->sc_dev.dv_xname)
471
472 struct ahci_device {
473 pci_vendor_id_t ad_vendor;
474 pci_product_id_t ad_product;
475 int (*ad_attach)(device_t dev);
476 int (*ad_detach)(device_t dev);
477 char *name;
478 };
479
480 /* Wait for all bits in _b to be cleared */
481 #define ahci_pwait_clr(_ap, _r, _b) \
482 ahci_pwait_eq((_ap), AHCI_PWAIT_TIMEOUT, (_r), (_b), 0)
483 #define ahci_pwait_clr_to(_ap, _to, _r, _b) \
484 ahci_pwait_eq((_ap), _to, (_r), (_b), 0)
485
486 /* Wait for all bits in _b to be set */
487 #define ahci_pwait_set(_ap, _r, _b) \
488 ahci_pwait_eq((_ap), AHCI_PWAIT_TIMEOUT, (_r), (_b), (_b))
489 #define ahci_pwait_set_to(_ap, _to, _r, _b) \
490 ahci_pwait_eq((_ap), _to, (_r), (_b), (_b))
491
492 #define AHCI_PWAIT_TIMEOUT 1000
493
494 const struct ahci_device *ahci_lookup_device(device_t dev);
495 int ahci_init(struct ahci_softc *);
496 int ahci_port_init(struct ahci_port *ap);
497 int ahci_port_alloc(struct ahci_softc *, u_int);
498 void ahci_port_state_machine(struct ahci_port *ap, int initial);
499 void ahci_port_free(struct ahci_softc *, u_int);
500 int ahci_port_reset(struct ahci_port *, struct ata_port *at, int);
501
502 u_int32_t ahci_read(struct ahci_softc *, bus_size_t);
503 void ahci_write(struct ahci_softc *, bus_size_t, u_int32_t);
504 int ahci_wait_ne(struct ahci_softc *, bus_size_t, u_int32_t, u_int32_t);
505 u_int32_t ahci_pread(struct ahci_port *, bus_size_t);
506 void ahci_pwrite(struct ahci_port *, bus_size_t, u_int32_t);
507 int ahci_pwait_eq(struct ahci_port *, int, bus_size_t,
508 u_int32_t, u_int32_t);
509 void ahci_intr(void *);
510 void ahci_port_intr(struct ahci_port *ap, int blockable);
511
512 int ahci_port_start(struct ahci_port *ap);
513 int ahci_port_stop(struct ahci_port *ap, int stop_fis_rx);
514 int ahci_port_clo(struct ahci_port *ap);
515 void ahci_flush_tfd(struct ahci_port *ap);
516
517 int ahci_cam_attach(struct ahci_port *ap);
518 void ahci_cam_changed(struct ahci_port *ap, struct ata_port *at, int found);
519 void ahci_cam_detach(struct ahci_port *ap);
520 int ahci_cam_probe(struct ahci_port *ap, struct ata_port *at);
521
522 struct ata_xfer *ahci_ata_get_xfer(struct ahci_port *ap, struct ata_port *at);
523 void ahci_ata_put_xfer(struct ata_xfer *xa);
524 int ahci_ata_cmd(struct ata_xfer *xa);
525
526 int ahci_pm_port_probe(struct ahci_port *ap, int);
527 int ahci_pm_port_init(struct ahci_port *ap, struct ata_port *at);
528 int ahci_pm_identify(struct ahci_port *ap);
529 int ahci_pm_set_feature(struct ahci_port *ap, int feature, int enable);
530 int ahci_pm_hardreset(struct ahci_port *ap, int target, int hard);
531 int ahci_pm_softreset(struct ahci_port *ap, int target);
532 int ahci_pm_phy_status(struct ahci_port *ap, int target, u_int32_t *datap);
533 int ahci_pm_read(struct ahci_port *ap, int target,
534 int which, u_int32_t *res);
535 int ahci_pm_write(struct ahci_port *ap, int target,
536 int which, u_int32_t data);
537 void ahci_pm_check_good(struct ahci_port *ap, int target);
538 void ahci_ata_cmd_timeout(struct ahci_ccb *ccb);
539 void ahci_quick_timeout(struct ahci_ccb *ccb);
540 struct ahci_ccb *ahci_get_ccb(struct ahci_port *ap);
541 void ahci_put_ccb(struct ahci_ccb *ccb);
542 struct ahci_ccb *ahci_get_err_ccb(struct ahci_port *);
543 void ahci_put_err_ccb(struct ahci_ccb *);
544 int ahci_poll(struct ahci_ccb *ccb, int timeout,
545 void (*timeout_fn)(struct ahci_ccb *));
546
547 int ahci_port_signature_detect(struct ahci_port *ap, struct ata_port *at);
548 void ahci_port_thread_core(struct ahci_port *ap, int mask);
549
550 void ahci_os_sleep(int ms);
551 void ahci_os_hardsleep(int us);
552 int ahci_os_softsleep(void);
553 void ahci_os_start_port(struct ahci_port *ap);
554 void ahci_os_stop_port(struct ahci_port *ap);
555 void ahci_os_signal_port_thread(struct ahci_port *ap, int mask);
556 void ahci_os_lock_port(struct ahci_port *ap);
557 int ahci_os_lock_port_nb(struct ahci_port *ap);
558 void ahci_os_unlock_port(struct ahci_port *ap);
559
560 extern u_int32_t AhciForceGen1;
561 extern u_int32_t AhciNoFeatures;
DragonFly BSD