?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
drm: Consolidate memory allocation types
[dragonfly.git] / sys / dev / drm / radeon / radeon_cp.c
blob92075f21df4585dc015c8d48a3982083935bc92b
1 /* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */
2 /*
3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * Copyright 2007 Advanced Micro Devices, Inc.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 *
27 * Authors:
28 * Kevin E. Martin <martin@valinux.com>
29 * Gareth Hughes <gareth@valinux.com>
30 *
31 * $FreeBSD: head/sys/dev/drm2/radeon/radeon_cp.c 254885 2013-08-25 19:37:15Z dumbbell $
32 */
33
34 #include <sys/param.h>
35 #include <sys/systm.h>
36 #include <sys/linker.h>
37 #include <sys/firmware.h>
38
39 #include <drm/drmP.h>
40 #include <uapi_drm/radeon_drm.h>
41 #include "radeon_drv.h"
42 #include "r300_reg.h"
43
44 #define RADEON_FIFO_DEBUG 0
45
46 /* Firmware Names */
47 #define FIRMWARE_R100 "radeonkmsfw_R100_cp"
48 #define FIRMWARE_R200 "radeonkmsfw_R200_cp"
49 #define FIRMWARE_R300 "radeonkmsfw_R300_cp"
50 #define FIRMWARE_R420 "radeonkmsfw_R420_cp"
51 #define FIRMWARE_RS690 "radeonkmsfw_RS690_cp"
52 #define FIRMWARE_RS600 "radeonkmsfw_RS600_cp"
53 #define FIRMWARE_R520 "radeonkmsfw_R520_cp"
54
55 static int radeon_do_cleanup_cp(struct drm_device * dev);
56 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv);
57
58 u32 radeon_read_ring_rptr(drm_radeon_private_t *dev_priv, u32 off)
59 {
60 u32 val;
61
62 if (dev_priv->flags & RADEON_IS_AGP) {
63 val = DRM_READ32(dev_priv->ring_rptr, off);
64 } else {
65 val = *(((volatile u32 *)
66 dev_priv->ring_rptr->handle) +
67 (off / sizeof(u32)));
68 val = le32_to_cpu(val);
69 }
70 return val;
71 }
72
73 u32 radeon_get_ring_head(drm_radeon_private_t *dev_priv)
74 {
75 if (dev_priv->writeback_works)
76 return radeon_read_ring_rptr(dev_priv, 0);
77 else {
78 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
79 return RADEON_READ(R600_CP_RB_RPTR);
80 else
81 return RADEON_READ(RADEON_CP_RB_RPTR);
82 }
83 }
84
85 void radeon_write_ring_rptr(drm_radeon_private_t *dev_priv, u32 off, u32 val)
86 {
87 if (dev_priv->flags & RADEON_IS_AGP)
88 DRM_WRITE32(dev_priv->ring_rptr, off, val);
89 else
90 *(((volatile u32 *) dev_priv->ring_rptr->handle) +
91 (off / sizeof(u32))) = cpu_to_le32(val);
92 }
93
94 void radeon_set_ring_head(drm_radeon_private_t *dev_priv, u32 val)
95 {
96 radeon_write_ring_rptr(dev_priv, 0, val);
97 }
98
99 u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index)
100 {
101 if (dev_priv->writeback_works) {
102 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
103 return radeon_read_ring_rptr(dev_priv,
104 R600_SCRATCHOFF(index));
105 else
106 return radeon_read_ring_rptr(dev_priv,
107 RADEON_SCRATCHOFF(index));
108 } else {
109 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
110 return RADEON_READ(R600_SCRATCH_REG0 + 4*index);
111 else
112 return RADEON_READ(RADEON_SCRATCH_REG0 + 4*index);
113 }
114 }
115
116 static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
117 {
118 u32 ret;
119 RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
120 ret = RADEON_READ(R520_MC_IND_DATA);
121 RADEON_WRITE(R520_MC_IND_INDEX, 0);
122 return ret;
123 }
124
125 static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
126 {
127 u32 ret;
128 RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff);
129 ret = RADEON_READ(RS480_NB_MC_DATA);
130 RADEON_WRITE(RS480_NB_MC_INDEX, 0xff);
131 return ret;
132 }
133
134 static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
135 {
136 u32 ret;
137 RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
138 ret = RADEON_READ(RS690_MC_DATA);
139 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK);
140 return ret;
141 }
142
143 static u32 RS600_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
144 {
145 u32 ret;
146 RADEON_WRITE(RS600_MC_INDEX, ((addr & RS600_MC_ADDR_MASK) |
147 RS600_MC_IND_CITF_ARB0));
148 ret = RADEON_READ(RS600_MC_DATA);
149 return ret;
150 }
151
152 static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
153 {
154 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
155 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
156 return RS690_READ_MCIND(dev_priv, addr);
157 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
158 return RS600_READ_MCIND(dev_priv, addr);
159 else
160 return RS480_READ_MCIND(dev_priv, addr);
161 }
162
163 u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
164 {
165
166 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
167 return RADEON_READ(R700_MC_VM_FB_LOCATION);
168 else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
169 return RADEON_READ(R600_MC_VM_FB_LOCATION);
170 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
171 return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
172 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
173 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
174 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
175 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
176 return RS600_READ_MCIND(dev_priv, RS600_MC_FB_LOCATION);
177 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
178 return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
179 else
180 return RADEON_READ(RADEON_MC_FB_LOCATION);
181 }
182
183 static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
184 {
185 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
186 RADEON_WRITE(R700_MC_VM_FB_LOCATION, fb_loc);
187 else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
188 RADEON_WRITE(R600_MC_VM_FB_LOCATION, fb_loc);
189 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
190 R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
191 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
192 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
193 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
194 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
195 RS600_WRITE_MCIND(RS600_MC_FB_LOCATION, fb_loc);
196 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
197 R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
198 else
199 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
200 }
201
202 void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
203 {
204 /*R6xx/R7xx: AGP_TOP and BOT are actually 18 bits each */
205 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) {
206 RADEON_WRITE(R700_MC_VM_AGP_BOT, agp_loc & 0xffff); /* FIX ME */
207 RADEON_WRITE(R700_MC_VM_AGP_TOP, (agp_loc >> 16) & 0xffff);
208 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
209 RADEON_WRITE(R600_MC_VM_AGP_BOT, agp_loc & 0xffff); /* FIX ME */
210 RADEON_WRITE(R600_MC_VM_AGP_TOP, (agp_loc >> 16) & 0xffff);
211 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
212 R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
213 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
214 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
215 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
216 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
217 RS600_WRITE_MCIND(RS600_MC_AGP_LOCATION, agp_loc);
218 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
219 R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
220 else
221 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
222 }
223
224 void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
225 {
226 u32 agp_base_hi = upper_32_bits(agp_base);
227 u32 agp_base_lo = agp_base & 0xffffffff;
228 u32 r6xx_agp_base = (agp_base >> 22) & 0x3ffff;
229
230 /* R6xx/R7xx must be aligned to a 4MB boundary */
231 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
232 RADEON_WRITE(R700_MC_VM_AGP_BASE, r6xx_agp_base);
233 else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
234 RADEON_WRITE(R600_MC_VM_AGP_BASE, r6xx_agp_base);
235 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) {
236 R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo);
237 R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi);
238 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
239 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
240 RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo);
241 RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi);
242 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
243 RS600_WRITE_MCIND(RS600_AGP_BASE, agp_base_lo);
244 RS600_WRITE_MCIND(RS600_AGP_BASE_2, agp_base_hi);
245 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) {
246 R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo);
247 R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi);
248 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
249 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
250 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
251 RADEON_WRITE(RS480_AGP_BASE_2, agp_base_hi);
252 } else {
253 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
254 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200)
255 RADEON_WRITE(RADEON_AGP_BASE_2, agp_base_hi);
256 }
257 }
258
259 void radeon_enable_bm(struct drm_radeon_private *dev_priv)
260 {
261 u32 tmp;
262 /* Turn on bus mastering */
263 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
264 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
265 /* rs600/rs690/rs740 */
266 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
267 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
268 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV350) ||
269 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
270 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
271 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
272 /* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
273 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
274 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
275 } /* PCIE cards appears to not need this */
276 }
277
278 static int RADEON_READ_PLL(struct drm_device * dev, int addr)
279 {
280 drm_radeon_private_t *dev_priv = dev->dev_private;
281
282 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
283 return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
284 }
285
286 static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
287 {
288 RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
289 return RADEON_READ(RADEON_PCIE_DATA);
290 }
291
292 #if RADEON_FIFO_DEBUG
293 static void radeon_status(drm_radeon_private_t * dev_priv)
294 {
295 printk("%s:\n", __func__);
296 printk("RBBM_STATUS = 0x%08x\n",
297 (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
298 printk("CP_RB_RTPR = 0x%08x\n",
299 (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
300 printk("CP_RB_WTPR = 0x%08x\n",
301 (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
302 printk("AIC_CNTL = 0x%08x\n",
303 (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
304 printk("AIC_STAT = 0x%08x\n",
305 (unsigned int)RADEON_READ(RADEON_AIC_STAT));
306 printk("AIC_PT_BASE = 0x%08x\n",
307 (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
308 printk("TLB_ADDR = 0x%08x\n",
309 (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
310 printk("TLB_DATA = 0x%08x\n",
311 (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
312 }
313 #endif
314
315 /* ================================================================
316 * Engine, FIFO control
317 */
318
319 static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
320 {
321 u32 tmp;
322 int i;
323
324 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
325
326 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {
327 tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
328 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
329 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
330
331 for (i = 0; i < dev_priv->usec_timeout; i++) {
332 if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
333 & RADEON_RB3D_DC_BUSY)) {
334 return 0;
335 }
336 DRM_UDELAY(1);
337 }
338 } else {
339 /* don't flush or purge cache here or lockup */
340 return 0;
341 }
342
343 #if RADEON_FIFO_DEBUG
344 DRM_ERROR("failed!\n");
345 radeon_status(dev_priv);
346 #endif
347 return -EBUSY;
348 }
349
350 static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
351 {
352 int i;
353
354 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
355
356 for (i = 0; i < dev_priv->usec_timeout; i++) {
357 int slots = (RADEON_READ(RADEON_RBBM_STATUS)
358 & RADEON_RBBM_FIFOCNT_MASK);
359 if (slots >= entries)
360 return 0;
361 DRM_UDELAY(1);
362 }
363 DRM_DEBUG("wait for fifo failed status : 0x%08X 0x%08X\n",
364 RADEON_READ(RADEON_RBBM_STATUS),
365 RADEON_READ(R300_VAP_CNTL_STATUS));
366
367 #if RADEON_FIFO_DEBUG
368 DRM_ERROR("failed!\n");
369 radeon_status(dev_priv);
370 #endif
371 return -EBUSY;
372 }
373
374 static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
375 {
376 int i, ret;
377
378 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
379
380 ret = radeon_do_wait_for_fifo(dev_priv, 64);
381 if (ret)
382 return ret;
383
384 for (i = 0; i < dev_priv->usec_timeout; i++) {
385 if (!(RADEON_READ(RADEON_RBBM_STATUS)
386 & RADEON_RBBM_ACTIVE)) {
387 radeon_do_pixcache_flush(dev_priv);
388 return 0;
389 }
390 DRM_UDELAY(1);
391 }
392 DRM_DEBUG("wait idle failed status : 0x%08X 0x%08X\n",
393 RADEON_READ(RADEON_RBBM_STATUS),
394 RADEON_READ(R300_VAP_CNTL_STATUS));
395
396 #if RADEON_FIFO_DEBUG
397 DRM_ERROR("failed!\n");
398 radeon_status(dev_priv);
399 #endif
400 return -EBUSY;
401 }
402
403 static void radeon_init_pipes(struct drm_device *dev)
404 {
405 drm_radeon_private_t *dev_priv = dev->dev_private;
406 uint32_t gb_tile_config, gb_pipe_sel = 0;
407
408 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) {
409 uint32_t z_pipe_sel = RADEON_READ(RV530_GB_PIPE_SELECT2);
410 if ((z_pipe_sel & 3) == 3)
411 dev_priv->num_z_pipes = 2;
412 else
413 dev_priv->num_z_pipes = 1;
414 } else
415 dev_priv->num_z_pipes = 1;
416
417 /* RS4xx/RS6xx/R4xx/R5xx */
418 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) {
419 gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT);
420 dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
421 /* SE cards have 1 pipe */
422 if ((dev->pci_device == 0x5e4c) ||
423 (dev->pci_device == 0x5e4f))
424 dev_priv->num_gb_pipes = 1;
425 } else {
426 /* R3xx */
427 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300 &&
428 dev->pci_device != 0x4144) ||
429 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350 &&
430 dev->pci_device != 0x4148)) {
431 dev_priv->num_gb_pipes = 2;
432 } else {
433 /* RV3xx/R300 AD/R350 AH */
434 dev_priv->num_gb_pipes = 1;
435 }
436 }
437 DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes);
438
439 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 /*| R300_SUBPIXEL_1_16*/);
440
441 switch (dev_priv->num_gb_pipes) {
442 case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
443 case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
444 case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
445 default:
446 case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break;
447 }
448
449 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
450 RADEON_WRITE_PLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4));
451 RADEON_WRITE(R300_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1));
452 }
453 RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config);
454 radeon_do_wait_for_idle(dev_priv);
455 RADEON_WRITE(R300_DST_PIPE_CONFIG, RADEON_READ(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG);
456 RADEON_WRITE(R300_RB2D_DSTCACHE_MODE, (RADEON_READ(R300_RB2D_DSTCACHE_MODE) |
457 R300_DC_AUTOFLUSH_ENABLE |
458 R300_DC_DC_DISABLE_IGNORE_PE));
459
460
461 }
462
463 /* ================================================================
464 * CP control, initialization
465 */
466
467 /* Load the microcode for the CP */
468 static int radeon_cp_init_microcode(drm_radeon_private_t *dev_priv)
469 {
470 const char *fw_name = NULL;
471 int err;
472
473 DRM_DEBUG("\n");
474
475 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) ||
476 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) ||
477 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) ||
478 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) ||
479 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) {
480 DRM_INFO("Loading R100 Microcode\n");
481 fw_name = FIRMWARE_R100;
482 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) ||
483 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) ||
484 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) ||
485 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) {
486 DRM_INFO("Loading R200 Microcode\n");
487 fw_name = FIRMWARE_R200;
488 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
489 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) ||
490 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) ||
491 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) ||
492 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
493 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
494 DRM_INFO("Loading R300 Microcode\n");
495 fw_name = FIRMWARE_R300;
496 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
497 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R423) ||
498 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) {
499 DRM_INFO("Loading R400 Microcode\n");
500 fw_name = FIRMWARE_R420;
501 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
502 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
503 DRM_INFO("Loading RS690/RS740 Microcode\n");
504 fw_name = FIRMWARE_RS690;
505 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
506 DRM_INFO("Loading RS600 Microcode\n");
507 fw_name = FIRMWARE_RS600;
508 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) ||
509 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) ||
510 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) ||
511 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R580) ||
512 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) ||
513 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) {
514 DRM_INFO("Loading R500 Microcode\n");
515 fw_name = FIRMWARE_R520;
516 }
517
518 err = 0;
519
520 dev_priv->me_fw = firmware_get(fw_name);
521 if (dev_priv->me_fw == NULL) {
522 err = -ENOENT;
523 DRM_ERROR("radeon_cp: Failed to load firmware \"%s\"\n",
524 fw_name);
525 } else if (dev_priv->me_fw->datasize % 8) {
526 DRM_ERROR(
527 "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
528 dev_priv->me_fw->datasize, fw_name);
529 err = -EINVAL;
530 firmware_put(dev_priv->me_fw, FIRMWARE_UNLOAD);
531 dev_priv->me_fw = NULL;
532 }
533 return err;
534 }
535
536 static void radeon_cp_load_microcode(drm_radeon_private_t *dev_priv)
537 {
538 const __be32 *fw_data;
539 int i, size;
540
541 radeon_do_wait_for_idle(dev_priv);
542
543 if (dev_priv->me_fw) {
544 size = dev_priv->me_fw->datasize / 4;
545 fw_data = (const __be32 *)dev_priv->me_fw->data;
546 RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
547 for (i = 0; i < size; i += 2) {
548 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
549 be32_to_cpup(&fw_data[i]));
550 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
551 be32_to_cpup(&fw_data[i + 1]));
552 }
553 }
554 }
555
556 /* Flush any pending commands to the CP. This should only be used just
557 * prior to a wait for idle, as it informs the engine that the command
558 * stream is ending.
559 */
560 static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
561 {
562 DRM_DEBUG("\n");
563 #if 0
564 u32 tmp;
565
566 tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
567 RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
568 #endif
569 }
570
571 /* Wait for the CP to go idle.
572 */
573 int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
574 {
575 RING_LOCALS;
576 DRM_DEBUG("\n");
577
578 BEGIN_RING(6);
579
580 RADEON_PURGE_CACHE();
581 RADEON_PURGE_ZCACHE();
582 RADEON_WAIT_UNTIL_IDLE();
583
584 ADVANCE_RING();
585 COMMIT_RING();
586
587 return radeon_do_wait_for_idle(dev_priv);
588 }
589
590 /* Start the Command Processor.
591 */
592 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
593 {
594 RING_LOCALS;
595 DRM_DEBUG("\n");
596
597 radeon_do_wait_for_idle(dev_priv);
598
599 RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
600
601 dev_priv->cp_running = 1;
602
603 /* on r420, any DMA from CP to system memory while 2D is active
604 * can cause a hang. workaround is to queue a CP RESYNC token
605 */
606 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) {
607 BEGIN_RING(3);
608 OUT_RING(CP_PACKET0(R300_CP_RESYNC_ADDR, 1));
609 OUT_RING(5); /* scratch reg 5 */
610 OUT_RING(0xdeadbeef);
611 ADVANCE_RING();
612 COMMIT_RING();
613 }
614
615 BEGIN_RING(8);
616 /* isync can only be written through cp on r5xx write it here */
617 OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0));
618 OUT_RING(RADEON_ISYNC_ANY2D_IDLE3D |
619 RADEON_ISYNC_ANY3D_IDLE2D |
620 RADEON_ISYNC_WAIT_IDLEGUI |
621 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
622 RADEON_PURGE_CACHE();
623 RADEON_PURGE_ZCACHE();
624 RADEON_WAIT_UNTIL_IDLE();
625 ADVANCE_RING();
626 COMMIT_RING();
627
628 dev_priv->track_flush |= RADEON_FLUSH_EMITED | RADEON_PURGE_EMITED;
629 }
630
631 /* Reset the Command Processor. This will not flush any pending
632 * commands, so you must wait for the CP command stream to complete
633 * before calling this routine.
634 */
635 static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
636 {
637 u32 cur_read_ptr;
638 DRM_DEBUG("\n");
639
640 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
641 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
642 SET_RING_HEAD(dev_priv, cur_read_ptr);
643 dev_priv->ring.tail = cur_read_ptr;
644 }
645
646 /* Stop the Command Processor. This will not flush any pending
647 * commands, so you must flush the command stream and wait for the CP
648 * to go idle before calling this routine.
649 */
650 static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
651 {
652 RING_LOCALS;
653 DRM_DEBUG("\n");
654
655 /* finish the pending CP_RESYNC token */
656 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) {
657 BEGIN_RING(2);
658 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
659 OUT_RING(R300_RB3D_DC_FINISH);
660 ADVANCE_RING();
661 COMMIT_RING();
662 radeon_do_wait_for_idle(dev_priv);
663 }
664
665 RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
666
667 dev_priv->cp_running = 0;
668 }
669
670 /* Reset the engine. This will stop the CP if it is running.
671 */
672 static int radeon_do_engine_reset(struct drm_device * dev)
673 {
674 drm_radeon_private_t *dev_priv = dev->dev_private;
675 u32 clock_cntl_index = 0, mclk_cntl = 0, rbbm_soft_reset;
676 DRM_DEBUG("\n");
677
678 radeon_do_pixcache_flush(dev_priv);
679
680 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
681 /* may need something similar for newer chips */
682 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
683 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
684
685 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
686 RADEON_FORCEON_MCLKA |
687 RADEON_FORCEON_MCLKB |
688 RADEON_FORCEON_YCLKA |
689 RADEON_FORCEON_YCLKB |
690 RADEON_FORCEON_MC |
691 RADEON_FORCEON_AIC));
692 }
693
694 rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
695
696 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
697 RADEON_SOFT_RESET_CP |
698 RADEON_SOFT_RESET_HI |
699 RADEON_SOFT_RESET_SE |
700 RADEON_SOFT_RESET_RE |
701 RADEON_SOFT_RESET_PP |
702 RADEON_SOFT_RESET_E2 |
703 RADEON_SOFT_RESET_RB));
704 RADEON_READ(RADEON_RBBM_SOFT_RESET);
705 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
706 ~(RADEON_SOFT_RESET_CP |
707 RADEON_SOFT_RESET_HI |
708 RADEON_SOFT_RESET_SE |
709 RADEON_SOFT_RESET_RE |
710 RADEON_SOFT_RESET_PP |
711 RADEON_SOFT_RESET_E2 |
712 RADEON_SOFT_RESET_RB)));
713 RADEON_READ(RADEON_RBBM_SOFT_RESET);
714
715 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
716 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
717 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
718 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
719 }
720
721 /* setup the raster pipes */
722 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300)
723 radeon_init_pipes(dev);
724
725 /* Reset the CP ring */
726 radeon_do_cp_reset(dev_priv);
727
728 /* The CP is no longer running after an engine reset */
729 dev_priv->cp_running = 0;
730
731 /* Reset any pending vertex, indirect buffers */
732 radeon_freelist_reset(dev);
733
734 return 0;
735 }
736
737 static void radeon_cp_init_ring_buffer(struct drm_device * dev,
738 drm_radeon_private_t *dev_priv,
739 struct drm_file *file_priv)
740 {
741 struct drm_radeon_master_private *master_priv;
742 u32 ring_start, cur_read_ptr;
743
744 /* Initialize the memory controller. With new memory map, the fb location
745 * is not changed, it should have been properly initialized already. Part
746 * of the problem is that the code below is bogus, assuming the GART is
747 * always appended to the fb which is not necessarily the case
748 */
749 if (!dev_priv->new_memmap)
750 radeon_write_fb_location(dev_priv,
751 ((dev_priv->gart_vm_start - 1) & 0xffff0000)
752 | (dev_priv->fb_location >> 16));
753
754 #if __OS_HAS_AGP
755 if (dev_priv->flags & RADEON_IS_AGP) {
756 radeon_write_agp_base(dev_priv, dev->agp->base);
757
758 radeon_write_agp_location(dev_priv,
759 (((dev_priv->gart_vm_start - 1 +
760 dev_priv->gart_size) & 0xffff0000) |
761 (dev_priv->gart_vm_start >> 16)));
762
763 ring_start = (dev_priv->cp_ring->offset
764 - dev->agp->base
765 + dev_priv->gart_vm_start);
766 } else
767 #endif
768 ring_start = (dev_priv->cp_ring->offset
769 - (unsigned long)dev->sg->vaddr
770 + dev_priv->gart_vm_start);
771
772 RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
773
774 /* Set the write pointer delay */
775 RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
776
777 /* Initialize the ring buffer's read and write pointers */
778 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
779 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
780 SET_RING_HEAD(dev_priv, cur_read_ptr);
781 dev_priv->ring.tail = cur_read_ptr;
782
783 #if __OS_HAS_AGP
784 if (dev_priv->flags & RADEON_IS_AGP) {
785 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
786 dev_priv->ring_rptr->offset
787 - dev->agp->base + dev_priv->gart_vm_start);
788 } else
789 #endif
790 {
791 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
792 dev_priv->ring_rptr->offset
793 - ((unsigned long) dev->sg->vaddr)
794 + dev_priv->gart_vm_start);
795 }
796
797 /* Set ring buffer size */
798 #ifdef __BIG_ENDIAN
799 RADEON_WRITE(RADEON_CP_RB_CNTL,
800 RADEON_BUF_SWAP_32BIT |
801 (dev_priv->ring.fetch_size_l2ow << 18) |
802 (dev_priv->ring.rptr_update_l2qw << 8) |
803 dev_priv->ring.size_l2qw);
804 #else
805 RADEON_WRITE(RADEON_CP_RB_CNTL,
806 (dev_priv->ring.fetch_size_l2ow << 18) |
807 (dev_priv->ring.rptr_update_l2qw << 8) |
808 dev_priv->ring.size_l2qw);
809 #endif
810
811
812 /* Initialize the scratch register pointer. This will cause
813 * the scratch register values to be written out to memory
814 * whenever they are updated.
815 *
816 * We simply put this behind the ring read pointer, this works
817 * with PCI GART as well as (whatever kind of) AGP GART
818 */
819 RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
820 + RADEON_SCRATCH_REG_OFFSET);
821
822 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
823
824 radeon_enable_bm(dev_priv);
825
826 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(0), 0);
827 RADEON_WRITE(RADEON_LAST_FRAME_REG, 0);
828
829 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0);
830 RADEON_WRITE(RADEON_LAST_DISPATCH_REG, 0);
831
832 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(2), 0);
833 RADEON_WRITE(RADEON_LAST_CLEAR_REG, 0);
834
835 /* reset sarea copies of these */
836 master_priv = file_priv->masterp->driver_priv;
837 if (master_priv->sarea_priv) {
838 master_priv->sarea_priv->last_frame = 0;
839 master_priv->sarea_priv->last_dispatch = 0;
840 master_priv->sarea_priv->last_clear = 0;
841 }
842
843 radeon_do_wait_for_idle(dev_priv);
844
845 /* Sync everything up */
846 RADEON_WRITE(RADEON_ISYNC_CNTL,
847 (RADEON_ISYNC_ANY2D_IDLE3D |
848 RADEON_ISYNC_ANY3D_IDLE2D |
849 RADEON_ISYNC_WAIT_IDLEGUI |
850 RADEON_ISYNC_CPSCRATCH_IDLEGUI));
851
852 }
853
854 static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
855 {
856 u32 tmp;
857
858 /* Start with assuming that writeback doesn't work */
859 dev_priv->writeback_works = 0;
860
861 /* Writeback doesn't seem to work everywhere, test it here and possibly
862 * enable it if it appears to work
863 */
864 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0);
865
866 RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
867
868 for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
869 u32 val;
870
871 val = radeon_read_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1));
872 if (val == 0xdeadbeef)
873 break;
874 DRM_UDELAY(1);
875 }
876
877 if (tmp < dev_priv->usec_timeout) {
878 dev_priv->writeback_works = 1;
879 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
880 } else {
881 dev_priv->writeback_works = 0;
882 DRM_INFO("writeback test failed\n");
883 }
884 if (radeon_no_wb == 1) {
885 dev_priv->writeback_works = 0;
886 DRM_INFO("writeback forced off\n");
887 }
888
889 if (!dev_priv->writeback_works) {
890 /* Disable writeback to avoid unnecessary bus master transfer */
891 RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) |
892 RADEON_RB_NO_UPDATE);
893 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
894 }
895 }
896
897 /* Enable or disable IGP GART on the chip */
898 static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
899 {
900 u32 temp;
901
902 if (on) {
903 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
904 dev_priv->gart_vm_start,
905 (long)dev_priv->gart_info.bus_addr,
906 dev_priv->gart_size);
907
908 temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);
909 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
910 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
911 IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN |
912 RS690_BLOCK_GFX_D3_EN));
913 else
914 IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
915
916 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
917 RS480_VA_SIZE_32MB));
918
919 temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID);
920 IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN |
921 RS480_TLB_ENABLE |
922 RS480_GTW_LAC_EN |
923 RS480_1LEVEL_GART));
924
925 temp = dev_priv->gart_info.bus_addr & 0xfffff000;
926 temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4;
927 IGP_WRITE_MCIND(RS480_GART_BASE, temp);
928
929 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL);
930 IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) |
931 RS480_REQ_TYPE_SNOOP_DIS));
932
933 radeon_write_agp_base(dev_priv, dev_priv->gart_vm_start);
934
935 dev_priv->gart_size = 32*1024*1024;
936 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
937 0xffff0000) | (dev_priv->gart_vm_start >> 16));
938
939 radeon_write_agp_location(dev_priv, temp);
940
941 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE);
942 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
943 RS480_VA_SIZE_32MB));
944
945 do {
946 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
947 if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
948 break;
949 DRM_UDELAY(1);
950 } while (1);
951
952 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL,
953 RS480_GART_CACHE_INVALIDATE);
954
955 do {
956 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
957 if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
958 break;
959 DRM_UDELAY(1);
960 } while (1);
961
962 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0);
963 } else {
964 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
965 }
966 }
967
968 /* Enable or disable IGP GART on the chip */
969 static void rs600_set_igpgart(drm_radeon_private_t *dev_priv, int on)
970 {
971 u32 temp;
972 int i;
973
974 if (on) {
975 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
976 dev_priv->gart_vm_start,
977 (long)dev_priv->gart_info.bus_addr,
978 dev_priv->gart_size);
979
980 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, (RS600_EFFECTIVE_L2_CACHE_SIZE(6) |
981 RS600_EFFECTIVE_L2_QUEUE_SIZE(6)));
982
983 for (i = 0; i < 19; i++)
984 IGP_WRITE_MCIND(RS600_MC_PT0_CLIENT0_CNTL + i,
985 (RS600_ENABLE_TRANSLATION_MODE_OVERRIDE |
986 RS600_SYSTEM_ACCESS_MODE_IN_SYS |
987 RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASSTHROUGH |
988 RS600_EFFECTIVE_L1_CACHE_SIZE(3) |
989 RS600_ENABLE_FRAGMENT_PROCESSING |
990 RS600_EFFECTIVE_L1_QUEUE_SIZE(3)));
991
992 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_CNTL, (RS600_ENABLE_PAGE_TABLE |
993 RS600_PAGE_TABLE_TYPE_FLAT));
994
995 /* disable all other contexts */
996 for (i = 1; i < 8; i++)
997 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_CNTL + i, 0);
998
999 /* setup the page table aperture */
1000 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
1001 dev_priv->gart_info.bus_addr);
1002 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR,
1003 dev_priv->gart_vm_start);
1004 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR,
1005 (dev_priv->gart_vm_start + dev_priv->gart_size - 1));
1006 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
1007
1008 /* setup the system aperture */
1009 IGP_WRITE_MCIND(RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR,
1010 dev_priv->gart_vm_start);
1011 IGP_WRITE_MCIND(RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR,
1012 (dev_priv->gart_vm_start + dev_priv->gart_size - 1));
1013
1014 /* enable page tables */
1015 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1016 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, (temp | RS600_ENABLE_PT));
1017
1018 temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1);
1019 IGP_WRITE_MCIND(RS600_MC_CNTL1, (temp | RS600_ENABLE_PAGE_TABLES));
1020
1021 /* invalidate the cache */
1022 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1023
1024 temp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE);
1025 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
1026 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1027
1028 temp |= RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE;
1029 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
1030 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1031
1032 temp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE);
1033 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
1034 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1035
1036 } else {
1037 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, 0);
1038 temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1);
1039 temp &= ~RS600_ENABLE_PAGE_TABLES;
1040 IGP_WRITE_MCIND(RS600_MC_CNTL1, temp);
1041 }
1042 }
1043
1044 static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
1045 {
1046 u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
1047 if (on) {
1048
1049 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
1050 dev_priv->gart_vm_start,
1051 (long)dev_priv->gart_info.bus_addr,
1052 dev_priv->gart_size);
1053 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
1054 dev_priv->gart_vm_start);
1055 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
1056 dev_priv->gart_info.bus_addr);
1057 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
1058 dev_priv->gart_vm_start);
1059 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
1060 dev_priv->gart_vm_start +
1061 dev_priv->gart_size - 1);
1062
1063 radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */
1064
1065 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1066 RADEON_PCIE_TX_GART_EN);
1067 } else {
1068 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1069 tmp & ~RADEON_PCIE_TX_GART_EN);
1070 }
1071 }
1072
1073 /* Enable or disable PCI GART on the chip */
1074 static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
1075 {
1076 u32 tmp;
1077
1078 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
1079 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740) ||
1080 (dev_priv->flags & RADEON_IS_IGPGART)) {
1081 radeon_set_igpgart(dev_priv, on);
1082 return;
1083 }
1084
1085 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
1086 rs600_set_igpgart(dev_priv, on);
1087 return;
1088 }
1089
1090 if (dev_priv->flags & RADEON_IS_PCIE) {
1091 radeon_set_pciegart(dev_priv, on);
1092 return;
1093 }
1094
1095 tmp = RADEON_READ(RADEON_AIC_CNTL);
1096
1097 if (on) {
1098 RADEON_WRITE(RADEON_AIC_CNTL,
1099 tmp | RADEON_PCIGART_TRANSLATE_EN);
1100
1101 /* set PCI GART page-table base address
1102 */
1103 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
1104
1105 /* set address range for PCI address translate
1106 */
1107 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
1108 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
1109 + dev_priv->gart_size - 1);
1110
1111 /* Turn off AGP aperture -- is this required for PCI GART?
1112 */
1113 radeon_write_agp_location(dev_priv, 0xffffffc0);
1114 RADEON_WRITE(RADEON_AGP_COMMAND, 0); /* clear AGP_COMMAND */
1115 } else {
1116 RADEON_WRITE(RADEON_AIC_CNTL,
1117 tmp & ~RADEON_PCIGART_TRANSLATE_EN);
1118 }
1119 }
1120
1121 static int radeon_setup_pcigart_surface(drm_radeon_private_t *dev_priv)
1122 {
1123 struct drm_ati_pcigart_info *gart_info = &dev_priv->gart_info;
1124 struct radeon_virt_surface *vp;
1125 int i;
1126
1127 for (i = 0; i < RADEON_MAX_SURFACES * 2; i++) {
1128 if (!dev_priv->virt_surfaces[i].file_priv ||
1129 dev_priv->virt_surfaces[i].file_priv == PCIGART_FILE_PRIV)
1130 break;
1131 }
1132 if (i >= 2 * RADEON_MAX_SURFACES)
1133 return -ENOMEM;
1134 vp = &dev_priv->virt_surfaces[i];
1135
1136 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1137 struct radeon_surface *sp = &dev_priv->surfaces[i];
1138 if (sp->refcount)
1139 continue;
1140
1141 vp->surface_index = i;
1142 vp->lower = gart_info->bus_addr;
1143 vp->upper = vp->lower + gart_info->table_size;
1144 vp->flags = 0;
1145 vp->file_priv = PCIGART_FILE_PRIV;
1146
1147 sp->refcount = 1;
1148 sp->lower = vp->lower;
1149 sp->upper = vp->upper;
1150 sp->flags = 0;
1151
1152 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, sp->flags);
1153 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16 * i, sp->lower);
1154 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16 * i, sp->upper);
1155 return 0;
1156 }
1157
1158 return -ENOMEM;
1159 }
1160
1161 static int radeon_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
1162 struct drm_file *file_priv)
1163 {
1164 drm_radeon_private_t *dev_priv = dev->dev_private;
1165 struct drm_radeon_master_private *master_priv = file_priv->masterp->driver_priv;
1166
1167 DRM_DEBUG("\n");
1168
1169 /* if we require new memory map but we don't have it fail */
1170 if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
1171 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
1172 radeon_do_cleanup_cp(dev);
1173 return -EINVAL;
1174 }
1175
1176 if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
1177 DRM_DEBUG("Forcing AGP card to PCI mode\n");
1178 dev_priv->flags &= ~RADEON_IS_AGP;
1179 } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
1180 && !init->is_pci) {
1181 DRM_DEBUG("Restoring AGP flag\n");
1182 dev_priv->flags |= RADEON_IS_AGP;
1183 }
1184
1185 if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) {
1186 DRM_ERROR("PCI GART memory not allocated!\n");
1187 radeon_do_cleanup_cp(dev);
1188 return -EINVAL;
1189 }
1190
1191 dev_priv->usec_timeout = init->usec_timeout;
1192 if (dev_priv->usec_timeout < 1 ||
1193 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
1194 DRM_DEBUG("TIMEOUT problem!\n");
1195 radeon_do_cleanup_cp(dev);
1196 return -EINVAL;
1197 }
1198
1199 /* Enable vblank on CRTC1 for older X servers
1200 */
1201 dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
1202
1203 switch(init->func) {
1204 case RADEON_INIT_R200_CP:
1205 dev_priv->microcode_version = UCODE_R200;
1206 break;
1207 case RADEON_INIT_R300_CP:
1208 dev_priv->microcode_version = UCODE_R300;
1209 break;
1210 default:
1211 dev_priv->microcode_version = UCODE_R100;
1212 }
1213
1214 dev_priv->do_boxes = 0;
1215 dev_priv->cp_mode = init->cp_mode;
1216
1217 /* We don't support anything other than bus-mastering ring mode,
1218 * but the ring can be in either AGP or PCI space for the ring
1219 * read pointer.
1220 */
1221 if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
1222 (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
1223 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
1224 radeon_do_cleanup_cp(dev);
1225 return -EINVAL;
1226 }
1227
1228 switch (init->fb_bpp) {
1229 case 16:
1230 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1231 break;
1232 case 32:
1233 default:
1234 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1235 break;
1236 }
1237 dev_priv->front_offset = init->front_offset;
1238 dev_priv->front_pitch = init->front_pitch;
1239 dev_priv->back_offset = init->back_offset;
1240 dev_priv->back_pitch = init->back_pitch;
1241
1242 switch (init->depth_bpp) {
1243 case 16:
1244 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
1245 break;
1246 case 32:
1247 default:
1248 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
1249 break;
1250 }
1251 dev_priv->depth_offset = init->depth_offset;
1252 dev_priv->depth_pitch = init->depth_pitch;
1253
1254 /* Hardware state for depth clears. Remove this if/when we no
1255 * longer clear the depth buffer with a 3D rectangle. Hard-code
1256 * all values to prevent unwanted 3D state from slipping through
1257 * and screwing with the clear operation.
1258 */
1259 dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1260 (dev_priv->color_fmt << 10) |
1261 (dev_priv->microcode_version ==
1262 UCODE_R100 ? RADEON_ZBLOCK16 : 0));
1263
1264 dev_priv->depth_clear.rb3d_zstencilcntl =
1265 (dev_priv->depth_fmt |
1266 RADEON_Z_TEST_ALWAYS |
1267 RADEON_STENCIL_TEST_ALWAYS |
1268 RADEON_STENCIL_S_FAIL_REPLACE |
1269 RADEON_STENCIL_ZPASS_REPLACE |
1270 RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
1271
1272 dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
1273 RADEON_BFACE_SOLID |
1274 RADEON_FFACE_SOLID |
1275 RADEON_FLAT_SHADE_VTX_LAST |
1276 RADEON_DIFFUSE_SHADE_FLAT |
1277 RADEON_ALPHA_SHADE_FLAT |
1278 RADEON_SPECULAR_SHADE_FLAT |
1279 RADEON_FOG_SHADE_FLAT |
1280 RADEON_VTX_PIX_CENTER_OGL |
1281 RADEON_ROUND_MODE_TRUNC |
1282 RADEON_ROUND_PREC_8TH_PIX);
1283
1284
1285 dev_priv->ring_offset = init->ring_offset;
1286 dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1287 dev_priv->buffers_offset = init->buffers_offset;
1288 dev_priv->gart_textures_offset = init->gart_textures_offset;
1289
1290 master_priv->sarea = drm_getsarea(dev);
1291 if (!master_priv->sarea) {
1292 DRM_ERROR("could not find sarea!\n");
1293 radeon_do_cleanup_cp(dev);
1294 return -EINVAL;
1295 }
1296
1297 dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
1298 if (!dev_priv->cp_ring) {
1299 DRM_ERROR("could not find cp ring region!\n");
1300 radeon_do_cleanup_cp(dev);
1301 return -EINVAL;
1302 }
1303 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1304 if (!dev_priv->ring_rptr) {
1305 DRM_ERROR("could not find ring read pointer!\n");
1306 radeon_do_cleanup_cp(dev);
1307 return -EINVAL;
1308 }
1309 dev->agp_buffer_token = init->buffers_offset;
1310 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
1311 if (!dev->agp_buffer_map) {
1312 DRM_ERROR("could not find dma buffer region!\n");
1313 radeon_do_cleanup_cp(dev);
1314 return -EINVAL;
1315 }
1316
1317 if (init->gart_textures_offset) {
1318 dev_priv->gart_textures =
1319 drm_core_findmap(dev, init->gart_textures_offset);
1320 if (!dev_priv->gart_textures) {
1321 DRM_ERROR("could not find GART texture region!\n");
1322 radeon_do_cleanup_cp(dev);
1323 return -EINVAL;
1324 }
1325 }
1326
1327 #if __OS_HAS_AGP
1328 if (dev_priv->flags & RADEON_IS_AGP) {
1329 drm_core_ioremap_wc(dev_priv->cp_ring, dev);
1330 drm_core_ioremap_wc(dev_priv->ring_rptr, dev);
1331 drm_core_ioremap_wc(dev->agp_buffer_map, dev);
1332 if (!dev_priv->cp_ring->handle ||
1333 !dev_priv->ring_rptr->handle ||
1334 !dev->agp_buffer_map->handle) {
1335 DRM_ERROR("could not find ioremap agp regions!\n");
1336 radeon_do_cleanup_cp(dev);
1337 return -EINVAL;
1338 }
1339 } else
1340 #endif
1341 {
1342 dev_priv->cp_ring->handle =
1343 (void *)(unsigned long)dev_priv->cp_ring->offset;
1344 dev_priv->ring_rptr->handle =
1345 (void *)(unsigned long)dev_priv->ring_rptr->offset;
1346 dev->agp_buffer_map->handle =
1347 (void *)(unsigned long)dev->agp_buffer_map->offset;
1348
1349 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1350 dev_priv->cp_ring->handle);
1351 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1352 dev_priv->ring_rptr->handle);
1353 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1354 dev->agp_buffer_map->handle);
1355 }
1356
1357 dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16;
1358 dev_priv->fb_size =
1359 ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000)
1360 - dev_priv->fb_location;
1361
1362 dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1363 ((dev_priv->front_offset
1364 + dev_priv->fb_location) >> 10));
1365
1366 dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1367 ((dev_priv->back_offset
1368 + dev_priv->fb_location) >> 10));
1369
1370 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1371 ((dev_priv->depth_offset
1372 + dev_priv->fb_location) >> 10));
1373
1374 dev_priv->gart_size = init->gart_size;
1375
1376 /* New let's set the memory map ... */
1377 if (dev_priv->new_memmap) {
1378 u32 base = 0;
1379
1380 DRM_INFO("Setting GART location based on new memory map\n");
1381
1382 /* If using AGP, try to locate the AGP aperture at the same
1383 * location in the card and on the bus, though we have to
1384 * align it down.
1385 */
1386 #if __OS_HAS_AGP
1387 if (dev_priv->flags & RADEON_IS_AGP) {
1388 base = dev->agp->base;
1389 /* Check if valid */
1390 if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
1391 base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
1392 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1393 dev->agp->base);
1394 base = 0;
1395 }
1396 }
1397 #endif
1398 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1399 if (base == 0) {
1400 base = dev_priv->fb_location + dev_priv->fb_size;
1401 if (base < dev_priv->fb_location ||
1402 ((base + dev_priv->gart_size) & 0xfffffffful) < base)
1403 base = dev_priv->fb_location
1404 - dev_priv->gart_size;
1405 }
1406 dev_priv->gart_vm_start = base & 0xffc00000u;
1407 if (dev_priv->gart_vm_start != base)
1408 DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1409 base, dev_priv->gart_vm_start);
1410 } else {
1411 DRM_INFO("Setting GART location based on old memory map\n");
1412 dev_priv->gart_vm_start = dev_priv->fb_location +
1413 RADEON_READ(RADEON_CONFIG_APER_SIZE);
1414 }
1415
1416 #if __OS_HAS_AGP
1417 if (dev_priv->flags & RADEON_IS_AGP)
1418 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1419 - dev->agp->base
1420 + dev_priv->gart_vm_start);
1421 else
1422 #endif
1423 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1424 - (unsigned long)dev->sg->vaddr
1425 + dev_priv->gart_vm_start);
1426
1427 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1428 DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1429 DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1430 dev_priv->gart_buffers_offset);
1431
1432 dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1433 dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1434 + init->ring_size / sizeof(u32));
1435 dev_priv->ring.size = init->ring_size;
1436 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1437
1438 dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
1439 dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8);
1440
1441 dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
1442 dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16);
1443 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1444
1445 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1446
1447 #if __OS_HAS_AGP
1448 if (dev_priv->flags & RADEON_IS_AGP) {
1449 /* Turn off PCI GART */
1450 radeon_set_pcigart(dev_priv, 0);
1451 } else
1452 #endif
1453 {
1454 u32 sctrl;
1455 int ret;
1456
1457 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
1458 /* if we have an offset set from userspace */
1459 if (dev_priv->pcigart_offset_set) {
1460 dev_priv->gart_info.bus_addr =
1461 (resource_size_t)dev_priv->pcigart_offset + dev_priv->fb_location;
1462 dev_priv->gart_info.mapping.offset =
1463 dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
1464 dev_priv->gart_info.mapping.size =
1465 dev_priv->gart_info.table_size;
1466
1467 drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev);
1468 dev_priv->gart_info.addr =
1469 dev_priv->gart_info.mapping.handle;
1470
1471 if (dev_priv->flags & RADEON_IS_PCIE)
1472 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE;
1473 else
1474 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1475 dev_priv->gart_info.gart_table_location =
1476 DRM_ATI_GART_FB;
1477
1478 DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
1479 dev_priv->gart_info.addr,
1480 dev_priv->pcigart_offset);
1481 } else {
1482 if (dev_priv->flags & RADEON_IS_IGPGART)
1483 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
1484 else
1485 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1486 dev_priv->gart_info.gart_table_location =
1487 DRM_ATI_GART_MAIN;
1488 dev_priv->gart_info.addr = NULL;
1489 dev_priv->gart_info.bus_addr = 0;
1490 if (dev_priv->flags & RADEON_IS_PCIE) {
1491 DRM_ERROR
1492 ("Cannot use PCI Express without GART in FB memory\n");
1493 radeon_do_cleanup_cp(dev);
1494 return -EINVAL;
1495 }
1496 }
1497
1498 sctrl = RADEON_READ(RADEON_SURFACE_CNTL);
1499 RADEON_WRITE(RADEON_SURFACE_CNTL, 0);
1500 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1501 ret = r600_page_table_init(dev);
1502 else
1503 ret = drm_ati_pcigart_init(dev, &dev_priv->gart_info);
1504 RADEON_WRITE(RADEON_SURFACE_CNTL, sctrl);
1505
1506 if (!ret) {
1507 DRM_ERROR("failed to init PCI GART!\n");
1508 radeon_do_cleanup_cp(dev);
1509 return -ENOMEM;
1510 }
1511
1512 ret = radeon_setup_pcigart_surface(dev_priv);
1513 if (ret) {
1514 DRM_ERROR("failed to setup GART surface!\n");
1515 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1516 r600_page_table_cleanup(dev, &dev_priv->gart_info);
1517 else
1518 drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info);
1519 radeon_do_cleanup_cp(dev);
1520 return ret;
1521 }
1522
1523 /* Turn on PCI GART */
1524 radeon_set_pcigart(dev_priv, 1);
1525 }
1526
1527 if (!dev_priv->me_fw) {
1528 int err = radeon_cp_init_microcode(dev_priv);
1529 if (err) {
1530 DRM_ERROR("Failed to load firmware!\n");
1531 radeon_do_cleanup_cp(dev);
1532 return err;
1533 }
1534 }
1535 radeon_cp_load_microcode(dev_priv);
1536 radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
1537
1538 dev_priv->last_buf = 0;
1539
1540 radeon_do_engine_reset(dev);
1541 radeon_test_writeback(dev_priv);
1542
1543 return 0;
1544 }
1545
1546 static int radeon_do_cleanup_cp(struct drm_device * dev)
1547 {
1548 drm_radeon_private_t *dev_priv = dev->dev_private;
1549 DRM_DEBUG("\n");
1550
1551 /* Make sure interrupts are disabled here because the uninstall ioctl
1552 * may not have been called from userspace and after dev_private
1553 * is freed, it's too late.
1554 */
1555 if (dev->irq_enabled)
1556 drm_irq_uninstall(dev);
1557
1558 #if __OS_HAS_AGP
1559 if (dev_priv->flags & RADEON_IS_AGP) {
1560 if (dev_priv->cp_ring != NULL) {
1561 drm_core_ioremapfree(dev_priv->cp_ring, dev);
1562 dev_priv->cp_ring = NULL;
1563 }
1564 if (dev_priv->ring_rptr != NULL) {
1565 drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1566 dev_priv->ring_rptr = NULL;
1567 }
1568 if (dev->agp_buffer_map != NULL) {
1569 drm_core_ioremapfree(dev->agp_buffer_map, dev);
1570 dev->agp_buffer_map = NULL;
1571 }
1572 } else
1573 #endif
1574 {
1575
1576 if (dev_priv->gart_info.bus_addr) {
1577 /* Turn off PCI GART */
1578 radeon_set_pcigart(dev_priv, 0);
1579 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1580 r600_page_table_cleanup(dev, &dev_priv->gart_info);
1581 else {
1582 if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1583 DRM_ERROR("failed to cleanup PCI GART!\n");
1584 }
1585 }
1586
1587 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
1588 {
1589 drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1590 dev_priv->gart_info.addr = NULL;
1591 }
1592 }
1593 /* only clear to the start of flags */
1594 memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1595
1596 return 0;
1597 }
1598
1599 /* This code will reinit the Radeon CP hardware after a resume from disc.
1600 * AFAIK, it would be very difficult to pickle the state at suspend time, so
1601 * here we make sure that all Radeon hardware initialisation is re-done without
1602 * affecting running applications.
1603 *
1604 * Charl P. Botha <http://cpbotha.net>
1605 */
1606 static int radeon_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv)
1607 {
1608 drm_radeon_private_t *dev_priv = dev->dev_private;
1609
1610 if (!dev_priv) {
1611 DRM_ERROR("Called with no initialization\n");
1612 return -EINVAL;
1613 }
1614
1615 DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1616
1617 #if __OS_HAS_AGP
1618 if (dev_priv->flags & RADEON_IS_AGP) {
1619 /* Turn off PCI GART */
1620 radeon_set_pcigart(dev_priv, 0);
1621 } else
1622 #endif
1623 {
1624 /* Turn on PCI GART */
1625 radeon_set_pcigart(dev_priv, 1);
1626 }
1627
1628 radeon_cp_load_microcode(dev_priv);
1629 radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
1630
1631 dev_priv->have_z_offset = 0;
1632 radeon_do_engine_reset(dev);
1633 radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);
1634
1635 DRM_DEBUG("radeon_do_resume_cp() complete\n");
1636
1637 return 0;
1638 }
1639
1640 int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
1641 {
1642 drm_radeon_private_t *dev_priv = dev->dev_private;
1643 drm_radeon_init_t *init = data;
1644
1645 LOCK_TEST_WITH_RETURN(dev, file_priv);
1646
1647 if (init->func == RADEON_INIT_R300_CP)
1648 r300_init_reg_flags(dev);
1649
1650 switch (init->func) {
1651 case RADEON_INIT_CP:
1652 case RADEON_INIT_R200_CP:
1653 case RADEON_INIT_R300_CP:
1654 return radeon_do_init_cp(dev, init, file_priv);
1655 case RADEON_INIT_R600_CP:
1656 return r600_do_init_cp(dev, init, file_priv);
1657 break;
1658 case RADEON_CLEANUP_CP:
1659 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1660 return r600_do_cleanup_cp(dev);
1661 else
1662 return radeon_do_cleanup_cp(dev);
1663 }
1664
1665 return -EINVAL;
1666 }
1667
1668 int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
1669 {
1670 drm_radeon_private_t *dev_priv = dev->dev_private;
1671 DRM_DEBUG("\n");
1672
1673 LOCK_TEST_WITH_RETURN(dev, file_priv);
1674
1675 if (dev_priv->cp_running) {
1676 DRM_DEBUG("while CP running\n");
1677 return 0;
1678 }
1679 if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
1680 DRM_DEBUG("called with bogus CP mode (%d)\n",
1681 dev_priv->cp_mode);
1682 return 0;
1683 }
1684
1685 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1686 r600_do_cp_start(dev_priv);
1687 else
1688 radeon_do_cp_start(dev_priv);
1689
1690 return 0;
1691 }
1692
1693 /* Stop the CP. The engine must have been idled before calling this
1694 * routine.
1695 */
1696 int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
1697 {
1698 drm_radeon_private_t *dev_priv = dev->dev_private;
1699 drm_radeon_cp_stop_t *stop = data;
1700 int ret;
1701 DRM_DEBUG("\n");
1702
1703 LOCK_TEST_WITH_RETURN(dev, file_priv);
1704
1705 if (!dev_priv->cp_running)
1706 return 0;
1707
1708 /* Flush any pending CP commands. This ensures any outstanding
1709 * commands are exectuted by the engine before we turn it off.
1710 */
1711 if (stop->flush) {
1712 radeon_do_cp_flush(dev_priv);
1713 }
1714
1715 /* If we fail to make the engine go idle, we return an error
1716 * code so that the DRM ioctl wrapper can try again.
1717 */
1718 if (stop->idle) {
1719 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1720 ret = r600_do_cp_idle(dev_priv);
1721 else
1722 ret = radeon_do_cp_idle(dev_priv);
1723 if (ret)
1724 return ret;
1725 }
1726
1727 /* Finally, we can turn off the CP. If the engine isn't idle,
1728 * we will get some dropped triangles as they won't be fully
1729 * rendered before the CP is shut down.
1730 */
1731 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1732 r600_do_cp_stop(dev_priv);
1733 else
1734 radeon_do_cp_stop(dev_priv);
1735
1736 /* Reset the engine */
1737 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1738 r600_do_engine_reset(dev);
1739 else
1740 radeon_do_engine_reset(dev);
1741
1742 return 0;
1743 }
1744
1745 void radeon_do_release(struct drm_device * dev)
1746 {
1747 drm_radeon_private_t *dev_priv = dev->dev_private;
1748 int i, ret;
1749
1750 if (dev_priv) {
1751 if (dev_priv->cp_running) {
1752 /* Stop the cp */
1753 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
1754 while ((ret = r600_do_cp_idle(dev_priv)) != 0) {
1755 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1756 #ifdef __linux__
1757 schedule();
1758 #else
1759 tsleep(&ret, 0, "rdnrel", 1);
1760 #endif
1761 }
1762 } else {
1763 while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1764 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1765 #ifdef __linux__
1766 schedule();
1767 #else
1768 tsleep(&ret, 0, "rdnrel", 1);
1769 #endif
1770 }
1771 }
1772 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
1773 r600_do_cp_stop(dev_priv);
1774 r600_do_engine_reset(dev);
1775 } else {
1776 radeon_do_cp_stop(dev_priv);
1777 radeon_do_engine_reset(dev);
1778 }
1779 }
1780
1781 if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_R600) {
1782 /* Disable *all* interrupts */
1783 if (dev_priv->mmio) /* remove this after permanent addmaps */
1784 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
1785
1786 if (dev_priv->mmio) { /* remove all surfaces */
1787 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1788 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
1789 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
1790 16 * i, 0);
1791 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
1792 16 * i, 0);
1793 }
1794 }
1795 }
1796
1797 /* Free memory heap structures */
1798 radeon_mem_takedown(&(dev_priv->gart_heap));
1799 radeon_mem_takedown(&(dev_priv->fb_heap));
1800
1801 /* deallocate kernel resources */
1802 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1803 r600_do_cleanup_cp(dev);
1804 else
1805 radeon_do_cleanup_cp(dev);
1806 if (dev_priv->me_fw != NULL) {
1807 firmware_put(dev_priv->me_fw, FIRMWARE_UNLOAD);
1808 dev_priv->me_fw = NULL;
1809 }
1810 if (dev_priv->pfp_fw != NULL) {
1811 firmware_put(dev_priv->pfp_fw, FIRMWARE_UNLOAD);
1812 dev_priv->pfp_fw = NULL;
1813 }
1814 }
1815 }
1816
1817 /* Just reset the CP ring. Called as part of an X Server engine reset.
1818 */
1819 int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1820 {
1821 drm_radeon_private_t *dev_priv = dev->dev_private;
1822 DRM_DEBUG("\n");
1823
1824 LOCK_TEST_WITH_RETURN(dev, file_priv);
1825
1826 if (!dev_priv) {
1827 DRM_DEBUG("called before init done\n");
1828 return -EINVAL;
1829 }
1830
1831 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1832 r600_do_cp_reset(dev_priv);
1833 else
1834 radeon_do_cp_reset(dev_priv);
1835
1836 /* The CP is no longer running after an engine reset */
1837 dev_priv->cp_running = 0;
1838
1839 return 0;
1840 }
1841
1842 int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
1843 {
1844 drm_radeon_private_t *dev_priv = dev->dev_private;
1845 DRM_DEBUG("\n");
1846
1847 LOCK_TEST_WITH_RETURN(dev, file_priv);
1848
1849 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1850 return r600_do_cp_idle(dev_priv);
1851 else
1852 return radeon_do_cp_idle(dev_priv);
1853 }
1854
1855 /* Added by Charl P. Botha to call radeon_do_resume_cp().
1856 */
1857 int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv)
1858 {
1859 drm_radeon_private_t *dev_priv = dev->dev_private;
1860 DRM_DEBUG("\n");
1861
1862 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1863 return r600_do_resume_cp(dev, file_priv);
1864 else
1865 return radeon_do_resume_cp(dev, file_priv);
1866 }
1867
1868 int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1869 {
1870 drm_radeon_private_t *dev_priv = dev->dev_private;
1871 DRM_DEBUG("\n");
1872
1873 LOCK_TEST_WITH_RETURN(dev, file_priv);
1874
1875 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1876 return r600_do_engine_reset(dev);
1877 else
1878 return radeon_do_engine_reset(dev);
1879 }
1880
1881 /* ================================================================
1882 * Fullscreen mode
1883 */
1884
1885 /* KW: Deprecated to say the least:
1886 */
1887 int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
1888 {
1889 return 0;
1890 }
1891
1892 /* ================================================================
1893 * Freelist management
1894 */
1895
1896 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1897 * bufs until freelist code is used. Note this hides a problem with
1898 * the scratch register * (used to keep track of last buffer
1899 * completed) being written to before * the last buffer has actually
1900 * completed rendering.
1901 *
1902 * KW: It's also a good way to find free buffers quickly.
1903 *
1904 * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1905 * sleep. However, bugs in older versions of radeon_accel.c mean that
1906 * we essentially have to do this, else old clients will break.
1907 *
1908 * However, it does leave open a potential deadlock where all the
1909 * buffers are held by other clients, which can't release them because
1910 * they can't get the lock.
1911 */
1912
1913 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1914 {
1915 struct drm_device_dma *dma = dev->dma;
1916 drm_radeon_private_t *dev_priv = dev->dev_private;
1917 drm_radeon_buf_priv_t *buf_priv;
1918 struct drm_buf *buf;
1919 int i, t;
1920 int start;
1921
1922 if (++dev_priv->last_buf >= dma->buf_count)
1923 dev_priv->last_buf = 0;
1924
1925 start = dev_priv->last_buf;
1926
1927 for (t = 0; t < dev_priv->usec_timeout; t++) {
1928 u32 done_age = GET_SCRATCH(dev_priv, 1);
1929 DRM_DEBUG("done_age = %d\n", done_age);
1930 for (i = 0; i < dma->buf_count; i++) {
1931 buf = dma->buflist[start];
1932 buf_priv = buf->dev_private;
1933 if (buf->file_priv == NULL || (buf->pending &&
1934 buf_priv->age <=
1935 done_age)) {
1936 dev_priv->stats.requested_bufs++;
1937 buf->pending = 0;
1938 return buf;
1939 }
1940 if (++start >= dma->buf_count)
1941 start = 0;
1942 }
1943
1944 if (t) {
1945 DRM_UDELAY(1);
1946 dev_priv->stats.freelist_loops++;
1947 }
1948 }
1949
1950 return NULL;
1951 }
1952
1953 void radeon_freelist_reset(struct drm_device * dev)
1954 {
1955 struct drm_device_dma *dma = dev->dma;
1956 drm_radeon_private_t *dev_priv = dev->dev_private;
1957 int i;
1958
1959 dev_priv->last_buf = 0;
1960 for (i = 0; i < dma->buf_count; i++) {
1961 struct drm_buf *buf = dma->buflist[i];
1962 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1963 buf_priv->age = 0;
1964 }
1965 }
1966
1967 /* ================================================================
1968 * CP command submission
1969 */
1970
1971 int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
1972 {
1973 drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1974 int i;
1975 u32 last_head = GET_RING_HEAD(dev_priv);
1976
1977 for (i = 0; i < dev_priv->usec_timeout; i++) {
1978 u32 head = GET_RING_HEAD(dev_priv);
1979
1980 ring->space = (head - ring->tail) * sizeof(u32);
1981 if (ring->space <= 0)
1982 ring->space += ring->size;
1983 if (ring->space > n)
1984 return 0;
1985
1986 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1987
1988 if (head != last_head)
1989 i = 0;
1990 last_head = head;
1991
1992 DRM_UDELAY(1);
1993 }
1994
1995 /* FIXME: This return value is ignored in the BEGIN_RING macro! */
1996 #if RADEON_FIFO_DEBUG
1997 radeon_status(dev_priv);
1998 DRM_ERROR("failed!\n");
1999 #endif
2000 return -EBUSY;
2001 }
2002
2003 static int radeon_cp_get_buffers(struct drm_device *dev,
2004 struct drm_file *file_priv,
2005 struct drm_dma * d)
2006 {
2007 int i;
2008 struct drm_buf *buf;
2009
2010 for (i = d->granted_count; i < d->request_count; i++) {
2011 buf = radeon_freelist_get(dev);
2012 if (!buf)
2013 return -EBUSY; /* NOTE: broken client */
2014
2015 buf->file_priv = file_priv;
2016
2017 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
2018 sizeof(buf->idx)))
2019 return -EFAULT;
2020 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
2021 sizeof(buf->total)))
2022 return -EFAULT;
2023
2024 d->granted_count++;
2025 }
2026 return 0;
2027 }
2028
2029 int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
2030 {
2031 struct drm_device_dma *dma = dev->dma;
2032 int ret = 0;
2033 struct drm_dma *d = data;
2034
2035 LOCK_TEST_WITH_RETURN(dev, file_priv);
2036
2037 /* Please don't send us buffers.
2038 */
2039 if (d->send_count != 0) {
2040 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
2041 DRM_CURRENTPID, d->send_count);
2042 return -EINVAL;
2043 }
2044
2045 /* We'll send you buffers.
2046 */
2047 if (d->request_count < 0 || d->request_count > dma->buf_count) {
2048 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
2049 DRM_CURRENTPID, d->request_count, dma->buf_count);
2050 return -EINVAL;
2051 }
2052
2053 d->granted_count = 0;
2054
2055 if (d->request_count) {
2056 ret = radeon_cp_get_buffers(dev, file_priv, d);
2057 }
2058
2059 return ret;
2060 }
2061
2062 int radeon_driver_load(struct drm_device *dev, unsigned long flags)
2063 {
2064 drm_radeon_private_t *dev_priv;
2065 int ret = 0;
2066
2067 dev_priv = kmalloc(sizeof(drm_radeon_private_t), M_DRM,
2068 M_ZERO | M_WAITOK);
2069 if (dev_priv == NULL)
2070 return -ENOMEM;
2071
2072 dev->dev_private = (void *)dev_priv;
2073 dev_priv->flags = flags;
2074
2075 switch (flags & RADEON_FAMILY_MASK) {
2076 case CHIP_R100:
2077 case CHIP_RV200:
2078 case CHIP_R200:
2079 case CHIP_R300:
2080 case CHIP_R350:
2081 case CHIP_R420:
2082 case CHIP_R423:
2083 case CHIP_RV410:
2084 case CHIP_RV515:
2085 case CHIP_R520:
2086 case CHIP_RV570:
2087 case CHIP_R580:
2088 dev_priv->flags |= RADEON_HAS_HIERZ;
2089 break;
2090 default:
2091 /* all other chips have no hierarchical z buffer */
2092 break;
2093 }
2094
2095 pci_enable_busmaster(dev->dev);
2096
2097 if (drm_device_is_agp(dev))
2098 dev_priv->flags |= RADEON_IS_AGP;
2099 else if (drm_device_is_pcie(dev))
2100 dev_priv->flags |= RADEON_IS_PCIE;
2101 else
2102 dev_priv->flags |= RADEON_IS_PCI;
2103
2104 ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
2105 drm_get_resource_len(dev, 2), _DRM_REGISTERS,
2106 _DRM_READ_ONLY | _DRM_DRIVER, &dev_priv->mmio);
2107 if (ret != 0)
2108 return ret;
2109
2110 ret = drm_vblank_init(dev, 2);
2111 if (ret) {
2112 radeon_driver_unload(dev);
2113 return ret;
2114 }
2115
2116 DRM_DEBUG("%s card detected\n",
2117 ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
2118 return ret;
2119 }
2120
2121 int radeon_master_create(struct drm_device *dev, struct drm_master *master)
2122 {
2123 struct drm_radeon_master_private *master_priv;
2124 unsigned long sareapage;
2125 int ret;
2126
2127 master_priv = kmalloc(sizeof(*master_priv), M_DRM,
2128 M_ZERO | M_WAITOK);
2129 if (!master_priv)
2130 return -ENOMEM;
2131
2132 /* prebuild the SAREA */
2133 sareapage = max_t(unsigned long, SAREA_MAX, PAGE_SIZE);
2134 ret = drm_addmap(dev, 0, sareapage, _DRM_SHM, _DRM_CONTAINS_LOCK,
2135 &master_priv->sarea);
2136 if (ret) {
2137 DRM_ERROR("SAREA setup failed\n");
2138 drm_free(master_priv, M_DRM);
2139 return ret;
2140 }
2141 master_priv->sarea_priv = (drm_radeon_sarea_t *)((char *)master_priv->sarea->handle) +
2142 sizeof(struct drm_sarea);
2143 master_priv->sarea_priv->pfCurrentPage = 0;
2144
2145 master->driver_priv = master_priv;
2146 return 0;
2147 }
2148
2149 void radeon_master_destroy(struct drm_device *dev, struct drm_master *master)
2150 {
2151 struct drm_radeon_master_private *master_priv = master->driver_priv;
2152
2153 if (!master_priv)
2154 return;
2155
2156 if (master_priv->sarea_priv &&
2157 master_priv->sarea_priv->pfCurrentPage != 0)
2158 radeon_cp_dispatch_flip(dev, master);
2159
2160 master_priv->sarea_priv = NULL;
2161 if (master_priv->sarea)
2162 #ifdef __linux__
2163 drm_rmmap_locked(dev, master_priv->sarea);
2164 #else
2165 drm_rmmap(dev, master_priv->sarea);
2166 #endif
2167
2168 drm_free(master_priv, M_DRM);
2169
2170 master->driver_priv = NULL;
2171 }
2172
2173 /* Create mappings for registers and framebuffer so userland doesn't necessarily
2174 * have to find them.
2175 */
2176 int radeon_driver_firstopen(struct drm_device *dev)
2177 {
2178 int ret;
2179 drm_local_map_t *map;
2180 drm_radeon_private_t *dev_priv = dev->dev_private;
2181
2182 dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
2183
2184 dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0);
2185 ret = drm_addmap(dev, dev_priv->fb_aper_offset,
2186 drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER,
2187 _DRM_WRITE_COMBINING, &map);
2188 if (ret != 0)
2189 return ret;
2190
2191 return 0;
2192 }
2193
2194 int radeon_driver_unload(struct drm_device *dev)
2195 {
2196 drm_radeon_private_t *dev_priv = dev->dev_private;
2197
2198 DRM_DEBUG("\n");
2199
2200 drm_rmmap(dev, dev_priv->mmio);
2201
2202 drm_free(dev_priv, M_DRM);
2203
2204 dev->dev_private = NULL;
2205 return 0;
2206 }
2207
2208 void radeon_commit_ring(drm_radeon_private_t *dev_priv)
2209 {
2210 int i;
2211 u32 *ring;
2212 int tail_aligned;
2213
2214 /* check if the ring is padded out to 16-dword alignment */
2215
2216 tail_aligned = dev_priv->ring.tail & (RADEON_RING_ALIGN-1);
2217 if (tail_aligned) {
2218 int num_p2 = RADEON_RING_ALIGN - tail_aligned;
2219
2220 ring = dev_priv->ring.start;
2221 /* pad with some CP_PACKET2 */
2222 for (i = 0; i < num_p2; i++)
2223 ring[dev_priv->ring.tail + i] = CP_PACKET2();
2224
2225 dev_priv->ring.tail += i;
2226
2227 dev_priv->ring.space -= num_p2 * sizeof(u32);
2228 }
2229
2230 dev_priv->ring.tail &= dev_priv->ring.tail_mask;
2231
2232 DRM_MEMORYBARRIER();
2233 GET_RING_HEAD( dev_priv );
2234
2235 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
2236 RADEON_WRITE(R600_CP_RB_WPTR, dev_priv->ring.tail);
2237 /* read from PCI bus to ensure correct posting */
2238 RADEON_READ(R600_CP_RB_RPTR);
2239 } else {
2240 RADEON_WRITE(RADEON_CP_RB_WPTR, dev_priv->ring.tail);
2241 /* read from PCI bus to ensure correct posting */
2242 RADEON_READ(RADEON_CP_RB_RPTR);
2243 }
2244 }
DragonFly BSD