sys/dev/drm/i915/i915_drv.h

   1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #ifndef _I915_DRV_H_
  31 #define _I915_DRV_H_
  32
  33 #include <dev/agp/intel-gtt.h>
  34 #include "i915_reg.h"
  35 #include "intel_bios.h"
  36 #include "intel_ringbuffer.h"
  37 #include <linux/completion.h>
  38 #include <linux/i2c.h>
  39 #include <linux/kref.h>
  40 #include <linux/workqueue.h>
  41
  42 #define CONFIG_ACPI 1
  43
  44 /* General customization:
  45  */
  46
  47 #define DRIVER_AUTHOR           "Tungsten Graphics, Inc."
  48
  49 #define DRIVER_NAME             "i915"
  50 #define DRIVER_DESC             "Intel Graphics"
  51 #define DRIVER_DATE             "20080730"
  52
  53 enum i915_pipe {
  54         PIPE_A = 0,
  55         PIPE_B,
  56         PIPE_C,
  57         I915_MAX_PIPES
  58 };
  59 #define pipe_name(p) ((p) + 'A')
  60
  61 enum transcoder {
  62         TRANSCODER_A = 0,
  63         TRANSCODER_B,
  64         TRANSCODER_C,
  65         TRANSCODER_EDP = 0xF,
  66 };
  67 #define transcoder_name(t) ((t) + 'A')
  68
  69 enum plane {
  70         PLANE_A = 0,
  71         PLANE_B,
  72         PLANE_C,
  73 };
  74 #define plane_name(p) ((p) + 'A')
  75
  76 enum port {
  77         PORT_A = 0,
  78         PORT_B,
  79         PORT_C,
  80         PORT_D,
  81         PORT_E,
  82         I915_MAX_PORTS
  83 };
  84 #define port_name(p) ((p) + 'A')
  85
  86 #define I915_GEM_GPU_DOMAINS    (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
  87
  88 #define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++)
  89
  90 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
  91         list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
  92                 if ((intel_encoder)->base.crtc == (__crtc))
  93
  94 struct intel_pch_pll {
  95         int refcount; /* count of number of CRTCs sharing this PLL */
  96         int active; /* count of number of active CRTCs (i.e. DPMS on) */
  97         bool on; /* is the PLL actually active? Disabled during modeset */
  98         int pll_reg;
  99         int fp0_reg;
 100         int fp1_reg;
 101 };
 102 #define I915_NUM_PLLS 2
 103
 104 struct intel_ddi_plls {
 105         int spll_refcount;
 106         int wrpll1_refcount;
 107         int wrpll2_refcount;
 108 };
 109
 110 /* Interface history:
 111  *
 112  * 1.1: Original.
 113  * 1.2: Add Power Management
 114  * 1.3: Add vblank support
 115  * 1.4: Fix cmdbuffer path, add heap destroy
 116  * 1.5: Add vblank pipe configuration
 117  * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
 118  *      - Support vertical blank on secondary display pipe
 119  */
 120 #define DRIVER_MAJOR            1
 121 #define DRIVER_MINOR            6
 122 #define DRIVER_PATCHLEVEL       0
 123
 124 #define WATCH_COHERENCY 0
 125 #define WATCH_LISTS     0
 126 #define WATCH_GTT       0
 127
 128 #define I915_GEM_PHYS_CURSOR_0 1
 129 #define I915_GEM_PHYS_CURSOR_1 2
 130 #define I915_GEM_PHYS_OVERLAY_REGS 3
 131 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
 132
 133 struct drm_i915_gem_phys_object {
 134         int id;
 135         drm_dma_handle_t *handle;
 136         struct drm_i915_gem_object *cur_obj;
 137 };
 138
 139 struct opregion_header;
 140 struct opregion_acpi;
 141 struct opregion_swsci;
 142 struct opregion_asle;
 143 struct drm_i915_private;
 144
 145 struct intel_opregion {
 146         struct opregion_header __iomem *header;
 147         struct opregion_acpi __iomem *acpi;
 148         struct opregion_swsci __iomem *swsci;
 149         struct opregion_asle __iomem *asle;
 150         void __iomem *vbt;
 151         u32 __iomem *lid_state;
 152 };
 153 #define OPREGION_SIZE            (8*1024)
 154
 155 struct intel_overlay;
 156 struct intel_overlay_error_state;
 157
 158 struct drm_i915_master_private {
 159         drm_local_map_t *sarea;
 160         struct _drm_i915_sarea *sarea_priv;
 161 };
 162 #define I915_FENCE_REG_NONE -1
 163 #define I915_MAX_NUM_FENCES 16
 164 /* 16 fences + sign bit for FENCE_REG_NONE */
 165 #define I915_MAX_NUM_FENCE_BITS 5
 166
 167 struct drm_i915_fence_reg {
 168         struct list_head lru_list;
 169         struct drm_i915_gem_object *obj;
 170         int pin_count;
 171 };
 172
 173 struct sdvo_device_mapping {
 174         u8 initialized;
 175         u8 dvo_port;
 176         u8 slave_addr;
 177         u8 dvo_wiring;
 178         u8 i2c_pin;
 179         u8 ddc_pin;
 180 };
 181
 182 struct intel_display_error_state;
 183
 184 struct drm_i915_error_state {
 185         struct kref ref;
 186         u32 eir;
 187         u32 pgtbl_er;
 188         u32 ier;
 189         u32 ccid;
 190         u32 derrmr;
 191         u32 forcewake;
 192         bool waiting[I915_NUM_RINGS];
 193         u32 pipestat[I915_MAX_PIPES];
 194         u32 tail[I915_NUM_RINGS];
 195         u32 head[I915_NUM_RINGS];
 196         u32 ctl[I915_NUM_RINGS];
 197         u32 ipeir[I915_NUM_RINGS];
 198         u32 ipehr[I915_NUM_RINGS];
 199         u32 instdone[I915_NUM_RINGS];
 200         u32 acthd[I915_NUM_RINGS];
 201         u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1];
 202         u32 semaphore_seqno[I915_NUM_RINGS][I915_NUM_RINGS - 1];
 203         u32 rc_psmi[I915_NUM_RINGS]; /* sleep state */
 204         /* our own tracking of ring head and tail */
 205         u32 cpu_ring_head[I915_NUM_RINGS];
 206         u32 cpu_ring_tail[I915_NUM_RINGS];
 207         u32 error; /* gen6+ */
 208         u32 err_int; /* gen7 */
 209         u32 instpm[I915_NUM_RINGS];
 210         u32 instps[I915_NUM_RINGS];
 211         u32 extra_instdone[I915_NUM_INSTDONE_REG];
 212         u32 seqno[I915_NUM_RINGS];
 213         u64 bbaddr;
 214         u32 fault_reg[I915_NUM_RINGS];
 215         u32 done_reg;
 216         u32 faddr[I915_NUM_RINGS];
 217         u64 fence[I915_MAX_NUM_FENCES];
 218         struct timeval time;
 219         struct drm_i915_error_ring {
 220                 struct drm_i915_error_object {
 221                         int page_count;
 222                         u32 gtt_offset;
 223                         u32 *pages[0];
 224                 } *ringbuffer, *batchbuffer;
 225                 struct drm_i915_error_request {
 226                         long jiffies;
 227                         u32 seqno;
 228                         u32 tail;
 229                 } *requests;
 230                 int num_requests;
 231         } ring[I915_NUM_RINGS];
 232         struct drm_i915_error_buffer {
 233                 u32 size;
 234                 u32 name;
 235                 u32 rseqno, wseqno;
 236                 u32 gtt_offset;
 237                 u32 read_domains;
 238                 u32 write_domain;
 239                 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
 240                 s32 pinned:2;
 241                 u32 tiling:2;
 242                 u32 dirty:1;
 243                 u32 purgeable:1;
 244                 s32 ring:4;
 245                 u32 cache_level:2;
 246         } *active_bo, *pinned_bo;
 247         u32 active_bo_count, pinned_bo_count;
 248         struct intel_overlay_error_state *overlay;
 249         struct intel_display_error_state *display;
 250 };
 251
 252 struct drm_i915_display_funcs {
 253         bool (*fbc_enabled)(struct drm_device *dev);
 254         void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
 255         void (*disable_fbc)(struct drm_device *dev);
 256         int (*get_display_clock_speed)(struct drm_device *dev);
 257         int (*get_fifo_size)(struct drm_device *dev, int plane);
 258         void (*update_wm)(struct drm_device *dev);
 259         void (*update_sprite_wm)(struct drm_device *dev, int pipe,
 260                                  uint32_t sprite_width, int pixel_size);
 261         void (*update_linetime_wm)(struct drm_device *dev, int pipe,
 262                                  struct drm_display_mode *mode);
 263         void (*modeset_global_resources)(struct drm_device *dev);
 264         int (*crtc_mode_set)(struct drm_crtc *crtc,
 265                              struct drm_display_mode *mode,
 266                              struct drm_display_mode *adjusted_mode,
 267                              int x, int y,
 268                              struct drm_framebuffer *old_fb);
 269         void (*crtc_enable)(struct drm_crtc *crtc);
 270         void (*crtc_disable)(struct drm_crtc *crtc);
 271         void (*off)(struct drm_crtc *crtc);
 272         void (*write_eld)(struct drm_connector *connector,
 273                           struct drm_crtc *crtc);
 274         void (*fdi_link_train)(struct drm_crtc *crtc);
 275         void (*init_clock_gating)(struct drm_device *dev);
 276         int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
 277                           struct drm_framebuffer *fb,
 278                           struct drm_i915_gem_object *obj);
 279         int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,
 280                             int x, int y);
 281         /* clock updates for mode set */
 282         /* cursor updates */
 283         /* render clock increase/decrease */
 284         /* display clock increase/decrease */
 285         /* pll clock increase/decrease */
 286 };
 287
 288 struct drm_i915_gt_funcs {
 289         void (*force_wake_get)(struct drm_i915_private *dev_priv);
 290         void (*force_wake_put)(struct drm_i915_private *dev_priv);
 291 };
 292
 293 #define DEV_INFO_FLAGS \
 294         DEV_INFO_FLAG(is_mobile) DEV_INFO_SEP \
 295         DEV_INFO_FLAG(is_i85x) DEV_INFO_SEP \
 296         DEV_INFO_FLAG(is_i915g) DEV_INFO_SEP \
 297         DEV_INFO_FLAG(is_i945gm) DEV_INFO_SEP \
 298         DEV_INFO_FLAG(is_g33) DEV_INFO_SEP \
 299         DEV_INFO_FLAG(need_gfx_hws) DEV_INFO_SEP \
 300         DEV_INFO_FLAG(is_g4x) DEV_INFO_SEP \
 301         DEV_INFO_FLAG(is_pineview) DEV_INFO_SEP \
 302         DEV_INFO_FLAG(is_broadwater) DEV_INFO_SEP \
 303         DEV_INFO_FLAG(is_crestline) DEV_INFO_SEP \
 304         DEV_INFO_FLAG(is_ivybridge) DEV_INFO_SEP \
 305         DEV_INFO_FLAG(is_valleyview) DEV_INFO_SEP \
 306         DEV_INFO_FLAG(is_haswell) DEV_INFO_SEP \
 307         DEV_INFO_FLAG(has_force_wake) DEV_INFO_SEP \
 308         DEV_INFO_FLAG(has_fbc) DEV_INFO_SEP \
 309         DEV_INFO_FLAG(has_pipe_cxsr) DEV_INFO_SEP \
 310         DEV_INFO_FLAG(has_hotplug) DEV_INFO_SEP \
 311         DEV_INFO_FLAG(cursor_needs_physical) DEV_INFO_SEP \
 312         DEV_INFO_FLAG(has_overlay) DEV_INFO_SEP \
 313         DEV_INFO_FLAG(overlay_needs_physical) DEV_INFO_SEP \
 314         DEV_INFO_FLAG(supports_tv) DEV_INFO_SEP \
 315         DEV_INFO_FLAG(has_bsd_ring) DEV_INFO_SEP \
 316         DEV_INFO_FLAG(has_blt_ring) DEV_INFO_SEP \
 317         DEV_INFO_FLAG(has_llc)
 318
 319 struct intel_device_info {
 320         u8 gen;
 321         u8 is_mobile:1;
 322         u8 is_i85x:1;
 323         u8 is_i915g:1;
 324         u8 is_i945gm:1;
 325         u8 is_g33:1;
 326         u8 need_gfx_hws:1;
 327         u8 is_g4x:1;
 328         u8 is_pineview:1;
 329         u8 is_broadwater:1;
 330         u8 is_crestline:1;
 331         u8 is_ivybridge:1;
 332         u8 is_valleyview:1;
 333         u8 has_force_wake:1;
 334         u8 is_haswell:1;
 335         u8 has_fbc:1;
 336         u8 has_pipe_cxsr:1;
 337         u8 has_hotplug:1;
 338         u8 cursor_needs_physical:1;
 339         u8 has_overlay:1;
 340         u8 overlay_needs_physical:1;
 341         u8 supports_tv:1;
 342         u8 has_bsd_ring:1;
 343         u8 has_blt_ring:1;
 344         u8 has_llc:1;
 345 };
 346
 347 #define I915_PPGTT_PD_ENTRIES 512
 348 #define I915_PPGTT_PT_ENTRIES 1024
 349 struct i915_hw_ppgtt {
 350         struct drm_device *dev;
 351         unsigned num_pd_entries;
 352         vm_page_t *pt_pages;
 353         uint32_t pd_offset;
 354         vm_paddr_t *pt_dma_addr;
 355         vm_paddr_t scratch_page_dma_addr;
 356 };
 357
 358
 359 /* This must match up with the value previously used for execbuf2.rsvd1. */
 360 #define DEFAULT_CONTEXT_ID 0
 361 struct i915_hw_context {
 362         int id;
 363         bool is_initialized;
 364         struct drm_i915_file_private *file_priv;
 365         struct intel_ring_buffer *ring;
 366         struct drm_i915_gem_object *obj;
 367 };
 368
 369 enum no_fbc_reason {
 370         FBC_NO_OUTPUT, /* no outputs enabled to compress */
 371         FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
 372         FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
 373         FBC_MODE_TOO_LARGE, /* mode too large for compression */
 374         FBC_BAD_PLANE, /* fbc not supported on plane */
 375         FBC_NOT_TILED, /* buffer not tiled */
 376         FBC_MULTIPLE_PIPES, /* more than one pipe active */
 377         FBC_MODULE_PARAM,
 378 };
 379
 380 enum intel_pch {
 381         PCH_NONE = 0,   /* No PCH present */
 382         PCH_IBX,        /* Ibexpeak PCH */
 383         PCH_CPT,        /* Cougarpoint PCH */
 384         PCH_LPT,        /* Lynxpoint PCH */
 385 };
 386
 387 enum intel_sbi_destination {
 388         SBI_ICLK,
 389         SBI_MPHY,
 390 };
 391
 392 #define QUIRK_PIPEA_FORCE (1<<0)
 393 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
 394 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
 395
 396 struct intel_fbdev;
 397 struct intel_fbc_work;
 398
 399 struct intel_gmbus {
 400         u32 force_bit;
 401         u32 reg0;
 402         u32 gpio_reg;
 403         struct drm_i915_private *dev_priv;
 404 };
 405
 406 struct intel_iic_softc {
 407         struct drm_device *drm_dev;
 408         device_t iic_dev;
 409         bool force_bit_dev;
 410         char name[32];
 411         uint32_t reg;
 412         uint32_t reg0;
 413 };
 414
 415 struct i915_suspend_saved_registers {
 416         u8 saveLBB;
 417         u32 saveDSPACNTR;
 418         u32 saveDSPBCNTR;
 419         u32 saveDSPARB;
 420         u32 savePIPEACONF;
 421         u32 savePIPEBCONF;
 422         u32 savePIPEASRC;
 423         u32 savePIPEBSRC;
 424         u32 saveFPA0;
 425         u32 saveFPA1;
 426         u32 saveDPLL_A;
 427         u32 saveDPLL_A_MD;
 428         u32 saveHTOTAL_A;
 429         u32 saveHBLANK_A;
 430         u32 saveHSYNC_A;
 431         u32 saveVTOTAL_A;
 432         u32 saveVBLANK_A;
 433         u32 saveVSYNC_A;
 434         u32 saveBCLRPAT_A;
 435         u32 saveTRANSACONF;
 436         u32 saveTRANS_HTOTAL_A;
 437         u32 saveTRANS_HBLANK_A;
 438         u32 saveTRANS_HSYNC_A;
 439         u32 saveTRANS_VTOTAL_A;
 440         u32 saveTRANS_VBLANK_A;
 441         u32 saveTRANS_VSYNC_A;
 442         u32 savePIPEASTAT;
 443         u32 saveDSPASTRIDE;
 444         u32 saveDSPASIZE;
 445         u32 saveDSPAPOS;
 446         u32 saveDSPAADDR;
 447         u32 saveDSPASURF;
 448         u32 saveDSPATILEOFF;
 449         u32 savePFIT_PGM_RATIOS;
 450         u32 saveBLC_HIST_CTL;
 451         u32 saveBLC_PWM_CTL;
 452         u32 saveBLC_PWM_CTL2;
 453         u32 saveBLC_CPU_PWM_CTL;
 454         u32 saveBLC_CPU_PWM_CTL2;
 455         u32 saveFPB0;
 456         u32 saveFPB1;
 457         u32 saveDPLL_B;
 458         u32 saveDPLL_B_MD;
 459         u32 saveHTOTAL_B;
 460         u32 saveHBLANK_B;
 461         u32 saveHSYNC_B;
 462         u32 saveVTOTAL_B;
 463         u32 saveVBLANK_B;
 464         u32 saveVSYNC_B;
 465         u32 saveBCLRPAT_B;
 466         u32 saveTRANSBCONF;
 467         u32 saveTRANS_HTOTAL_B;
 468         u32 saveTRANS_HBLANK_B;
 469         u32 saveTRANS_HSYNC_B;
 470         u32 saveTRANS_VTOTAL_B;
 471         u32 saveTRANS_VBLANK_B;
 472         u32 saveTRANS_VSYNC_B;
 473         u32 savePIPEBSTAT;
 474         u32 saveDSPBSTRIDE;
 475         u32 saveDSPBSIZE;
 476         u32 saveDSPBPOS;
 477         u32 saveDSPBADDR;
 478         u32 saveDSPBSURF;
 479         u32 saveDSPBTILEOFF;
 480         u32 saveVGA0;
 481         u32 saveVGA1;
 482         u32 saveVGA_PD;
 483         u32 saveVGACNTRL;
 484         u32 saveADPA;
 485         u32 saveLVDS;
 486         u32 savePP_ON_DELAYS;
 487         u32 savePP_OFF_DELAYS;
 488         u32 saveDVOA;
 489         u32 saveDVOB;
 490         u32 saveDVOC;
 491         u32 savePP_ON;
 492         u32 savePP_OFF;
 493         u32 savePP_CONTROL;
 494         u32 savePP_DIVISOR;
 495         u32 savePFIT_CONTROL;
 496         u32 save_palette_a[256];
 497         u32 save_palette_b[256];
 498         u32 saveDPFC_CB_BASE;
 499         u32 saveFBC_CFB_BASE;
 500         u32 saveFBC_LL_BASE;
 501         u32 saveFBC_CONTROL;
 502         u32 saveFBC_CONTROL2;
 503         u32 saveIER;
 504         u32 saveIIR;
 505         u32 saveIMR;
 506         u32 saveDEIER;
 507         u32 saveDEIMR;
 508         u32 saveGTIER;
 509         u32 saveGTIMR;
 510         u32 saveFDI_RXA_IMR;
 511         u32 saveFDI_RXB_IMR;
 512         u32 saveCACHE_MODE_0;
 513         u32 saveMI_ARB_STATE;
 514         u32 saveSWF0[16];
 515         u32 saveSWF1[16];
 516         u32 saveSWF2[3];
 517         u8 saveMSR;
 518         u8 saveSR[8];
 519         u8 saveGR[25];
 520         u8 saveAR_INDEX;
 521         u8 saveAR[21];
 522         u8 saveDACMASK;
 523         u8 saveCR[37];
 524         uint64_t saveFENCE[I915_MAX_NUM_FENCES];
 525         u32 saveCURACNTR;
 526         u32 saveCURAPOS;
 527         u32 saveCURABASE;
 528         u32 saveCURBCNTR;
 529         u32 saveCURBPOS;
 530         u32 saveCURBBASE;
 531         u32 saveCURSIZE;
 532         u32 saveDP_B;
 533         u32 saveDP_C;
 534         u32 saveDP_D;
 535         u32 savePIPEA_GMCH_DATA_M;
 536         u32 savePIPEB_GMCH_DATA_M;
 537         u32 savePIPEA_GMCH_DATA_N;
 538         u32 savePIPEB_GMCH_DATA_N;
 539         u32 savePIPEA_DP_LINK_M;
 540         u32 savePIPEB_DP_LINK_M;
 541         u32 savePIPEA_DP_LINK_N;
 542         u32 savePIPEB_DP_LINK_N;
 543         u32 saveFDI_RXA_CTL;
 544         u32 saveFDI_TXA_CTL;
 545         u32 saveFDI_RXB_CTL;
 546         u32 saveFDI_TXB_CTL;
 547         u32 savePFA_CTL_1;
 548         u32 savePFB_CTL_1;
 549         u32 savePFA_WIN_SZ;
 550         u32 savePFB_WIN_SZ;
 551         u32 savePFA_WIN_POS;
 552         u32 savePFB_WIN_POS;
 553         u32 savePCH_DREF_CONTROL;
 554         u32 saveDISP_ARB_CTL;
 555         u32 savePIPEA_DATA_M1;
 556         u32 savePIPEA_DATA_N1;
 557         u32 savePIPEA_LINK_M1;
 558         u32 savePIPEA_LINK_N1;
 559         u32 savePIPEB_DATA_M1;
 560         u32 savePIPEB_DATA_N1;
 561         u32 savePIPEB_LINK_M1;
 562         u32 savePIPEB_LINK_N1;
 563         u32 saveMCHBAR_RENDER_STANDBY;
 564         u32 savePCH_PORT_HOTPLUG;
 565 };
 566
 567 struct intel_gen6_power_mgmt {
 568         struct work_struct work;
 569         u32 pm_iir;
 570         /* lock - irqsave spinlock that protectects the work_struct and
 571          * pm_iir. */
 572         struct spinlock lock;
 573
 574         /* The below variables an all the rps hw state are protected by
 575          * dev->struct mutext. */
 576         u8 cur_delay;
 577         u8 min_delay;
 578         u8 max_delay;
 579
 580         struct delayed_work delayed_resume_work;
 581
 582         /*
 583          * Protects RPS/RC6 register access and PCU communication.
 584          * Must be taken after struct_mutex if nested.
 585          */
 586         struct lock hw_lock;
 587 };
 588
 589 struct intel_ilk_power_mgmt {
 590         u8 cur_delay;
 591         u8 min_delay;
 592         u8 max_delay;
 593         u8 fmax;
 594         u8 fstart;
 595
 596         u64 last_count1;
 597         unsigned long last_time1;
 598         unsigned long chipset_power;
 599         u64 last_count2;
 600         struct timespec last_time2;
 601         unsigned long gfx_power;
 602         u8 corr;
 603
 604         int c_m;
 605         int r_t;
 606
 607         struct drm_i915_gem_object *pwrctx;
 608         struct drm_i915_gem_object *renderctx;
 609 };
 610
 611 struct i915_dri1_state {
 612         unsigned allow_batchbuffer : 1;
 613         u32 __iomem *gfx_hws_cpu_addr;
 614
 615         unsigned int cpp;
 616         int back_offset;
 617         int front_offset;
 618         int current_page;
 619         int page_flipping;
 620
 621         uint32_t counter;
 622 };
 623
 624 struct intel_l3_parity {
 625         u32 *remap_info;
 626         struct work_struct error_work;
 627 };
 628
 629 typedef struct drm_i915_private {
 630         struct drm_device *dev;
 631
 632         const struct intel_device_info *info;
 633
 634         int relative_constants_mode;
 635
 636         device_t *gmbus_bridge;
 637         device_t *bbbus_bridge;
 638         device_t *bbbus;
 639
 640         drm_local_map_t *sarea;
 641         drm_local_map_t *mmio_map;
 642         void __iomem *regs;
 643
 644         struct drm_i915_gt_funcs gt;
 645         /** gt_fifo_count and the subsequent register write are synchronized
 646          * with dev->struct_mutex. */
 647         unsigned gt_fifo_count;
 648         /** forcewake_count is protected by gt_lock */
 649         unsigned forcewake_count;
 650         /** gt_lock is also taken in irq contexts. */
 651         struct lock gt_lock;
 652
 653         device_t *gmbus;
 654
 655         /** gmbus_mutex protects against concurrent usage of the single hw gmbus
 656          * controller on different i2c buses. */
 657         struct lock gmbus_mutex;
 658
 659         drm_i915_sarea_t *sarea_priv;
 660         /**
 661          * Base address of the gmbus and gpio block.
 662          */
 663         uint32_t gpio_mmio_base;
 664
 665         struct device *bridge_dev;
 666         struct intel_ring_buffer ring[I915_NUM_RINGS];
 667         uint32_t next_seqno;
 668
 669         drm_dma_handle_t *status_page_dmah;
 670         struct resource *mch_res;
 671         int mch_res_rid;
 672
 673         void *hw_status_page;
 674         dma_addr_t dma_status_page;
 675         unsigned int status_gfx_addr;
 676         drm_local_map_t hws_map;
 677
 678         unsigned int cpp;
 679         int back_offset;
 680         int front_offset;
 681         int current_page;
 682
 683         atomic_t irq_received;
 684
 685         /* protects the irq masks */
 686         struct lock irq_lock;
 687
 688         /* DPIO indirect register protection */
 689         struct spinlock dpio_lock;
 690
 691         /** Cached value of IMR to avoid reads in updating the bitfield */
 692         u32 pipestat[2];
 693         u32 irq_mask;
 694         u32 gt_irq_mask;
 695         u32 pch_irq_mask;
 696
 697         u32 hotplug_supported_mask;
 698         struct work_struct hotplug_work;
 699
 700         int num_pipe;
 701         int num_pch_pll;
 702
 703         /* For hangcheck timer */
 704 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
 705 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
 706         struct timer_list hangcheck_timer;
 707         int hangcheck_count;
 708         uint32_t last_acthd[I915_NUM_RINGS];
 709         uint32_t prev_instdone[I915_NUM_INSTDONE_REG];
 710
 711         unsigned int stop_rings;
 712
 713         unsigned long cfb_size;
 714         unsigned int cfb_fb;
 715         enum plane cfb_plane;
 716         int cfb_y;
 717         struct intel_fbc_work *fbc_work;
 718
 719         struct intel_opregion opregion;
 720
 721         /* overlay */
 722         struct intel_overlay *overlay;
 723         bool sprite_scaling_enabled;
 724
 725         /* LVDS info */
 726         int backlight_level;  /* restore backlight to this value */
 727         bool backlight_enabled;
 728         struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
 729         struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
 730
 731         /* Feature bits from the VBIOS */
 732         unsigned int int_tv_support:1;
 733         unsigned int lvds_dither:1;
 734         unsigned int lvds_vbt:1;
 735         unsigned int int_crt_support:1;
 736         unsigned int lvds_use_ssc:1;
 737         unsigned int display_clock_mode:1;
 738         unsigned int fdi_rx_polarity_inverted:1;
 739         int lvds_ssc_freq;
 740         unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
 741         unsigned int lvds_val; /* used for checking LVDS channel mode */
 742         struct {
 743                 int rate;
 744                 int lanes;
 745                 int preemphasis;
 746                 int vswing;
 747
 748                 bool initialized;
 749                 bool support;
 750                 int bpp;
 751                 struct edp_power_seq pps;
 752         } edp;
 753         bool no_aux_handshake;
 754
 755         int crt_ddc_pin;
 756         struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
 757         int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
 758         int num_fence_regs; /* 8 on pre-965, 16 otherwise */
 759
 760         unsigned int fsb_freq, mem_freq, is_ddr3;
 761
 762         struct lock error_lock;
 763         /* Protected by dev->error_lock. */
 764         struct drm_i915_error_state *first_error;
 765         struct work_struct error_work;
 766         struct completion error_completion;
 767         struct workqueue_struct *wq;
 768
 769         /* Display functions */
 770         struct drm_i915_display_funcs display;
 771
 772         /* PCH chipset type */
 773         enum intel_pch pch_type;
 774         unsigned short pch_id;
 775
 776         unsigned long quirks;
 777
 778         /* Register state */
 779         bool modeset_on_lid;
 780
 781         struct {
 782                 /** Bridge to intel-gtt-ko */
 783                 const struct intel_gtt *gtt;
 784                 /** Memory allocator for GTT stolen memory */
 785                 struct drm_mm stolen;
 786                 /** Memory allocator for GTT */
 787                 struct drm_mm gtt_space;
 788                 /** List of all objects in gtt_space. Used to restore gtt
 789                  * mappings on resume */
 790                 struct list_head gtt_list;
 791                 /**
 792                  * List of objects which are not bound to the GTT (thus
 793                  * are idle and not used by the GPU) but still have
 794                  * (presumably uncached) pages still attached.
 795                  */
 796                 struct list_head unbound_list;
 797
 798                 /** Usable portion of the GTT for GEM */
 799                 unsigned long gtt_start;
 800                 unsigned long gtt_mappable_end;
 801                 unsigned long gtt_end;
 802                 unsigned long stolen_base; /* limited to low memory (32-bit) */
 803
 804                 struct io_mapping *gtt_mapping;
 805                 phys_addr_t gtt_base_addr;
 806                 int gtt_mtrr;
 807
 808                 /** PPGTT used for aliasing the PPGTT with the GTT */
 809                 struct i915_hw_ppgtt *aliasing_ppgtt;
 810
 811                 bool shrinker_no_lock_stealing;
 812
 813                 /**
 814                  * List of objects currently involved in rendering.
 815                  *
 816                  * Includes buffers having the contents of their GPU caches
 817                  * flushed, not necessarily primitives.  last_rendering_seqno
 818                  * represents when the rendering involved will be completed.
 819                  *
 820                  * A reference is held on the buffer while on this list.
 821                  */
 822                 struct list_head active_list;
 823
 824                 /**
 825                  * LRU list of objects which are not in the ringbuffer and
 826                  * are ready to unbind, but are still in the GTT.
 827                  *
 828                  * last_rendering_seqno is 0 while an object is in this list.
 829                  *
 830                  * A reference is not held on the buffer while on this list,
 831                  * as merely being GTT-bound shouldn't prevent its being
 832                  * freed, and we'll pull it off the list in the free path.
 833                  */
 834                 struct list_head inactive_list;
 835
 836                 /** LRU list of objects with fence regs on them. */
 837                 struct list_head fence_list;
 838
 839                 /**
 840                  * We leave the user IRQ off as much as possible,
 841                  * but this means that requests will finish and never
 842                  * be retired once the system goes idle. Set a timer to
 843                  * fire periodically while the ring is running. When it
 844                  * fires, go retire requests.
 845                  */
 846                 struct delayed_work retire_work;
 847
 848                 /**
 849                  * Are we in a non-interruptible section of code like
 850                  * modesetting?
 851                  */
 852                 bool interruptible;
 853
 854                 /**
 855                  * Flag if the X Server, and thus DRM, is not currently in
 856                  * control of the device.
 857                  *
 858                  * This is set between LeaveVT and EnterVT.  It needs to be
 859                  * replaced with a semaphore.  It also needs to be
 860                  * transitioned away from for kernel modesetting.
 861                  */
 862                 int suspended;
 863
 864                 /**
 865                  * Flag if the hardware appears to be wedged.
 866                  *
 867                  * This is set when attempts to idle the device timeout.
 868                  * It prevents command submission from occurring and makes
 869                  * every pending request fail
 870                  */
 871                 atomic_t wedged;
 872
 873                 /** Bit 6 swizzling required for X tiling */
 874                 uint32_t bit_6_swizzle_x;
 875                 /** Bit 6 swizzling required for Y tiling */
 876                 uint32_t bit_6_swizzle_y;
 877
 878                 /* storage for physical objects */
 879                 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
 880
 881                 /* accounting, useful for userland debugging */
 882                 size_t gtt_total;
 883                 size_t mappable_gtt_total;
 884                 size_t object_memory;
 885                 u32 object_count;
 886
 887                 eventhandler_tag i915_lowmem;
 888         } mm;
 889
 890         /* Kernel Modesetting */
 891
 892         struct sdvo_device_mapping sdvo_mappings[2];
 893         /* indicate whether the LVDS_BORDER should be enabled or not */
 894         unsigned int lvds_border_bits;
 895         /* Panel fitter placement and size for Ironlake+ */
 896         u32 pch_pf_pos, pch_pf_size;
 897
 898         struct drm_crtc *plane_to_crtc_mapping[3];
 899         struct drm_crtc *pipe_to_crtc_mapping[3];
 900         wait_queue_head_t pending_flip_queue;
 901
 902         struct intel_pch_pll pch_plls[I915_NUM_PLLS];
 903         struct intel_ddi_plls ddi_plls;
 904
 905         /* Reclocking support */
 906         bool render_reclock_avail;
 907         bool lvds_downclock_avail;
 908         /* indicates the reduced downclock for LVDS*/
 909         int lvds_downclock;
 910         u16 orig_clock;
 911         int child_dev_num;
 912         struct child_device_config *child_dev;
 913
 914         bool mchbar_need_disable;
 915
 916         struct intel_l3_parity l3_parity;
 917
 918         /* gen6+ rps state */
 919         struct intel_gen6_power_mgmt rps;
 920
 921         /* ilk-only ips/rps state. Everything in here is protected by the global
 922          * mchdev_lock in intel_pm.c */
 923         struct intel_ilk_power_mgmt ips;
 924
 925         enum no_fbc_reason no_fbc_reason;
 926
 927         struct drm_mm_node *compressed_fb;
 928         struct drm_mm_node *compressed_llb;
 929
 930         unsigned long last_gpu_reset;
 931
 932         /* list of fbdev register on this device */
 933         struct intel_fbdev *fbdev;
 934
 935         /*
 936          * The console may be contended at resume, but we don't
 937          * want it to block on it.
 938          */
 939         struct work_struct console_resume_work;
 940
 941         struct backlight_device *backlight;
 942
 943         struct drm_property *broadcast_rgb_property;
 944         struct drm_property *force_audio_property;
 945
 946         bool hw_contexts_disabled;
 947         uint32_t hw_context_size;
 948
 949         u32 fdi_rx_config;
 950
 951         struct i915_suspend_saved_registers regfile;
 952
 953         /* Old dri1 support infrastructure, beware the dragons ya fools entering
 954          * here! */
 955         struct i915_dri1_state dri1;
 956 } drm_i915_private_t;
 957
 958 /* Iterate over initialised rings */
 959 #define for_each_ring(ring__, dev_priv__, i__) \
 960         for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
 961                 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
 962
 963 enum hdmi_force_audio {
 964         HDMI_AUDIO_OFF_DVI = -2,        /* no aux data for HDMI-DVI converter */
 965         HDMI_AUDIO_OFF,                 /* force turn off HDMI audio */
 966         HDMI_AUDIO_AUTO,                /* trust EDID */
 967         HDMI_AUDIO_ON,                  /* force turn on HDMI audio */
 968 };
 969
 970 enum i915_cache_level {
 971         I915_CACHE_NONE = 0,
 972         I915_CACHE_LLC,
 973         I915_CACHE_LLC_MLC, /* gen6+, in docs at least! */
 974 };
 975
 976 struct drm_i915_gem_object_ops {
 977         /* Interface between the GEM object and its backing storage.
 978          * get_pages() is called once prior to the use of the associated set
 979          * of pages before to binding them into the GTT, and put_pages() is
 980          * called after we no longer need them. As we expect there to be
 981          * associated cost with migrating pages between the backing storage
 982          * and making them available for the GPU (e.g. clflush), we may hold
 983          * onto the pages after they are no longer referenced by the GPU
 984          * in case they may be used again shortly (for example migrating the
 985          * pages to a different memory domain within the GTT). put_pages()
 986          * will therefore most likely be called when the object itself is
 987          * being released or under memory pressure (where we attempt to
 988          * reap pages for the shrinker).
 989          */
 990         int (*get_pages)(struct drm_i915_gem_object *);
 991         void (*put_pages)(struct drm_i915_gem_object *);
 992 };
 993
 994 struct drm_i915_gem_object {
 995         struct drm_gem_object base;
 996
 997         const struct drm_i915_gem_object_ops *ops;
 998
 999         /** Current space allocated to this object in the GTT, if any. */
1000         struct drm_mm_node *gtt_space;
1001         struct list_head gtt_list;
1002
1003         /** This object's place on the active/inactive lists */
1004         struct list_head ring_list;
1005         struct list_head mm_list;
1006         /** This object's place in the batchbuffer or on the eviction list */
1007         struct list_head exec_list;
1008
1009         /**
1010          * This is set if the object is on the active lists (has pending
1011          * rendering and so a non-zero seqno), and is not set if it i s on
1012          * inactive (ready to be unbound) list.
1013          */
1014         unsigned int active:1;
1015
1016         /**
1017          * This is set if the object has been written to since last bound
1018          * to the GTT
1019          */
1020         unsigned int dirty:1;
1021
1022         /**
1023          * Fence register bits (if any) for this object.  Will be set
1024          * as needed when mapped into the GTT.
1025          * Protected by dev->struct_mutex.
1026          */
1027         signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
1028
1029         /**
1030          * Advice: are the backing pages purgeable?
1031          */
1032         unsigned int madv:2;
1033
1034         /**
1035          * Current tiling mode for the object.
1036          */
1037         unsigned int tiling_mode:2;
1038         /**
1039          * Whether the tiling parameters for the currently associated fence
1040          * register have changed. Note that for the purposes of tracking
1041          * tiling changes we also treat the unfenced register, the register
1042          * slot that the object occupies whilst it executes a fenced
1043          * command (such as BLT on gen2/3), as a "fence".
1044          */
1045         unsigned int fence_dirty:1;
1046
1047         /** How many users have pinned this object in GTT space. The following
1048          * users can each hold at most one reference: pwrite/pread, pin_ioctl
1049          * (via user_pin_count), execbuffer (objects are not allowed multiple
1050          * times for the same batchbuffer), and the framebuffer code. When
1051          * switching/pageflipping, the framebuffer code has at most two buffers
1052          * pinned per crtc.
1053          *
1054          * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
1055          * bits with absolutely no headroom. So use 4 bits. */
1056         unsigned int pin_count:4;
1057 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
1058
1059         /**
1060          * Is the object at the current location in the gtt mappable and
1061          * fenceable? Used to avoid costly recalculations.
1062          */
1063         unsigned int map_and_fenceable:1;
1064
1065         /**
1066          * Whether the current gtt mapping needs to be mappable (and isn't just
1067          * mappable by accident). Track pin and fault separate for a more
1068          * accurate mappable working set.
1069          */
1070         unsigned int fault_mappable:1;
1071         unsigned int pin_mappable:1;
1072
1073         /*
1074          * Is the GPU currently using a fence to access this buffer,
1075          */
1076         unsigned int pending_fenced_gpu_access:1;
1077         unsigned int fenced_gpu_access:1;
1078
1079         unsigned int cache_level:2;
1080
1081         unsigned int has_aliasing_ppgtt_mapping:1;
1082         unsigned int has_global_gtt_mapping:1;
1083         unsigned int has_dma_mapping:1;
1084
1085         vm_page_t *pages;
1086
1087         /**
1088          * Used for performing relocations during execbuffer insertion.
1089          */
1090         struct hlist_node exec_node;
1091         unsigned long exec_handle;
1092         struct drm_i915_gem_exec_object2 *exec_entry;
1093
1094         /**
1095          * Current offset of the object in GTT space.
1096          *
1097          * This is the same as gtt_space->start
1098          */
1099         uint32_t gtt_offset;
1100
1101         struct intel_ring_buffer *ring;
1102
1103         /** Breadcrumb of last rendering to the buffer. */
1104         uint32_t last_read_seqno;
1105         uint32_t last_write_seqno;
1106         /** Breadcrumb of last fenced GPU access to the buffer. */
1107         uint32_t last_fenced_seqno;
1108
1109         /** Current tiling stride for the object, if it's tiled. */
1110         uint32_t stride;
1111
1112         /** Record of address bit 17 of each page at last unbind. */
1113         unsigned long *bit_17;
1114
1115         /** User space pin count and filp owning the pin */
1116         uint32_t user_pin_count;
1117         struct drm_file *pin_filp;
1118
1119         /** for phy allocated objects */
1120         struct drm_i915_gem_phys_object *phys_obj;
1121
1122         /**
1123          * Number of crtcs where this object is currently the fb, but
1124          * will be page flipped away on the next vblank.  When it
1125          * reaches 0, dev_priv->pending_flip_queue will be woken up.
1126          */
1127         atomic_t pending_flip;
1128 };
1129 #define to_gem_object(obj) (&((struct drm_i915_gem_object *)(obj))->base)
1130
1131 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1132
1133 /**
1134  * Request queue structure.
1135  *
1136  * The request queue allows us to note sequence numbers that have been emitted
1137  * and may be associated with active buffers to be retired.
1138  *
1139  * By keeping this list, we can avoid having to do questionable
1140  * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1141  * an emission time with seqnos for tracking how far ahead of the GPU we are.
1142  */
1143 struct drm_i915_gem_request {
1144         /** On Which ring this request was generated */
1145         struct intel_ring_buffer *ring;
1146
1147         /** GEM sequence number associated with this request. */
1148         uint32_t seqno;
1149
1150         /** Postion in the ringbuffer of the end of the request */
1151         u32 tail;
1152
1153         /** Time at which this request was emitted, in jiffies. */
1154         unsigned long emitted_jiffies;
1155
1156         /** global list entry for this request */
1157         struct list_head list;
1158
1159         struct drm_i915_file_private *file_priv;
1160         /** file_priv list entry for this request */
1161         struct list_head client_list;
1162 };
1163
1164 struct drm_i915_file_private {
1165         struct {
1166                 struct spinlock lock;
1167                 struct list_head request_list;
1168         } mm;
1169         struct idr context_idr;
1170 };
1171
1172 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
1173
1174 #define IS_I830(dev)            ((dev)->pci_device == 0x3577)
1175 #define IS_845G(dev)            ((dev)->pci_device == 0x2562)
1176 #define IS_I85X(dev)            (INTEL_INFO(dev)->is_i85x)
1177 #define IS_I865G(dev)           ((dev)->pci_device == 0x2572)
1178 #define IS_I915G(dev)           (INTEL_INFO(dev)->is_i915g)
1179 #define IS_I915GM(dev)          ((dev)->pci_device == 0x2592)
1180 #define IS_I945G(dev)           ((dev)->pci_device == 0x2772)
1181 #define IS_I945GM(dev)          (INTEL_INFO(dev)->is_i945gm)
1182 #define IS_BROADWATER(dev)      (INTEL_INFO(dev)->is_broadwater)
1183 #define IS_CRESTLINE(dev)       (INTEL_INFO(dev)->is_crestline)
1184 #define IS_GM45(dev)            ((dev)->pci_device == 0x2A42)
1185 #define IS_G4X(dev)             (INTEL_INFO(dev)->is_g4x)
1186 #define IS_PINEVIEW_G(dev)      ((dev)->pci_device == 0xa001)
1187 #define IS_PINEVIEW_M(dev)      ((dev)->pci_device == 0xa011)
1188 #define IS_PINEVIEW(dev)        (INTEL_INFO(dev)->is_pineview)
1189 #define IS_G33(dev)             (INTEL_INFO(dev)->is_g33)
1190 #define IS_IRONLAKE_D(dev)      ((dev)->pci_device == 0x0042)
1191 #define IS_IRONLAKE_M(dev)      ((dev)->pci_device == 0x0046)
1192 #define IS_IVYBRIDGE(dev)       (INTEL_INFO(dev)->is_ivybridge)
1193 #define IS_IVB_GT1(dev)         ((dev)->pci_device == 0x0156 || \
1194                                  (dev)->pci_device == 0x0152 || \
1195                                  (dev)->pci_device == 0x015a)
1196 #define IS_SNB_GT1(dev)         ((dev)->pci_device == 0x0102 || \
1197                                  (dev)->pci_device == 0x0106 || \
1198                                  (dev)->pci_device == 0x010A)
1199 #define IS_VALLEYVIEW(dev)      (INTEL_INFO(dev)->is_valleyview)
1200 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
1201 #define IS_MOBILE(dev)          (INTEL_INFO(dev)->is_mobile)
1202 #define IS_ULT(dev)             (IS_HASWELL(dev) && \
1203                                  ((dev)->pci_device & 0xFF00) == 0x0A00)
1204
1205 /*
1206  * The genX designation typically refers to the render engine, so render
1207  * capability related checks should use IS_GEN, while display and other checks
1208  * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
1209  * chips, etc.).
1210  */
1211 #define IS_GEN2(dev)    (INTEL_INFO(dev)->gen == 2)
1212 #define IS_GEN3(dev)    (INTEL_INFO(dev)->gen == 3)
1213 #define IS_GEN4(dev)    (INTEL_INFO(dev)->gen == 4)
1214 #define IS_GEN5(dev)    (INTEL_INFO(dev)->gen == 5)
1215 #define IS_GEN6(dev)    (INTEL_INFO(dev)->gen == 6)
1216 #define IS_GEN7(dev)    (INTEL_INFO(dev)->gen == 7)
1217
1218 #define HAS_BSD(dev)            (INTEL_INFO(dev)->has_bsd_ring)
1219 #define HAS_BLT(dev)            (INTEL_INFO(dev)->has_blt_ring)
1220 #define HAS_LLC(dev)            (INTEL_INFO(dev)->has_llc)
1221 #define I915_NEED_GFX_HWS(dev)  (INTEL_INFO(dev)->need_gfx_hws)
1222
1223 #define HAS_HW_CONTEXTS(dev)    (INTEL_INFO(dev)->gen >= 6)
1224 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev))
1225
1226 #define HAS_OVERLAY(dev)                (INTEL_INFO(dev)->has_overlay)
1227 #define OVERLAY_NEEDS_PHYSICAL(dev)     (INTEL_INFO(dev)->overlay_needs_physical)
1228
1229 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
1230 #define HAS_BROKEN_CS_TLB(dev)          (IS_I830(dev) || IS_845G(dev))
1231
1232 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1233  * rows, which changed the alignment requirements and fence programming.
1234  */
1235 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1236                                                       IS_I915GM(dev)))
1237 #define SUPPORTS_DIGITAL_OUTPUTS(dev)   (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1238 #define SUPPORTS_INTEGRATED_HDMI(dev)   (IS_G4X(dev) || IS_GEN5(dev))
1239 #define SUPPORTS_INTEGRATED_DP(dev)     (IS_G4X(dev) || IS_GEN5(dev))
1240 #define SUPPORTS_EDP(dev)               (IS_IRONLAKE_M(dev))
1241 #define SUPPORTS_TV(dev)                (INTEL_INFO(dev)->supports_tv)
1242 #define I915_HAS_HOTPLUG(dev)            (INTEL_INFO(dev)->has_hotplug)
1243 /* dsparb controlled by hw only */
1244 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1245
1246 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1247 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1248 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1249
1250 #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
1251
1252 #define INTEL_PCH_DEVICE_ID_MASK                0xff00
1253 #define INTEL_PCH_IBX_DEVICE_ID_TYPE            0x3b00
1254 #define INTEL_PCH_CPT_DEVICE_ID_TYPE            0x1c00
1255 #define INTEL_PCH_PPT_DEVICE_ID_TYPE            0x1e00
1256 #define INTEL_PCH_LPT_DEVICE_ID_TYPE            0x8c00
1257 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE         0x9c00
1258
1259 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
1260 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
1261 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1262 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1263 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
1264
1265 #define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake)
1266
1267 #define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1268
1269 #define GT_FREQUENCY_MULTIPLIER 50
1270
1271 /**
1272  * RC6 is a special power stage which allows the GPU to enter an very
1273  * low-voltage mode when idle, using down to 0V while at this stage.  This
1274  * stage is entered automatically when the GPU is idle when RC6 support is
1275  * enabled, and as soon as new workload arises GPU wakes up automatically as well.
1276  *
1277  * There are different RC6 modes available in Intel GPU, which differentiate
1278  * among each other with the latency required to enter and leave RC6 and
1279  * voltage consumed by the GPU in different states.
1280  *
1281  * The combination of the following flags define which states GPU is allowed
1282  * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
1283  * RC6pp is deepest RC6. Their support by hardware varies according to the
1284  * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
1285  * which brings the most power savings; deeper states save more power, but
1286  * require higher latency to switch to and wake up.
1287  */
1288 #define INTEL_RC6_ENABLE                        (1<<0)
1289 #define INTEL_RC6p_ENABLE                       (1<<1)
1290 #define INTEL_RC6pp_ENABLE                      (1<<2)
1291
1292 extern int intel_iommu_enabled;
1293 extern struct drm_ioctl_desc i915_ioctls[];
1294 extern struct drm_driver i915_driver_info;
1295 extern struct cdev_pager_ops i915_gem_pager_ops;
1296 extern int i915_max_ioctl;
1297 extern unsigned int i915_fbpercrtc __always_unused;
1298 extern int i915_panel_ignore_lid __read_mostly;
1299 extern unsigned int i915_powersave __read_mostly;
1300 extern int i915_semaphores __read_mostly;
1301 extern unsigned int i915_lvds_downclock __read_mostly;
1302 extern int i915_lvds_channel_mode __read_mostly;
1303 extern int i915_panel_use_ssc __read_mostly;
1304 extern int i915_vbt_sdvo_panel_type __read_mostly;
1305 extern int i915_enable_rc6 __read_mostly;
1306 extern int i915_enable_fbc __read_mostly;
1307 extern int i915_enable_hangcheck;
1308 extern int i915_enable_ppgtt __read_mostly;
1309 extern unsigned int i915_preliminary_hw_support __read_mostly;
1310
1311                                 /* i915_dma.c */
1312 void i915_update_dri1_breadcrumb(struct drm_device *dev);
1313 extern void i915_kernel_lost_context(struct drm_device * dev);
1314 extern int i915_driver_load(struct drm_device *, unsigned long flags);
1315 extern int i915_driver_unload(struct drm_device *);
1316 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
1317 extern void i915_driver_lastclose(struct drm_device * dev);
1318 extern void i915_driver_preclose(struct drm_device *dev,
1319                                  struct drm_file *file_priv);
1320 extern void i915_driver_postclose(struct drm_device *dev,
1321                                   struct drm_file *file_priv);
1322 extern int i915_driver_device_is_agp(struct drm_device * dev);
1323 #ifdef CONFIG_COMPAT
1324 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
1325                               unsigned long arg);
1326 #endif
1327 extern int i915_emit_box(struct drm_device *dev,
1328                          struct drm_clip_rect *box,
1329                          int DR1, int DR4);
1330 extern int intel_gpu_reset(struct drm_device *dev);
1331 extern int i915_reset(struct drm_device *dev);
1332 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
1333 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
1334 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
1335 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
1336
1337 extern void intel_console_resume(struct work_struct *work);
1338
1339 /* i915_irq.c */
1340 void i915_hangcheck_elapsed(unsigned long data);
1341 void i915_handle_error(struct drm_device *dev, bool wedged);
1342
1343 extern void intel_irq_init(struct drm_device *dev);
1344 extern void intel_gt_init(struct drm_device *dev);
1345 extern void intel_gt_reset(struct drm_device *dev);
1346
1347 void i915_error_state_free(struct kref *error_ref);
1348
1349 void
1350 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1351
1352 void
1353 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1354
1355 void intel_enable_asle(struct drm_device *dev);
1356
1357 #ifdef CONFIG_DEBUG_FS
1358 extern void i915_destroy_error_state(struct drm_device *dev);
1359 #else
1360 #define i915_destroy_error_state(x)
1361 #endif
1362
1363
1364 /* i915_gem.c */
1365 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
1366                         struct drm_file *file_priv);
1367 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
1368                           struct drm_file *file_priv);
1369 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1370                          struct drm_file *file_priv);
1371 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1372                           struct drm_file *file_priv);
1373 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1374                         struct drm_file *file_priv);
1375 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1376                         struct drm_file *file_priv);
1377 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1378                               struct drm_file *file_priv);
1379 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1380                              struct drm_file *file_priv);
1381 int i915_gem_execbuffer(struct drm_device *dev, void *data,
1382                         struct drm_file *file_priv);
1383 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
1384                          struct drm_file *file_priv);
1385 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
1386                        struct drm_file *file_priv);
1387 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
1388                          struct drm_file *file_priv);
1389 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
1390                         struct drm_file *file_priv);
1391 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
1392                                struct drm_file *file);
1393 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
1394                                struct drm_file *file);
1395 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
1396                             struct drm_file *file_priv);
1397 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
1398                            struct drm_file *file_priv);
1399 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
1400                            struct drm_file *file_priv);
1401 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
1402                            struct drm_file *file_priv);
1403 int i915_gem_set_tiling(struct drm_device *dev, void *data,
1404                         struct drm_file *file_priv);
1405 int i915_gem_get_tiling(struct drm_device *dev, void *data,
1406                         struct drm_file *file_priv);
1407 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
1408                                 struct drm_file *file_priv);
1409 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
1410                         struct drm_file *file_priv);
1411 void i915_gem_load(struct drm_device *dev);
1412 void i915_gem_unload(struct drm_device *dev);
1413 int i915_gem_init_object(struct drm_gem_object *obj);
1414 void i915_gem_object_init(struct drm_i915_gem_object *obj,
1415                          const struct drm_i915_gem_object_ops *ops);
1416 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
1417                                                   size_t size);
1418 void i915_gem_free_object(struct drm_gem_object *obj);
1419 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
1420                                      uint32_t alignment,
1421                                      bool map_and_fenceable,
1422                                      bool nonblocking);
1423 void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
1424 int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj);
1425 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
1426 void i915_gem_lastclose(struct drm_device *dev);
1427
1428 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
1429 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
1430                          struct intel_ring_buffer *to);
1431 void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1432                                     struct intel_ring_buffer *ring);
1433
1434 int i915_gem_dumb_create(struct drm_file *file_priv,
1435                          struct drm_device *dev,
1436                          struct drm_mode_create_dumb *args);
1437 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
1438                       uint32_t handle, uint64_t *offset);
1439 int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev,
1440                           uint32_t handle);
1441 /**
1442  * Returns true if seq1 is later than seq2.
1443  */
1444 static inline bool
1445 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1446 {
1447         return (int32_t)(seq1 - seq2) >= 0;
1448 }
1449
1450 extern int i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
1451
1452 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
1453 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
1454
1455 static inline bool
1456 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
1457 {
1458         if (obj->fence_reg != I915_FENCE_REG_NONE) {
1459                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1460                 dev_priv->fence_regs[obj->fence_reg].pin_count++;
1461                 return true;
1462         } else
1463                 return false;
1464 }
1465
1466 static inline void
1467 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
1468 {
1469         if (obj->fence_reg != I915_FENCE_REG_NONE) {
1470                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1471                 dev_priv->fence_regs[obj->fence_reg].pin_count--;
1472         }
1473 }
1474
1475 void i915_gem_retire_requests(struct drm_device *dev);
1476 void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring);
1477 int __must_check i915_gem_check_wedge(struct drm_i915_private *dev_priv,
1478                                       bool interruptible);
1479
1480 void i915_gem_reset(struct drm_device *dev);
1481 void i915_gem_clflush_object(struct drm_i915_gem_object *obj);
1482 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
1483     unsigned long mappable_end, unsigned long end);
1484 int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj,
1485                                             uint32_t read_domains,
1486                                             uint32_t write_domain);
1487 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
1488 int __must_check i915_gem_init(struct drm_device *dev);
1489 int __must_check i915_gem_init_hw(struct drm_device *dev);
1490 void i915_gem_l3_remap(struct drm_device *dev);
1491 void i915_gem_init_swizzling(struct drm_device *dev);
1492 void i915_gem_init_ppgtt(struct drm_device *dev);
1493 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
1494 int __must_check i915_gpu_idle(struct drm_device *dev);
1495 int __must_check i915_gem_idle(struct drm_device *dev);
1496 int i915_add_request(struct intel_ring_buffer *ring,
1497                      struct drm_file *file,
1498                      u32 *seqno);
1499 int __must_check i915_wait_seqno(struct intel_ring_buffer *ring,
1500                                  uint32_t seqno);
1501 int i915_gem_fault(struct drm_device *dev, uint64_t offset, int prot,
1502     uint64_t *phys);
1503 int __must_check
1504 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
1505                                   bool write);
1506 int __must_check
1507 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
1508 int __must_check
1509 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
1510                                      u32 alignment,
1511                                      struct intel_ring_buffer *pipelined);
1512 int i915_gem_attach_phys_object(struct drm_device *dev,
1513                                 struct drm_i915_gem_object *obj,
1514                                 int id,
1515                                 int align);
1516 void i915_gem_detach_phys_object(struct drm_device *dev,
1517                                  struct drm_i915_gem_object *obj);
1518 void i915_gem_free_all_phys_object(struct drm_device *dev);
1519 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
1520
1521 uint32_t
1522 i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
1523                                     uint32_t size,
1524                                     int tiling_mode);
1525
1526 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
1527                                     enum i915_cache_level cache_level);
1528
1529 /* i915_gem_context.c */
1530 void i915_gem_context_init(struct drm_device *dev);
1531 void i915_gem_context_fini(struct drm_device *dev);
1532 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
1533 int i915_switch_context(struct intel_ring_buffer *ring,
1534                         struct drm_file *file, int to_id);
1535 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
1536                                   struct drm_file *file);
1537 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
1538                                    struct drm_file *file);
1539
1540 /* i915_gem_gtt.c */
1541 int __must_check i915_gem_init_aliasing_ppgtt(struct drm_device *dev);
1542 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev);
1543 void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
1544                             struct drm_i915_gem_object *obj,
1545                             enum i915_cache_level cache_level);
1546 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
1547                               struct drm_i915_gem_object *obj);
1548
1549 void i915_gem_restore_gtt_mappings(struct drm_device *dev);
1550 int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj);
1551 void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
1552                                 enum i915_cache_level cache_level);
1553 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);
1554 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj);
1555 void i915_gem_init_global_gtt(struct drm_device *dev,
1556                               unsigned long start,
1557                               unsigned long mappable_end,
1558                               unsigned long end);
1559 int i915_gem_gtt_init(struct drm_device *dev);
1560 void i915_gem_gtt_fini(struct drm_device *dev);
1561 static inline void i915_gem_chipset_flush(struct drm_device *dev)
1562 {
1563         if (INTEL_INFO(dev)->gen < 6)
1564                 intel_gtt_chipset_flush();
1565 }
1566
1567
1568 /* i915_gem_evict.c */
1569 int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size,
1570                                           unsigned alignment,
1571                                           unsigned cache_level,
1572                                           bool mappable,
1573                                           bool nonblock);
1574 int i915_gem_evict_everything(struct drm_device *dev);
1575
1576 /* i915_gem_stolen.c */
1577 int i915_gem_init_stolen(struct drm_device *dev);
1578 void i915_gem_cleanup_stolen(struct drm_device *dev);
1579
1580 /* i915_gem_tiling.c */
1581 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
1582 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
1583 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
1584
1585 /* i915_gem_debug.c */
1586 #if WATCH_LISTS
1587 int i915_verify_lists(struct drm_device *dev);
1588 #else
1589 #define i915_verify_lists(dev) 0
1590 #endif
1591 void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj,
1592                                      int handle);
1593
1594 /* i915_debugfs.c */
1595 int i915_debugfs_init(struct drm_minor *minor);
1596 void i915_debugfs_cleanup(struct drm_minor *minor);
1597
1598 /* i915_suspend.c */
1599 extern int i915_save_state(struct drm_device *dev);
1600 extern int i915_restore_state(struct drm_device *dev);
1601
1602 /* i915_sysfs.c */
1603 void i915_setup_sysfs(struct drm_device *dev_priv);
1604 void i915_teardown_sysfs(struct drm_device *dev_priv);
1605
1606 /* intel_i2c.c */
1607 extern int intel_setup_gmbus(struct drm_device *dev);
1608 extern void intel_teardown_gmbus(struct drm_device *dev);
1609 static inline bool intel_gmbus_is_port_valid(unsigned port)
1610 {
1611         return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
1612 }
1613
1614 extern struct device *intel_gmbus_get_adapter(
1615                 struct drm_i915_private *dev_priv, unsigned port);
1616 extern void intel_gmbus_set_speed(device_t idev, int speed);
1617 extern void intel_gmbus_force_bit(device_t idev, bool force_bit);
1618 static inline bool intel_gmbus_is_forced_bit(struct device *adapter)
1619 {
1620         struct intel_iic_softc *sc;
1621         sc = device_get_softc(device_get_parent(adapter));
1622
1623         return sc->force_bit_dev;
1624 }
1625 extern void intel_i2c_reset(struct drm_device *dev);
1626
1627 /* intel_opregion.c */
1628 extern int intel_opregion_setup(struct drm_device *dev);
1629 #ifdef CONFIG_ACPI
1630 extern void intel_opregion_init(struct drm_device *dev);
1631 extern void intel_opregion_fini(struct drm_device *dev);
1632 extern void intel_opregion_asle_intr(struct drm_device *dev);
1633 extern void intel_opregion_gse_intr(struct drm_device *dev);
1634 extern void intel_opregion_enable_asle(struct drm_device *dev);
1635 #else
1636 static inline void intel_opregion_init(struct drm_device *dev) { return; }
1637 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
1638 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
1639 static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; }
1640 static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; }
1641 #endif
1642
1643 /* intel_acpi.c */
1644 #ifdef CONFIG_ACPI
1645 extern void intel_register_dsm_handler(void);
1646 extern void intel_unregister_dsm_handler(void);
1647 #else
1648 static inline void intel_register_dsm_handler(void) { return; }
1649 static inline void intel_unregister_dsm_handler(void) { return; }
1650 #endif /* CONFIG_ACPI */
1651
1652 /* modesetting */
1653 extern void intel_modeset_init_hw(struct drm_device *dev);
1654 extern void intel_modeset_init(struct drm_device *dev);
1655 extern void intel_modeset_gem_init(struct drm_device *dev);
1656 extern void intel_modeset_cleanup(struct drm_device *dev);
1657 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
1658 extern void intel_modeset_setup_hw_state(struct drm_device *dev,
1659                                          bool force_restore);
1660 extern void intel_disable_fbc(struct drm_device *dev);
1661 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
1662 extern void intel_init_pch_refclk(struct drm_device *dev);
1663 extern void gen6_set_rps(struct drm_device *dev, u8 val);
1664 extern void intel_detect_pch(struct drm_device *dev);
1665 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
1666 extern int intel_enable_rc6(const struct drm_device *dev);
1667
1668 extern bool i915_semaphore_is_enabled(struct drm_device *dev);
1669 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
1670                         struct drm_file *file);
1671
1672 extern void intel_overlay_print_error_state(struct sbuf *m,
1673     struct intel_overlay_error_state *error);
1674 extern void intel_display_print_error_state(struct sbuf *m,
1675     struct drm_device *dev, struct intel_display_error_state *error);
1676
1677 static inline void
1678 trace_i915_reg_rw(boolean_t rw, int reg, uint64_t val, int sz)
1679 {
1680         return;
1681 }
1682
1683 const struct intel_device_info *i915_get_device_id(int device);
1684
1685 /* overlay */
1686 #ifdef CONFIG_DEBUG_FS
1687 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
1688 extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error);
1689
1690 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
1691 extern void intel_display_print_error_state(struct seq_file *m,
1692                                             struct drm_device *dev,
1693                                             struct intel_display_error_state *error);
1694 #endif
1695
1696 /* On SNB platform, before reading ring registers forcewake bit
1697  * must be set to prevent GT core from power down and stale values being
1698  * returned.
1699  */
1700 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
1701 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
1702 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
1703
1704 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
1705 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
1706
1707 #define __i915_read(x, y) \
1708         u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
1709
1710 __i915_read(8, 8)
1711 __i915_read(16, 16)
1712 __i915_read(32, 32)
1713 __i915_read(64, 64)
1714 #undef __i915_read
1715
1716 #define __i915_write(x, y) \
1717         void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val);
1718
1719 __i915_write(8, 8)
1720 __i915_write(16, 16)
1721 __i915_write(32, 32)
1722 __i915_write(64, 64)
1723 #undef __i915_write
1724
1725 #define I915_READ8(reg)         i915_read8(dev_priv, (reg))
1726 #define I915_WRITE8(reg, val)   i915_write8(dev_priv, (reg), (val))
1727
1728 #define I915_READ16(reg)        i915_read16(dev_priv, (reg))
1729 #define I915_WRITE16(reg, val)  i915_write16(dev_priv, (reg), (val))
1730 #define I915_READ16_NOTRACE(reg)        DRM_READ16(dev_priv->mmio_map, (reg))
1731 #define I915_WRITE16_NOTRACE(reg, val)  DRM_WRITE16(dev_priv->mmio_map, (reg), (val))
1732
1733 #define I915_READ(reg)          i915_read32(dev_priv, (reg))
1734 #define I915_WRITE(reg, val)    i915_write32(dev_priv, (reg), (val))
1735 #define I915_READ_NOTRACE(reg)          DRM_READ32(dev_priv->mmio_map, (reg))
1736 #define I915_WRITE_NOTRACE(reg, val)    DRM_WRITE32(dev_priv->mmio_map, (reg), (val))
1737
1738 #define I915_WRITE64(reg, val)  i915_write64(dev_priv, (reg), (val))
1739 #define I915_READ64(reg)        i915_read64(dev_priv, (reg))
1740
1741 #define POSTING_READ(reg)       (void)I915_READ_NOTRACE(reg)
1742 #define POSTING_READ16(reg)     (void)I915_READ16_NOTRACE(reg)
1743
1744
1745 #endif