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kernel/ath_hal: Add missing header to fix build with -Wundef.
[dragonfly.git] / sys / contrib / dev / ath / ath_hal / ar9300 / ar9300_tx99_tgt.c
blobcf8867453fa1fcbdf769eba9ba2ee460a203e931
1 /*
2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
14 * PERFORMANCE OF THIS SOFTWARE.
15 */
16 /*
17 * Copyright (c) 2010 Atheros Communications Inc.
18 *
19 * Permission to use, copy, modify, and/or distribute this software for any
20 * purpose with or without fee is hereby granted, provided that the above
21 * copyright notice and this permission notice appear in all copies.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
24 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
26 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
27 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
28 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
29 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
30 */
31
32 #include "ah.h"
33 #include "ah_internal.h"
34 #include "ar9300.h"
35 #include "ar9300phy.h"
36 #include "ar9300reg.h"
37 #include "ar9300eep.h"
38
39 #ifdef ATH_TX99_DIAG
40 void
41 ar9300_tx99_tgt_channel_pwr_update(struct ath_hal *ah, HAL_CHANNEL *c, u_int32_t txpower)
42 {
43 #define PWR_MAS(_r, _s) (((_r) & 0x3f) << (_s))
44 static int16_t pPwrArray[ar9300_rate_size] = { 0 };
45 int32_t i;
46 //u_int8_t ht40PowerIncForPdadc = 2;
47
48 for (i = 0; i < ar9300_rate_size; i++)
49 pPwrArray[i] = txpower;
50
51 OS_REG_WRITE(ah, AR_PHY_TX_FORCED_GAIN, 0);
52
53 /* Write the OFDM power per rate set */
54 /* 6 (LSB), 9, 12, 18 (MSB) */
55 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE(1),
56 PWR_MAS(pPwrArray[ALL_TARGET_LEGACY_6_24], 24)
57 | PWR_MAS(pPwrArray[ALL_TARGET_LEGACY_6_24], 16)
58 | PWR_MAS(pPwrArray[ALL_TARGET_LEGACY_6_24], 8)
59 | PWR_MAS(pPwrArray[ALL_TARGET_LEGACY_6_24], 0)
60 );
61 /* 24 (LSB), 36, 48, 54 (MSB) */
62 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE(2),
63 PWR_MAS(pPwrArray[ALL_TARGET_LEGACY_54], 24)
64 | PWR_MAS(pPwrArray[ALL_TARGET_LEGACY_48], 16)
65 | PWR_MAS(pPwrArray[ALL_TARGET_LEGACY_36], 8)
66 | PWR_MAS(pPwrArray[ALL_TARGET_LEGACY_6_24], 0)
67 );
68
69 /* Write the CCK power per rate set */
70 /* 1L (LSB), reserved, 2L, 2S (MSB) */
71 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE(3),
72 PWR_MAS(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 24)
73 | PWR_MAS(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16)
74 // | PWR_MAS(txPowerTimes2, 8) /* this is reserved for Osprey */
75 | PWR_MAS(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0)
76 );
77 /* 5.5L (LSB), 5.5S, 11L, 11S (MSB) */
78 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE(4),
79 PWR_MAS(pPwrArray[ALL_TARGET_LEGACY_11S], 24)
80 | PWR_MAS(pPwrArray[ALL_TARGET_LEGACY_11L], 16)
81 | PWR_MAS(pPwrArray[ALL_TARGET_LEGACY_5S], 8)
82 | PWR_MAS(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0)
83 );
84
85 /* Write the HT20 power per rate set */
86 /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */
87 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE(5),
88 PWR_MAS(pPwrArray[ALL_TARGET_HT20_5], 24)
89 | PWR_MAS(pPwrArray[ALL_TARGET_HT20_4], 16)
90 | PWR_MAS(pPwrArray[ALL_TARGET_HT20_1_3_9_11_17_19], 8)
91 | PWR_MAS(pPwrArray[ALL_TARGET_HT20_0_8_16], 0)
92 );
93
94 /* 6 (LSB), 7, 12, 13 (MSB) */
95 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE(6),
96 PWR_MAS(pPwrArray[ALL_TARGET_HT20_13], 24)
97 | PWR_MAS(pPwrArray[ALL_TARGET_HT20_12], 16)
98 | PWR_MAS(pPwrArray[ALL_TARGET_HT20_7], 8)
99 | PWR_MAS(pPwrArray[ALL_TARGET_HT20_6], 0)
100 );
101
102 /* 14 (LSB), 15, 20, 21 */
103 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE(10),
104 PWR_MAS(pPwrArray[ALL_TARGET_HT20_21], 24)
105 | PWR_MAS(pPwrArray[ALL_TARGET_HT20_20], 16)
106 | PWR_MAS(pPwrArray[ALL_TARGET_HT20_15], 8)
107 | PWR_MAS(pPwrArray[ALL_TARGET_HT20_14], 0)
108 );
109
110 /* Mixed HT20 and HT40 rates */
111 /* HT20 22 (LSB), HT20 23, HT40 22, HT40 23 (MSB) */
112 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE(11),
113 PWR_MAS(pPwrArray[ALL_TARGET_HT40_23], 24)
114 | PWR_MAS(pPwrArray[ALL_TARGET_HT40_22], 16)
115 | PWR_MAS(pPwrArray[ALL_TARGET_HT20_23], 8)
116 | PWR_MAS(pPwrArray[ALL_TARGET_HT20_22], 0)
117 );
118
119 /* Write the HT40 power per rate set */
120 // correct PAR difference between HT40 and HT20/LEGACY
121 /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */
122 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE(7),
123 PWR_MAS(pPwrArray[ALL_TARGET_HT40_5], 24)
124 | PWR_MAS(pPwrArray[ALL_TARGET_HT40_4], 16)
125 | PWR_MAS(pPwrArray[ALL_TARGET_HT40_1_3_9_11_17_19], 8)
126 | PWR_MAS(pPwrArray[ALL_TARGET_HT40_0_8_16], 0)
127 );
128
129 /* 6 (LSB), 7, 12, 13 (MSB) */
130 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE(8),
131 PWR_MAS(pPwrArray[ALL_TARGET_HT40_13], 24)
132 | PWR_MAS(pPwrArray[ALL_TARGET_HT40_12], 16)
133 | PWR_MAS(pPwrArray[ALL_TARGET_HT40_7], 8)
134 | PWR_MAS(pPwrArray[ALL_TARGET_HT40_6], 0)
135 );
136
137 /* 14 (LSB), 15, 20, 21 */
138 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE(12),
139 PWR_MAS(pPwrArray[ALL_TARGET_HT40_21], 24)
140 | PWR_MAS(pPwrArray[ALL_TARGET_HT40_20], 16)
141 | PWR_MAS(pPwrArray[ALL_TARGET_HT40_15], 8)
142 | PWR_MAS(pPwrArray[ALL_TARGET_HT40_14], 0)
143 );
144 #undef PWR_MAS
145 }
146
147 void
148 ar9300_tx99_tgt_chainmsk_setup(struct ath_hal *ah, int tx_chainmask)
149 {
150 if (tx_chainmask == 0x5) {
151 OS_REG_WRITE(ah, AR_PHY_ANALOG_SWAP, OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) | AR_PHY_SWAP_ALT_CHAIN);
152 }
153 OS_REG_WRITE(ah, AR_PHY_RX_CHAINMASK, tx_chainmask);
154 OS_REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, tx_chainmask);
155
156 OS_REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
157 if (tx_chainmask == 0x5) {
158 OS_REG_WRITE(ah, AR_PHY_ANALOG_SWAP, OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) | AR_PHY_SWAP_ALT_CHAIN);
159 }
160 }
161
162 void
163 ar9300_tx99_tgt_set_single_carrier(struct ath_hal *ah, int tx_chain_mask, int chtype)
164 {
165 OS_REG_WRITE(ah, AR_PHY_TST_DAC_CONST, OS_REG_READ(ah, AR_PHY_TST_DAC_CONST) | (0x7ff<<11) | 0x7ff);
166 OS_REG_WRITE(ah, AR_PHY_TEST_CTL_STATUS, OS_REG_READ(ah, AR_PHY_TEST_CTL_STATUS) | (1<<7) | (1<<1));
167 OS_REG_WRITE(ah, AR_PHY_ADDAC_PARA_CTL, (OS_REG_READ(ah, AR_PHY_ADDAC_PARA_CTL) | (1<<31) | (1<<15)) & ~(1<<13));
168
169 /* 11G mode */
170 if (!chtype)
171 {
172 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2)
173 | (0x1 << 3) | (0x1 << 2));
174 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) {
175 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP, OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP)
176 & ~(0x1 << 4));
177 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2, (OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2)
178 | (0x1 << 26) | (0x7 << 24))
179 & ~(0x1 << 22));
180 } else {
181 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP, OS_REG_READ(ah, AR_HORNET_CH0_TOP)
182 & ~(0x1 << 4));
183 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2, (OS_REG_READ(ah, AR_HORNET_CH0_TOP2)
184 | (0x1 << 26) | (0x7 << 24))
185 & ~(0x1 << 22));
186 }
187
188 /* chain zero */
189 if((tx_chain_mask & 0x01) == 0x01) {
190 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX1, (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX1)
191 | (0x1 << 31) | (0x5 << 15)
192 | (0x3 << 9)) & ~(0x1 << 27)
193 & ~(0x1 << 12));
194 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2)
195 | (0x1 << 12) | (0x1 << 10)
196 | (0x1 << 9) | (0x1 << 8)
197 | (0x1 << 7)) & ~(0x1 << 11));
198 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3, (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3)
199 | (0x1 << 29) | (0x1 << 25)
200 | (0x1 << 23) | (0x1 << 19)
201 | (0x1 << 10) | (0x1 << 9)
202 | (0x1 << 8) | (0x1 << 3))
203 & ~(0x1 << 28)& ~(0x1 << 24)
204 & ~(0x1 << 22)& ~(0x1 << 7));
205 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1, (OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1)
206 | (0x1 << 23))& ~(0x1 << 21));
207 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB1, OS_REG_READ(ah, AR_PHY_65NM_CH0_BB1)
208 | (0x1 << 12) | (0x1 << 10)
209 | (0x1 << 9) | (0x1 << 8)
210 | (0x1 << 6) | (0x1 << 5)
211 | (0x1 << 4) | (0x1 << 3)
212 | (0x1 << 2));
213 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB2, OS_REG_READ(ah, AR_PHY_65NM_CH0_BB2)
214 | (0x1 << 31));
215 }
216 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) {
217 /* chain one */
218 if ((tx_chain_mask & 0x02) == 0x02 ) {
219 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX1, (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX1)
220 | (0x1 << 31) | (0x5 << 15)
221 | (0x3 << 9)) & ~(0x1 << 27)
222 & ~(0x1 << 12));
223 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2, (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2)
224 | (0x1 << 12) | (0x1 << 10)
225 | (0x1 << 9) | (0x1 << 8)
226 | (0x1 << 7)) & ~(0x1 << 11));
227 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3, (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3)
228 | (0x1 << 29) | (0x1 << 25)
229 | (0x1 << 23) | (0x1 << 19)
230 | (0x1 << 10) | (0x1 << 9)
231 | (0x1 << 8) | (0x1 << 3))
232 & ~(0x1 << 28)& ~(0x1 << 24)
233 & ~(0x1 << 22)& ~(0x1 << 7));
234 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1, (OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1)
235 | (0x1 << 23))& ~(0x1 << 21));
236 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB1, OS_REG_READ(ah, AR_PHY_65NM_CH1_BB1)
237 | (0x1 << 12) | (0x1 << 10)
238 | (0x1 << 9) | (0x1 << 8)
239 | (0x1 << 6) | (0x1 << 5)
240 | (0x1 << 4) | (0x1 << 3)
241 | (0x1 << 2));
242 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB2, OS_REG_READ(ah, AR_PHY_65NM_CH1_BB2)
243 | (0x1 << 31));
244 }
245 }
246 if (AR_SREV_OSPREY(ah)) {
247 /* chain two */
248 if ((tx_chain_mask & 0x04) == 0x04 ) {
249 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX1, (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX1)
250 | (0x1 << 31) | (0x5 << 15)
251 | (0x3 << 9)) & ~(0x1 << 27)
252 & ~(0x1 << 12));
253 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2, (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2)
254 | (0x1 << 12) | (0x1 << 10)
255 | (0x1 << 9) | (0x1 << 8)
256 | (0x1 << 7)) & ~(0x1 << 11));
257 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3, (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3)
258 | (0x1 << 29) | (0x1 << 25)
259 | (0x1 << 23) | (0x1 << 19)
260 | (0x1 << 10) | (0x1 << 9)
261 | (0x1 << 8) | (0x1 << 3))
262 & ~(0x1 << 28)& ~(0x1 << 24)
263 & ~(0x1 << 22)& ~(0x1 << 7));
264 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1, (OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1)
265 | (0x1 << 23))& ~(0x1 << 21));
266 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB1, OS_REG_READ(ah, AR_PHY_65NM_CH2_BB1)
267 | (0x1 << 12) | (0x1 << 10)
268 | (0x1 << 9) | (0x1 << 8)
269 | (0x1 << 6) | (0x1 << 5)
270 | (0x1 << 4) | (0x1 << 3)
271 | (0x1 << 2));
272 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB2, OS_REG_READ(ah, AR_PHY_65NM_CH2_BB2)
273 | (0x1 << 31));
274 }
275 }
276
277 OS_REG_WRITE(ah, AR_PHY_SWITCH_COM_2, 0x11111);
278 OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, 0x111);
279 }
280 else
281 {
282 /* chain zero */
283 if((tx_chain_mask & 0x01) == 0x01) {
284 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX1, (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX1)
285 | (0x1 << 31) | (0x1 << 27)
286 | (0x3 << 23) | (0x1 << 19)
287 | (0x1 << 15) | (0x3 << 9))
288 & ~(0x1 << 12));
289 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2)
290 | (0x1 << 12) | (0x1 << 10)
291 | (0x1 << 9) | (0x1 << 8)
292 | (0x1 << 7) | (0x1 << 3)
293 | (0x1 << 2) | (0x1 << 1))
294 & ~(0x1 << 11)& ~(0x1 << 0));
295 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3, (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3)
296 | (0x1 << 29) | (0x1 << 25)
297 | (0x1 << 23) | (0x1 << 19)
298 | (0x1 << 10) | (0x1 << 9)
299 | (0x1 << 8) | (0x1 << 3))
300 & ~(0x1 << 28)& ~(0x1 << 24)
301 & ~(0x1 << 22)& ~(0x1 << 7));
302 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1, (OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1)
303 | (0x1 << 23))& ~(0x1 << 21));
304 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF2, OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF2)
305 | (0x3 << 3) | (0x3 << 0));
306 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF3, (OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF3)
307 | (0x3 << 29) | (0x3 << 26)
308 | (0x2 << 23) | (0x2 << 20)
309 | (0x2 << 17))& ~(0x1 << 14));
310 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB1, OS_REG_READ(ah, AR_PHY_65NM_CH0_BB1)
311 | (0x1 << 12) | (0x1 << 10)
312 | (0x1 << 9) | (0x1 << 8)
313 | (0x1 << 6) | (0x1 << 5)
314 | (0x1 << 4) | (0x1 << 3)
315 | (0x1 << 2));
316 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB2, OS_REG_READ(ah, AR_PHY_65NM_CH0_BB2)
317 | (0x1 << 31));
318 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) {
319 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP, OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP)
320 & ~(0x1 << 4));
321 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2, OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2)
322 | (0x1 << 26) | (0x7 << 24)
323 | (0x3 << 22));
324 } else {
325 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP, OS_REG_READ(ah, AR_HORNET_CH0_TOP)
326 & ~(0x1 << 4));
327 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2, OS_REG_READ(ah, AR_HORNET_CH0_TOP2)
328 | (0x1 << 26) | (0x7 << 24)
329 | (0x3 << 22));
330 }
331
332 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) {
333 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2, (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2)
334 | (0x1 << 3) | (0x1 << 2)
335 | (0x1 << 1)) & ~(0x1 << 0));
336 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3, OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3)
337 | (0x1 << 19) | (0x1 << 3));
338 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1, OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1)
339 | (0x1 << 23));
340 }
341 if (AR_SREV_OSPREY(ah)) {
342 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2, (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2)
343 | (0x1 << 3) | (0x1 << 2)
344 | (0x1 << 1)) & ~(0x1 << 0));
345 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3, OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3)
346 | (0x1 << 19) | (0x1 << 3));
347 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1, OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1)
348 | (0x1 << 23));
349 }
350 }
351 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) {
352 /* chain one */
353 if ((tx_chain_mask & 0x02) == 0x02 ) {
354 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2)
355 | (0x1 << 3) | (0x1 << 2)
356 | (0x1 << 1)) & ~(0x1 << 0));
357 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3, OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3)
358 | (0x1 << 19) | (0x1 << 3));
359 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1, OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1)
360 | (0x1 << 23));
361 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) {
362 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP, OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP)
363 & ~(0x1 << 4));
364 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2, OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2)
365 | (0x1 << 26) | (0x7 << 24)
366 | (0x3 << 22));
367 } else {
368 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP, OS_REG_READ(ah, AR_HORNET_CH0_TOP)
369 & ~(0x1 << 4));
370 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2, OS_REG_READ(ah, AR_HORNET_CH0_TOP2)
371 | (0x1 << 26) | (0x7 << 24)
372 | (0x3 << 22));
373 }
374
375 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX1, (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX1)
376 | (0x1 << 31) | (0x1 << 27)
377 | (0x3 << 23) | (0x1 << 19)
378 | (0x1 << 15) | (0x3 << 9))
379 & ~(0x1 << 12));
380 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2, (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2)
381 | (0x1 << 12) | (0x1 << 10)
382 | (0x1 << 9) | (0x1 << 8)
383 | (0x1 << 7) | (0x1 << 3)
384 | (0x1 << 2) | (0x1 << 1))
385 & ~(0x1 << 11)& ~(0x1 << 0));
386 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3, (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3)
387 | (0x1 << 29) | (0x1 << 25)
388 | (0x1 << 23) | (0x1 << 19)
389 | (0x1 << 10) | (0x1 << 9)
390 | (0x1 << 8) | (0x1 << 3))
391 & ~(0x1 << 28)& ~(0x1 << 24)
392 & ~(0x1 << 22)& ~(0x1 << 7));
393 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1, (OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1)
394 | (0x1 << 23))& ~(0x1 << 21));
395 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF2, OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF2)
396 | (0x3 << 3) | (0x3 << 0));
397 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF3, (OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF3)
398 | (0x3 << 29) | (0x3 << 26)
399 | (0x2 << 23) | (0x2 << 20)
400 | (0x2 << 17))& ~(0x1 << 14));
401 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB1, OS_REG_READ(ah, AR_PHY_65NM_CH1_BB1)
402 | (0x1 << 12) | (0x1 << 10)
403 | (0x1 << 9) | (0x1 << 8)
404 | (0x1 << 6) | (0x1 << 5)
405 | (0x1 << 4) | (0x1 << 3)
406 | (0x1 << 2));
407 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB2, OS_REG_READ(ah, AR_PHY_65NM_CH1_BB2)
408 | (0x1 << 31));
409
410 if (AR_SREV_OSPREY(ah)) {
411 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2, (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2)
412 | (0x1 << 3) | (0x1 << 2)
413 | (0x1 << 1)) & ~(0x1 << 0));
414 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3, OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3)
415 | (0x1 << 19) | (0x1 << 3));
416 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1, OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1)
417 | (0x1 << 23));
418 }
419 }
420 }
421 if (AR_SREV_OSPREY(ah)) {
422 /* chain two */
423 if ((tx_chain_mask & 0x04) == 0x04 ) {
424 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2)
425 | (0x1 << 3) | (0x1 << 2)
426 | (0x1 << 1)) & ~(0x1 << 0));
427 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3, OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3)
428 | (0x1 << 19) | (0x1 << 3));
429 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1, OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1)
430 | (0x1 << 23));
431 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) {
432 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP, OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP)
433 & ~(0x1 << 4));
434 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2, OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2)
435 | (0x1 << 26) | (0x7 << 24)
436 | (0x3 << 22));
437 } else {
438 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP, OS_REG_READ(ah, AR_HORNET_CH0_TOP)
439 & ~(0x1 << 4));
440 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2, OS_REG_READ(ah, AR_HORNET_CH0_TOP2)
441 | (0x1 << 26) | (0x7 << 24)
442 | (0x3 << 22));
443 }
444
445 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2, (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2)
446 | (0x1 << 3) | (0x1 << 2)
447 | (0x1 << 1)) & ~(0x1 << 0));
448 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3, OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3)
449 | (0x1 << 19) | (0x1 << 3));
450 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1, OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1)
451 | (0x1 << 23));
452
453 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX1, (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX1)
454 | (0x1 << 31) | (0x1 << 27)
455 | (0x3 << 23) | (0x1 << 19)
456 | (0x1 << 15) | (0x3 << 9))
457 & ~(0x1 << 12));
458 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2, (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2)
459 | (0x1 << 12) | (0x1 << 10)
460 | (0x1 << 9) | (0x1 << 8)
461 | (0x1 << 7) | (0x1 << 3)
462 | (0x1 << 2) | (0x1 << 1))
463 & ~(0x1 << 11)& ~(0x1 << 0));
464 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3, (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3)
465 | (0x1 << 29) | (0x1 << 25)
466 | (0x1 << 23) | (0x1 << 19)
467 | (0x1 << 10) | (0x1 << 9)
468 | (0x1 << 8) | (0x1 << 3))
469 & ~(0x1 << 28)& ~(0x1 << 24)
470 & ~(0x1 << 22)& ~(0x1 << 7));
471 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1, (OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1)
472 | (0x1 << 23))& ~(0x1 << 21));
473 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF2, OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF2)
474 | (0x3 << 3) | (0x3 << 0));
475 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF3, (OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF3)
476 | (0x3 << 29) | (0x3 << 26)
477 | (0x2 << 23) | (0x2 << 20)
478 | (0x2 << 17))& ~(0x1 << 14));
479 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB1, OS_REG_READ(ah, AR_PHY_65NM_CH2_BB1)
480 | (0x1 << 12) | (0x1 << 10)
481 | (0x1 << 9) | (0x1 << 8)
482 | (0x1 << 6) | (0x1 << 5)
483 | (0x1 << 4) | (0x1 << 3)
484 | (0x1 << 2));
485 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB2, OS_REG_READ(ah, AR_PHY_65NM_CH2_BB2)
486 | (0x1 << 31));
487 }
488 }
489
490 OS_REG_WRITE(ah, AR_PHY_SWITCH_COM_2, 0x22222);
491 OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, 0x222);
492 }
493 }
494
495 void
496 ar9300_tx99_tgt_start(struct ath_hal *ah, u_int8_t data)
497 {
498 a_uint32_t val;
499 a_uint32_t qnum = (a_uint32_t)data;
500
501 /* Disable AGC to A2 */
502 OS_REG_WRITE(ah, AR_PHY_TEST, (OS_REG_READ(ah, AR_PHY_TEST) | PHY_AGC_CLR) );
503 OS_REG_WRITE(ah, 0x9864, OS_REG_READ(ah, 0x9864) | 0x7f000);
504 OS_REG_WRITE(ah, 0x9924, OS_REG_READ(ah, 0x9924) | 0x7f00fe);
505 OS_REG_WRITE(ah, AR_DIAG_SW, OS_REG_READ(ah, AR_DIAG_SW) &~ AR_DIAG_RX_DIS);
506 //OS_REG_WRITE(ah, AR_DIAG_SW, OS_REG_READ(ah, AR_DIAG_SW) | (AR_DIAG_FORCE_RX_CLEAR+AR_DIAG_IGNORE_VIRT_CS));
507 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); // set receive disable
508 //set CW_MIN and CW_MAX both to 0, AIFS=2
509 OS_REG_WRITE(ah, AR_DLCL_IFS(qnum), 0);
510 OS_REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 20); //50 OK
511 OS_REG_WRITE(ah, AR_D_GBL_IFS_EIFS, 20);
512 OS_REG_WRITE(ah, AR_TIME_OUT, 0x00000400); //200 ok for HT20, 400 ok for HT40
513 OS_REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff);
514
515 /* set QCU modes to early termination */
516 val = OS_REG_READ(ah, AR_QMISC(qnum));
517 OS_REG_WRITE(ah, AR_QMISC(qnum), val | AR_Q_MISC_DCU_EARLY_TERM_REQ);
518 }
519
520 void
521 ar9300_tx99_tgt_stop(struct ath_hal *ah)
522 {
523 OS_REG_WRITE(ah, AR_PHY_TEST, OS_REG_READ(ah, AR_PHY_TEST) &~ PHY_AGC_CLR);
524 OS_REG_WRITE(ah, AR_DIAG_SW, OS_REG_READ(ah, AR_DIAG_SW) &~ (AR_DIAG_FORCE_RX_CLEAR | AR_DIAG_IGNORE_VIRT_CS));
525 }
526 #endif
DragonFly BSD