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acpi: restructure genwakecode.sh
[dragonfly.git] / sys / bus / usb / ehci.c
bloba0185d3765e50531bd8aae75ce6bc84aaa409ee3
1 /* $NetBSD: ehci.c,v 1.91 2005/02/27 00:27:51 perry Exp $ */
2 /* $FreeBSD: src/sys/dev/usb/ehci.c,v 1.36.2.3 2006/09/24 13:39:04 iedowse Exp $ */
3 /* $DragonFly: src/sys/bus/usb/ehci.c,v 1.36 2008/08/14 20:55:53 hasso Exp $ */
4
5 /*
6 * Copyright (c) 2004 The NetBSD Foundation, Inc.
7 * All rights reserved.
8 *
9 * This code is derived from software contributed to The NetBSD Foundation
10 * by Lennart Augustsson (lennart@augustsson.net) and by Charles M. Hannum.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 * 3. All advertising materials mentioning features or use of this software
21 * must display the following acknowledgement:
22 * This product includes software developed by the NetBSD
23 * Foundation, Inc. and its contributors.
24 * 4. Neither the name of The NetBSD Foundation nor the names of its
25 * contributors may be used to endorse or promote products derived
26 * from this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
29 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
30 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
31 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
32 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
33 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
34 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
35 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
36 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
37 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGE.
39 */
40
41 /*
42 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller.
43 *
44 * The EHCI 1.0 spec can be found at
45 * http://developer.intel.com/technology/usb/download/ehci-r10.pdf
46 * and the USB 2.0 spec at
47 * http://www.usb.org/developers/docs/usb_20.zip
48 *
49 */
50
51 /*
52 * TODO:
53 * 1) The EHCI driver lacks support for isochronous transfers, so
54 * devices using them don't work.
55 *
56 * 2) Interrupt transfer scheduling does not manage the time available
57 * in each frame, so it is possible for the transfers to overrun
58 * the end of the frame.
59 *
60 * 3) Command failures are not recovered correctly.
61 */
62
63 #include <sys/param.h>
64 #include <sys/systm.h>
65 #include <sys/malloc.h>
66 #include <sys/kernel.h>
67 #include <sys/endian.h>
68 #include <sys/module.h>
69 #include <sys/bus.h>
70 #include <sys/lock.h>
71 #include <sys/proc.h>
72 #include <sys/queue.h>
73 #include <sys/sysctl.h>
74 #include <sys/thread2.h>
75
76 #include <machine/cpu.h>
77 #include <machine/endian.h>
78
79 #include <bus/usb/usb.h>
80 #include <bus/usb/usbdi.h>
81 #include <bus/usb/usbdivar.h>
82 #include <bus/usb/usb_mem.h>
83 #include <bus/usb/usb_quirks.h>
84
85 #include <bus/usb/ehcireg.h>
86 #include <bus/usb/ehcivar.h>
87
88 #ifdef USB_DEBUG
89 #define EHCI_DEBUG USB_DEBUG
90 #define DPRINTF(x) do { if (ehcidebug) kprintf x; } while (0)
91 #define DPRINTFN(n,x) do { if (ehcidebug>(n)) kprintf x; } while (0)
92 int ehcidebug = 0;
93 SYSCTL_NODE(_hw_usb, OID_AUTO, ehci, CTLFLAG_RW, 0, "USB ehci");
94 SYSCTL_INT(_hw_usb_ehci, OID_AUTO, debug, CTLFLAG_RW,
95 &ehcidebug, 0, "ehci debug level");
96 #define bitmask_snprintf(q,f,b,l) ksnprintf((b), (l), "%b", (q), (f))
97 #else
98 #define DPRINTF(x)
99 #define DPRINTFN(n,x)
100 #endif
101
102 struct ehci_pipe {
103 struct usbd_pipe pipe;
104
105 ehci_soft_qh_t *sqh;
106 union {
107 ehci_soft_qtd_t *qtd;
108 /* ehci_soft_itd_t *itd; */
109 } tail;
110 union {
111 /* Control pipe */
112 struct {
113 usb_dma_t reqdma;
114 u_int length;
115 /*ehci_soft_qtd_t *setup, *data, *stat;*/
116 } ctl;
117 /* Interrupt pipe */
118 struct {
119 u_int length;
120 } intr;
121 /* Bulk pipe */
122 struct {
123 u_int length;
124 } bulk;
125 /* Iso pipe */
126 /* XXX */
127 } u;
128 };
129
130 static usbd_status ehci_open(usbd_pipe_handle);
131 static void ehci_poll(struct usbd_bus *);
132 static void ehci_softintr(void *);
133 static int ehci_intr1(ehci_softc_t *);
134 static void ehci_waitintr(ehci_softc_t *, usbd_xfer_handle);
135 static void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *);
136 static void ehci_idone(struct ehci_xfer *);
137 static void ehci_timeout(void *);
138 static void ehci_timeout_task(void *);
139 static void ehci_intrlist_timeout(void *);
140
141 static usbd_status ehci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t);
142 static void ehci_freem(struct usbd_bus *, usb_dma_t *);
143
144 static usbd_xfer_handle ehci_allocx(struct usbd_bus *);
145 static void ehci_freex(struct usbd_bus *, usbd_xfer_handle);
146
147 static usbd_status ehci_root_ctrl_transfer(usbd_xfer_handle);
148 static usbd_status ehci_root_ctrl_start(usbd_xfer_handle);
149 static void ehci_root_ctrl_abort(usbd_xfer_handle);
150 static void ehci_root_ctrl_close(usbd_pipe_handle);
151 static void ehci_root_ctrl_done(usbd_xfer_handle);
152
153 static usbd_status ehci_root_intr_transfer(usbd_xfer_handle);
154 static usbd_status ehci_root_intr_start(usbd_xfer_handle);
155 static void ehci_root_intr_abort(usbd_xfer_handle);
156 static void ehci_root_intr_close(usbd_pipe_handle);
157 static void ehci_root_intr_done(usbd_xfer_handle);
158
159 static usbd_status ehci_device_ctrl_transfer(usbd_xfer_handle);
160 static usbd_status ehci_device_ctrl_start(usbd_xfer_handle);
161 static void ehci_device_ctrl_abort(usbd_xfer_handle);
162 static void ehci_device_ctrl_close(usbd_pipe_handle);
163 static void ehci_device_ctrl_done(usbd_xfer_handle);
164
165 static usbd_status ehci_device_bulk_transfer(usbd_xfer_handle);
166 static usbd_status ehci_device_bulk_start(usbd_xfer_handle);
167 static void ehci_device_bulk_abort(usbd_xfer_handle);
168 static void ehci_device_bulk_close(usbd_pipe_handle);
169 static void ehci_device_bulk_done(usbd_xfer_handle);
170
171 static usbd_status ehci_device_intr_transfer(usbd_xfer_handle);
172 static usbd_status ehci_device_intr_start(usbd_xfer_handle);
173 static void ehci_device_intr_abort(usbd_xfer_handle);
174 static void ehci_device_intr_close(usbd_pipe_handle);
175 static void ehci_device_intr_done(usbd_xfer_handle);
176
177 static usbd_status ehci_device_isoc_transfer(usbd_xfer_handle);
178 static usbd_status ehci_device_isoc_start(usbd_xfer_handle);
179 static void ehci_device_isoc_abort(usbd_xfer_handle);
180 static void ehci_device_isoc_close(usbd_pipe_handle);
181 static void ehci_device_isoc_done(usbd_xfer_handle);
182
183 static void ehci_device_clear_toggle(usbd_pipe_handle pipe);
184 static void ehci_noop(usbd_pipe_handle pipe);
185
186 static int ehci_str(usb_string_descriptor_t *, int, char *);
187 static void ehci_pcd(ehci_softc_t *, usbd_xfer_handle);
188 static void ehci_disown(ehci_softc_t *, int, int);
189
190 static ehci_soft_qh_t *ehci_alloc_sqh(ehci_softc_t *);
191 static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *);
192
193 static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *);
194 static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *);
195 static usbd_status ehci_alloc_sqtd_chain(struct ehci_pipe *,
196 ehci_softc_t *, int, int, usbd_xfer_handle,
197 ehci_soft_qtd_t **, ehci_soft_qtd_t **);
198 static void ehci_free_sqtd_chain(ehci_softc_t *, ehci_soft_qtd_t *,
199 ehci_soft_qtd_t *);
200
201 static usbd_status ehci_device_request(usbd_xfer_handle xfer);
202
203 static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *,
204 int ival);
205
206 static void ehci_add_qh(ehci_soft_qh_t *, ehci_soft_qh_t *);
207 static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *,
208 ehci_soft_qh_t *);
209 static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *);
210 static void ehci_sync_hc(ehci_softc_t *);
211
212 static void ehci_close_pipe(usbd_pipe_handle, ehci_soft_qh_t *);
213 static void ehci_abort_xfer(usbd_xfer_handle, usbd_status);
214
215 #ifdef EHCI_DEBUG
216 static void ehci_dump_regs(ehci_softc_t *);
217 void ehci_dump(void);
218 static ehci_softc_t *theehci;
219 static void ehci_dump_link(ehci_link_t, int);
220 static void ehci_dump_sqtds(ehci_soft_qtd_t *);
221 static void ehci_dump_sqtd(ehci_soft_qtd_t *);
222 static void ehci_dump_qtd(ehci_qtd_t *);
223 static void ehci_dump_sqh(ehci_soft_qh_t *);
224 #ifdef DIAGNOSTIC
225 static void ehci_dump_exfer(struct ehci_xfer *);
226 #endif
227 #endif
228
229 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE)
230
231 #define EHCI_INTR_ENDPT 1
232
233 #define ehci_add_intr_list(sc, ex) \
234 LIST_INSERT_HEAD(&(sc)->sc_intrhead, (ex), inext);
235 #define ehci_del_intr_list(ex) \
236 do { \
237 LIST_REMOVE((ex), inext); \
238 (ex)->inext.le_prev = NULL; \
239 } while (0)
240 #define ehci_active_intr_list(ex) ((ex)->inext.le_prev != NULL)
241
242 static struct usbd_bus_methods ehci_bus_methods = {
243 ehci_open,
244 ehci_softintr,
245 ehci_poll,
246 ehci_allocm,
247 ehci_freem,
248 ehci_allocx,
249 ehci_freex,
250 };
251
252 static struct usbd_pipe_methods ehci_root_ctrl_methods = {
253 ehci_root_ctrl_transfer,
254 ehci_root_ctrl_start,
255 ehci_root_ctrl_abort,
256 ehci_root_ctrl_close,
257 ehci_noop,
258 ehci_root_ctrl_done,
259 };
260
261 static struct usbd_pipe_methods ehci_root_intr_methods = {
262 ehci_root_intr_transfer,
263 ehci_root_intr_start,
264 ehci_root_intr_abort,
265 ehci_root_intr_close,
266 ehci_noop,
267 ehci_root_intr_done,
268 };
269
270 static struct usbd_pipe_methods ehci_device_ctrl_methods = {
271 ehci_device_ctrl_transfer,
272 ehci_device_ctrl_start,
273 ehci_device_ctrl_abort,
274 ehci_device_ctrl_close,
275 ehci_noop,
276 ehci_device_ctrl_done,
277 };
278
279 static struct usbd_pipe_methods ehci_device_intr_methods = {
280 ehci_device_intr_transfer,
281 ehci_device_intr_start,
282 ehci_device_intr_abort,
283 ehci_device_intr_close,
284 ehci_device_clear_toggle,
285 ehci_device_intr_done,
286 };
287
288 static struct usbd_pipe_methods ehci_device_bulk_methods = {
289 ehci_device_bulk_transfer,
290 ehci_device_bulk_start,
291 ehci_device_bulk_abort,
292 ehci_device_bulk_close,
293 ehci_device_clear_toggle,
294 ehci_device_bulk_done,
295 };
296
297 static struct usbd_pipe_methods ehci_device_isoc_methods = {
298 ehci_device_isoc_transfer,
299 ehci_device_isoc_start,
300 ehci_device_isoc_abort,
301 ehci_device_isoc_close,
302 ehci_noop,
303 ehci_device_isoc_done,
304 };
305
306 usbd_status
307 ehci_init(ehci_softc_t *sc)
308 {
309 u_int32_t vers, sparams, cparams, hcr;
310 u_int i;
311 usbd_status err;
312 ehci_soft_qh_t *sqh;
313 u_int ncomp;
314 int lev;
315
316 DPRINTF(("ehci_init: start\n"));
317 #ifdef EHCI_DEBUG
318 theehci = sc;
319 #endif
320
321 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH);
322
323 vers = EREAD2(sc, EHCI_HCIVERSION);
324 device_printf(sc->sc_bus.bdev,
325 "EHCI version %x.%x\n", vers >> 8, vers & 0xff);
326 /* Disable all interrupts */
327 EOWRITE4(sc, EHCI_USBINTR, 0);
328
329 sparams = EREAD4(sc, EHCI_HCSPARAMS);
330 DPRINTF(("ehci_init: sparams=0x%x\n", sparams));
331 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams);
332 ncomp = EHCI_HCS_N_CC(sparams);
333 if (ncomp != sc->sc_ncomp) {
334 device_printf(sc->sc_bus.bdev,
335 "wrong number of companions (%d != %d)\n",
336 ncomp, sc->sc_ncomp);
337 if (ncomp < sc->sc_ncomp)
338 sc->sc_ncomp = ncomp;
339 }
340 if (sc->sc_ncomp > 0) {
341 device_printf(sc->sc_bus.bdev,
342 "companion controller%s, %d port%s each:",
343 sc->sc_ncomp!=1 ? "s" : "",
344 EHCI_HCS_N_PCC(sparams),
345 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : "");
346 for (i = 0; i < sc->sc_ncomp; i++)
347 kprintf(" %s", device_get_nameunit(sc->sc_comps[i]->bdev));
348 kprintf("\n");
349 }
350 sc->sc_noport = EHCI_HCS_N_PORTS(sparams);
351 cparams = EREAD4(sc, EHCI_HCCPARAMS);
352 DPRINTF(("ehci_init: cparams=0x%x\n", cparams));
353
354 if (EHCI_HCC_64BIT(cparams)) {
355 /* MUST clear segment register if 64 bit capable. */
356 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0);
357 }
358
359 sc->sc_bus.usbrev = USBREV_2_0;
360
361 /* Reset the controller */
362 DPRINTF(("%s: resetting\n", device_get_nameunit(sc->sc_bus.bdev)));
363 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */
364 usb_delay_ms(&sc->sc_bus, 1);
365 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET);
366 for (i = 0; i < 100; i++) {
367 usb_delay_ms(&sc->sc_bus, 1);
368 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET;
369 if (!hcr)
370 break;
371 }
372 if (hcr) {
373 device_printf(sc->sc_bus.bdev, "reset timeout\n");
374 return (USBD_IOERROR);
375 }
376
377 /* frame list size at default, read back what we got and use that */
378 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) {
379 case 0: sc->sc_flsize = 1024; break;
380 case 1: sc->sc_flsize = 512; break;
381 case 2: sc->sc_flsize = 256; break;
382 case 3: return (USBD_IOERROR);
383 }
384 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t),
385 EHCI_FLALIGN_ALIGN, &sc->sc_fldma);
386 if (err)
387 return (err);
388 DPRINTF(("%s: flsize=%d\n", device_get_nameunit(sc->sc_bus.bdev),sc->sc_flsize));
389 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0);
390 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0));
391
392 /* Set up the bus struct. */
393 sc->sc_bus.methods = &ehci_bus_methods;
394 sc->sc_bus.pipe_size = sizeof(struct ehci_pipe);
395
396 sc->sc_eintrs = EHCI_NORMAL_INTRS;
397
398 /*
399 * Allocate the interrupt dummy QHs. These are arranged to give
400 * poll intervals that are powers of 2 times 1ms.
401 */
402 for (i = 0; i < EHCI_INTRQHS; i++) {
403 sqh = ehci_alloc_sqh(sc);
404 if (sqh == NULL) {
405 err = USBD_NOMEM;
406 goto bad1;
407 }
408 sc->sc_islots[i].sqh = sqh;
409 }
410 lev = 0;
411 for (i = 0; i < EHCI_INTRQHS; i++) {
412 if (i == EHCI_IQHIDX(lev + 1, 0))
413 lev++;
414 sqh = sc->sc_islots[i].sqh;
415 if (i == 0) {
416 /* The last (1ms) QH terminates. */
417 sqh->qh.qh_link = EHCI_NULL;
418 sqh->next = NULL;
419 } else {
420 /* Otherwise the next QH has half the poll interval */
421 sqh->next =
422 sc->sc_islots[EHCI_IQHIDX(lev - 1, i + 1)].sqh;
423 sqh->qh.qh_link = htole32(sqh->next->physaddr |
424 EHCI_LINK_QH);
425 }
426 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH));
427 sqh->qh.qh_endphub = htole32(EHCI_QH_SET_MULT(1));
428 sqh->qh.qh_curqtd = EHCI_NULL;
429 sqh->qh.qh_qtd.qtd_next = EHCI_NULL;
430 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL;
431 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED);
432 sqh->sqtd = NULL;
433 }
434 /* Point the frame list at the last level (128ms). */
435 for (i = 0; i < sc->sc_flsize; i++) {
436 sc->sc_flist[i] = htole32(EHCI_LINK_QH |
437 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1,
438 i)].sqh->physaddr);
439 }
440
441 /* Allocate dummy QH that starts the async list. */
442 sqh = ehci_alloc_sqh(sc);
443 if (sqh == NULL) {
444 err = USBD_NOMEM;
445 goto bad1;
446 }
447 /* Fill the QH */
448 sqh->qh.qh_endp =
449 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL);
450 sqh->qh.qh_link =
451 htole32(sqh->physaddr | EHCI_LINK_QH);
452 sqh->qh.qh_curqtd = EHCI_NULL;
453 sqh->prev = sqh; /*It's a circular list.. */
454 sqh->next = sqh;
455 /* Fill the overlay qTD */
456 sqh->qh.qh_qtd.qtd_next = EHCI_NULL;
457 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL;
458 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED);
459 sqh->sqtd = NULL;
460 #ifdef EHCI_DEBUG
461 if (ehcidebug) {
462 ehci_dump_sqh(sqh);
463 }
464 #endif
465
466 /* Point to async list */
467 sc->sc_async_head = sqh;
468 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH);
469
470 callout_init(&sc->sc_tmo_intrlist);
471
472 lockinit(&sc->sc_doorbell_lock, "ehcidb", 0, 0);
473
474 /* Turn on controller */
475 EOWRITE4(sc, EHCI_USBCMD,
476 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */
477 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) |
478 EHCI_CMD_ASE |
479 EHCI_CMD_PSE |
480 EHCI_CMD_RS);
481
482 /* Take over port ownership */
483 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF);
484
485 for (i = 0; i < 100; i++) {
486 usb_delay_ms(&sc->sc_bus, 1);
487 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
488 if (!hcr)
489 break;
490 }
491 if (hcr) {
492 device_printf(sc->sc_bus.bdev, "run timeout\n");
493 return (USBD_IOERROR);
494 }
495
496 crit_enter();
497 sc->sc_flags |= EHCI_SCFLG_DONEINIT;
498 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
499 ehci_intr(sc);
500 crit_exit();
501
502 return (USBD_NORMAL_COMPLETION);
503
504 #if 0
505 bad2:
506 ehci_free_sqh(sc, sc->sc_async_head);
507 sc->sc_async_head = NULL;
508 #endif
509 bad1:
510 usb_freemem(&sc->sc_bus, &sc->sc_fldma);
511 return (err);
512 }
513
514 int
515 ehci_intr(void *v)
516 {
517 ehci_softc_t *sc = v;
518
519 if (sc->sc_dying || (sc->sc_flags & EHCI_SCFLG_DONEINIT) == 0)
520 return (0);
521
522 /* If we get an interrupt while polling, then just ignore it. */
523 if (sc->sc_bus.use_polling) {
524 u_int32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS));
525
526 if (intrs)
527 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */
528 sc->sc_dintrs |= intrs;
529 #ifdef DIAGNOSTIC
530 DPRINTFN(16, ("ehci_intr: ignored interrupt while polling\n"));
531 #endif
532 return (0);
533 }
534
535 return (ehci_intr1(sc));
536 }
537
538 static int
539 ehci_intr1(ehci_softc_t *sc)
540 {
541 u_int32_t intrs, eintrs;
542
543 DPRINTFN(20,("ehci_intr1: enter\n"));
544
545 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) | sc->sc_dintrs;
546 if (intrs == 0)
547 return (0);
548
549 sc->sc_dintrs = 0;
550 eintrs = intrs & sc->sc_eintrs;
551 DPRINTFN(7, ("ehci_intr1: sc=%p intrs=0x%x(0x%x) eintrs=0x%x\n",
552 sc, (u_int)intrs, EOREAD4(sc, EHCI_USBSTS),
553 (u_int)eintrs));
554 if (!eintrs)
555 return (0);
556
557 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */
558 sc->sc_bus.intr_context++;
559 sc->sc_bus.no_intrs++;
560 if (eintrs & EHCI_STS_IAA) {
561 DPRINTF(("ehci_intr1: door bell\n"));
562 wakeup(&sc->sc_async_head);
563 eintrs &= ~EHCI_STS_IAA;
564 }
565 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) {
566 DPRINTFN(5,("ehci_intr1: %s %s\n",
567 eintrs & EHCI_STS_INT ? "INT" : "",
568 eintrs & EHCI_STS_ERRINT ? "ERRINT" : ""));
569 usb_schedsoftintr(&sc->sc_bus);
570 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT);
571 }
572 if (eintrs & EHCI_STS_HSE) {
573 device_printf(sc->sc_bus.bdev,
574 "unrecoverable error, controller halted\n");
575 /* XXX what else */
576 }
577 if (eintrs & EHCI_STS_PCD) {
578 ehci_pcd(sc, sc->sc_intrxfer);
579 eintrs &= ~EHCI_STS_PCD;
580 }
581
582 sc->sc_bus.intr_context--;
583
584 if (eintrs != 0) {
585 /* Block unprocessed interrupts. */
586 sc->sc_eintrs &= ~eintrs;
587 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
588 device_printf(sc->sc_bus.bdev,
589 "blocking intrs 0x%x\n", eintrs);
590 }
591
592 return (1);
593 }
594
595 void
596 ehci_pcd(ehci_softc_t *sc, usbd_xfer_handle xfer)
597 {
598 u_char *p;
599 int i, m;
600
601 if (xfer == NULL) {
602 /* Just ignore the change. */
603 return;
604 }
605
606 p = KERNADDR(&xfer->dmabuf, 0);
607 m = min(sc->sc_noport, xfer->length * 8 - 1);
608 memset(p, 0, xfer->length);
609 for (i = 1; i <= m; i++) {
610 /* Pick out CHANGE bits from the status reg. */
611 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR)
612 p[i/8] |= 1 << (i%8);
613 }
614 DPRINTF(("ehci_pcd: change=0x%02x\n", *p));
615 xfer->actlen = xfer->length;
616 xfer->status = USBD_NORMAL_COMPLETION;
617
618 usb_transfer_complete(xfer);
619 }
620
621 void
622 ehci_softintr(void *v)
623 {
624 ehci_softc_t *sc = v;
625 struct ehci_xfer *ex, *nextex;
626
627 DPRINTFN(10,("%s: ehci_softintr (%d)\n", device_get_nameunit(sc->sc_bus.bdev),
628 sc->sc_bus.intr_context));
629
630 sc->sc_bus.intr_context++;
631
632 /*
633 * The only explanation I can think of for why EHCI is as brain dead
634 * as UHCI interrupt-wise is that Intel was involved in both.
635 * An interrupt just tells us that something is done, we have no
636 * clue what, so we need to scan through all active transfers. :-(
637 */
638 for (ex = LIST_FIRST(&sc->sc_intrhead); ex; ex = nextex) {
639 nextex = LIST_NEXT(ex, inext);
640 ehci_check_intr(sc, ex);
641 }
642
643 /* Schedule a callout to catch any dropped transactions. */
644 if ((sc->sc_flags & EHCI_SCFLG_LOSTINTRBUG) &&
645 !LIST_EMPTY(&sc->sc_intrhead))
646 callout_reset(&sc->sc_tmo_intrlist, hz / 5, ehci_intrlist_timeout,
647 sc);
648
649 #ifdef USB_USE_SOFTINTR
650 if (sc->sc_softwake) {
651 sc->sc_softwake = 0;
652 wakeup(&sc->sc_softwake);
653 }
654 #endif /* USB_USE_SOFTINTR */
655
656 sc->sc_bus.intr_context--;
657 }
658
659 /* Check for an interrupt. */
660 void
661 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex)
662 {
663 ehci_soft_qtd_t *sqtd, *lsqtd;
664 u_int32_t status;
665
666 DPRINTFN(/*15*/2, ("ehci_check_intr: ex=%p\n", ex));
667
668 if (ex->sqtdstart == NULL) {
669 kprintf("ehci_check_intr: sqtdstart=NULL\n");
670 return;
671 }
672 lsqtd = ex->sqtdend;
673 #ifdef DIAGNOSTIC
674 if (lsqtd == NULL) {
675 kprintf("ehci_check_intr: lsqtd==0\n");
676 return;
677 }
678 #endif
679 /*
680 * If the last TD is still active we need to check whether there
681 * is a an error somewhere in the middle, or whether there was a
682 * short packet (SPD and not ACTIVE).
683 */
684 if (le32toh(lsqtd->qtd.qtd_status) & EHCI_QTD_ACTIVE) {
685 DPRINTFN(12, ("ehci_check_intr: active ex=%p\n", ex));
686 for (sqtd = ex->sqtdstart; sqtd != lsqtd; sqtd=sqtd->nextqtd) {
687 status = le32toh(sqtd->qtd.qtd_status);
688 /* If there's an active QTD the xfer isn't done. */
689 if (status & EHCI_QTD_ACTIVE)
690 break;
691 /* Any kind of error makes the xfer done. */
692 if (status & EHCI_QTD_HALTED)
693 goto done;
694 /* We want short packets, and it is short: it's done */
695 if (EHCI_QTD_GET_BYTES(status) != 0)
696 goto done;
697 }
698 DPRINTFN(12, ("ehci_check_intr: ex=%p std=%p still active\n",
699 ex, ex->sqtdstart));
700 return;
701 }
702 done:
703 DPRINTFN(12, ("ehci_check_intr: ex=%p done\n", ex));
704 callout_stop(&ex->xfer.timeout_handle);
705 usb_rem_task(ex->xfer.pipe->device, &ex->abort_task);
706 ehci_idone(ex);
707 }
708
709 void
710 ehci_idone(struct ehci_xfer *ex)
711 {
712 usbd_xfer_handle xfer = &ex->xfer;
713 #ifdef USB_DEBUG
714 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;
715 #endif
716 ehci_soft_qtd_t *sqtd, *lsqtd;
717 u_int32_t status = 0, nstatus = 0;
718 int actlen, cerr;
719
720 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p\n", ex));
721 #ifdef DIAGNOSTIC
722 {
723 crit_enter();
724 if (ex->isdone) {
725 crit_exit();
726 #ifdef EHCI_DEBUG
727 kprintf("ehci_idone: ex is done!\n ");
728 ehci_dump_exfer(ex);
729 #else
730 kprintf("ehci_idone: ex=%p is done!\n", ex);
731 #endif
732 return;
733 }
734 ex->isdone = 1;
735 crit_exit();
736 }
737 #endif
738
739 if (xfer->status == USBD_CANCELLED ||
740 xfer->status == USBD_TIMEOUT) {
741 DPRINTF(("ehci_idone: aborted xfer=%p\n", xfer));
742 return;
743 }
744
745 #ifdef EHCI_DEBUG
746 DPRINTFN(/*10*/2, ("ehci_idone: xfer=%p, pipe=%p ready\n", xfer, epipe));
747 if (ehcidebug > 10)
748 ehci_dump_sqtds(ex->sqtdstart);
749 #endif
750
751 /* The transfer is done, compute actual length and status. */
752 lsqtd = ex->sqtdend;
753 actlen = 0;
754 for (sqtd = ex->sqtdstart; sqtd != lsqtd->nextqtd; sqtd=sqtd->nextqtd) {
755 nstatus = le32toh(sqtd->qtd.qtd_status);
756 if (nstatus & EHCI_QTD_ACTIVE)
757 break;
758
759 status = nstatus;
760 /* halt is ok if descriptor is last, and complete */
761 if (sqtd->qtd.qtd_next == EHCI_NULL &&
762 EHCI_QTD_GET_BYTES(status) == 0)
763 status &= ~EHCI_QTD_HALTED;
764 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP)
765 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status);
766 }
767
768 cerr = EHCI_QTD_GET_CERR(status);
769 DPRINTFN(/*10*/2, ("ehci_idone: len=%d, actlen=%d, cerr=%d, "
770 "status=0x%x\n", xfer->length, actlen, cerr, status));
771 xfer->actlen = actlen;
772 if ((status & EHCI_QTD_HALTED) != 0) {
773 #ifdef EHCI_DEBUG
774 char sbuf[128];
775
776 bitmask_snprintf((u_int32_t)status,
777 "\20\7HALTED\6BUFERR\5BABBLE\4XACTERR"
778 "\3MISSED\2SPLIT\1PING", sbuf, sizeof(sbuf));
779
780 DPRINTFN(2,
781 ("ehci_idone: error, addr=%d, endpt=0x%02x, "
782 "status 0x%s\n",
783 xfer->pipe->device->address,
784 xfer->pipe->endpoint->edesc->bEndpointAddress,
785 sbuf));
786 if (ehcidebug > 2) {
787 ehci_dump_sqh(epipe->sqh);
788 ehci_dump_sqtds(ex->sqtdstart);
789 }
790 #endif
791 if ((status & EHCI_QTD_BABBLE) == 0 && cerr > 0)
792 xfer->status = USBD_STALLED;
793 else
794 xfer->status = USBD_IOERROR; /* more info XXX */
795 } else {
796 xfer->status = USBD_NORMAL_COMPLETION;
797 }
798
799 usb_transfer_complete(xfer);
800 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p done\n", ex));
801 }
802
803 /*
804 * Wait here until controller claims to have an interrupt.
805 * Then call ehci_intr and return. Use timeout to avoid waiting
806 * too long.
807 */
808 void
809 ehci_waitintr(ehci_softc_t *sc, usbd_xfer_handle xfer)
810 {
811 int timo = xfer->timeout;
812 int usecs;
813
814 xfer->status = USBD_IN_PROGRESS;
815 for (usecs = timo * 1000000 / hz; usecs > 0; usecs -= 1000) {
816 usb_delay_ms(&sc->sc_bus, 1);
817 if (sc->sc_dying)
818 break;
819 ehci_intr1(sc);
820 if (xfer->status != USBD_IN_PROGRESS)
821 return;
822 }
823
824 /* Timeout */
825 DPRINTF(("ehci_waitintr: timeout\n"));
826 xfer->status = USBD_TIMEOUT;
827 usb_transfer_complete(xfer);
828 /* XXX should free TD */
829 }
830
831 void
832 ehci_poll(struct usbd_bus *bus)
833 {
834 ehci_softc_t *sc = (ehci_softc_t *)bus;
835 #ifdef EHCI_DEBUG
836 static int last;
837 int new;
838 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS));
839 if (new != last) {
840 DPRINTFN(10,("ehci_poll: intrs=0x%04x\n", new));
841 last = new;
842 }
843 #endif
844 crit_enter();
845 ehci_intr1(sc);
846 ehci_softintr(sc);
847 crit_exit();
848 }
849
850 int
851 ehci_detach(struct ehci_softc *sc, int flags)
852 {
853 int rv = 0;
854
855 crit_enter();
856 sc->sc_dying = 1;
857 callout_stop(&sc->sc_tmo_intrlist);
858 EOWRITE4(sc, EHCI_USBINTR, 0);
859 EOWRITE4(sc, EHCI_USBCMD, 0);
860 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET);
861 crit_exit();
862
863 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */
864
865 usb_freemem(&sc->sc_bus, &sc->sc_fldma);
866 /* XXX free other data structures XXX */
867
868 return (rv);
869 }
870
871 /*
872 * Handle suspend/resume.
873 *
874 * We need to switch to polling mode here, because this routine is
875 * called from an interrupt context. This is all right since we
876 * are almost suspended anyway.
877 */
878 void
879 ehci_power(int why, void *v)
880 {
881 ehci_softc_t *sc = v;
882 u_int32_t cmd, hcr;
883 int i;
884
885 #ifdef EHCI_DEBUG
886 DPRINTF(("ehci_power: sc=%p, why=%d\n", sc, why));
887 if (ehcidebug > 0)
888 ehci_dump_regs(sc);
889 #endif
890
891 crit_enter();
892
893 switch (why) {
894 case PWR_SUSPEND:
895 sc->sc_bus.use_polling++;
896
897 for (i = 1; i <= sc->sc_noport; i++) {
898 cmd = EOREAD4(sc, EHCI_PORTSC(i));
899 if ((cmd & EHCI_PS_PO) == 0 &&
900 (cmd & EHCI_PS_PE) == EHCI_PS_PE)
901 EOWRITE4(sc, EHCI_PORTSC(i),
902 cmd | EHCI_PS_SUSP);
903 }
904
905 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD);
906
907 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE);
908 EOWRITE4(sc, EHCI_USBCMD, cmd);
909
910 for (i = 0; i < 100; i++) {
911 hcr = EOREAD4(sc, EHCI_USBSTS) &
912 (EHCI_STS_ASS | EHCI_STS_PSS);
913 if (hcr == 0)
914 break;
915
916 usb_delay_ms(&sc->sc_bus, 1);
917 }
918 if (hcr != 0) {
919 device_printf(sc->sc_bus.bdev, "reset timeout\n");
920 }
921
922 cmd &= ~EHCI_CMD_RS;
923 EOWRITE4(sc, EHCI_USBCMD, cmd);
924
925 for (i = 0; i < 100; i++) {
926 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
927 if (hcr == EHCI_STS_HCH)
928 break;
929
930 usb_delay_ms(&sc->sc_bus, 1);
931 }
932 if (hcr != EHCI_STS_HCH) {
933 device_printf(sc->sc_bus.bdev, "config timeout\n");
934 }
935
936 sc->sc_bus.use_polling--;
937 break;
938
939 case PWR_RESUME:
940 sc->sc_bus.use_polling++;
941
942 /* restore things in case the bios sucks */
943 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0);
944 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0));
945 EOWRITE4(sc, EHCI_ASYNCLISTADDR,
946 sc->sc_async_head->physaddr | EHCI_LINK_QH);
947 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
948
949 hcr = 0;
950 for (i = 1; i <= sc->sc_noport; i++) {
951 cmd = EOREAD4(sc, EHCI_PORTSC(i));
952 if ((cmd & EHCI_PS_PO) == 0 &&
953 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) {
954 EOWRITE4(sc, EHCI_PORTSC(i),
955 cmd | EHCI_PS_FPR);
956 hcr = 1;
957 }
958 }
959
960 if (hcr) {
961 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT);
962
963 for (i = 1; i <= sc->sc_noport; i++) {
964 cmd = EOREAD4(sc, EHCI_PORTSC(i));
965 if ((cmd & EHCI_PS_PO) == 0 &&
966 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP)
967 EOWRITE4(sc, EHCI_PORTSC(i),
968 cmd & ~EHCI_PS_FPR);
969 }
970 }
971
972 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd);
973
974 for (i = 0; i < 100; i++) {
975 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
976 if (hcr != EHCI_STS_HCH)
977 break;
978
979 usb_delay_ms(&sc->sc_bus, 1);
980 }
981 if (hcr == EHCI_STS_HCH) {
982 device_printf(sc->sc_bus.bdev, "config timeout\n");
983 }
984
985 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT);
986
987 sc->sc_bus.use_polling--;
988 break;
989 }
990 crit_exit();
991
992 #ifdef EHCI_DEBUG
993 DPRINTF(("ehci_power: sc=%p\n", sc));
994 if (ehcidebug > 0)
995 ehci_dump_regs(sc);
996 #endif
997 }
998
999 /*
1000 * Shut down the controller when the system is going down.
1001 */
1002 void
1003 ehci_shutdown(void *v)
1004 {
1005 ehci_softc_t *sc = v;
1006
1007 DPRINTF(("ehci_shutdown: stopping the HC\n"));
1008 crit_enter();
1009 sc->sc_dying = 1;
1010 callout_stop(&sc->sc_tmo_intrlist);
1011 EOWRITE4(sc, EHCI_USBINTR, 0);
1012 EOWRITE4(sc, EHCI_USBCMD, 0);
1013 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET);
1014 crit_exit();
1015 }
1016
1017 usbd_status
1018 ehci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size)
1019 {
1020 usbd_status err;
1021
1022 err = usb_allocmem(bus, size, 0, dma);
1023 #ifdef EHCI_DEBUG
1024 if (err)
1025 kprintf("ehci_allocm: usb_allocmem()=%d\n", err);
1026 #endif
1027 return (err);
1028 }
1029
1030 void
1031 ehci_freem(struct usbd_bus *bus, usb_dma_t *dma)
1032 {
1033 usb_freemem(bus, dma);
1034 }
1035
1036 usbd_xfer_handle
1037 ehci_allocx(struct usbd_bus *bus)
1038 {
1039 struct ehci_softc *sc = (struct ehci_softc *)bus;
1040 usbd_xfer_handle xfer;
1041
1042 xfer = STAILQ_FIRST(&sc->sc_free_xfers);
1043 if (xfer != NULL) {
1044 STAILQ_REMOVE_HEAD(&sc->sc_free_xfers, next);
1045 #ifdef DIAGNOSTIC
1046 if (xfer->busy_free != XFER_FREE) {
1047 kprintf("ehci_allocx: xfer=%p not free, 0x%08x\n", xfer,
1048 xfer->busy_free);
1049 }
1050 #endif
1051 } else {
1052 xfer = kmalloc(sizeof(struct ehci_xfer), M_USB, M_INTWAIT);
1053 }
1054 if (xfer != NULL) {
1055 memset(xfer, 0, sizeof(struct ehci_xfer));
1056 usb_init_task(&EXFER(xfer)->abort_task, ehci_timeout_task,
1057 xfer);
1058 EXFER(xfer)->ehci_xfer_flags = 0;
1059 #ifdef DIAGNOSTIC
1060 EXFER(xfer)->isdone = 1;
1061 xfer->busy_free = XFER_BUSY;
1062 #endif
1063 }
1064 return (xfer);
1065 }
1066
1067 void
1068 ehci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer)
1069 {
1070 struct ehci_softc *sc = (struct ehci_softc *)bus;
1071
1072 #ifdef DIAGNOSTIC
1073 if (xfer->busy_free != XFER_BUSY) {
1074 kprintf("ehci_freex: xfer=%p not busy, 0x%08x\n", xfer,
1075 xfer->busy_free);
1076 return;
1077 }
1078 xfer->busy_free = XFER_FREE;
1079 if (!EXFER(xfer)->isdone) {
1080 kprintf("ehci_freex: !isdone\n");
1081 return;
1082 }
1083 #endif
1084 STAILQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next);
1085 }
1086
1087 static void
1088 ehci_device_clear_toggle(usbd_pipe_handle pipe)
1089 {
1090 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;
1091
1092 DPRINTF(("ehci_device_clear_toggle: epipe=%p status=0x%x\n",
1093 epipe, epipe->sqh->qh.qh_qtd.qtd_status));
1094 #ifdef USB_DEBUG
1095 if (ehcidebug)
1096 usbd_dump_pipe(pipe);
1097 #endif
1098 KASSERT((epipe->sqh->qh.qh_qtd.qtd_status &
1099 htole32(EHCI_QTD_ACTIVE)) == 0,
1100 ("ehci_device_clear_toggle: queue active"));
1101 epipe->sqh->qh.qh_qtd.qtd_status &= htole32(~EHCI_QTD_TOGGLE_MASK);
1102 }
1103
1104 static void
1105 ehci_noop(usbd_pipe_handle pipe)
1106 {
1107 }
1108
1109 #ifdef EHCI_DEBUG
1110 void
1111 ehci_dump_regs(ehci_softc_t *sc)
1112 {
1113 int i;
1114 kprintf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n",
1115 EOREAD4(sc, EHCI_USBCMD),
1116 EOREAD4(sc, EHCI_USBSTS),
1117 EOREAD4(sc, EHCI_USBINTR));
1118 kprintf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n",
1119 EOREAD4(sc, EHCI_FRINDEX),
1120 EOREAD4(sc, EHCI_CTRLDSSEGMENT),
1121 EOREAD4(sc, EHCI_PERIODICLISTBASE),
1122 EOREAD4(sc, EHCI_ASYNCLISTADDR));
1123 for (i = 1; i <= sc->sc_noport; i++)
1124 kprintf("port %d status=0x%08x\n", i,
1125 EOREAD4(sc, EHCI_PORTSC(i)));
1126 }
1127
1128 /*
1129 * Unused function - this is meant to be called from a kernel
1130 * debugger.
1131 */
1132 void
1133 ehci_dump(void)
1134 {
1135 ehci_dump_regs(theehci);
1136 }
1137
1138 void
1139 ehci_dump_link(ehci_link_t link, int type)
1140 {
1141 link = le32toh(link);
1142 kprintf("0x%08x", link);
1143 if (link & EHCI_LINK_TERMINATE)
1144 kprintf("<T>");
1145 else {
1146 kprintf("<");
1147 if (type) {
1148 switch (EHCI_LINK_TYPE(link)) {
1149 case EHCI_LINK_ITD: kprintf("ITD"); break;
1150 case EHCI_LINK_QH: kprintf("QH"); break;
1151 case EHCI_LINK_SITD: kprintf("SITD"); break;
1152 case EHCI_LINK_FSTN: kprintf("FSTN"); break;
1153 }
1154 }
1155 kprintf(">");
1156 }
1157 }
1158
1159 void
1160 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd)
1161 {
1162 int i;
1163 u_int32_t stop;
1164
1165 stop = 0;
1166 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) {
1167 ehci_dump_sqtd(sqtd);
1168 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE);
1169 }
1170 if (sqtd)
1171 kprintf("dump aborted, too many TDs\n");
1172 }
1173
1174 void
1175 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd)
1176 {
1177 kprintf("QTD(%p) at 0x%08x:\n", sqtd, sqtd->physaddr);
1178 ehci_dump_qtd(&sqtd->qtd);
1179 }
1180
1181 void
1182 ehci_dump_qtd(ehci_qtd_t *qtd)
1183 {
1184 u_int32_t s;
1185 char sbuf[128];
1186
1187 kprintf(" next="); ehci_dump_link(qtd->qtd_next, 0);
1188 kprintf(" altnext="); ehci_dump_link(qtd->qtd_altnext, 0);
1189 kprintf("\n");
1190 s = le32toh(qtd->qtd_status);
1191 bitmask_snprintf(EHCI_QTD_GET_STATUS(s),
1192 "\20\10ACTIVE\7HALTED\6BUFERR\5BABBLE\4XACTERR"
1193 "\3MISSED\2SPLIT\1PING", sbuf, sizeof(sbuf));
1194 kprintf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n",
1195 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s),
1196 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s));
1197 kprintf(" cerr=%d pid=%d stat=0x%s\n", EHCI_QTD_GET_CERR(s),
1198 EHCI_QTD_GET_PID(s), sbuf);
1199 for (s = 0; s < 5; s++)
1200 kprintf(" buffer[%d]=0x%08x\n", s, le32toh(qtd->qtd_buffer[s]));
1201 }
1202
1203 void
1204 ehci_dump_sqh(ehci_soft_qh_t *sqh)
1205 {
1206 ehci_qh_t *qh = &sqh->qh;
1207 u_int32_t endp, endphub;
1208
1209 kprintf("QH(%p) at 0x%08x:\n", sqh, sqh->physaddr);
1210 kprintf(" link="); ehci_dump_link(qh->qh_link, 1); kprintf("\n");
1211 endp = le32toh(qh->qh_endp);
1212 kprintf(" endp=0x%08x\n", endp);
1213 kprintf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n",
1214 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp),
1215 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp),
1216 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp));
1217 kprintf(" mpl=0x%x ctl=%d nrl=%d\n",
1218 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp),
1219 EHCI_QH_GET_NRL(endp));
1220 endphub = le32toh(qh->qh_endphub);
1221 kprintf(" endphub=0x%08x\n", endphub);
1222 kprintf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n",
1223 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub),
1224 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub),
1225 EHCI_QH_GET_MULT(endphub));
1226 kprintf(" curqtd="); ehci_dump_link(qh->qh_curqtd, 0); kprintf("\n");
1227 kprintf("Overlay qTD:\n");
1228 ehci_dump_qtd(&qh->qh_qtd);
1229 }
1230
1231 #ifdef DIAGNOSTIC
1232 static void
1233 ehci_dump_exfer(struct ehci_xfer *ex)
1234 {
1235 kprintf("ehci_dump_exfer: ex=%p\n", ex);
1236 }
1237 #endif
1238 #endif
1239
1240 usbd_status
1241 ehci_open(usbd_pipe_handle pipe)
1242 {
1243 usbd_device_handle dev = pipe->device;
1244 ehci_softc_t *sc = (ehci_softc_t *)dev->bus;
1245 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc;
1246 u_int8_t addr = dev->address;
1247 u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE;
1248 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;
1249 ehci_soft_qh_t *sqh;
1250 usbd_status err;
1251 int ival, speed, naks;
1252 int hshubaddr, hshubport;
1253
1254 DPRINTFN(1, ("ehci_open: pipe=%p, addr=%d, endpt=%d (%d)\n",
1255 pipe, addr, ed->bEndpointAddress, sc->sc_addr));
1256
1257 if (dev->myhsport) {
1258 hshubaddr = dev->myhsport->parent->address;
1259 hshubport = dev->myhsport->portno;
1260 } else {
1261 hshubaddr = 0;
1262 hshubport = 0;
1263 }
1264
1265 if (sc->sc_dying)
1266 return (USBD_IOERROR);
1267
1268 if (addr == sc->sc_addr) {
1269 switch (ed->bEndpointAddress) {
1270 case USB_CONTROL_ENDPOINT:
1271 pipe->methods = &ehci_root_ctrl_methods;
1272 break;
1273 case UE_DIR_IN | EHCI_INTR_ENDPT:
1274 pipe->methods = &ehci_root_intr_methods;
1275 break;
1276 default:
1277 return (USBD_INVAL);
1278 }
1279 return (USBD_NORMAL_COMPLETION);
1280 }
1281
1282 /* XXX All this stuff is only valid for async. */
1283 switch (dev->speed) {
1284 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break;
1285 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break;
1286 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break;
1287 default: panic("ehci_open: bad device speed %d", dev->speed);
1288 }
1289 if (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_ISOCHRONOUS) {
1290 device_printf(sc->sc_bus.bdev,
1291 "*** WARNING: opening low/full speed device, this "
1292 "does not work yet.\n");
1293 DPRINTFN(1,("ehci_open: hshubaddr=%d hshubport=%d\n",
1294 hshubaddr, hshubport));
1295 return USBD_INVAL;
1296 }
1297
1298 naks = 8; /* XXX */
1299 sqh = ehci_alloc_sqh(sc);
1300 if (sqh == NULL)
1301 goto bad0;
1302 /* qh_link filled when the QH is added */
1303 sqh->qh.qh_endp = htole32(
1304 EHCI_QH_SET_ADDR(addr) |
1305 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) |
1306 EHCI_QH_SET_EPS(speed) |
1307 (xfertype == UE_CONTROL ? EHCI_QH_DTC : 0) |
1308 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) |
1309 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ?
1310 EHCI_QH_CTL : 0) |
1311 EHCI_QH_SET_NRL(naks)
1312 );
1313 sqh->qh.qh_endphub = htole32(
1314 EHCI_QH_SET_MULT(1) |
1315 EHCI_QH_SET_HUBA(hshubaddr) |
1316 EHCI_QH_SET_PORT(hshubport) |
1317 EHCI_QH_SET_CMASK(0x1c) |
1318 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x01 : 0)
1319 );
1320 sqh->qh.qh_curqtd = EHCI_NULL;
1321 /* Fill the overlay qTD */
1322 sqh->qh.qh_qtd.qtd_next = EHCI_NULL;
1323 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL;
1324 sqh->qh.qh_qtd.qtd_status =
1325 htole32(EHCI_QTD_SET_TOGGLE(pipe->endpoint->savedtoggle));
1326
1327 epipe->sqh = sqh;
1328
1329 switch (xfertype) {
1330 case UE_CONTROL:
1331 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t),
1332 0, &epipe->u.ctl.reqdma);
1333 #ifdef EHCI_DEBUG
1334 if (err)
1335 kprintf("ehci_open: usb_allocmem()=%d\n", err);
1336 #endif
1337 if (err)
1338 goto bad1;
1339 pipe->methods = &ehci_device_ctrl_methods;
1340 crit_enter();
1341 ehci_add_qh(sqh, sc->sc_async_head);
1342 crit_exit();
1343 break;
1344 case UE_BULK:
1345 pipe->methods = &ehci_device_bulk_methods;
1346 crit_enter();
1347 ehci_add_qh(sqh, sc->sc_async_head);
1348 crit_exit();
1349 break;
1350 case UE_INTERRUPT:
1351 pipe->methods = &ehci_device_intr_methods;
1352 ival = pipe->interval;
1353 if (ival == USBD_DEFAULT_INTERVAL)
1354 ival = ed->bInterval;
1355 return (ehci_device_setintr(sc, sqh, ival));
1356 case UE_ISOCHRONOUS:
1357 pipe->methods = &ehci_device_isoc_methods;
1358 return (USBD_INVAL);
1359 default:
1360 return (USBD_INVAL);
1361 }
1362 return (USBD_NORMAL_COMPLETION);
1363
1364 bad1:
1365 ehci_free_sqh(sc, sqh);
1366 epipe->sqh = NULL;
1367 bad0:
1368 return (USBD_NOMEM);
1369 }
1370
1371 /*
1372 * Add an ED to the schedule. Called while in a critical section.
1373 * If in the async schedule, it will always have a next.
1374 * If in the intr schedule it may not.
1375 */
1376 void
1377 ehci_add_qh(ehci_soft_qh_t *sqh, ehci_soft_qh_t *head)
1378 {
1379 sqh->next = head->next;
1380 sqh->prev = head;
1381 sqh->qh.qh_link = head->qh.qh_link;
1382 head->next = sqh;
1383 if (sqh->next)
1384 sqh->next->prev = sqh;
1385 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH);
1386
1387 #ifdef EHCI_DEBUG
1388 if (ehcidebug > 5) {
1389 kprintf("ehci_add_qh:\n");
1390 ehci_dump_sqh(sqh);
1391 }
1392 #endif
1393 }
1394
1395 /*
1396 * Remove an ED from the schedule. Called while in a critical section.
1397 * Will always have a 'next' if it's in the async list as it's circular.
1398 */
1399 void
1400 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head)
1401 {
1402 /* XXX */
1403 sqh->prev->qh.qh_link = sqh->qh.qh_link;
1404 sqh->prev->next = sqh->next;
1405 if (sqh->next)
1406 sqh->next->prev = sqh->prev;
1407 ehci_sync_hc(sc);
1408 }
1409
1410 void
1411 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd)
1412 {
1413 int i;
1414 u_int32_t status;
1415
1416 /* Save toggle bit and ping status. */
1417 status = sqh->qh.qh_qtd.qtd_status &
1418 htole32(EHCI_QTD_TOGGLE_MASK |
1419 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE));
1420 /* Set HALTED to make hw leave it alone. */
1421 sqh->qh.qh_qtd.qtd_status =
1422 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED));
1423 sqh->qh.qh_curqtd = 0;
1424 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr);
1425 sqh->qh.qh_qtd.qtd_altnext = 0;
1426 for (i = 0; i < EHCI_QTD_NBUFFERS; i++)
1427 sqh->qh.qh_qtd.qtd_buffer[i] = 0;
1428 sqh->sqtd = sqtd;
1429 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */
1430 sqh->qh.qh_qtd.qtd_status = status;
1431 }
1432
1433 /*
1434 * Ensure that the HC has released all references to the QH. We do this
1435 * by asking for a Async Advance Doorbell interrupt and then we wait for
1436 * the interrupt.
1437 * To make this easier we first obtain exclusive use of the doorbell.
1438 */
1439 void
1440 ehci_sync_hc(ehci_softc_t *sc)
1441 {
1442 int error;
1443
1444 if (sc->sc_dying) {
1445 DPRINTFN(2,("ehci_sync_hc: dying\n"));
1446 return;
1447 }
1448 DPRINTFN(2,("ehci_sync_hc: enter\n"));
1449 /* get doorbell */
1450 lockmgr(&sc->sc_doorbell_lock, LK_EXCLUSIVE);
1451 crit_enter();
1452 /* ask for doorbell */
1453 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD);
1454 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n",
1455 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS)));
1456 error = tsleep(&sc->sc_async_head, 0, "ehcidi", hz); /* bell wait */
1457 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n",
1458 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS)));
1459 crit_exit();
1460 /* release doorbell */
1461 lockmgr(&sc->sc_doorbell_lock, LK_RELEASE);
1462 #ifdef DIAGNOSTIC
1463 if (error)
1464 kprintf("ehci_sync_hc: tsleep() = %d\n", error);
1465 #endif
1466 DPRINTFN(2,("ehci_sync_hc: exit\n"));
1467 }
1468
1469 /***********/
1470
1471 /*
1472 * Data structures and routines to emulate the root hub.
1473 */
1474 static usb_device_descriptor_t ehci_devd = {
1475 USB_DEVICE_DESCRIPTOR_SIZE,
1476 UDESC_DEVICE, /* type */
1477 {0x00, 0x02}, /* USB version */
1478 UDCLASS_HUB, /* class */
1479 UDSUBCLASS_HUB, /* subclass */
1480 UDPROTO_HSHUBSTT, /* protocol */
1481 64, /* max packet */
1482 {0},{0},{0x00,0x01}, /* device id */
1483 1,2,0, /* string indicies */
1484 1 /* # of configurations */
1485 };
1486
1487 static usb_device_qualifier_t ehci_odevd = {
1488 USB_DEVICE_DESCRIPTOR_SIZE,
1489 UDESC_DEVICE_QUALIFIER, /* type */
1490 {0x00, 0x02}, /* USB version */
1491 UDCLASS_HUB, /* class */
1492 UDSUBCLASS_HUB, /* subclass */
1493 UDPROTO_FSHUB, /* protocol */
1494 64, /* max packet */
1495 1, /* # of configurations */
1496 0
1497 };
1498
1499 static usb_config_descriptor_t ehci_confd = {
1500 USB_CONFIG_DESCRIPTOR_SIZE,
1501 UDESC_CONFIG,
1502 {USB_CONFIG_DESCRIPTOR_SIZE +
1503 USB_INTERFACE_DESCRIPTOR_SIZE +
1504 USB_ENDPOINT_DESCRIPTOR_SIZE},
1505 1,
1506 1,
1507 0,
1508 UC_SELF_POWERED,
1509 0 /* max power */
1510 };
1511
1512 static usb_interface_descriptor_t ehci_ifcd = {
1513 USB_INTERFACE_DESCRIPTOR_SIZE,
1514 UDESC_INTERFACE,
1515 0,
1516 0,
1517 1,
1518 UICLASS_HUB,
1519 UISUBCLASS_HUB,
1520 UIPROTO_HSHUBSTT,
1521 0
1522 };
1523
1524 static usb_endpoint_descriptor_t ehci_endpd = {
1525 USB_ENDPOINT_DESCRIPTOR_SIZE,
1526 UDESC_ENDPOINT,
1527 UE_DIR_IN | EHCI_INTR_ENDPT,
1528 UE_INTERRUPT,
1529 {8, 0}, /* max packet */
1530 255
1531 };
1532
1533 static usb_hub_descriptor_t ehci_hubd = {
1534 USB_HUB_DESCRIPTOR_SIZE,
1535 UDESC_HUB,
1536 0,
1537 {0,0},
1538 0,
1539 0,
1540 {0},
1541 };
1542
1543 static int
1544 ehci_str(usb_string_descriptor_t *p, int l, char *s)
1545 {
1546 int i;
1547
1548 if (l == 0)
1549 return (0);
1550 p->bLength = 2 * strlen(s) + 2;
1551 if (l == 1)
1552 return (1);
1553 p->bDescriptorType = UDESC_STRING;
1554 l -= 2;
1555 for (i = 0; s[i] && l > 1; i++, l -= 2)
1556 USETW2(p->bString[i], 0, s[i]);
1557 return (2*i+2);
1558 }
1559
1560 /*
1561 * Simulate a hardware hub by handling all the necessary requests.
1562 */
1563 static usbd_status
1564 ehci_root_ctrl_transfer(usbd_xfer_handle xfer)
1565 {
1566 usbd_status err;
1567
1568 /* Insert last in queue. */
1569 err = usb_insert_transfer(xfer);
1570 if (err)
1571 return (err);
1572
1573 /* Pipe isn't running, start first */
1574 return (ehci_root_ctrl_start(STAILQ_FIRST(&xfer->pipe->queue)));
1575 }
1576
1577 static usbd_status
1578 ehci_root_ctrl_start(usbd_xfer_handle xfer)
1579 {
1580 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus;
1581 usb_device_request_t *req;
1582 void *buf = NULL;
1583 int port, i;
1584 int len, value, index, l, totlen = 0;
1585 usb_port_status_t ps;
1586 usb_hub_descriptor_t hubd;
1587 usbd_status err;
1588 u_int32_t v;
1589
1590 if (sc->sc_dying)
1591 return (USBD_IOERROR);
1592
1593 #ifdef DIAGNOSTIC
1594 if (!(xfer->rqflags & URQ_REQUEST))
1595 /* XXX panic */
1596 return (USBD_INVAL);
1597 #endif
1598 req = &xfer->request;
1599
1600 DPRINTFN(4,("ehci_root_ctrl_start: type=0x%02x request=%02x\n",
1601 req->bmRequestType, req->bRequest));
1602
1603 len = UGETW(req->wLength);
1604 value = UGETW(req->wValue);
1605 index = UGETW(req->wIndex);
1606
1607 if (len != 0)
1608 buf = KERNADDR(&xfer->dmabuf, 0);
1609
1610 #define C(x,y) ((x) | ((y) << 8))
1611 switch(C(req->bRequest, req->bmRequestType)) {
1612 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
1613 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
1614 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
1615 /*
1616 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
1617 * for the integrated root hub.
1618 */
1619 break;
1620 case C(UR_GET_CONFIG, UT_READ_DEVICE):
1621 if (len > 0) {
1622 *(u_int8_t *)buf = sc->sc_conf;
1623 totlen = 1;
1624 }
1625 break;
1626 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
1627 DPRINTFN(8,("ehci_root_ctrl_start: wValue=0x%04x\n", value));
1628 switch(value >> 8) {
1629 case UDESC_DEVICE:
1630 if ((value & 0xff) != 0) {
1631 err = USBD_IOERROR;
1632 goto ret;
1633 }
1634 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE);
1635 USETW(ehci_devd.idVendor, sc->sc_id_vendor);
1636 memcpy(buf, &ehci_devd, l);
1637 break;
1638 /*
1639 * We can't really operate at another speed, but the spec says
1640 * we need this descriptor.
1641 */
1642 case UDESC_DEVICE_QUALIFIER:
1643 if ((value & 0xff) != 0) {
1644 err = USBD_IOERROR;
1645 goto ret;
1646 }
1647 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE);
1648 memcpy(buf, &ehci_odevd, l);
1649 break;
1650 /*
1651 * We can't really operate at another speed, but the spec says
1652 * we need this descriptor.
1653 */
1654 case UDESC_OTHER_SPEED_CONFIGURATION:
1655 case UDESC_CONFIG:
1656 if ((value & 0xff) != 0) {
1657 err = USBD_IOERROR;
1658 goto ret;
1659 }
1660 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE);
1661 memcpy(buf, &ehci_confd, l);
1662 ((usb_config_descriptor_t *)buf)->bDescriptorType =
1663 value >> 8;
1664 buf = (char *)buf + l;
1665 len -= l;
1666 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE);
1667 totlen += l;
1668 memcpy(buf, &ehci_ifcd, l);
1669 buf = (char *)buf + l;
1670 len -= l;
1671 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE);
1672 totlen += l;
1673 memcpy(buf, &ehci_endpd, l);
1674 break;
1675 case UDESC_STRING:
1676 if (len == 0)
1677 break;
1678 *(u_int8_t *)buf = 0;
1679 totlen = 1;
1680 switch (value & 0xff) {
1681 case 0: /* Language table */
1682 totlen = ehci_str(buf, len, "\001");
1683 break;
1684 case 1: /* Vendor */
1685 totlen = ehci_str(buf, len, sc->sc_vendor);
1686 break;
1687 case 2: /* Product */
1688 totlen = ehci_str(buf, len, "EHCI root hub");
1689 break;
1690 }
1691 break;
1692 default:
1693 err = USBD_IOERROR;
1694 goto ret;
1695 }
1696 break;
1697 case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
1698 if (len > 0) {
1699 *(u_int8_t *)buf = 0;
1700 totlen = 1;
1701 }
1702 break;
1703 case C(UR_GET_STATUS, UT_READ_DEVICE):
1704 if (len > 1) {
1705 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED);
1706 totlen = 2;
1707 }
1708 break;
1709 case C(UR_GET_STATUS, UT_READ_INTERFACE):
1710 case C(UR_GET_STATUS, UT_READ_ENDPOINT):
1711 if (len > 1) {
1712 USETW(((usb_status_t *)buf)->wStatus, 0);
1713 totlen = 2;
1714 }
1715 break;
1716 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
1717 if (value >= USB_MAX_DEVICES) {
1718 err = USBD_IOERROR;
1719 goto ret;
1720 }
1721 sc->sc_addr = value;
1722 break;
1723 case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
1724 if (value != 0 && value != 1) {
1725 err = USBD_IOERROR;
1726 goto ret;
1727 }
1728 sc->sc_conf = value;
1729 break;
1730 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
1731 break;
1732 case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
1733 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
1734 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
1735 err = USBD_IOERROR;
1736 goto ret;
1737 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
1738 break;
1739 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
1740 break;
1741 /* Hub requests */
1742 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
1743 break;
1744 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
1745 DPRINTFN(8, ("ehci_root_ctrl_start: UR_CLEAR_PORT_FEATURE "
1746 "port=%d feature=%d\n",
1747 index, value));
1748 if (index < 1 || index > sc->sc_noport) {
1749 err = USBD_IOERROR;
1750 goto ret;
1751 }
1752 port = EHCI_PORTSC(index);
1753 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR;
1754 switch(value) {
1755 case UHF_PORT_ENABLE:
1756 EOWRITE4(sc, port, v &~ EHCI_PS_PE);
1757 break;
1758 case UHF_PORT_SUSPEND:
1759 EOWRITE4(sc, port, v &~ EHCI_PS_SUSP);
1760 break;
1761 case UHF_PORT_POWER:
1762 EOWRITE4(sc, port, v &~ EHCI_PS_PP);
1763 break;
1764 case UHF_PORT_TEST:
1765 DPRINTFN(2,("ehci_root_ctrl_start: clear port test "
1766 "%d\n", index));
1767 break;
1768 case UHF_PORT_INDICATOR:
1769 DPRINTFN(2,("ehci_root_ctrl_start: clear port ind "
1770 "%d\n", index));
1771 EOWRITE4(sc, port, v &~ EHCI_PS_PIC);
1772 break;
1773 case UHF_C_PORT_CONNECTION:
1774 EOWRITE4(sc, port, v | EHCI_PS_CSC);
1775 break;
1776 case UHF_C_PORT_ENABLE:
1777 EOWRITE4(sc, port, v | EHCI_PS_PEC);
1778 break;
1779 case UHF_C_PORT_SUSPEND:
1780 /* how? */
1781 break;
1782 case UHF_C_PORT_OVER_CURRENT:
1783 EOWRITE4(sc, port, v | EHCI_PS_OCC);
1784 break;
1785 case UHF_C_PORT_RESET:
1786 sc->sc_isreset = 0;
1787 break;
1788 default:
1789 err = USBD_IOERROR;
1790 goto ret;
1791 }
1792 break;
1793 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
1794 if ((value & 0xff) != 0) {
1795 err = USBD_IOERROR;
1796 goto ret;
1797 }
1798 hubd = ehci_hubd;
1799 hubd.bNbrPorts = sc->sc_noport;
1800 v = EOREAD4(sc, EHCI_HCSPARAMS);
1801 USETW(hubd.wHubCharacteristics,
1802 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH |
1803 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS))
1804 ? UHD_PORT_IND : 0);
1805 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */
1806 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8)
1807 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */
1808 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i;
1809 l = min(len, hubd.bDescLength);
1810 totlen = l;
1811 memcpy(buf, &hubd, l);
1812 break;
1813 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
1814 if (len != 4) {
1815 err = USBD_IOERROR;
1816 goto ret;
1817 }
1818 memset(buf, 0, len); /* ? XXX */
1819 totlen = len;
1820 break;
1821 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
1822 DPRINTFN(8,("ehci_root_ctrl_start: get port status i=%d\n",
1823 index));
1824 if (index < 1 || index > sc->sc_noport) {
1825 err = USBD_IOERROR;
1826 goto ret;
1827 }
1828 if (len != 4) {
1829 err = USBD_IOERROR;
1830 goto ret;
1831 }
1832 v = EOREAD4(sc, EHCI_PORTSC(index));
1833 DPRINTFN(8,("ehci_root_ctrl_start: port status=0x%04x\n", v));
1834 i = UPS_HIGH_SPEED;
1835 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS;
1836 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED;
1837 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND;
1838 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR;
1839 if (v & EHCI_PS_PR) i |= UPS_RESET;
1840 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER;
1841 USETW(ps.wPortStatus, i);
1842 i = 0;
1843 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS;
1844 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED;
1845 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR;
1846 if (sc->sc_isreset) i |= UPS_C_PORT_RESET;
1847 USETW(ps.wPortChange, i);
1848 l = min(len, sizeof ps);
1849 memcpy(buf, &ps, l);
1850 totlen = l;
1851 break;
1852 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
1853 err = USBD_IOERROR;
1854 goto ret;
1855 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
1856 break;
1857 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
1858 if (index < 1 || index > sc->sc_noport) {
1859 err = USBD_IOERROR;
1860 goto ret;
1861 }
1862 port = EHCI_PORTSC(index);
1863 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR;
1864 switch(value) {
1865 case UHF_PORT_ENABLE:
1866 EOWRITE4(sc, port, v | EHCI_PS_PE);
1867 break;
1868 case UHF_PORT_SUSPEND:
1869 EOWRITE4(sc, port, v | EHCI_PS_SUSP);
1870 break;
1871 case UHF_PORT_RESET:
1872 DPRINTFN(5,("ehci_root_ctrl_start: reset port %d\n",
1873 index));
1874 if (EHCI_PS_IS_LOWSPEED(v)) {
1875 /* Low speed device, give up ownership. */
1876 ehci_disown(sc, index, 1);
1877 break;
1878 }
1879 /* Start reset sequence. */
1880 v &= ~ (EHCI_PS_PE | EHCI_PS_PR);
1881 EOWRITE4(sc, port, v | EHCI_PS_PR);
1882 /* Wait for reset to complete. */
1883 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY);
1884 if (sc->sc_dying) {
1885 err = USBD_IOERROR;
1886 goto ret;
1887 }
1888 /* Terminate reset sequence. */
1889 EOWRITE4(sc, port, v);
1890 /* Wait for HC to complete reset. */
1891 usb_delay_ms(&sc->sc_bus, EHCI_PORT_RESET_COMPLETE);
1892 if (sc->sc_dying) {
1893 err = USBD_IOERROR;
1894 goto ret;
1895 }
1896 v = EOREAD4(sc, port);
1897 DPRINTF(("ehci after reset, status=0x%08x\n", v));
1898 if (v & EHCI_PS_PR) {
1899 device_printf(sc->sc_bus.bdev,
1900 "port reset timeout\n");
1901 return (USBD_TIMEOUT);
1902 }
1903 if (!(v & EHCI_PS_PE)) {
1904 /* Not a high speed device, give up ownership.*/
1905 ehci_disown(sc, index, 0);
1906 break;
1907 }
1908 sc->sc_isreset = 1;
1909 DPRINTF(("ehci port %d reset, status = 0x%08x\n",
1910 index, v));
1911 break;
1912 case UHF_PORT_POWER:
1913 DPRINTFN(2,("ehci_root_ctrl_start: set port power "
1914 "%d\n", index));
1915 EOWRITE4(sc, port, v | EHCI_PS_PP);
1916 break;
1917 case UHF_PORT_TEST:
1918 DPRINTFN(2,("ehci_root_ctrl_start: set port test "
1919 "%d\n", index));
1920 break;
1921 case UHF_PORT_INDICATOR:
1922 DPRINTFN(2,("ehci_root_ctrl_start: set port ind "
1923 "%d\n", index));
1924 EOWRITE4(sc, port, v | EHCI_PS_PIC);
1925 break;
1926 default:
1927 err = USBD_IOERROR;
1928 goto ret;
1929 }
1930 break;
1931 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER):
1932 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER):
1933 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER):
1934 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER):
1935 break;
1936 default:
1937 err = USBD_IOERROR;
1938 goto ret;
1939 }
1940 xfer->actlen = totlen;
1941 err = USBD_NORMAL_COMPLETION;
1942 ret:
1943 xfer->status = err;
1944 crit_enter();
1945 usb_transfer_complete(xfer);
1946 crit_exit();
1947 return (USBD_IN_PROGRESS);
1948 }
1949
1950 void
1951 ehci_disown(ehci_softc_t *sc, int index, int lowspeed)
1952 {
1953 int port;
1954 u_int32_t v;
1955
1956 DPRINTF(("ehci_disown: index=%d lowspeed=%d\n", index, lowspeed));
1957 #ifdef DIAGNOSTIC
1958 if (sc->sc_npcomp != 0) {
1959 int i = (index-1) / sc->sc_npcomp;
1960 if (i >= sc->sc_ncomp)
1961 device_printf(sc->sc_bus.bdev, "strange port\n");
1962 else
1963 device_printf(sc->sc_bus.bdev,
1964 "handing over %s speed device on port %d to %s\n",
1965 (lowspeed ? "low" : "full"),
1966 index, device_get_nameunit(sc->sc_comps[i]->bdev));
1967 } else {
1968 device_printf(sc->sc_bus.bdev, "npcomp == 0\n");
1969 }
1970 #endif
1971 port = EHCI_PORTSC(index);
1972 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR;
1973 EOWRITE4(sc, port, v | EHCI_PS_PO);
1974 }
1975
1976 /* Abort a root control request. */
1977 static void
1978 ehci_root_ctrl_abort(usbd_xfer_handle xfer)
1979 {
1980 /* Nothing to do, all transfers are synchronous. */
1981 }
1982
1983 /* Close the root pipe. */
1984 static void
1985 ehci_root_ctrl_close(usbd_pipe_handle pipe)
1986 {
1987 DPRINTF(("ehci_root_ctrl_close\n"));
1988 /* Nothing to do. */
1989 }
1990
1991 void
1992 ehci_root_intr_done(usbd_xfer_handle xfer)
1993 {
1994 }
1995
1996 static usbd_status
1997 ehci_root_intr_transfer(usbd_xfer_handle xfer)
1998 {
1999 usbd_status err;
2000
2001 /* Insert last in queue. */
2002 err = usb_insert_transfer(xfer);
2003 if (err)
2004 return (err);
2005
2006 /* Pipe isn't running, start first */
2007 return (ehci_root_intr_start(STAILQ_FIRST(&xfer->pipe->queue)));
2008 }
2009
2010 static usbd_status
2011 ehci_root_intr_start(usbd_xfer_handle xfer)
2012 {
2013 usbd_pipe_handle pipe = xfer->pipe;
2014 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus;
2015
2016 if (sc->sc_dying)
2017 return (USBD_IOERROR);
2018
2019 sc->sc_intrxfer = xfer;
2020
2021 return (USBD_IN_PROGRESS);
2022 }
2023
2024 /* Abort a root interrupt request. */
2025 static void
2026 ehci_root_intr_abort(usbd_xfer_handle xfer)
2027 {
2028 if (xfer->pipe->intrxfer == xfer) {
2029 DPRINTF(("ehci_root_intr_abort: remove\n"));
2030 xfer->pipe->intrxfer = NULL;
2031 }
2032 xfer->status = USBD_CANCELLED;
2033 crit_enter();
2034 usb_transfer_complete(xfer);
2035 crit_exit();
2036 }
2037
2038 /* Close the root pipe. */
2039 static void
2040 ehci_root_intr_close(usbd_pipe_handle pipe)
2041 {
2042 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus;
2043
2044 DPRINTF(("ehci_root_intr_close\n"));
2045
2046 sc->sc_intrxfer = NULL;
2047 }
2048
2049 void
2050 ehci_root_ctrl_done(usbd_xfer_handle xfer)
2051 {
2052 }
2053
2054 /************************/
2055
2056 ehci_soft_qh_t *
2057 ehci_alloc_sqh(ehci_softc_t *sc)
2058 {
2059 ehci_soft_qh_t *sqh;
2060 usbd_status err;
2061 int i, offs;
2062 usb_dma_t dma;
2063
2064 if (sc->sc_freeqhs == NULL) {
2065 DPRINTFN(2, ("ehci_alloc_sqh: allocating chunk\n"));
2066 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK,
2067 EHCI_PAGE_SIZE, &dma);
2068 #ifdef EHCI_DEBUG
2069 if (err)
2070 kprintf("ehci_alloc_sqh: usb_allocmem()=%d\n", err);
2071 #endif
2072 if (err)
2073 return (NULL);
2074 for(i = 0; i < EHCI_SQH_CHUNK; i++) {
2075 offs = i * EHCI_SQH_SIZE;
2076 sqh = KERNADDR(&dma, offs);
2077 sqh->physaddr = DMAADDR(&dma, offs);
2078 sqh->next = sc->sc_freeqhs;
2079 sc->sc_freeqhs = sqh;
2080 }
2081 }
2082 sqh = sc->sc_freeqhs;
2083 sc->sc_freeqhs = sqh->next;
2084 memset(&sqh->qh, 0, sizeof(ehci_qh_t));
2085 sqh->next = NULL;
2086 sqh->prev = NULL;
2087 return (sqh);
2088 }
2089
2090 void
2091 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh)
2092 {
2093 sqh->next = sc->sc_freeqhs;
2094 sc->sc_freeqhs = sqh;
2095 }
2096
2097 ehci_soft_qtd_t *
2098 ehci_alloc_sqtd(ehci_softc_t *sc)
2099 {
2100 ehci_soft_qtd_t *sqtd;
2101 usbd_status err;
2102 int i, offs;
2103 usb_dma_t dma;
2104
2105 if (sc->sc_freeqtds == NULL) {
2106 DPRINTFN(2, ("ehci_alloc_sqtd: allocating chunk\n"));
2107 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK,
2108 EHCI_PAGE_SIZE, &dma);
2109 #ifdef EHCI_DEBUG
2110 if (err)
2111 kprintf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err);
2112 #endif
2113 if (err)
2114 return (NULL);
2115 crit_enter();
2116 for(i = 0; i < EHCI_SQTD_CHUNK; i++) {
2117 offs = i * EHCI_SQTD_SIZE;
2118 sqtd = KERNADDR(&dma, offs);
2119 sqtd->physaddr = DMAADDR(&dma, offs);
2120 sqtd->nextqtd = sc->sc_freeqtds;
2121 sc->sc_freeqtds = sqtd;
2122 }
2123 crit_exit();
2124 }
2125
2126 crit_enter();
2127 sqtd = sc->sc_freeqtds;
2128 sc->sc_freeqtds = sqtd->nextqtd;
2129 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t));
2130 sqtd->nextqtd = NULL;
2131 sqtd->xfer = NULL;
2132 crit_exit();
2133
2134 return (sqtd);
2135 }
2136
2137 void
2138 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd)
2139 {
2140 crit_enter();
2141 sqtd->nextqtd = sc->sc_freeqtds;
2142 sc->sc_freeqtds = sqtd;
2143 crit_exit();
2144 }
2145
2146 usbd_status
2147 ehci_alloc_sqtd_chain(struct ehci_pipe *epipe, ehci_softc_t *sc,
2148 int alen, int rd, usbd_xfer_handle xfer,
2149 ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep)
2150 {
2151 ehci_soft_qtd_t *next, *cur;
2152 ehci_physaddr_t dataphys, dataphyspage, dataphyslastpage, nextphys;
2153 u_int32_t qtdstatus;
2154 int len, curlen, mps, offset;
2155 int i, iscontrol;
2156 usb_dma_t *dma = &xfer->dmabuf;
2157
2158 DPRINTFN(alen<4*4096,("ehci_alloc_sqtd_chain: start len=%d\n", alen));
2159
2160 offset = 0;
2161 len = alen;
2162 iscontrol = (epipe->pipe.endpoint->edesc->bmAttributes & UE_XFERTYPE) ==
2163 UE_CONTROL;
2164 dataphys = DMAADDR(dma, 0);
2165 dataphyslastpage = EHCI_PAGE(DMAADDR(dma, len - 1));
2166 qtdstatus = EHCI_QTD_ACTIVE |
2167 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) |
2168 EHCI_QTD_SET_CERR(3)
2169 /* IOC set below */
2170 /* BYTES set below */
2171 ;
2172 mps = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize);
2173 /*
2174 * The control transfer data stage always starts with a toggle of 1.
2175 * For other transfers we let the hardware track the toggle state.
2176 */
2177 if (iscontrol)
2178 qtdstatus |= EHCI_QTD_SET_TOGGLE(1);
2179
2180 cur = ehci_alloc_sqtd(sc);
2181 *sp = cur;
2182 if (cur == NULL)
2183 goto nomem;
2184 for (;;) {
2185 dataphyspage = EHCI_PAGE(dataphys);
2186 /* XXX This is pretty broken: Because we do not allocate
2187 * a contiguous buffer (contiguous in physical pages) we
2188 * can only transfer one page in one go.
2189 * So check whether the start and end of the buffer are on
2190 * the same page.
2191 */
2192 if (dataphyspage == dataphyslastpage) {
2193 curlen = len;
2194 }
2195 else {
2196 /* See comment above (XXX) */
2197 curlen = EHCI_PAGE_SIZE -
2198 EHCI_PAGE_MASK(dataphys);
2199 /* the length must be a multiple of the max size */
2200 curlen -= curlen % mps;
2201 DPRINTFN(1,("ehci_alloc_sqtd_chain: multiple QTDs, "
2202 "curlen=%d\n", curlen));
2203 KASSERT(curlen != 0, ("ehci_alloc_std: curlen == 0"));
2204 }
2205 DPRINTFN(4,("ehci_alloc_sqtd_chain: dataphys=0x%08x "
2206 "dataphyslastpage=0x%08x len=%d curlen=%d\n",
2207 dataphys, dataphyslastpage,
2208 len, curlen));
2209 len -= curlen;
2210
2211 if (len != 0) {
2212 next = ehci_alloc_sqtd(sc);
2213 if (next == NULL)
2214 goto nomem;
2215 nextphys = htole32(next->physaddr);
2216 } else {
2217 next = NULL;
2218 nextphys = EHCI_NULL;
2219 }
2220
2221 for (i = 0; i * EHCI_PAGE_SIZE < curlen; i++) {
2222 ehci_physaddr_t a = dataphys + i * EHCI_PAGE_SIZE;
2223 if (i != 0) /* use offset only in first buffer */
2224 a = EHCI_PAGE(a);
2225 cur->qtd.qtd_buffer[i] = htole32(a);
2226 cur->qtd.qtd_buffer_hi[i] = 0;
2227 #ifdef DIAGNOSTIC
2228 if (i >= EHCI_QTD_NBUFFERS) {
2229 kprintf("ehci_alloc_sqtd_chain: i=%d\n", i);
2230 goto nomem;
2231 }
2232 #endif
2233 }
2234 cur->nextqtd = next;
2235 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys;
2236 cur->qtd.qtd_status =
2237 htole32(qtdstatus | EHCI_QTD_SET_BYTES(curlen));
2238 cur->xfer = xfer;
2239 cur->len = curlen;
2240 DPRINTFN(10,("ehci_alloc_sqtd_chain: cbp=0x%08x end=0x%08x\n",
2241 dataphys, dataphys + curlen));
2242 if (iscontrol) {
2243 /*
2244 * adjust the toggle based on the number of packets
2245 * in this qtd
2246 */
2247 if (((curlen + mps - 1) / mps) & 1)
2248 qtdstatus ^= EHCI_QTD_TOGGLE_MASK;
2249 }
2250 if (len == 0)
2251 break;
2252 DPRINTFN(10,("ehci_alloc_sqtd_chain: extend chain\n"));
2253 offset += curlen;
2254 dataphys = DMAADDR(dma, offset);
2255 cur = next;
2256 }
2257 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC);
2258 *ep = cur;
2259
2260 DPRINTFN(10,("ehci_alloc_sqtd_chain: return sqtd=%p sqtdend=%p\n",
2261 *sp, *ep));
2262
2263 return (USBD_NORMAL_COMPLETION);
2264
2265 nomem:
2266 /* XXX free chain */
2267 DPRINTFN(-1,("ehci_alloc_sqtd_chain: no memory\n"));
2268 return (USBD_NOMEM);
2269 }
2270
2271 static void
2272 ehci_free_sqtd_chain(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd,
2273 ehci_soft_qtd_t *sqtdend)
2274 {
2275 ehci_soft_qtd_t *p;
2276 int i;
2277
2278 DPRINTFN(10,("ehci_free_sqtd_chain: sqtd=%p sqtdend=%p\n",
2279 sqtd, sqtdend));
2280
2281 for (i = 0; sqtd != sqtdend; sqtd = p, i++) {
2282 p = sqtd->nextqtd;
2283 ehci_free_sqtd(sc, sqtd);
2284 }
2285 }
2286
2287 /****************/
2288
2289 /*
2290 * Close a reqular pipe.
2291 * Assumes that there are no pending transactions.
2292 */
2293 void
2294 ehci_close_pipe(usbd_pipe_handle pipe, ehci_soft_qh_t *head)
2295 {
2296 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;
2297 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus;
2298 ehci_soft_qh_t *sqh = epipe->sqh;
2299
2300 crit_enter();
2301 ehci_rem_qh(sc, sqh, head);
2302 crit_exit();
2303 pipe->endpoint->savedtoggle =
2304 EHCI_QTD_GET_TOGGLE(le32toh(sqh->qh.qh_qtd.qtd_status));
2305 ehci_free_sqh(sc, epipe->sqh);
2306 epipe->sqh = NULL;
2307 }
2308
2309 /*
2310 * Abort a device request.
2311 * If this routine is called from a critical section it guarantees that the
2312 * request will be removed from the hardware scheduling and that the callback
2313 * for it will be called with USBD_CANCELLED status.
2314 * It's impossible to guarantee that the requested transfer will not
2315 * have happened since the hardware runs concurrently.
2316 * If the transaction has already happened we rely on the ordinary
2317 * interrupt processing to process it.
2318 * XXX This is most probably wrong.
2319 */
2320 void
2321 ehci_abort_xfer(usbd_xfer_handle xfer, usbd_status status)
2322 {
2323 #define exfer EXFER(xfer)
2324 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;
2325 ehci_softc_t *sc = (ehci_softc_t *)epipe->pipe.device->bus;
2326 ehci_soft_qh_t *sqh = epipe->sqh;
2327 ehci_soft_qtd_t *sqtd, *snext, **psqtd;
2328 ehci_physaddr_t cur, us, next;
2329 int hit;
2330 /* int count = 0; */
2331 ehci_soft_qh_t *psqh;
2332
2333 DPRINTF(("ehci_abort_xfer: xfer=%p pipe=%p\n", xfer, epipe));
2334
2335 if (sc->sc_dying) {
2336 /* If we're dying, just do the software part. */
2337 crit_enter();
2338 xfer->status = status; /* make software ignore it */
2339 callout_stop(&xfer->timeout_handle);
2340 usb_rem_task(epipe->pipe.device, &exfer->abort_task);
2341 usb_transfer_complete(xfer);
2342 crit_exit();
2343 return;
2344 }
2345
2346 if (xfer->device->bus->intr_context /* || !curproc REMOVED DFly */)
2347 panic("ehci_abort_xfer: not in process context");
2348
2349 /*
2350 * If an abort is already in progress then just wait for it to
2351 * complete and return.
2352 */
2353 if (exfer->ehci_xfer_flags & EHCI_XFER_ABORTING) {
2354 DPRINTFN(2, ("ehci_abort_xfer: already aborting\n"));
2355 /* No need to wait if we're aborting from a timeout. */
2356 if (status == USBD_TIMEOUT)
2357 return;
2358 /* Override the status which might be USBD_TIMEOUT. */
2359 xfer->status = status;
2360 DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n"));
2361 exfer->ehci_xfer_flags |= EHCI_XFER_ABORTWAIT;
2362 while (exfer->ehci_xfer_flags & EHCI_XFER_ABORTING)
2363 tsleep(&exfer->ehci_xfer_flags, 0, "ehciaw", 0);
2364 return;
2365 }
2366
2367 /*
2368 * Step 1: Make interrupt routine and timeouts ignore xfer.
2369 */
2370 crit_enter();
2371 exfer->ehci_xfer_flags |= EHCI_XFER_ABORTING;
2372 xfer->status = status; /* make software ignore it */
2373 callout_stop(&xfer->timeout_handle);
2374 usb_rem_task(epipe->pipe.device, &exfer->abort_task);
2375 crit_exit();
2376
2377 /*
2378 * Step 2: Wait until we know hardware has finished any possible
2379 * use of the xfer. We do this by removing the entire
2380 * queue from the async schedule and waiting for the doorbell.
2381 * Nothing else should be touching the queue now.
2382 */
2383 psqh = sqh->prev;
2384 ehci_rem_qh(sc, sqh, psqh);
2385
2386 /*
2387 * Step 3: make sure the soft interrupt routine
2388 * has run. This should remove any completed items off the queue.
2389 * The hardware has no reference to completed items (TDs).
2390 * It's safe to remove them at any time.
2391 */
2392 crit_enter();
2393 #ifdef USB_USE_SOFTINTR
2394 sc->sc_softwake = 1;
2395 #endif /* USB_USE_SOFTINTR */
2396 usb_schedsoftintr(&sc->sc_bus);
2397 #ifdef USB_USE_SOFTINTR
2398 tsleep(&sc->sc_softwake, 0, "ehciab", 0);
2399 #endif /* USB_USE_SOFTINTR */
2400
2401 /*
2402 * Step 4: Remove any vestiges of the xfer from the hardware.
2403 * The complication here is that the hardware may have executed
2404 * into or even beyond the xfer we're trying to abort.
2405 * So as we're scanning the TDs of this xfer we check if
2406 * the hardware points to any of them.
2407 *
2408 * first we need to see if there are any transfers
2409 * on this queue before the xfer we are aborting.. we need
2410 * to update any pointers that point to us to point past
2411 * the aborting xfer. (If there is something past us).
2412 * Hardware and software.
2413 */
2414 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd));
2415 hit = 0;
2416
2417 /* If they initially point here. */
2418 us = exfer->sqtdstart->physaddr;
2419
2420 /* We will change them to point here */
2421 snext = exfer->sqtdend->nextqtd;
2422 next = snext ? htole32(snext->physaddr) : EHCI_NULL;
2423
2424 /*
2425 * Now loop through any qTDs before us and keep track of the pointer
2426 * that points to us for the end.
2427 */
2428 psqtd = &sqh->sqtd;
2429 sqtd = sqh->sqtd;
2430 while (sqtd && sqtd != exfer->sqtdstart) {
2431 hit |= (cur == sqtd->physaddr);
2432 if (EHCI_LINK_ADDR(le32toh(sqtd->qtd.qtd_next)) == us)
2433 sqtd->qtd.qtd_next = next;
2434 if (EHCI_LINK_ADDR(le32toh(sqtd->qtd.qtd_altnext)) == us)
2435 sqtd->qtd.qtd_altnext = next;
2436 psqtd = &sqtd->nextqtd;
2437 sqtd = sqtd->nextqtd;
2438 }
2439 /* make the software pointer bypass us too */
2440 *psqtd = exfer->sqtdend->nextqtd;
2441
2442 /*
2443 * If we already saw the active one then we are pretty much done.
2444 * We've done all the relinking we need to do.
2445 */
2446 if (!hit) {
2447
2448 /*
2449 * Now reinitialise the QH to point to the next qTD
2450 * (if there is one). We only need to do this if
2451 * it was previously pointing to us.
2452 */
2453 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) {
2454 if (cur == sqtd->physaddr) {
2455 hit++;
2456 }
2457 if (sqtd == exfer->sqtdend)
2458 break;
2459 }
2460 sqtd = sqtd->nextqtd;
2461 /*
2462 * Only need to alter the QH if it was pointing at a qTD
2463 * that we are removing.
2464 */
2465 if (hit) {
2466 if (snext) {
2467 ehci_set_qh_qtd(sqh, snext);
2468 } else {
2469
2470 sqh->qh.qh_curqtd = 0; /* unlink qTDs */
2471 sqh->qh.qh_qtd.qtd_status &=
2472 htole32(EHCI_QTD_TOGGLE_MASK);
2473 sqh->qh.qh_qtd.qtd_next =
2474 sqh->qh.qh_qtd.qtd_altnext
2475 = EHCI_NULL;
2476 DPRINTFN(1,("ehci_abort_xfer: no hit\n"));
2477 }
2478 }
2479 }
2480 ehci_add_qh(sqh, psqh);
2481 /*
2482 * Step 5: Execute callback.
2483 */
2484 #ifdef DIAGNOSTIC
2485 exfer->isdone = 1;
2486 #endif
2487 /* Do the wakeup first to avoid touching the xfer after the callback. */
2488 exfer->ehci_xfer_flags &= ~EHCI_XFER_ABORTING;
2489 if (exfer->ehci_xfer_flags & EHCI_XFER_ABORTWAIT) {
2490 exfer->ehci_xfer_flags &= ~EHCI_XFER_ABORTWAIT;
2491 wakeup(&exfer->ehci_xfer_flags);
2492 }
2493 usb_transfer_complete(xfer);
2494
2495 /* kprintf("%s: %d TDs aborted\n", __func__, count); */
2496 crit_exit();
2497 #undef exfer
2498 }
2499
2500 void
2501 ehci_timeout(void *addr)
2502 {
2503 struct ehci_xfer *exfer = addr;
2504 struct ehci_pipe *epipe = (struct ehci_pipe *)exfer->xfer.pipe;
2505 ehci_softc_t *sc = (ehci_softc_t *)epipe->pipe.device->bus;
2506
2507 DPRINTF(("ehci_timeout: exfer=%p\n", exfer));
2508 #ifdef USB_DEBUG
2509 if (ehcidebug > 1)
2510 usbd_dump_pipe(exfer->xfer.pipe);
2511 #endif
2512
2513 if (sc->sc_dying) {
2514 ehci_abort_xfer(&exfer->xfer, USBD_TIMEOUT);
2515 return;
2516 }
2517
2518 /* Execute the abort in a process context. */
2519 usb_add_task(exfer->xfer.pipe->device, &exfer->abort_task,
2520 USB_TASKQ_HC);
2521 }
2522
2523 void
2524 ehci_timeout_task(void *addr)
2525 {
2526 usbd_xfer_handle xfer = addr;
2527
2528 DPRINTF(("ehci_timeout_task: xfer=%p\n", xfer));
2529 crit_enter();
2530 ehci_abort_xfer(xfer, USBD_TIMEOUT);
2531 crit_exit();
2532 }
2533
2534 /*
2535 * Some EHCI chips from VIA / ATI seem to trigger interrupts before writing
2536 * back the qTD status, or miss signalling occasionally under heavy load.
2537 * If the host machine is too fast, we can miss transaction completion - when
2538 * we scan the active list the transaction still seems to be active. This
2539 * generally exhibits itself as a umass stall that never recovers.
2540 *
2541 * We work around this behaviour by setting up this callback after any softintr
2542 * that completes with transactions still pending, giving us another chance to
2543 * check for completion after the writeback has taken place.
2544 */
2545 void
2546 ehci_intrlist_timeout(void *arg)
2547 {
2548 ehci_softc_t *sc = arg;
2549
2550 DPRINTFN(3, ("ehci_intrlist_timeout\n"));
2551 usb_schedsoftintr(&sc->sc_bus);
2552 }
2553
2554 /************************/
2555
2556 static usbd_status
2557 ehci_device_ctrl_transfer(usbd_xfer_handle xfer)
2558 {
2559 usbd_status err;
2560
2561 /* Insert last in queue. */
2562 err = usb_insert_transfer(xfer);
2563 if (err)
2564 return (err);
2565
2566 /* Pipe isn't running, start first */
2567 return (ehci_device_ctrl_start(STAILQ_FIRST(&xfer->pipe->queue)));
2568 }
2569
2570 static usbd_status
2571 ehci_device_ctrl_start(usbd_xfer_handle xfer)
2572 {
2573 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus;
2574 usbd_status err;
2575
2576 if (sc->sc_dying)
2577 return (USBD_IOERROR);
2578
2579 #ifdef DIAGNOSTIC
2580 if (!(xfer->rqflags & URQ_REQUEST)) {
2581 /* XXX panic */
2582 kprintf("ehci_device_ctrl_transfer: not a request\n");
2583 return (USBD_INVAL);
2584 }
2585 #endif
2586
2587 err = ehci_device_request(xfer);
2588 if (err)
2589 return (err);
2590
2591 if (sc->sc_bus.use_polling)
2592 ehci_waitintr(sc, xfer);
2593 return (USBD_IN_PROGRESS);
2594 }
2595
2596 void
2597 ehci_device_ctrl_done(usbd_xfer_handle xfer)
2598 {
2599 struct ehci_xfer *ex = EXFER(xfer);
2600 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus;
2601 /*struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;*/
2602
2603 DPRINTFN(10,("ehci_ctrl_done: xfer=%p\n", xfer));
2604
2605 #ifdef DIAGNOSTIC
2606 if (!(xfer->rqflags & URQ_REQUEST)) {
2607 panic("ehci_ctrl_done: not a request");
2608 }
2609 #endif
2610
2611 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) {
2612 ehci_del_intr_list(ex); /* remove from active list */
2613 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL);
2614 }
2615
2616 DPRINTFN(5, ("ehci_ctrl_done: length=%d\n", xfer->actlen));
2617 }
2618
2619 /* Abort a device control request. */
2620 static void
2621 ehci_device_ctrl_abort(usbd_xfer_handle xfer)
2622 {
2623 DPRINTF(("ehci_device_ctrl_abort: xfer=%p\n", xfer));
2624 ehci_abort_xfer(xfer, USBD_CANCELLED);
2625 }
2626
2627 /* Close a device control pipe. */
2628 static void
2629 ehci_device_ctrl_close(usbd_pipe_handle pipe)
2630 {
2631 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus;
2632 /*struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;*/
2633
2634 DPRINTF(("ehci_device_ctrl_close: pipe=%p\n", pipe));
2635 ehci_close_pipe(pipe, sc->sc_async_head);
2636 }
2637
2638 usbd_status
2639 ehci_device_request(usbd_xfer_handle xfer)
2640 {
2641 #define exfer EXFER(xfer)
2642 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;
2643 usb_device_request_t *req = &xfer->request;
2644 usbd_device_handle dev = epipe->pipe.device;
2645 ehci_softc_t *sc = (ehci_softc_t *)dev->bus;
2646 ehci_soft_qtd_t *setup, *stat, *next;
2647 ehci_soft_qh_t *sqh;
2648 int isread;
2649 int len;
2650 int addr = dev->address;
2651 usbd_status err;
2652
2653 isread = req->bmRequestType & UT_READ;
2654 len = UGETW(req->wLength);
2655
2656 DPRINTFN(3,("ehci_device_request: type=0x%02x, request=0x%02x, "
2657 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n",
2658 req->bmRequestType, req->bRequest, UGETW(req->wValue),
2659 UGETW(req->wIndex), len, dev->address,
2660 epipe->pipe.endpoint->edesc->bEndpointAddress));
2661
2662 setup = ehci_alloc_sqtd(sc);
2663 if (setup == NULL) {
2664 err = USBD_NOMEM;
2665 goto bad1;
2666 }
2667 stat = ehci_alloc_sqtd(sc);
2668 if (stat == NULL) {
2669 err = USBD_NOMEM;
2670 goto bad2;
2671 }
2672
2673 sqh = epipe->sqh;
2674 epipe->u.ctl.length = len;
2675
2676 #if 1
2677 /* Update device address and length since they may have changed
2678 during the setup of the control pipe in usbd_new_device(). */
2679 /* XXX This only needs to be done once, but it's too early in open. */
2680 /* XXXX Should not touch ED here! */
2681 sqh->qh.qh_endp =
2682 (sqh->qh.qh_endp & htole32(~(EHCI_QH_ADDRMASK | EHCI_QH_MPLMASK))) |
2683 htole32(
2684 EHCI_QH_SET_ADDR(addr) |
2685 EHCI_QH_SET_MPL(UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize))
2686 );
2687 #endif
2688
2689 /* Set up data transaction */
2690 if (len != 0) {
2691 ehci_soft_qtd_t *end;
2692
2693 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer,
2694 &next, &end);
2695 if (err)
2696 goto bad3;
2697 end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC);
2698 end->nextqtd = stat;
2699 end->qtd.qtd_next =
2700 end->qtd.qtd_altnext = htole32(stat->physaddr);
2701 } else {
2702 next = stat;
2703 }
2704
2705 memcpy(KERNADDR(&epipe->u.ctl.reqdma, 0), req, sizeof *req);
2706
2707 /* Clear toggle */
2708 setup->qtd.qtd_status = htole32(
2709 EHCI_QTD_ACTIVE |
2710 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) |
2711 EHCI_QTD_SET_CERR(3) |
2712 EHCI_QTD_SET_TOGGLE(0) |
2713 EHCI_QTD_SET_BYTES(sizeof *req)
2714 );
2715 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma, 0));
2716 setup->qtd.qtd_buffer_hi[0] = 0;
2717 setup->nextqtd = next;
2718 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr);
2719 setup->xfer = xfer;
2720 setup->len = sizeof *req;
2721
2722 stat->qtd.qtd_status = htole32(
2723 EHCI_QTD_ACTIVE |
2724 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) |
2725 EHCI_QTD_SET_CERR(3) |
2726 EHCI_QTD_SET_TOGGLE(1) |
2727 EHCI_QTD_IOC
2728 );
2729 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */
2730 stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */
2731 stat->nextqtd = NULL;
2732 stat->qtd.qtd_next = stat->qtd.qtd_altnext = EHCI_NULL;
2733 stat->xfer = xfer;
2734 stat->len = 0;
2735
2736 #ifdef EHCI_DEBUG
2737 if (ehcidebug > 5) {
2738 DPRINTF(("ehci_device_request:\n"));
2739 ehci_dump_sqh(sqh);
2740 ehci_dump_sqtds(setup);
2741 }
2742 #endif
2743
2744 exfer->sqtdstart = setup;
2745 exfer->sqtdend = stat;
2746 #ifdef DIAGNOSTIC
2747 if (!exfer->isdone) {
2748 kprintf("ehci_device_request: not done, exfer=%p\n", exfer);
2749 }
2750 exfer->isdone = 0;
2751 #endif
2752
2753 /* Insert qTD in QH list. */
2754 crit_enter();
2755 ehci_set_qh_qtd(sqh, setup);
2756 if (xfer->timeout && !sc->sc_bus.use_polling) {
2757 callout_reset(&xfer->timeout_handle, MS_TO_TICKS(xfer->timeout),
2758 ehci_timeout, xfer);
2759 }
2760 ehci_add_intr_list(sc, exfer);
2761 xfer->status = USBD_IN_PROGRESS;
2762 crit_exit();
2763
2764 #ifdef EHCI_DEBUG
2765 if (ehcidebug > 10) {
2766 DPRINTF(("ehci_device_request: status=%x\n",
2767 EOREAD4(sc, EHCI_USBSTS)));
2768 DELAY(10000);
2769 ehci_dump_regs(sc);
2770 ehci_dump_sqh(sc->sc_async_head);
2771 ehci_dump_sqh(sqh);
2772 ehci_dump_sqtds(setup);
2773 }
2774 #endif
2775
2776 return (USBD_NORMAL_COMPLETION);
2777
2778 bad3:
2779 ehci_free_sqtd(sc, stat);
2780 bad2:
2781 ehci_free_sqtd(sc, setup);
2782 bad1:
2783 DPRINTFN(-1,("ehci_device_request: no memory\n"));
2784 xfer->status = err;
2785 usb_transfer_complete(xfer);
2786 return (err);
2787 #undef exfer
2788 }
2789
2790 /************************/
2791
2792 static usbd_status
2793 ehci_device_bulk_transfer(usbd_xfer_handle xfer)
2794 {
2795 usbd_status err;
2796
2797 /* Insert last in queue. */
2798 err = usb_insert_transfer(xfer);
2799 if (err)
2800 return (err);
2801
2802 /* Pipe isn't running, start first */
2803 return (ehci_device_bulk_start(STAILQ_FIRST(&xfer->pipe->queue)));
2804 }
2805
2806 usbd_status
2807 ehci_device_bulk_start(usbd_xfer_handle xfer)
2808 {
2809 #define exfer EXFER(xfer)
2810 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;
2811 usbd_device_handle dev = epipe->pipe.device;
2812 ehci_softc_t *sc = (ehci_softc_t *)dev->bus;
2813 ehci_soft_qtd_t *data, *dataend;
2814 ehci_soft_qh_t *sqh;
2815 usbd_status err;
2816 int len, isread, endpt;
2817
2818 DPRINTFN(2, ("ehci_device_bulk_start: xfer=%p len=%d flags=%d\n",
2819 xfer, xfer->length, xfer->flags));
2820
2821 if (sc->sc_dying)
2822 return (USBD_IOERROR);
2823
2824 #ifdef DIAGNOSTIC
2825 if (xfer->rqflags & URQ_REQUEST)
2826 panic("ehci_device_bulk_start: a request");
2827 #endif
2828
2829 len = xfer->length;
2830 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress;
2831 isread = UE_GET_DIR(endpt) == UE_DIR_IN;
2832 sqh = epipe->sqh;
2833
2834 epipe->u.bulk.length = len;
2835
2836 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data,
2837 &dataend);
2838 if (err) {
2839 DPRINTFN(-1,("ehci_device_bulk_start: no memory\n"));
2840 xfer->status = err;
2841 usb_transfer_complete(xfer);
2842 return (err);
2843 }
2844
2845 #ifdef EHCI_DEBUG
2846 if (ehcidebug > 5) {
2847 DPRINTF(("ehci_device_bulk_start: data(1)\n"));
2848 ehci_dump_sqh(sqh);
2849 ehci_dump_sqtds(data);
2850 }
2851 #endif
2852
2853 /* Set up interrupt info. */
2854 exfer->sqtdstart = data;
2855 exfer->sqtdend = dataend;
2856 #ifdef DIAGNOSTIC
2857 if (!exfer->isdone) {
2858 kprintf("ehci_device_bulk_start: not done, ex=%p\n", exfer);
2859 }
2860 exfer->isdone = 0;
2861 #endif
2862
2863 crit_enter();
2864 ehci_set_qh_qtd(sqh, data);
2865 if (xfer->timeout && !sc->sc_bus.use_polling) {
2866 callout_reset(&xfer->timeout_handle, MS_TO_TICKS(xfer->timeout),
2867 ehci_timeout, xfer);
2868 }
2869 ehci_add_intr_list(sc, exfer);
2870 xfer->status = USBD_IN_PROGRESS;
2871 crit_exit();
2872
2873 #ifdef EHCI_DEBUG
2874 if (ehcidebug > 10) {
2875 DPRINTF(("ehci_device_bulk_start: data(2)\n"));
2876 DELAY(10000);
2877 DPRINTF(("ehci_device_bulk_start: data(3)\n"));
2878 ehci_dump_regs(sc);
2879 #if 0
2880 kprintf("async_head:\n");
2881 ehci_dump_sqh(sc->sc_async_head);
2882 #endif
2883 kprintf("sqh:\n");
2884 ehci_dump_sqh(sqh);
2885 ehci_dump_sqtds(data);
2886 }
2887 #endif
2888
2889 if (sc->sc_bus.use_polling)
2890 ehci_waitintr(sc, xfer);
2891
2892 return (USBD_IN_PROGRESS);
2893 #undef exfer
2894 }
2895
2896 static void
2897 ehci_device_bulk_abort(usbd_xfer_handle xfer)
2898 {
2899 DPRINTF(("ehci_device_bulk_abort: xfer=%p\n", xfer));
2900 ehci_abort_xfer(xfer, USBD_CANCELLED);
2901 }
2902
2903 /*
2904 * Close a device bulk pipe.
2905 */
2906 static void
2907 ehci_device_bulk_close(usbd_pipe_handle pipe)
2908 {
2909 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus;
2910
2911 DPRINTF(("ehci_device_bulk_close: pipe=%p\n", pipe));
2912 ehci_close_pipe(pipe, sc->sc_async_head);
2913 }
2914
2915 void
2916 ehci_device_bulk_done(usbd_xfer_handle xfer)
2917 {
2918 struct ehci_xfer *ex = EXFER(xfer);
2919 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus;
2920 /*struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;*/
2921
2922 DPRINTFN(10,("ehci_bulk_done: xfer=%p, actlen=%d\n",
2923 xfer, xfer->actlen));
2924
2925 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) {
2926 ehci_del_intr_list(ex); /* remove from active list */
2927 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL);
2928 }
2929
2930 DPRINTFN(5, ("ehci_bulk_done: length=%d\n", xfer->actlen));
2931 }
2932
2933 /************************/
2934
2935 static usbd_status
2936 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival)
2937 {
2938 struct ehci_soft_islot *isp;
2939 int islot, lev;
2940
2941 /* Find a poll rate that is large enough. */
2942 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--)
2943 if (EHCI_ILEV_IVAL(lev) <= ival)
2944 break;
2945
2946 /* Pick an interrupt slot at the right level. */
2947 /* XXX could do better than picking at random. */
2948 islot = EHCI_IQHIDX(lev, karc4random());
2949
2950 sqh->islot = islot;
2951 isp = &sc->sc_islots[islot];
2952 ehci_add_qh(sqh, isp->sqh);
2953
2954 return (USBD_NORMAL_COMPLETION);
2955 }
2956
2957 static usbd_status
2958 ehci_device_intr_transfer(usbd_xfer_handle xfer)
2959 {
2960 usbd_status err;
2961
2962 /* Insert last in queue. */
2963 err = usb_insert_transfer(xfer);
2964 if (err)
2965 return (err);
2966
2967 /*
2968 * Pipe isn't running (otherwise err would be USBD_INPROG),
2969 * so start it first.
2970 */
2971 return (ehci_device_intr_start(STAILQ_FIRST(&xfer->pipe->queue)));
2972 }
2973
2974 static usbd_status
2975 ehci_device_intr_start(usbd_xfer_handle xfer)
2976 {
2977 #define exfer EXFER(xfer)
2978 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;
2979 usbd_device_handle dev = xfer->pipe->device;
2980 ehci_softc_t *sc = (ehci_softc_t *)dev->bus;
2981 ehci_soft_qtd_t *data, *dataend;
2982 ehci_soft_qh_t *sqh;
2983 usbd_status err;
2984 int len, isread, endpt;
2985
2986 DPRINTFN(2, ("ehci_device_intr_start: xfer=%p len=%d flags=%d\n",
2987 xfer, xfer->length, xfer->flags));
2988
2989 if (sc->sc_dying)
2990 return (USBD_IOERROR);
2991
2992 #ifdef DIAGNOSTIC
2993 if (xfer->rqflags & URQ_REQUEST)
2994 panic("ehci_device_intr_start: a request");
2995 #endif
2996
2997 len = xfer->length;
2998 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress;
2999 isread = UE_GET_DIR(endpt) == UE_DIR_IN;
3000 sqh = epipe->sqh;
3001
3002 epipe->u.intr.length = len;
3003
3004 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data,
3005 &dataend);
3006 if (err) {
3007 DPRINTFN(-1, ("ehci_device_intr_start: no memory\n"));
3008 xfer->status = err;
3009 usb_transfer_complete(xfer);
3010 return (err);
3011 }
3012
3013 #ifdef EHCI_DEBUG
3014 if (ehcidebug > 5) {
3015 DPRINTF(("ehci_device_intr_start: data(1)\n"));
3016 ehci_dump_sqh(sqh);
3017 ehci_dump_sqtds(data);
3018 }
3019 #endif
3020
3021 /* Set up interrupt info. */
3022 exfer->sqtdstart = data;
3023 exfer->sqtdend = dataend;
3024 #ifdef DIAGNOSTIC
3025 if (!exfer->isdone) {
3026 kprintf("ehci_device_intr_start: not done, ex=%p\n", exfer);
3027 }
3028 exfer->isdone = 0;
3029 #endif
3030
3031 crit_enter();
3032 ehci_set_qh_qtd(sqh, data);
3033 if (xfer->timeout && !sc->sc_bus.use_polling) {
3034 callout_reset(&xfer->timeout_handle, MS_TO_TICKS(xfer->timeout),
3035 ehci_timeout, xfer);
3036 }
3037 ehci_add_intr_list(sc, exfer);
3038 xfer->status = USBD_IN_PROGRESS;
3039 crit_exit();
3040
3041 #ifdef EHCI_DEBUG
3042 if (ehcidebug > 10) {
3043 DPRINTF(("ehci_device_intr_start: data(2)\n"));
3044 DELAY(10000);
3045 DPRINTF(("ehci_device_intr_start: data(3)\n"));
3046 ehci_dump_regs(sc);
3047 kprintf("sqh:\n");
3048 ehci_dump_sqh(sqh);
3049 ehci_dump_sqtds(data);
3050 }
3051 #endif
3052
3053 if (sc->sc_bus.use_polling)
3054 ehci_waitintr(sc, xfer);
3055
3056 return (USBD_IN_PROGRESS);
3057 #undef exfer
3058 }
3059
3060 static void
3061 ehci_device_intr_abort(usbd_xfer_handle xfer)
3062 {
3063 DPRINTFN(1, ("ehci_device_intr_abort: xfer=%p\n", xfer));
3064 if (xfer->pipe->intrxfer == xfer) {
3065 DPRINTFN(1, ("ehci_device_intr_abort: remove\n"));
3066 xfer->pipe->intrxfer = NULL;
3067 }
3068 ehci_abort_xfer(xfer, USBD_CANCELLED);
3069 }
3070
3071 static void
3072 ehci_device_intr_close(usbd_pipe_handle pipe)
3073 {
3074 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus;
3075 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;
3076 struct ehci_soft_islot *isp;
3077
3078 isp = &sc->sc_islots[epipe->sqh->islot];
3079 ehci_close_pipe(pipe, isp->sqh);
3080 }
3081
3082 static void
3083 ehci_device_intr_done(usbd_xfer_handle xfer)
3084 {
3085 #define exfer EXFER(xfer)
3086 struct ehci_xfer *ex = EXFER(xfer);
3087 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus;
3088 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;
3089 ehci_soft_qtd_t *data, *dataend;
3090 ehci_soft_qh_t *sqh;
3091 usbd_status err;
3092 int len, isread, endpt;
3093
3094 DPRINTFN(10, ("ehci_device_intr_done: xfer=%p, actlen=%d\n",
3095 xfer, xfer->actlen));
3096
3097 if (xfer->pipe->repeat) {
3098 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL);
3099
3100 len = epipe->u.intr.length;
3101 xfer->length = len;
3102 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress;
3103 isread = UE_GET_DIR(endpt) == UE_DIR_IN;
3104 sqh = epipe->sqh;
3105
3106 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer,
3107 &data, &dataend);
3108 if (err) {
3109 DPRINTFN(-1, ("ehci_device_intr_done: no memory\n"));
3110 xfer->status = err;
3111 return;
3112 }
3113
3114 /* Set up interrupt info. */
3115 exfer->sqtdstart = data;
3116 exfer->sqtdend = dataend;
3117 #ifdef DIAGNOSTIC
3118 if (!exfer->isdone) {
3119 kprintf("ehci_device_intr_done: not done, ex=%p\n",
3120 exfer);
3121 }
3122 exfer->isdone = 0;
3123 #endif
3124
3125 crit_enter();
3126 ehci_set_qh_qtd(sqh, data);
3127 if (xfer->timeout && !sc->sc_bus.use_polling) {
3128 callout_reset(&xfer->timeout_handle,
3129 MS_TO_TICKS(xfer->timeout), ehci_timeout, xfer);
3130 }
3131 crit_exit();
3132
3133 xfer->status = USBD_IN_PROGRESS;
3134 } else if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) {
3135 ehci_del_intr_list(ex); /* remove from active list */
3136 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL);
3137 }
3138 #undef exfer
3139 }
3140
3141 /************************/
3142
3143 static usbd_status
3144 ehci_device_isoc_transfer(usbd_xfer_handle xfer)
3145 {
3146 return USBD_IOERROR;
3147 }
3148
3149 static usbd_status
3150 ehci_device_isoc_start(usbd_xfer_handle xfer)
3151 {
3152 return USBD_IOERROR;
3153 }
3154
3155 static void
3156 ehci_device_isoc_abort(usbd_xfer_handle xfer)
3157 {
3158 }
3159
3160 static void
3161 ehci_device_isoc_close(usbd_pipe_handle pipe)
3162 {
3163 }
3164
3165 static void
3166 ehci_device_isoc_done(usbd_xfer_handle xfer)
3167 {
3168 }
DragonFly BSD