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Use same naming convention as other host controller stats
[dragonfly.git] / sys / dev / netif / bce / if_bce.c
blobcdbaef06d3d7e88908011fc66626ed4be42d93b3
1 /*-
2 * Copyright (c) 2006-2007 Broadcom Corporation
3 * David Christensen <davidch@broadcom.com>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. Neither the name of Broadcom Corporation nor the name of its contributors
15 * may be used to endorse or promote products derived from this software
16 * without specific prior written consent.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
28 * THE POSSIBILITY OF SUCH DAMAGE.
29 *
30 * $FreeBSD: src/sys/dev/bce/if_bce.c,v 1.31 2007/05/16 23:34:11 davidch Exp $
31 * $DragonFly: src/sys/dev/netif/bce/if_bce.c,v 1.12 2008/05/31 11:18:09 sephe Exp $
32 */
33
34 /*
35 * The following controllers are supported by this driver:
36 * BCM5706C A2, A3
37 * BCM5708C B1, B2
38 *
39 * The following controllers are not supported by this driver:
40 * BCM5706C A0, A1
41 * BCM5706S A0, A1, A2, A3
42 * BCM5708C A0, B0
43 * BCM5708S A0, B0, B1, B2
44 */
45
46 #include "opt_bce.h"
47 #include "opt_polling.h"
48
49 #include <sys/param.h>
50 #include <sys/bus.h>
51 #include <sys/endian.h>
52 #include <sys/kernel.h>
53 #include <sys/interrupt.h>
54 #include <sys/mbuf.h>
55 #include <sys/malloc.h>
56 #include <sys/queue.h>
57 #ifdef BCE_DEBUG
58 #include <sys/random.h>
59 #endif
60 #include <sys/rman.h>
61 #include <sys/serialize.h>
62 #include <sys/socket.h>
63 #include <sys/sockio.h>
64 #include <sys/sysctl.h>
65
66 #include <net/bpf.h>
67 #include <net/ethernet.h>
68 #include <net/if.h>
69 #include <net/if_arp.h>
70 #include <net/if_dl.h>
71 #include <net/if_media.h>
72 #include <net/if_types.h>
73 #include <net/ifq_var.h>
74 #include <net/vlan/if_vlan_var.h>
75 #include <net/vlan/if_vlan_ether.h>
76
77 #include <dev/netif/mii_layer/mii.h>
78 #include <dev/netif/mii_layer/miivar.h>
79
80 #include <bus/pci/pcireg.h>
81 #include <bus/pci/pcivar.h>
82
83 #include "miibus_if.h"
84
85 #include <dev/netif/bce/if_bcereg.h>
86 #include <dev/netif/bce/if_bcefw.h>
87
88 /****************************************************************************/
89 /* BCE Debug Options */
90 /****************************************************************************/
91 #ifdef BCE_DEBUG
92
93 static uint32_t bce_debug = BCE_WARN;
94
95 /*
96 * 0 = Never
97 * 1 = 1 in 2,147,483,648
98 * 256 = 1 in 8,388,608
99 * 2048 = 1 in 1,048,576
100 * 65536 = 1 in 32,768
101 * 1048576 = 1 in 2,048
102 * 268435456 = 1 in 8
103 * 536870912 = 1 in 4
104 * 1073741824 = 1 in 2
105 *
106 * bce_debug_l2fhdr_status_check:
107 * How often the l2_fhdr frame error check will fail.
108 *
109 * bce_debug_unexpected_attention:
110 * How often the unexpected attention check will fail.
111 *
112 * bce_debug_mbuf_allocation_failure:
113 * How often to simulate an mbuf allocation failure.
114 *
115 * bce_debug_dma_map_addr_failure:
116 * How often to simulate a DMA mapping failure.
117 *
118 * bce_debug_bootcode_running_failure:
119 * How often to simulate a bootcode failure.
120 */
121 static int bce_debug_l2fhdr_status_check = 0;
122 static int bce_debug_unexpected_attention = 0;
123 static int bce_debug_mbuf_allocation_failure = 0;
124 static int bce_debug_dma_map_addr_failure = 0;
125 static int bce_debug_bootcode_running_failure = 0;
126
127 #endif /* BCE_DEBUG */
128
129
130 /****************************************************************************/
131 /* PCI Device ID Table */
132 /* */
133 /* Used by bce_probe() to identify the devices supported by this driver. */
134 /****************************************************************************/
135 #define BCE_DEVDESC_MAX 64
136
137 static struct bce_type bce_devs[] = {
138 /* BCM5706C Controllers and OEM boards. */
139 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3101,
140 "HP NC370T Multifunction Gigabit Server Adapter" },
141 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3106,
142 "HP NC370i Multifunction Gigabit Server Adapter" },
143 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, PCI_ANY_ID, PCI_ANY_ID,
144 "Broadcom NetXtreme II BCM5706 1000Base-T" },
145
146 /* BCM5706S controllers and OEM boards. */
147 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102,
148 "HP NC370F Multifunction Gigabit Server Adapter" },
149 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID, PCI_ANY_ID,
150 "Broadcom NetXtreme II BCM5706 1000Base-SX" },
151
152 /* BCM5708C controllers and OEM boards. */
153 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, PCI_ANY_ID, PCI_ANY_ID,
154 "Broadcom NetXtreme II BCM5708 1000Base-T" },
155
156 /* BCM5708S controllers and OEM boards. */
157 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, PCI_ANY_ID, PCI_ANY_ID,
158 "Broadcom NetXtreme II BCM5708S 1000Base-T" },
159 { 0, 0, 0, 0, NULL }
160 };
161
162
163 /****************************************************************************/
164 /* Supported Flash NVRAM device data. */
165 /****************************************************************************/
166 static const struct flash_spec flash_table[] =
167 {
168 /* Slow EEPROM */
169 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
170 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
171 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
172 "EEPROM - slow"},
173 /* Expansion entry 0001 */
174 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
175 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
176 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
177 "Entry 0001"},
178 /* Saifun SA25F010 (non-buffered flash) */
179 /* strap, cfg1, & write1 need updates */
180 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
181 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
182 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
183 "Non-buffered flash (128kB)"},
184 /* Saifun SA25F020 (non-buffered flash) */
185 /* strap, cfg1, & write1 need updates */
186 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
187 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
188 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
189 "Non-buffered flash (256kB)"},
190 /* Expansion entry 0100 */
191 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
192 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
193 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
194 "Entry 0100"},
195 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
196 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
197 0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
198 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
199 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
200 /* Entry 0110: ST M45PE20 (non-buffered flash)*/
201 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
202 0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
203 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
204 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
205 /* Saifun SA25F005 (non-buffered flash) */
206 /* strap, cfg1, & write1 need updates */
207 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
208 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
209 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
210 "Non-buffered flash (64kB)"},
211 /* Fast EEPROM */
212 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
213 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
214 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
215 "EEPROM - fast"},
216 /* Expansion entry 1001 */
217 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
218 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
219 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
220 "Entry 1001"},
221 /* Expansion entry 1010 */
222 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
223 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
224 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
225 "Entry 1010"},
226 /* ATMEL AT45DB011B (buffered flash) */
227 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
228 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
229 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
230 "Buffered flash (128kB)"},
231 /* Expansion entry 1100 */
232 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
233 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
234 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
235 "Entry 1100"},
236 /* Expansion entry 1101 */
237 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
238 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
239 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
240 "Entry 1101"},
241 /* Ateml Expansion entry 1110 */
242 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
243 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
244 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
245 "Entry 1110 (Atmel)"},
246 /* ATMEL AT45DB021B (buffered flash) */
247 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
248 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
249 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
250 "Buffered flash (256kB)"},
251 };
252
253
254 /****************************************************************************/
255 /* DragonFly device entry points. */
256 /****************************************************************************/
257 static int bce_probe(device_t);
258 static int bce_attach(device_t);
259 static int bce_detach(device_t);
260 static void bce_shutdown(device_t);
261
262 /****************************************************************************/
263 /* BCE Debug Data Structure Dump Routines */
264 /****************************************************************************/
265 #ifdef BCE_DEBUG
266 static void bce_dump_mbuf(struct bce_softc *, struct mbuf *);
267 static void bce_dump_tx_mbuf_chain(struct bce_softc *, int, int);
268 static void bce_dump_rx_mbuf_chain(struct bce_softc *, int, int);
269 static void bce_dump_txbd(struct bce_softc *, int, struct tx_bd *);
270 static void bce_dump_rxbd(struct bce_softc *, int, struct rx_bd *);
271 static void bce_dump_l2fhdr(struct bce_softc *, int,
272 struct l2_fhdr *) __unused;
273 static void bce_dump_tx_chain(struct bce_softc *, int, int);
274 static void bce_dump_rx_chain(struct bce_softc *, int, int);
275 static void bce_dump_status_block(struct bce_softc *);
276 static void bce_dump_driver_state(struct bce_softc *);
277 static void bce_dump_stats_block(struct bce_softc *) __unused;
278 static void bce_dump_hw_state(struct bce_softc *);
279 static void bce_dump_txp_state(struct bce_softc *);
280 static void bce_dump_rxp_state(struct bce_softc *) __unused;
281 static void bce_dump_tpat_state(struct bce_softc *) __unused;
282 static void bce_freeze_controller(struct bce_softc *) __unused;
283 static void bce_unfreeze_controller(struct bce_softc *) __unused;
284 static void bce_breakpoint(struct bce_softc *);
285 #endif /* BCE_DEBUG */
286
287
288 /****************************************************************************/
289 /* BCE Register/Memory Access Routines */
290 /****************************************************************************/
291 static uint32_t bce_reg_rd_ind(struct bce_softc *, uint32_t);
292 static void bce_reg_wr_ind(struct bce_softc *, uint32_t, uint32_t);
293 static void bce_ctx_wr(struct bce_softc *, uint32_t, uint32_t, uint32_t);
294 static int bce_miibus_read_reg(device_t, int, int);
295 static int bce_miibus_write_reg(device_t, int, int, int);
296 static void bce_miibus_statchg(device_t);
297
298
299 /****************************************************************************/
300 /* BCE NVRAM Access Routines */
301 /****************************************************************************/
302 static int bce_acquire_nvram_lock(struct bce_softc *);
303 static int bce_release_nvram_lock(struct bce_softc *);
304 static void bce_enable_nvram_access(struct bce_softc *);
305 static void bce_disable_nvram_access(struct bce_softc *);
306 static int bce_nvram_read_dword(struct bce_softc *, uint32_t, uint8_t *,
307 uint32_t);
308 static int bce_init_nvram(struct bce_softc *);
309 static int bce_nvram_read(struct bce_softc *, uint32_t, uint8_t *, int);
310 static int bce_nvram_test(struct bce_softc *);
311 #ifdef BCE_NVRAM_WRITE_SUPPORT
312 static int bce_enable_nvram_write(struct bce_softc *);
313 static void bce_disable_nvram_write(struct bce_softc *);
314 static int bce_nvram_erase_page(struct bce_softc *, uint32_t);
315 static int bce_nvram_write_dword(struct bce_softc *, uint32_t, uint8_t *, uint32_t);
316 static int bce_nvram_write(struct bce_softc *, uint32_t, uint8_t *,
317 int) __unused;
318 #endif
319
320 /****************************************************************************/
321 /* BCE DMA Allocate/Free Routines */
322 /****************************************************************************/
323 static int bce_dma_alloc(struct bce_softc *);
324 static void bce_dma_free(struct bce_softc *);
325 static void bce_dma_map_addr(void *, bus_dma_segment_t *, int, int);
326 static void bce_dma_map_mbuf(void *, bus_dma_segment_t *, int,
327 bus_size_t, int);
328
329 /****************************************************************************/
330 /* BCE Firmware Synchronization and Load */
331 /****************************************************************************/
332 static int bce_fw_sync(struct bce_softc *, uint32_t);
333 static void bce_load_rv2p_fw(struct bce_softc *, uint32_t *,
334 uint32_t, uint32_t);
335 static void bce_load_cpu_fw(struct bce_softc *, struct cpu_reg *,
336 struct fw_info *);
337 static void bce_init_cpus(struct bce_softc *);
338
339 static void bce_stop(struct bce_softc *);
340 static int bce_reset(struct bce_softc *, uint32_t);
341 static int bce_chipinit(struct bce_softc *);
342 static int bce_blockinit(struct bce_softc *);
343 static int bce_newbuf_std(struct bce_softc *, struct mbuf *,
344 uint16_t *, uint16_t *, uint32_t *);
345
346 static int bce_init_tx_chain(struct bce_softc *);
347 static int bce_init_rx_chain(struct bce_softc *);
348 static void bce_free_rx_chain(struct bce_softc *);
349 static void bce_free_tx_chain(struct bce_softc *);
350
351 static int bce_encap(struct bce_softc *, struct mbuf **);
352 static void bce_start(struct ifnet *);
353 static int bce_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
354 static void bce_watchdog(struct ifnet *);
355 static int bce_ifmedia_upd(struct ifnet *);
356 static void bce_ifmedia_sts(struct ifnet *, struct ifmediareq *);
357 static void bce_init(void *);
358 static void bce_mgmt_init(struct bce_softc *);
359
360 static void bce_init_ctx(struct bce_softc *);
361 static void bce_get_mac_addr(struct bce_softc *);
362 static void bce_set_mac_addr(struct bce_softc *);
363 static void bce_phy_intr(struct bce_softc *);
364 static void bce_rx_intr(struct bce_softc *, int);
365 static void bce_tx_intr(struct bce_softc *);
366 static void bce_disable_intr(struct bce_softc *);
367 static void bce_enable_intr(struct bce_softc *);
368
369 #ifdef DEVICE_POLLING
370 static void bce_poll(struct ifnet *, enum poll_cmd, int);
371 #endif
372 static void bce_intr(void *);
373 static void bce_set_rx_mode(struct bce_softc *);
374 static void bce_stats_update(struct bce_softc *);
375 static void bce_tick(void *);
376 static void bce_tick_serialized(struct bce_softc *);
377 static void bce_add_sysctls(struct bce_softc *);
378
379 static void bce_coal_change(struct bce_softc *);
380 static int bce_sysctl_tx_bds_int(SYSCTL_HANDLER_ARGS);
381 static int bce_sysctl_tx_bds(SYSCTL_HANDLER_ARGS);
382 static int bce_sysctl_tx_ticks_int(SYSCTL_HANDLER_ARGS);
383 static int bce_sysctl_tx_ticks(SYSCTL_HANDLER_ARGS);
384 static int bce_sysctl_rx_bds_int(SYSCTL_HANDLER_ARGS);
385 static int bce_sysctl_rx_bds(SYSCTL_HANDLER_ARGS);
386 static int bce_sysctl_rx_ticks_int(SYSCTL_HANDLER_ARGS);
387 static int bce_sysctl_rx_ticks(SYSCTL_HANDLER_ARGS);
388 static int bce_sysctl_coal_change(SYSCTL_HANDLER_ARGS,
389 uint32_t *, uint32_t);
390
391 static uint32_t bce_tx_bds_int = 20; /* bcm: 20 */
392 static uint32_t bce_tx_bds = 24; /* bcm: 20 */
393 static uint32_t bce_tx_ticks_int = 80; /* bcm: 80 */
394 static uint32_t bce_tx_ticks = 1000; /* bcm: 80 */
395 static uint32_t bce_rx_bds_int = 6; /* bcm: 6 */
396 static uint32_t bce_rx_bds = 24; /* bcm: 6 */
397 static uint32_t bce_rx_ticks_int = 18; /* bcm: 18 */
398 static uint32_t bce_rx_ticks = 125; /* bcm: 18 */
399
400 TUNABLE_INT("hw.bce.tx_bds_int", &bce_tx_bds_int);
401 TUNABLE_INT("hw.bce.tx_bds", &bce_tx_bds);
402 TUNABLE_INT("hw.bce.tx_ticks_int", &bce_tx_ticks_int);
403 TUNABLE_INT("hw.bce.tx_ticks", &bce_tx_ticks);
404 TUNABLE_INT("hw.bce.rx_bds_int", &bce_rx_bds_int);
405 TUNABLE_INT("hw.bce.rx_bds", &bce_rx_bds);
406 TUNABLE_INT("hw.bce.rx_ticks_int", &bce_rx_ticks_int);
407 TUNABLE_INT("hw.bce.rx_ticks", &bce_rx_ticks);
408
409 /****************************************************************************/
410 /* DragonFly device dispatch table. */
411 /****************************************************************************/
412 static device_method_t bce_methods[] = {
413 /* Device interface */
414 DEVMETHOD(device_probe, bce_probe),
415 DEVMETHOD(device_attach, bce_attach),
416 DEVMETHOD(device_detach, bce_detach),
417 DEVMETHOD(device_shutdown, bce_shutdown),
418
419 /* bus interface */
420 DEVMETHOD(bus_print_child, bus_generic_print_child),
421 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
422
423 /* MII interface */
424 DEVMETHOD(miibus_readreg, bce_miibus_read_reg),
425 DEVMETHOD(miibus_writereg, bce_miibus_write_reg),
426 DEVMETHOD(miibus_statchg, bce_miibus_statchg),
427
428 { 0, 0 }
429 };
430
431 static driver_t bce_driver = {
432 "bce",
433 bce_methods,
434 sizeof(struct bce_softc)
435 };
436
437 static devclass_t bce_devclass;
438
439 MODULE_DEPEND(bce, pci, 1, 1, 1);
440 MODULE_DEPEND(bce, ether, 1, 1, 1);
441 MODULE_DEPEND(bce, miibus, 1, 1, 1);
442
443 DRIVER_MODULE(bce, pci, bce_driver, bce_devclass, 0, 0);
444 DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, 0, 0);
445
446
447 /****************************************************************************/
448 /* Device probe function. */
449 /* */
450 /* Compares the device to the driver's list of supported devices and */
451 /* reports back to the OS whether this is the right driver for the device. */
452 /* */
453 /* Returns: */
454 /* BUS_PROBE_DEFAULT on success, positive value on failure. */
455 /****************************************************************************/
456 static int
457 bce_probe(device_t dev)
458 {
459 struct bce_type *t;
460 uint16_t vid, did, svid, sdid;
461
462 /* Get the data for the device to be probed. */
463 vid = pci_get_vendor(dev);
464 did = pci_get_device(dev);
465 svid = pci_get_subvendor(dev);
466 sdid = pci_get_subdevice(dev);
467
468 /* Look through the list of known devices for a match. */
469 for (t = bce_devs; t->bce_name != NULL; ++t) {
470 if (vid == t->bce_vid && did == t->bce_did &&
471 (svid == t->bce_svid || t->bce_svid == PCI_ANY_ID) &&
472 (sdid == t->bce_sdid || t->bce_sdid == PCI_ANY_ID)) {
473 uint32_t revid = pci_read_config(dev, PCIR_REVID, 4);
474 char *descbuf;
475
476 descbuf = kmalloc(BCE_DEVDESC_MAX, M_TEMP, M_WAITOK);
477
478 /* Print out the device identity. */
479 ksnprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)",
480 t->bce_name,
481 ((revid & 0xf0) >> 4) + 'A', revid & 0xf);
482
483 device_set_desc_copy(dev, descbuf);
484 kfree(descbuf, M_TEMP);
485 return 0;
486 }
487 }
488 return ENXIO;
489 }
490
491
492 /****************************************************************************/
493 /* Device attach function. */
494 /* */
495 /* Allocates device resources, performs secondary chip identification, */
496 /* resets and initializes the hardware, and initializes driver instance */
497 /* variables. */
498 /* */
499 /* Returns: */
500 /* 0 on success, positive value on failure. */
501 /****************************************************************************/
502 static int
503 bce_attach(device_t dev)
504 {
505 struct bce_softc *sc = device_get_softc(dev);
506 struct ifnet *ifp = &sc->arpcom.ac_if;
507 uint32_t val;
508 int rid, rc = 0;
509 #ifdef notyet
510 int count;
511 #endif
512
513 sc->bce_dev = dev;
514 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
515
516 pci_enable_busmaster(dev);
517
518 /* Allocate PCI memory resources. */
519 rid = PCIR_BAR(0);
520 sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
521 RF_ACTIVE | PCI_RF_DENSE);
522 if (sc->bce_res_mem == NULL) {
523 device_printf(dev, "PCI memory allocation failed\n");
524 return ENXIO;
525 }
526 sc->bce_btag = rman_get_bustag(sc->bce_res_mem);
527 sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem);
528
529 /* Allocate PCI IRQ resources. */
530 #ifdef notyet
531 count = pci_msi_count(dev);
532 if (count == 1 && pci_alloc_msi(dev, &count) == 0) {
533 rid = 1;
534 sc->bce_flags |= BCE_USING_MSI_FLAG;
535 } else
536 #endif
537 rid = 0;
538 sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
539 RF_SHAREABLE | RF_ACTIVE);
540 if (sc->bce_res_irq == NULL) {
541 device_printf(dev, "PCI map interrupt failed\n");
542 rc = ENXIO;
543 goto fail;
544 }
545
546 /*
547 * Configure byte swap and enable indirect register access.
548 * Rely on CPU to do target byte swapping on big endian systems.
549 * Access to registers outside of PCI configurtion space are not
550 * valid until this is done.
551 */
552 pci_write_config(dev, BCE_PCICFG_MISC_CONFIG,
553 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
554 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4);
555
556 /* Save ASIC revsion info. */
557 sc->bce_chipid = REG_RD(sc, BCE_MISC_ID);
558
559 /* Weed out any non-production controller revisions. */
560 switch(BCE_CHIP_ID(sc)) {
561 case BCE_CHIP_ID_5706_A0:
562 case BCE_CHIP_ID_5706_A1:
563 case BCE_CHIP_ID_5708_A0:
564 case BCE_CHIP_ID_5708_B0:
565 device_printf(dev, "Unsupported chip id 0x%08x!\n",
566 BCE_CHIP_ID(sc));
567 rc = ENODEV;
568 goto fail;
569 }
570
571 /*
572 * The embedded PCIe to PCI-X bridge (EPB)
573 * in the 5708 cannot address memory above
574 * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043).
575 */
576 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)
577 sc->max_bus_addr = BCE_BUS_SPACE_MAXADDR;
578 else
579 sc->max_bus_addr = BUS_SPACE_MAXADDR;
580
581 /*
582 * Find the base address for shared memory access.
583 * Newer versions of bootcode use a signature and offset
584 * while older versions use a fixed address.
585 */
586 val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE);
587 if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) == BCE_SHM_HDR_SIGNATURE_SIG)
588 sc->bce_shmem_base = REG_RD_IND(sc, BCE_SHM_HDR_ADDR_0);
589 else
590 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE;
591
592 DBPRINT(sc, BCE_INFO, "bce_shmem_base = 0x%08X\n", sc->bce_shmem_base);
593
594 /* Get PCI bus information (speed and type). */
595 val = REG_RD(sc, BCE_PCICFG_MISC_STATUS);
596 if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) {
597 uint32_t clkreg;
598
599 sc->bce_flags |= BCE_PCIX_FLAG;
600
601 clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS) &
602 BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
603 switch (clkreg) {
604 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
605 sc->bus_speed_mhz = 133;
606 break;
607
608 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
609 sc->bus_speed_mhz = 100;
610 break;
611
612 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
613 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
614 sc->bus_speed_mhz = 66;
615 break;
616
617 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
618 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
619 sc->bus_speed_mhz = 50;
620 break;
621
622 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
623 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
624 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
625 sc->bus_speed_mhz = 33;
626 break;
627 }
628 } else {
629 if (val & BCE_PCICFG_MISC_STATUS_M66EN)
630 sc->bus_speed_mhz = 66;
631 else
632 sc->bus_speed_mhz = 33;
633 }
634
635 if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET)
636 sc->bce_flags |= BCE_PCI_32BIT_FLAG;
637
638 device_printf(dev, "ASIC ID 0x%08X; Revision (%c%d); PCI%s %s %dMHz\n",
639 sc->bce_chipid,
640 ((BCE_CHIP_ID(sc) & 0xf000) >> 12) + 'A',
641 (BCE_CHIP_ID(sc) & 0x0ff0) >> 4,
642 (sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : "",
643 (sc->bce_flags & BCE_PCI_32BIT_FLAG) ?
644 "32-bit" : "64-bit", sc->bus_speed_mhz);
645
646 /* Reset the controller. */
647 rc = bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
648 if (rc != 0)
649 goto fail;
650
651 /* Initialize the controller. */
652 rc = bce_chipinit(sc);
653 if (rc != 0) {
654 device_printf(dev, "Controller initialization failed!\n");
655 goto fail;
656 }
657
658 /* Perform NVRAM test. */
659 rc = bce_nvram_test(sc);
660 if (rc != 0) {
661 device_printf(dev, "NVRAM test failed!\n");
662 goto fail;
663 }
664
665 /* Fetch the permanent Ethernet MAC address. */
666 bce_get_mac_addr(sc);
667
668 /*
669 * Trip points control how many BDs
670 * should be ready before generating an
671 * interrupt while ticks control how long
672 * a BD can sit in the chain before
673 * generating an interrupt. Set the default
674 * values for the RX and TX rings.
675 */
676
677 #ifdef BCE_DRBUG
678 /* Force more frequent interrupts. */
679 sc->bce_tx_quick_cons_trip_int = 1;
680 sc->bce_tx_quick_cons_trip = 1;
681 sc->bce_tx_ticks_int = 0;
682 sc->bce_tx_ticks = 0;
683
684 sc->bce_rx_quick_cons_trip_int = 1;
685 sc->bce_rx_quick_cons_trip = 1;
686 sc->bce_rx_ticks_int = 0;
687 sc->bce_rx_ticks = 0;
688 #else
689 sc->bce_tx_quick_cons_trip_int = bce_tx_bds_int;
690 sc->bce_tx_quick_cons_trip = bce_tx_bds;
691 sc->bce_tx_ticks_int = bce_tx_ticks_int;
692 sc->bce_tx_ticks = bce_tx_ticks;
693
694 sc->bce_rx_quick_cons_trip_int = bce_rx_bds_int;
695 sc->bce_rx_quick_cons_trip = bce_rx_bds;
696 sc->bce_rx_ticks_int = bce_rx_ticks_int;
697 sc->bce_rx_ticks = bce_rx_ticks;
698 #endif
699
700 /* Update statistics once every second. */
701 sc->bce_stats_ticks = 1000000 & 0xffff00;
702
703 /*
704 * The copper based NetXtreme II controllers
705 * use an integrated PHY at address 1 while
706 * the SerDes controllers use a PHY at
707 * address 2.
708 */
709 sc->bce_phy_addr = 1;
710
711 if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT) {
712 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
713 sc->bce_flags |= BCE_NO_WOL_FLAG;
714 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708) {
715 sc->bce_phy_addr = 2;
716 val = REG_RD_IND(sc, sc->bce_shmem_base +
717 BCE_SHARED_HW_CFG_CONFIG);
718 if (val & BCE_SHARED_HW_CFG_PHY_2_5G)
719 sc->bce_phy_flags |= BCE_PHY_2_5G_CAPABLE_FLAG;
720 }
721 }
722
723 /* Allocate DMA memory resources. */
724 rc = bce_dma_alloc(sc);
725 if (rc != 0) {
726 device_printf(dev, "DMA resource allocation failed!\n");
727 goto fail;
728 }
729
730 /* Initialize the ifnet interface. */
731 ifp->if_softc = sc;
732 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
733 ifp->if_ioctl = bce_ioctl;
734 ifp->if_start = bce_start;
735 ifp->if_init = bce_init;
736 ifp->if_watchdog = bce_watchdog;
737 #ifdef DEVICE_POLLING
738 ifp->if_poll = bce_poll;
739 #endif
740 ifp->if_mtu = ETHERMTU;
741 ifp->if_hwassist = BCE_IF_HWASSIST;
742 ifp->if_capabilities = BCE_IF_CAPABILITIES;
743 ifp->if_capenable = ifp->if_capabilities;
744 ifq_set_maxlen(&ifp->if_snd, USABLE_TX_BD);
745 ifq_set_ready(&ifp->if_snd);
746
747 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
748 ifp->if_baudrate = IF_Gbps(2.5);
749 else
750 ifp->if_baudrate = IF_Gbps(1);
751
752 /* Assume a standard 1500 byte MTU size for mbuf allocations. */
753 sc->mbuf_alloc_size = MCLBYTES;
754
755 /* Look for our PHY. */
756 rc = mii_phy_probe(dev, &sc->bce_miibus,
757 bce_ifmedia_upd, bce_ifmedia_sts);
758 if (rc != 0) {
759 device_printf(dev, "PHY probe failed!\n");
760 goto fail;
761 }
762
763 /* Attach to the Ethernet interface list. */
764 ether_ifattach(ifp, sc->eaddr, NULL);
765
766 callout_init(&sc->bce_stat_ch);
767
768 /* Hookup IRQ last. */
769 rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_NETSAFE, bce_intr, sc,
770 &sc->bce_intrhand, ifp->if_serializer);
771 if (rc != 0) {
772 device_printf(dev, "Failed to setup IRQ!\n");
773 ether_ifdetach(ifp);
774 goto fail;
775 }
776
777 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->bce_res_irq));
778 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
779
780 /* Print some important debugging info. */
781 DBRUN(BCE_INFO, bce_dump_driver_state(sc));
782
783 /* Add the supported sysctls to the kernel. */
784 bce_add_sysctls(sc);
785
786 /* Get the firmware running so IPMI still works */
787 bce_mgmt_init(sc);
788
789 return 0;
790 fail:
791 bce_detach(dev);
792 return(rc);
793 }
794
795
796 /****************************************************************************/
797 /* Device detach function. */
798 /* */
799 /* Stops the controller, resets the controller, and releases resources. */
800 /* */
801 /* Returns: */
802 /* 0 on success, positive value on failure. */
803 /****************************************************************************/
804 static int
805 bce_detach(device_t dev)
806 {
807 struct bce_softc *sc = device_get_softc(dev);
808
809 if (device_is_attached(dev)) {
810 struct ifnet *ifp = &sc->arpcom.ac_if;
811
812 /* Stop and reset the controller. */
813 lwkt_serialize_enter(ifp->if_serializer);
814 bce_stop(sc);
815 bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
816 bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand);
817 lwkt_serialize_exit(ifp->if_serializer);
818
819 ether_ifdetach(ifp);
820 }
821
822 /* If we have a child device on the MII bus remove it too. */
823 if (sc->bce_miibus)
824 device_delete_child(dev, sc->bce_miibus);
825 bus_generic_detach(dev);
826
827 if (sc->bce_res_irq != NULL) {
828 bus_release_resource(dev, SYS_RES_IRQ,
829 sc->bce_flags & BCE_USING_MSI_FLAG ? 1 : 0,
830 sc->bce_res_irq);
831 }
832
833 #ifdef notyet
834 if (sc->bce_flags & BCE_USING_MSI_FLAG)
835 pci_release_msi(dev);
836 #endif
837
838 if (sc->bce_res_mem != NULL) {
839 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0),
840 sc->bce_res_mem);
841 }
842
843 bce_dma_free(sc);
844
845 if (sc->bce_sysctl_tree != NULL)
846 sysctl_ctx_free(&sc->bce_sysctl_ctx);
847
848 return 0;
849 }
850
851
852 /****************************************************************************/
853 /* Device shutdown function. */
854 /* */
855 /* Stops and resets the controller. */
856 /* */
857 /* Returns: */
858 /* Nothing */
859 /****************************************************************************/
860 static void
861 bce_shutdown(device_t dev)
862 {
863 struct bce_softc *sc = device_get_softc(dev);
864 struct ifnet *ifp = &sc->arpcom.ac_if;
865
866 lwkt_serialize_enter(ifp->if_serializer);
867 bce_stop(sc);
868 bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
869 lwkt_serialize_exit(ifp->if_serializer);
870 }
871
872
873 /****************************************************************************/
874 /* Indirect register read. */
875 /* */
876 /* Reads NetXtreme II registers using an index/data register pair in PCI */
877 /* configuration space. Using this mechanism avoids issues with posted */
878 /* reads but is much slower than memory-mapped I/O. */
879 /* */
880 /* Returns: */
881 /* The value of the register. */
882 /****************************************************************************/
883 static uint32_t
884 bce_reg_rd_ind(struct bce_softc *sc, uint32_t offset)
885 {
886 device_t dev = sc->bce_dev;
887
888 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
889 #ifdef BCE_DEBUG
890 {
891 uint32_t val;
892 val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
893 DBPRINT(sc, BCE_EXCESSIVE,
894 "%s(); offset = 0x%08X, val = 0x%08X\n",
895 __func__, offset, val);
896 return val;
897 }
898 #else
899 return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
900 #endif
901 }
902
903
904 /****************************************************************************/
905 /* Indirect register write. */
906 /* */
907 /* Writes NetXtreme II registers using an index/data register pair in PCI */
908 /* configuration space. Using this mechanism avoids issues with posted */
909 /* writes but is muchh slower than memory-mapped I/O. */
910 /* */
911 /* Returns: */
912 /* Nothing. */
913 /****************************************************************************/
914 static void
915 bce_reg_wr_ind(struct bce_softc *sc, uint32_t offset, uint32_t val)
916 {
917 device_t dev = sc->bce_dev;
918
919 DBPRINT(sc, BCE_EXCESSIVE, "%s(); offset = 0x%08X, val = 0x%08X\n",
920 __func__, offset, val);
921
922 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
923 pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4);
924 }
925
926
927 /****************************************************************************/
928 /* Context memory write. */
929 /* */
930 /* The NetXtreme II controller uses context memory to track connection */
931 /* information for L2 and higher network protocols. */
932 /* */
933 /* Returns: */
934 /* Nothing. */
935 /****************************************************************************/
936 static void
937 bce_ctx_wr(struct bce_softc *sc, uint32_t cid_addr, uint32_t offset,
938 uint32_t val)
939 {
940 DBPRINT(sc, BCE_EXCESSIVE, "%s(); cid_addr = 0x%08X, offset = 0x%08X, "
941 "val = 0x%08X\n", __func__, cid_addr, offset, val);
942
943 offset += cid_addr;
944 REG_WR(sc, BCE_CTX_DATA_ADR, offset);
945 REG_WR(sc, BCE_CTX_DATA, val);
946 }
947
948
949 /****************************************************************************/
950 /* PHY register read. */
951 /* */
952 /* Implements register reads on the MII bus. */
953 /* */
954 /* Returns: */
955 /* The value of the register. */
956 /****************************************************************************/
957 static int
958 bce_miibus_read_reg(device_t dev, int phy, int reg)
959 {
960 struct bce_softc *sc = device_get_softc(dev);
961 uint32_t val;
962 int i;
963
964 /* Make sure we are accessing the correct PHY address. */
965 if (phy != sc->bce_phy_addr) {
966 DBPRINT(sc, BCE_VERBOSE,
967 "Invalid PHY address %d for PHY read!\n", phy);
968 return 0;
969 }
970
971 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
972 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
973 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
974
975 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
976 REG_RD(sc, BCE_EMAC_MDIO_MODE);
977
978 DELAY(40);
979 }
980
981 val = BCE_MIPHY(phy) | BCE_MIREG(reg) |
982 BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT |
983 BCE_EMAC_MDIO_COMM_START_BUSY;
984 REG_WR(sc, BCE_EMAC_MDIO_COMM, val);
985
986 for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
987 DELAY(10);
988
989 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
990 if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) {
991 DELAY(5);
992
993 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
994 val &= BCE_EMAC_MDIO_COMM_DATA;
995 break;
996 }
997 }
998
999 if (val & BCE_EMAC_MDIO_COMM_START_BUSY) {
1000 if_printf(&sc->arpcom.ac_if,
1001 "Error: PHY read timeout! phy = %d, reg = 0x%04X\n",
1002 phy, reg);
1003 val = 0x0;
1004 } else {
1005 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1006 }
1007
1008 DBPRINT(sc, BCE_EXCESSIVE,
1009 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n",
1010 __func__, phy, (uint16_t)reg & 0xffff, (uint16_t) val & 0xffff);
1011
1012 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1013 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1014 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1015
1016 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1017 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1018
1019 DELAY(40);
1020 }
1021 return (val & 0xffff);
1022 }
1023
1024
1025 /****************************************************************************/
1026 /* PHY register write. */
1027 /* */
1028 /* Implements register writes on the MII bus. */
1029 /* */
1030 /* Returns: */
1031 /* The value of the register. */
1032 /****************************************************************************/
1033 static int
1034 bce_miibus_write_reg(device_t dev, int phy, int reg, int val)
1035 {
1036 struct bce_softc *sc = device_get_softc(dev);
1037 uint32_t val1;
1038 int i;
1039
1040 /* Make sure we are accessing the correct PHY address. */
1041 if (phy != sc->bce_phy_addr) {
1042 DBPRINT(sc, BCE_WARN,
1043 "Invalid PHY address %d for PHY write!\n", phy);
1044 return(0);
1045 }
1046
1047 DBPRINT(sc, BCE_EXCESSIVE,
1048 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n",
1049 __func__, phy, (uint16_t)(reg & 0xffff),
1050 (uint16_t)(val & 0xffff));
1051
1052 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1053 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1054 val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1055
1056 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1057 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1058
1059 DELAY(40);
1060 }
1061
1062 val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val |
1063 BCE_EMAC_MDIO_COMM_COMMAND_WRITE |
1064 BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT;
1065 REG_WR(sc, BCE_EMAC_MDIO_COMM, val1);
1066
1067 for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1068 DELAY(10);
1069
1070 val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1071 if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1072 DELAY(5);
1073 break;
1074 }
1075 }
1076
1077 if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY)
1078 if_printf(&sc->arpcom.ac_if, "PHY write timeout!\n");
1079
1080 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1081 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1082 val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1083
1084 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1085 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1086
1087 DELAY(40);
1088 }
1089 return 0;
1090 }
1091
1092
1093 /****************************************************************************/
1094 /* MII bus status change. */
1095 /* */
1096 /* Called by the MII bus driver when the PHY establishes link to set the */
1097 /* MAC interface registers. */
1098 /* */
1099 /* Returns: */
1100 /* Nothing. */
1101 /****************************************************************************/
1102 static void
1103 bce_miibus_statchg(device_t dev)
1104 {
1105 struct bce_softc *sc = device_get_softc(dev);
1106 struct mii_data *mii = device_get_softc(sc->bce_miibus);
1107
1108 DBPRINT(sc, BCE_INFO, "mii_media_active = 0x%08X\n",
1109 mii->mii_media_active);
1110
1111 #ifdef BCE_DEBUG
1112 /* Decode the interface media flags. */
1113 if_printf(&sc->arpcom.ac_if, "Media: ( ");
1114 switch(IFM_TYPE(mii->mii_media_active)) {
1115 case IFM_ETHER:
1116 kprintf("Ethernet )");
1117 break;
1118 default:
1119 kprintf("Unknown )");
1120 break;
1121 }
1122
1123 kprintf(" Media Options: ( ");
1124 switch(IFM_SUBTYPE(mii->mii_media_active)) {
1125 case IFM_AUTO:
1126 kprintf("Autoselect )");
1127 break;
1128 case IFM_MANUAL:
1129 kprintf("Manual )");
1130 break;
1131 case IFM_NONE:
1132 kprintf("None )");
1133 break;
1134 case IFM_10_T:
1135 kprintf("10Base-T )");
1136 break;
1137 case IFM_100_TX:
1138 kprintf("100Base-TX )");
1139 break;
1140 case IFM_1000_SX:
1141 kprintf("1000Base-SX )");
1142 break;
1143 case IFM_1000_T:
1144 kprintf("1000Base-T )");
1145 break;
1146 default:
1147 kprintf("Other )");
1148 break;
1149 }
1150
1151 kprintf(" Global Options: (");
1152 if (mii->mii_media_active & IFM_FDX)
1153 kprintf(" FullDuplex");
1154 if (mii->mii_media_active & IFM_HDX)
1155 kprintf(" HalfDuplex");
1156 if (mii->mii_media_active & IFM_LOOP)
1157 kprintf(" Loopback");
1158 if (mii->mii_media_active & IFM_FLAG0)
1159 kprintf(" Flag0");
1160 if (mii->mii_media_active & IFM_FLAG1)
1161 kprintf(" Flag1");
1162 if (mii->mii_media_active & IFM_FLAG2)
1163 kprintf(" Flag2");
1164 kprintf(" )\n");
1165 #endif
1166
1167 BCE_CLRBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT);
1168
1169 /*
1170 * Set MII or GMII interface based on the speed negotiated
1171 * by the PHY.
1172 */
1173 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
1174 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
1175 DBPRINT(sc, BCE_INFO, "Setting GMII interface.\n");
1176 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT_GMII);
1177 } else {
1178 DBPRINT(sc, BCE_INFO, "Setting MII interface.\n");
1179 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT_MII);
1180 }
1181
1182 /*
1183 * Set half or full duplex based on the duplicity negotiated
1184 * by the PHY.
1185 */
1186 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
1187 DBPRINT(sc, BCE_INFO, "Setting Full-Duplex interface.\n");
1188 BCE_CLRBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_HALF_DUPLEX);
1189 } else {
1190 DBPRINT(sc, BCE_INFO, "Setting Half-Duplex interface.\n");
1191 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_HALF_DUPLEX);
1192 }
1193 }
1194
1195
1196 /****************************************************************************/
1197 /* Acquire NVRAM lock. */
1198 /* */
1199 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock. */
1200 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */
1201 /* for use by the driver. */
1202 /* */
1203 /* Returns: */
1204 /* 0 on success, positive value on failure. */
1205 /****************************************************************************/
1206 static int
1207 bce_acquire_nvram_lock(struct bce_softc *sc)
1208 {
1209 uint32_t val;
1210 int j;
1211
1212 DBPRINT(sc, BCE_VERBOSE, "Acquiring NVRAM lock.\n");
1213
1214 /* Request access to the flash interface. */
1215 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2);
1216 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1217 val = REG_RD(sc, BCE_NVM_SW_ARB);
1218 if (val & BCE_NVM_SW_ARB_ARB_ARB2)
1219 break;
1220
1221 DELAY(5);
1222 }
1223
1224 if (j >= NVRAM_TIMEOUT_COUNT) {
1225 DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n");
1226 return EBUSY;
1227 }
1228 return 0;
1229 }
1230
1231
1232 /****************************************************************************/
1233 /* Release NVRAM lock. */
1234 /* */
1235 /* When the caller is finished accessing NVRAM the lock must be released. */
1236 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */
1237 /* for use by the driver. */
1238 /* */
1239 /* Returns: */
1240 /* 0 on success, positive value on failure. */
1241 /****************************************************************************/
1242 static int
1243 bce_release_nvram_lock(struct bce_softc *sc)
1244 {
1245 int j;
1246 uint32_t val;
1247
1248 DBPRINT(sc, BCE_VERBOSE, "Releasing NVRAM lock.\n");
1249
1250 /*
1251 * Relinquish nvram interface.
1252 */
1253 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2);
1254
1255 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1256 val = REG_RD(sc, BCE_NVM_SW_ARB);
1257 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2))
1258 break;
1259
1260 DELAY(5);
1261 }
1262
1263 if (j >= NVRAM_TIMEOUT_COUNT) {
1264 DBPRINT(sc, BCE_WARN, "Timeout reeasing NVRAM lock!\n");
1265 return EBUSY;
1266 }
1267 return 0;
1268 }
1269
1270
1271 #ifdef BCE_NVRAM_WRITE_SUPPORT
1272 /****************************************************************************/
1273 /* Enable NVRAM write access. */
1274 /* */
1275 /* Before writing to NVRAM the caller must enable NVRAM writes. */
1276 /* */
1277 /* Returns: */
1278 /* 0 on success, positive value on failure. */
1279 /****************************************************************************/
1280 static int
1281 bce_enable_nvram_write(struct bce_softc *sc)
1282 {
1283 uint32_t val;
1284
1285 DBPRINT(sc, BCE_VERBOSE, "Enabling NVRAM write.\n");
1286
1287 val = REG_RD(sc, BCE_MISC_CFG);
1288 REG_WR(sc, BCE_MISC_CFG, val | BCE_MISC_CFG_NVM_WR_EN_PCI);
1289
1290 if (!sc->bce_flash_info->buffered) {
1291 int j;
1292
1293 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
1294 REG_WR(sc, BCE_NVM_COMMAND,
1295 BCE_NVM_COMMAND_WREN | BCE_NVM_COMMAND_DOIT);
1296
1297 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1298 DELAY(5);
1299
1300 val = REG_RD(sc, BCE_NVM_COMMAND);
1301 if (val & BCE_NVM_COMMAND_DONE)
1302 break;
1303 }
1304
1305 if (j >= NVRAM_TIMEOUT_COUNT) {
1306 DBPRINT(sc, BCE_WARN, "Timeout writing NVRAM!\n");
1307 return EBUSY;
1308 }
1309 }
1310 return 0;
1311 }
1312
1313
1314 /****************************************************************************/
1315 /* Disable NVRAM write access. */
1316 /* */
1317 /* When the caller is finished writing to NVRAM write access must be */
1318 /* disabled. */
1319 /* */
1320 /* Returns: */
1321 /* Nothing. */
1322 /****************************************************************************/
1323 static void
1324 bce_disable_nvram_write(struct bce_softc *sc)
1325 {
1326 uint32_t val;
1327
1328 DBPRINT(sc, BCE_VERBOSE, "Disabling NVRAM write.\n");
1329
1330 val = REG_RD(sc, BCE_MISC_CFG);
1331 REG_WR(sc, BCE_MISC_CFG, val & ~BCE_MISC_CFG_NVM_WR_EN);
1332 }
1333 #endif /* BCE_NVRAM_WRITE_SUPPORT */
1334
1335
1336 /****************************************************************************/
1337 /* Enable NVRAM access. */
1338 /* */
1339 /* Before accessing NVRAM for read or write operations the caller must */
1340 /* enabled NVRAM access. */
1341 /* */
1342 /* Returns: */
1343 /* Nothing. */
1344 /****************************************************************************/
1345 static void
1346 bce_enable_nvram_access(struct bce_softc *sc)
1347 {
1348 uint32_t val;
1349
1350 DBPRINT(sc, BCE_VERBOSE, "Enabling NVRAM access.\n");
1351
1352 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1353 /* Enable both bits, even on read. */
1354 REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
1355 val | BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN);
1356 }
1357
1358
1359 /****************************************************************************/
1360 /* Disable NVRAM access. */
1361 /* */
1362 /* When the caller is finished accessing NVRAM access must be disabled. */
1363 /* */
1364 /* Returns: */
1365 /* Nothing. */
1366 /****************************************************************************/
1367 static void
1368 bce_disable_nvram_access(struct bce_softc *sc)
1369 {
1370 uint32_t val;
1371
1372 DBPRINT(sc, BCE_VERBOSE, "Disabling NVRAM access.\n");
1373
1374 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1375
1376 /* Disable both bits, even after read. */
1377 REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
1378 val & ~(BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN));
1379 }
1380
1381
1382 #ifdef BCE_NVRAM_WRITE_SUPPORT
1383 /****************************************************************************/
1384 /* Erase NVRAM page before writing. */
1385 /* */
1386 /* Non-buffered flash parts require that a page be erased before it is */
1387 /* written. */
1388 /* */
1389 /* Returns: */
1390 /* 0 on success, positive value on failure. */
1391 /****************************************************************************/
1392 static int
1393 bce_nvram_erase_page(struct bce_softc *sc, uint32_t offset)
1394 {
1395 uint32_t cmd;
1396 int j;
1397
1398 /* Buffered flash doesn't require an erase. */
1399 if (sc->bce_flash_info->buffered)
1400 return 0;
1401
1402 DBPRINT(sc, BCE_VERBOSE, "Erasing NVRAM page.\n");
1403
1404 /* Build an erase command. */
1405 cmd = BCE_NVM_COMMAND_ERASE | BCE_NVM_COMMAND_WR |
1406 BCE_NVM_COMMAND_DOIT;
1407
1408 /*
1409 * Clear the DONE bit separately, set the NVRAM adress to erase,
1410 * and issue the erase command.
1411 */
1412 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
1413 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
1414 REG_WR(sc, BCE_NVM_COMMAND, cmd);
1415
1416 /* Wait for completion. */
1417 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1418 uint32_t val;
1419
1420 DELAY(5);
1421
1422 val = REG_RD(sc, BCE_NVM_COMMAND);
1423 if (val & BCE_NVM_COMMAND_DONE)
1424 break;
1425 }
1426
1427 if (j >= NVRAM_TIMEOUT_COUNT) {
1428 DBPRINT(sc, BCE_WARN, "Timeout erasing NVRAM.\n");
1429 return EBUSY;
1430 }
1431 return 0;
1432 }
1433 #endif /* BCE_NVRAM_WRITE_SUPPORT */
1434
1435
1436 /****************************************************************************/
1437 /* Read a dword (32 bits) from NVRAM. */
1438 /* */
1439 /* Read a 32 bit word from NVRAM. The caller is assumed to have already */
1440 /* obtained the NVRAM lock and enabled the controller for NVRAM access. */
1441 /* */
1442 /* Returns: */
1443 /* 0 on success and the 32 bit value read, positive value on failure. */
1444 /****************************************************************************/
1445 static int
1446 bce_nvram_read_dword(struct bce_softc *sc, uint32_t offset, uint8_t *ret_val,
1447 uint32_t cmd_flags)
1448 {
1449 uint32_t cmd;
1450 int i, rc = 0;
1451
1452 /* Build the command word. */
1453 cmd = BCE_NVM_COMMAND_DOIT | cmd_flags;
1454
1455 /* Calculate the offset for buffered flash. */
1456 if (sc->bce_flash_info->buffered) {
1457 offset = ((offset / sc->bce_flash_info->page_size) <<
1458 sc->bce_flash_info->page_bits) +
1459 (offset % sc->bce_flash_info->page_size);
1460 }
1461
1462 /*
1463 * Clear the DONE bit separately, set the address to read,
1464 * and issue the read.
1465 */
1466 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
1467 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
1468 REG_WR(sc, BCE_NVM_COMMAND, cmd);
1469
1470 /* Wait for completion. */
1471 for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) {
1472 uint32_t val;
1473
1474 DELAY(5);
1475
1476 val = REG_RD(sc, BCE_NVM_COMMAND);
1477 if (val & BCE_NVM_COMMAND_DONE) {
1478 val = REG_RD(sc, BCE_NVM_READ);
1479
1480 val = be32toh(val);
1481 memcpy(ret_val, &val, 4);
1482 break;
1483 }
1484 }
1485
1486 /* Check for errors. */
1487 if (i >= NVRAM_TIMEOUT_COUNT) {
1488 if_printf(&sc->arpcom.ac_if,
1489 "Timeout error reading NVRAM at offset 0x%08X!\n",
1490 offset);
1491 rc = EBUSY;
1492 }
1493 return rc;
1494 }
1495
1496
1497 #ifdef BCE_NVRAM_WRITE_SUPPORT
1498 /****************************************************************************/
1499 /* Write a dword (32 bits) to NVRAM. */
1500 /* */
1501 /* Write a 32 bit word to NVRAM. The caller is assumed to have already */
1502 /* obtained the NVRAM lock, enabled the controller for NVRAM access, and */
1503 /* enabled NVRAM write access. */
1504 /* */
1505 /* Returns: */
1506 /* 0 on success, positive value on failure. */
1507 /****************************************************************************/
1508 static int
1509 bce_nvram_write_dword(struct bce_softc *sc, uint32_t offset, uint8_t *val,
1510 uint32_t cmd_flags)
1511 {
1512 uint32_t cmd, val32;
1513 int j;
1514
1515 /* Build the command word. */
1516 cmd = BCE_NVM_COMMAND_DOIT | BCE_NVM_COMMAND_WR | cmd_flags;
1517
1518 /* Calculate the offset for buffered flash. */
1519 if (sc->bce_flash_info->buffered) {
1520 offset = ((offset / sc->bce_flash_info->page_size) <<
1521 sc->bce_flash_info->page_bits) +
1522 (offset % sc->bce_flash_info->page_size);
1523 }
1524
1525 /*
1526 * Clear the DONE bit separately, convert NVRAM data to big-endian,
1527 * set the NVRAM address to write, and issue the write command
1528 */
1529 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
1530 memcpy(&val32, val, 4);
1531 val32 = htobe32(val32);
1532 REG_WR(sc, BCE_NVM_WRITE, val32);
1533 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
1534 REG_WR(sc, BCE_NVM_COMMAND, cmd);
1535
1536 /* Wait for completion. */
1537 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1538 DELAY(5);
1539
1540 if (REG_RD(sc, BCE_NVM_COMMAND) & BCE_NVM_COMMAND_DONE)
1541 break;
1542 }
1543 if (j >= NVRAM_TIMEOUT_COUNT) {
1544 if_printf(&sc->arpcom.ac_if,
1545 "Timeout error writing NVRAM at offset 0x%08X\n",
1546 offset);
1547 return EBUSY;
1548 }
1549 return 0;
1550 }
1551 #endif /* BCE_NVRAM_WRITE_SUPPORT */
1552
1553
1554 /****************************************************************************/
1555 /* Initialize NVRAM access. */
1556 /* */
1557 /* Identify the NVRAM device in use and prepare the NVRAM interface to */
1558 /* access that device. */
1559 /* */
1560 /* Returns: */
1561 /* 0 on success, positive value on failure. */
1562 /****************************************************************************/
1563 static int
1564 bce_init_nvram(struct bce_softc *sc)
1565 {
1566 uint32_t val;
1567 int j, entry_count, rc = 0;
1568 const struct flash_spec *flash;
1569
1570 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
1571
1572 /* Determine the selected interface. */
1573 val = REG_RD(sc, BCE_NVM_CFG1);
1574
1575 entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
1576
1577 /*
1578 * Flash reconfiguration is required to support additional
1579 * NVRAM devices not directly supported in hardware.
1580 * Check if the flash interface was reconfigured
1581 * by the bootcode.
1582 */
1583
1584 if (val & 0x40000000) {
1585 /* Flash interface reconfigured by bootcode. */
1586
1587 DBPRINT(sc, BCE_INFO_LOAD,
1588 "%s(): Flash WAS reconfigured.\n", __func__);
1589
1590 for (j = 0, flash = flash_table; j < entry_count;
1591 j++, flash++) {
1592 if ((val & FLASH_BACKUP_STRAP_MASK) ==
1593 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
1594 sc->bce_flash_info = flash;
1595 break;
1596 }
1597 }
1598 } else {
1599 /* Flash interface not yet reconfigured. */
1600 uint32_t mask;
1601
1602 DBPRINT(sc, BCE_INFO_LOAD,
1603 "%s(): Flash was NOT reconfigured.\n", __func__);
1604
1605 if (val & (1 << 23))
1606 mask = FLASH_BACKUP_STRAP_MASK;
1607 else
1608 mask = FLASH_STRAP_MASK;
1609
1610 /* Look for the matching NVRAM device configuration data. */
1611 for (j = 0, flash = flash_table; j < entry_count;
1612 j++, flash++) {
1613 /* Check if the device matches any of the known devices. */
1614 if ((val & mask) == (flash->strapping & mask)) {
1615 /* Found a device match. */
1616 sc->bce_flash_info = flash;
1617
1618 /* Request access to the flash interface. */
1619 rc = bce_acquire_nvram_lock(sc);
1620 if (rc != 0)
1621 return rc;
1622
1623 /* Reconfigure the flash interface. */
1624 bce_enable_nvram_access(sc);
1625 REG_WR(sc, BCE_NVM_CFG1, flash->config1);
1626 REG_WR(sc, BCE_NVM_CFG2, flash->config2);
1627 REG_WR(sc, BCE_NVM_CFG3, flash->config3);
1628 REG_WR(sc, BCE_NVM_WRITE1, flash->write1);
1629 bce_disable_nvram_access(sc);
1630 bce_release_nvram_lock(sc);
1631 break;
1632 }
1633 }
1634 }
1635
1636 /* Check if a matching device was found. */
1637 if (j == entry_count) {
1638 sc->bce_flash_info = NULL;
1639 if_printf(&sc->arpcom.ac_if, "Unknown Flash NVRAM found!\n");
1640 rc = ENODEV;
1641 }
1642
1643 /* Write the flash config data to the shared memory interface. */
1644 val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_SHARED_HW_CFG_CONFIG2) &
1645 BCE_SHARED_HW_CFG2_NVM_SIZE_MASK;
1646 if (val)
1647 sc->bce_flash_size = val;
1648 else
1649 sc->bce_flash_size = sc->bce_flash_info->total_size;
1650
1651 DBPRINT(sc, BCE_INFO_LOAD, "%s() flash->total_size = 0x%08X\n",
1652 __func__, sc->bce_flash_info->total_size);
1653
1654 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
1655
1656 return rc;
1657 }
1658
1659
1660 /****************************************************************************/
1661 /* Read an arbitrary range of data from NVRAM. */
1662 /* */
1663 /* Prepares the NVRAM interface for access and reads the requested data */
1664 /* into the supplied buffer. */
1665 /* */
1666 /* Returns: */
1667 /* 0 on success and the data read, positive value on failure. */
1668 /****************************************************************************/
1669 static int
1670 bce_nvram_read(struct bce_softc *sc, uint32_t offset, uint8_t *ret_buf,
1671 int buf_size)
1672 {
1673 uint32_t cmd_flags, offset32, len32, extra;
1674 int rc = 0;
1675
1676 if (buf_size == 0)
1677 return 0;
1678
1679 /* Request access to the flash interface. */
1680 rc = bce_acquire_nvram_lock(sc);
1681 if (rc != 0)
1682 return rc;
1683
1684 /* Enable access to flash interface */
1685 bce_enable_nvram_access(sc);
1686
1687 len32 = buf_size;
1688 offset32 = offset;
1689 extra = 0;
1690
1691 cmd_flags = 0;
1692
1693 /* XXX should we release nvram lock if read_dword() fails? */
1694 if (offset32 & 3) {
1695 uint8_t buf[4];
1696 uint32_t pre_len;
1697
1698 offset32 &= ~3;
1699 pre_len = 4 - (offset & 3);
1700
1701 if (pre_len >= len32) {
1702 pre_len = len32;
1703 cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST;
1704 } else {
1705 cmd_flags = BCE_NVM_COMMAND_FIRST;
1706 }
1707
1708 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1709 if (rc)
1710 return rc;
1711
1712 memcpy(ret_buf, buf + (offset & 3), pre_len);
1713
1714 offset32 += 4;
1715 ret_buf += pre_len;
1716 len32 -= pre_len;
1717 }
1718
1719 if (len32 & 3) {
1720 extra = 4 - (len32 & 3);
1721 len32 = (len32 + 4) & ~3;
1722 }
1723
1724 if (len32 == 4) {
1725 uint8_t buf[4];
1726
1727 if (cmd_flags)
1728 cmd_flags = BCE_NVM_COMMAND_LAST;
1729 else
1730 cmd_flags = BCE_NVM_COMMAND_FIRST |
1731 BCE_NVM_COMMAND_LAST;
1732
1733 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1734
1735 memcpy(ret_buf, buf, 4 - extra);
1736 } else if (len32 > 0) {
1737 uint8_t buf[4];
1738
1739 /* Read the first word. */
1740 if (cmd_flags)
1741 cmd_flags = 0;
1742 else
1743 cmd_flags = BCE_NVM_COMMAND_FIRST;
1744
1745 rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags);
1746
1747 /* Advance to the next dword. */
1748 offset32 += 4;
1749 ret_buf += 4;
1750 len32 -= 4;
1751
1752 while (len32 > 4 && rc == 0) {
1753 rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0);
1754
1755 /* Advance to the next dword. */
1756 offset32 += 4;
1757 ret_buf += 4;
1758 len32 -= 4;
1759 }
1760
1761 if (rc)
1762 return rc;
1763
1764 cmd_flags = BCE_NVM_COMMAND_LAST;
1765 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1766
1767 memcpy(ret_buf, buf, 4 - extra);
1768 }
1769
1770 /* Disable access to flash interface and release the lock. */
1771 bce_disable_nvram_access(sc);
1772 bce_release_nvram_lock(sc);
1773
1774 return rc;
1775 }
1776
1777
1778 #ifdef BCE_NVRAM_WRITE_SUPPORT
1779 /****************************************************************************/
1780 /* Write an arbitrary range of data from NVRAM. */
1781 /* */
1782 /* Prepares the NVRAM interface for write access and writes the requested */
1783 /* data from the supplied buffer. The caller is responsible for */
1784 /* calculating any appropriate CRCs. */
1785 /* */
1786 /* Returns: */
1787 /* 0 on success, positive value on failure. */
1788 /****************************************************************************/
1789 static int
1790 bce_nvram_write(struct bce_softc *sc, uint32_t offset, uint8_t *data_buf,
1791 int buf_size)
1792 {
1793 uint32_t written, offset32, len32;
1794 uint8_t *buf, start[4], end[4];
1795 int rc = 0;
1796 int align_start, align_end;
1797
1798 buf = data_buf;
1799 offset32 = offset;
1800 len32 = buf_size;
1801 align_end = 0;
1802 align_start = (offset32 & 3);
1803
1804 if (align_start) {
1805 offset32 &= ~3;
1806 len32 += align_start;
1807 rc = bce_nvram_read(sc, offset32, start, 4);
1808 if (rc)
1809 return rc;
1810 }
1811
1812 if (len32 & 3) {
1813 if (len32 > 4 || !align_start) {
1814 align_end = 4 - (len32 & 3);
1815 len32 += align_end;
1816 rc = bce_nvram_read(sc, offset32 + len32 - 4, end, 4);
1817 if (rc)
1818 return rc;
1819 }
1820 }
1821
1822 if (align_start || align_end) {
1823 buf = kmalloc(len32, M_DEVBUF, M_NOWAIT);
1824 if (buf == NULL)
1825 return ENOMEM;
1826 if (align_start)
1827 memcpy(buf, start, 4);
1828 if (align_end)
1829 memcpy(buf + len32 - 4, end, 4);
1830 memcpy(buf + align_start, data_buf, buf_size);
1831 }
1832
1833 written = 0;
1834 while (written < len32 && rc == 0) {
1835 uint32_t page_start, page_end, data_start, data_end;
1836 uint32_t addr, cmd_flags;
1837 int i;
1838 uint8_t flash_buffer[264];
1839
1840 /* Find the page_start addr */
1841 page_start = offset32 + written;
1842 page_start -= (page_start % sc->bce_flash_info->page_size);
1843 /* Find the page_end addr */
1844 page_end = page_start + sc->bce_flash_info->page_size;
1845 /* Find the data_start addr */
1846 data_start = (written == 0) ? offset32 : page_start;
1847 /* Find the data_end addr */
1848 data_end = (page_end > offset32 + len32) ? (offset32 + len32)
1849 : page_end;
1850
1851 /* Request access to the flash interface. */
1852 rc = bce_acquire_nvram_lock(sc);
1853 if (rc != 0)
1854 goto nvram_write_end;
1855
1856 /* Enable access to flash interface */
1857 bce_enable_nvram_access(sc);
1858
1859 cmd_flags = BCE_NVM_COMMAND_FIRST;
1860 if (sc->bce_flash_info->buffered == 0) {
1861 int j;
1862
1863 /*
1864 * Read the whole page into the buffer
1865 * (non-buffer flash only)
1866 */
1867 for (j = 0; j < sc->bce_flash_info->page_size; j += 4) {
1868 if (j == (sc->bce_flash_info->page_size - 4))
1869 cmd_flags |= BCE_NVM_COMMAND_LAST;
1870
1871 rc = bce_nvram_read_dword(sc, page_start + j,
1872 &flash_buffer[j],
1873 cmd_flags);
1874 if (rc)
1875 goto nvram_write_end;
1876
1877 cmd_flags = 0;
1878 }
1879 }
1880
1881 /* Enable writes to flash interface (unlock write-protect) */
1882 rc = bce_enable_nvram_write(sc);
1883 if (rc != 0)
1884 goto nvram_write_end;
1885
1886 /* Erase the page */
1887 rc = bce_nvram_erase_page(sc, page_start);
1888 if (rc != 0)
1889 goto nvram_write_end;
1890
1891 /* Re-enable the write again for the actual write */
1892 bce_enable_nvram_write(sc);
1893
1894 /* Loop to write back the buffer data from page_start to
1895 * data_start */
1896 i = 0;
1897 if (sc->bce_flash_info->buffered == 0) {
1898 for (addr = page_start; addr < data_start;
1899 addr += 4, i += 4) {
1900 rc = bce_nvram_write_dword(sc, addr,
1901 &flash_buffer[i],
1902 cmd_flags);
1903 if (rc != 0)
1904 goto nvram_write_end;
1905
1906 cmd_flags = 0;
1907 }
1908 }
1909
1910 /* Loop to write the new data from data_start to data_end */
1911 for (addr = data_start; addr < data_end; addr += 4, i++) {
1912 if (addr == page_end - 4 ||
1913 (sc->bce_flash_info->buffered &&
1914 addr == data_end - 4))
1915 cmd_flags |= BCE_NVM_COMMAND_LAST;
1916
1917 rc = bce_nvram_write_dword(sc, addr, buf, cmd_flags);
1918 if (rc != 0)
1919 goto nvram_write_end;
1920
1921 cmd_flags = 0;
1922 buf += 4;
1923 }
1924
1925 /* Loop to write back the buffer data from data_end
1926 * to page_end */
1927 if (sc->bce_flash_info->buffered == 0) {
1928 for (addr = data_end; addr < page_end;
1929 addr += 4, i += 4) {
1930 if (addr == page_end-4)
1931 cmd_flags = BCE_NVM_COMMAND_LAST;
1932
1933 rc = bce_nvram_write_dword(sc, addr,
1934 &flash_buffer[i], cmd_flags);
1935 if (rc != 0)
1936 goto nvram_write_end;
1937
1938 cmd_flags = 0;
1939 }
1940 }
1941
1942 /* Disable writes to flash interface (lock write-protect) */
1943 bce_disable_nvram_write(sc);
1944
1945 /* Disable access to flash interface */
1946 bce_disable_nvram_access(sc);
1947 bce_release_nvram_lock(sc);
1948
1949 /* Increment written */
1950 written += data_end - data_start;
1951 }
1952
1953 nvram_write_end:
1954 if (align_start || align_end)
1955 kfree(buf, M_DEVBUF);
1956 return rc;
1957 }
1958 #endif /* BCE_NVRAM_WRITE_SUPPORT */
1959
1960
1961 /****************************************************************************/
1962 /* Verifies that NVRAM is accessible and contains valid data. */
1963 /* */
1964 /* Reads the configuration data from NVRAM and verifies that the CRC is */
1965 /* correct. */
1966 /* */
1967 /* Returns: */
1968 /* 0 on success, positive value on failure. */
1969 /****************************************************************************/
1970 static int
1971 bce_nvram_test(struct bce_softc *sc)
1972 {
1973 uint32_t buf[BCE_NVRAM_SIZE / 4];
1974 uint32_t magic, csum;
1975 uint8_t *data = (uint8_t *)buf;
1976 int rc = 0;
1977
1978 /*
1979 * Check that the device NVRAM is valid by reading
1980 * the magic value at offset 0.
1981 */
1982 rc = bce_nvram_read(sc, 0, data, 4);
1983 if (rc != 0)
1984 return rc;
1985
1986 magic = be32toh(buf[0]);
1987 if (magic != BCE_NVRAM_MAGIC) {
1988 if_printf(&sc->arpcom.ac_if,
1989 "Invalid NVRAM magic value! Expected: 0x%08X, "
1990 "Found: 0x%08X\n", BCE_NVRAM_MAGIC, magic);
1991 return ENODEV;
1992 }
1993
1994 /*
1995 * Verify that the device NVRAM includes valid
1996 * configuration data.
1997 */
1998 rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE);
1999 if (rc != 0)
2000 return rc;
2001
2002 csum = ether_crc32_le(data, 0x100);
2003 if (csum != BCE_CRC32_RESIDUAL) {
2004 if_printf(&sc->arpcom.ac_if,
2005 "Invalid Manufacturing Information NVRAM CRC! "
2006 "Expected: 0x%08X, Found: 0x%08X\n",
2007 BCE_CRC32_RESIDUAL, csum);
2008 return ENODEV;
2009 }
2010
2011 csum = ether_crc32_le(data + 0x100, 0x100);
2012 if (csum != BCE_CRC32_RESIDUAL) {
2013 if_printf(&sc->arpcom.ac_if,
2014 "Invalid Feature Configuration Information "
2015 "NVRAM CRC! Expected: 0x%08X, Found: 08%08X\n",
2016 BCE_CRC32_RESIDUAL, csum);
2017 rc = ENODEV;
2018 }
2019 return rc;
2020 }
2021
2022
2023 /****************************************************************************/
2024 /* Free any DMA memory owned by the driver. */
2025 /* */
2026 /* Scans through each data structre that requires DMA memory and frees */
2027 /* the memory if allocated. */
2028 /* */
2029 /* Returns: */
2030 /* Nothing. */
2031 /****************************************************************************/
2032 static void
2033 bce_dma_free(struct bce_softc *sc)
2034 {
2035 int i;
2036
2037 /* Destroy the status block. */
2038 if (sc->status_tag != NULL) {
2039 if (sc->status_block != NULL) {
2040 bus_dmamap_unload(sc->status_tag, sc->status_map);
2041 bus_dmamem_free(sc->status_tag, sc->status_block,
2042 sc->status_map);
2043 }
2044 bus_dma_tag_destroy(sc->status_tag);
2045 }
2046
2047
2048 /* Destroy the statistics block. */
2049 if (sc->stats_tag != NULL) {
2050 if (sc->stats_block != NULL) {
2051 bus_dmamap_unload(sc->stats_tag, sc->stats_map);
2052 bus_dmamem_free(sc->stats_tag, sc->stats_block,
2053 sc->stats_map);
2054 }
2055 bus_dma_tag_destroy(sc->stats_tag);
2056 }
2057
2058 /* Destroy the TX buffer descriptor DMA stuffs. */
2059 if (sc->tx_bd_chain_tag != NULL) {
2060 for (i = 0; i < TX_PAGES; i++) {
2061 if (sc->tx_bd_chain[i] != NULL) {
2062 bus_dmamap_unload(sc->tx_bd_chain_tag,
2063 sc->tx_bd_chain_map[i]);
2064 bus_dmamem_free(sc->tx_bd_chain_tag,
2065 sc->tx_bd_chain[i],
2066 sc->tx_bd_chain_map[i]);
2067 }
2068 }
2069 bus_dma_tag_destroy(sc->tx_bd_chain_tag);
2070 }
2071
2072 /* Destroy the RX buffer descriptor DMA stuffs. */
2073 if (sc->rx_bd_chain_tag != NULL) {
2074 for (i = 0; i < RX_PAGES; i++) {
2075 if (sc->rx_bd_chain[i] != NULL) {
2076 bus_dmamap_unload(sc->rx_bd_chain_tag,
2077 sc->rx_bd_chain_map[i]);
2078 bus_dmamem_free(sc->rx_bd_chain_tag,
2079 sc->rx_bd_chain[i],
2080 sc->rx_bd_chain_map[i]);
2081 }
2082 }
2083 bus_dma_tag_destroy(sc->rx_bd_chain_tag);
2084 }
2085
2086 /* Destroy the TX mbuf DMA stuffs. */
2087 if (sc->tx_mbuf_tag != NULL) {
2088 for (i = 0; i < TOTAL_TX_BD; i++) {
2089 /* Must have been unloaded in bce_stop() */
2090 KKASSERT(sc->tx_mbuf_ptr[i] == NULL);
2091 bus_dmamap_destroy(sc->tx_mbuf_tag,
2092 sc->tx_mbuf_map[i]);
2093 }
2094 bus_dma_tag_destroy(sc->tx_mbuf_tag);
2095 }
2096
2097 /* Destroy the RX mbuf DMA stuffs. */
2098 if (sc->rx_mbuf_tag != NULL) {
2099 for (i = 0; i < TOTAL_RX_BD; i++) {
2100 /* Must have been unloaded in bce_stop() */
2101 KKASSERT(sc->rx_mbuf_ptr[i] == NULL);
2102 bus_dmamap_destroy(sc->rx_mbuf_tag,
2103 sc->rx_mbuf_map[i]);
2104 }
2105 bus_dma_tag_destroy(sc->rx_mbuf_tag);
2106 }
2107
2108 /* Destroy the parent tag */
2109 if (sc->parent_tag != NULL)
2110 bus_dma_tag_destroy(sc->parent_tag);
2111 }
2112
2113
2114 /****************************************************************************/
2115 /* Get DMA memory from the OS. */
2116 /* */
2117 /* Validates that the OS has provided DMA buffers in response to a */
2118 /* bus_dmamap_load() call and saves the physical address of those buffers. */
2119 /* When the callback is used the OS will return 0 for the mapping function */
2120 /* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any */
2121 /* failures back to the caller. */
2122 /* */
2123 /* Returns: */
2124 /* Nothing. */
2125 /****************************************************************************/
2126 static void
2127 bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2128 {
2129 bus_addr_t *busaddr = arg;
2130
2131 /*
2132 * Simulate a mapping failure.
2133 * XXX not correct.
2134 */
2135 DBRUNIF(DB_RANDOMTRUE(bce_debug_dma_map_addr_failure),
2136 kprintf("bce: %s(%d): Simulating DMA mapping error.\n",
2137 __FILE__, __LINE__);
2138 error = ENOMEM);
2139
2140 /* Check for an error and signal the caller that an error occurred. */
2141 if (error)
2142 return;
2143
2144 KASSERT(nseg == 1, ("only one segment is allowed\n"));
2145 *busaddr = segs->ds_addr;
2146 }
2147
2148
2149 static void
2150 bce_dma_map_mbuf(void *arg, bus_dma_segment_t *segs, int nsegs,
2151 bus_size_t mapsz __unused, int error)
2152 {
2153 struct bce_dmamap_arg *ctx = arg;
2154 int i;
2155
2156 if (error)
2157 return;
2158
2159 if (nsegs > ctx->bce_maxsegs) {
2160 ctx->bce_maxsegs = 0;
2161 return;
2162 }
2163
2164 ctx->bce_maxsegs = nsegs;
2165 for (i = 0; i < nsegs; ++i)
2166 ctx->bce_segs[i] = segs[i];
2167 }
2168
2169
2170 /****************************************************************************/
2171 /* Allocate any DMA memory needed by the driver. */
2172 /* */
2173 /* Allocates DMA memory needed for the various global structures needed by */
2174 /* hardware. */
2175 /* */
2176 /* Returns: */
2177 /* 0 for success, positive value for failure. */
2178 /****************************************************************************/
2179 static int
2180 bce_dma_alloc(struct bce_softc *sc)
2181 {
2182 struct ifnet *ifp = &sc->arpcom.ac_if;
2183 int i, j, rc = 0;
2184 bus_addr_t busaddr;
2185
2186 /*
2187 * Allocate the parent bus DMA tag appropriate for PCI.
2188 */
2189 rc = bus_dma_tag_create(NULL, 1, BCE_DMA_BOUNDARY,
2190 sc->max_bus_addr, BUS_SPACE_MAXADDR,
2191 NULL, NULL,
2192 MAXBSIZE, BUS_SPACE_UNRESTRICTED,
2193 BUS_SPACE_MAXSIZE_32BIT,
2194 0, &sc->parent_tag);
2195 if (rc != 0) {
2196 if_printf(ifp, "Could not allocate parent DMA tag!\n");
2197 return rc;
2198 }
2199
2200 /*
2201 * Create a DMA tag for the status block, allocate and clear the
2202 * memory, map the memory into DMA space, and fetch the physical
2203 * address of the block.
2204 */
2205 rc = bus_dma_tag_create(sc->parent_tag,
2206 BCE_DMA_ALIGN, BCE_DMA_BOUNDARY,
2207 sc->max_bus_addr, BUS_SPACE_MAXADDR,
2208 NULL, NULL,
2209 BCE_STATUS_BLK_SZ, 1, BCE_STATUS_BLK_SZ,
2210 0, &sc->status_tag);
2211 if (rc != 0) {
2212 if_printf(ifp, "Could not allocate status block DMA tag!\n");
2213 return rc;
2214 }
2215
2216 rc = bus_dmamem_alloc(sc->status_tag, (void **)&sc->status_block,
2217 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2218 &sc->status_map);
2219 if (rc != 0) {
2220 if_printf(ifp, "Could not allocate status block DMA memory!\n");
2221 return rc;
2222 }
2223
2224 rc = bus_dmamap_load(sc->status_tag, sc->status_map,
2225 sc->status_block, BCE_STATUS_BLK_SZ,
2226 bce_dma_map_addr, &busaddr, BUS_DMA_WAITOK);
2227 if (rc != 0) {
2228 if_printf(ifp, "Could not map status block DMA memory!\n");
2229 bus_dmamem_free(sc->status_tag, sc->status_block,
2230 sc->status_map);
2231 sc->status_block = NULL;
2232 return rc;
2233 }
2234
2235 sc->status_block_paddr = busaddr;
2236 /* DRC - Fix for 64 bit addresses. */
2237 DBPRINT(sc, BCE_INFO, "status_block_paddr = 0x%08X\n",
2238 (uint32_t)sc->status_block_paddr);
2239
2240 /*
2241 * Create a DMA tag for the statistics block, allocate and clear the
2242 * memory, map the memory into DMA space, and fetch the physical
2243 * address of the block.
2244 */
2245 rc = bus_dma_tag_create(sc->parent_tag,
2246 BCE_DMA_ALIGN, BCE_DMA_BOUNDARY,
2247 sc->max_bus_addr, BUS_SPACE_MAXADDR,
2248 NULL, NULL,
2249 BCE_STATS_BLK_SZ, 1, BCE_STATS_BLK_SZ,
2250 0, &sc->stats_tag);
2251 if (rc != 0) {
2252 if_printf(ifp, "Could not allocate "
2253 "statistics block DMA tag!\n");
2254 return rc;
2255 }
2256
2257 rc = bus_dmamem_alloc(sc->stats_tag, (void **)&sc->stats_block,
2258 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2259 &sc->stats_map);
2260 if (rc != 0) {
2261 if_printf(ifp, "Could not allocate "
2262 "statistics block DMA memory!\n");
2263 return rc;
2264 }
2265
2266 rc = bus_dmamap_load(sc->stats_tag, sc->stats_map,
2267 sc->stats_block, BCE_STATS_BLK_SZ,
2268 bce_dma_map_addr, &busaddr, BUS_DMA_WAITOK);
2269 if (rc != 0) {
2270 if_printf(ifp, "Could not map statistics block DMA memory!\n");
2271 bus_dmamem_free(sc->stats_tag, sc->stats_block, sc->stats_map);
2272 sc->stats_block = NULL;
2273 return rc;
2274 }
2275
2276 sc->stats_block_paddr = busaddr;
2277 /* DRC - Fix for 64 bit address. */
2278 DBPRINT(sc, BCE_INFO, "stats_block_paddr = 0x%08X\n",
2279 (uint32_t)sc->stats_block_paddr);
2280
2281 /*
2282 * Create a DMA tag for the TX buffer descriptor chain,
2283 * allocate and clear the memory, and fetch the
2284 * physical address of the block.
2285 */
2286 rc = bus_dma_tag_create(sc->parent_tag,
2287 BCM_PAGE_SIZE, BCE_DMA_BOUNDARY,
2288 sc->max_bus_addr, BUS_SPACE_MAXADDR,
2289 NULL, NULL,
2290 BCE_TX_CHAIN_PAGE_SZ, 1, BCE_TX_CHAIN_PAGE_SZ,
2291 0, &sc->tx_bd_chain_tag);
2292 if (rc != 0) {
2293 if_printf(ifp, "Could not allocate "
2294 "TX descriptor chain DMA tag!\n");
2295 return rc;
2296 }
2297
2298 for (i = 0; i < TX_PAGES; i++) {
2299 rc = bus_dmamem_alloc(sc->tx_bd_chain_tag,
2300 (void **)&sc->tx_bd_chain[i],
2301 BUS_DMA_WAITOK, &sc->tx_bd_chain_map[i]);
2302 if (rc != 0) {
2303 if_printf(ifp, "Could not allocate %dth TX descriptor "
2304 "chain DMA memory!\n", i);
2305 return rc;
2306 }
2307
2308 rc = bus_dmamap_load(sc->tx_bd_chain_tag,
2309 sc->tx_bd_chain_map[i],
2310 sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ,
2311 bce_dma_map_addr, &busaddr,
2312 BUS_DMA_WAITOK);
2313 if (rc != 0) {
2314 if_printf(ifp, "Could not map %dth TX descriptor "
2315 "chain DMA memory!\n", i);
2316 bus_dmamem_free(sc->tx_bd_chain_tag,
2317 sc->tx_bd_chain[i],
2318 sc->tx_bd_chain_map[i]);
2319 sc->tx_bd_chain[i] = NULL;
2320 return rc;
2321 }
2322
2323 sc->tx_bd_chain_paddr[i] = busaddr;
2324 /* DRC - Fix for 64 bit systems. */
2325 DBPRINT(sc, BCE_INFO, "tx_bd_chain_paddr[%d] = 0x%08X\n",
2326 i, (uint32_t)sc->tx_bd_chain_paddr[i]);
2327 }
2328
2329 /* Create a DMA tag for TX mbufs. */
2330 rc = bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY,
2331 sc->max_bus_addr, BUS_SPACE_MAXADDR,
2332 NULL, NULL,
2333 MCLBYTES * BCE_MAX_SEGMENTS,
2334 BCE_MAX_SEGMENTS, MCLBYTES,
2335 0, &sc->tx_mbuf_tag);
2336 if (rc != 0) {
2337 if_printf(ifp, "Could not allocate TX mbuf DMA tag!\n");
2338 return rc;
2339 }
2340
2341 /* Create DMA maps for the TX mbufs clusters. */
2342 for (i = 0; i < TOTAL_TX_BD; i++) {
2343 rc = bus_dmamap_create(sc->tx_mbuf_tag, BUS_DMA_WAITOK,
2344 &sc->tx_mbuf_map[i]);
2345 if (rc != 0) {
2346 for (j = 0; j < i; ++j) {
2347 bus_dmamap_destroy(sc->tx_mbuf_tag,
2348 sc->tx_mbuf_map[i]);
2349 }
2350 bus_dma_tag_destroy(sc->tx_mbuf_tag);
2351 sc->tx_mbuf_tag = NULL;
2352
2353 if_printf(ifp, "Unable to create "
2354 "%dth TX mbuf DMA map!\n", i);
2355 return rc;
2356 }
2357 }
2358
2359 /*
2360 * Create a DMA tag for the RX buffer descriptor chain,
2361 * allocate and clear the memory, and fetch the physical
2362 * address of the blocks.
2363 */
2364 rc = bus_dma_tag_create(sc->parent_tag,
2365 BCM_PAGE_SIZE, BCE_DMA_BOUNDARY,
2366 sc->max_bus_addr, BUS_SPACE_MAXADDR,
2367 NULL, NULL,
2368 BCE_RX_CHAIN_PAGE_SZ, 1, BCE_RX_CHAIN_PAGE_SZ,
2369 0, &sc->rx_bd_chain_tag);
2370 if (rc != 0) {
2371 if_printf(ifp, "Could not allocate "
2372 "RX descriptor chain DMA tag!\n");
2373 return rc;
2374 }
2375
2376 for (i = 0; i < RX_PAGES; i++) {
2377 rc = bus_dmamem_alloc(sc->rx_bd_chain_tag,
2378 (void **)&sc->rx_bd_chain[i],
2379 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2380 &sc->rx_bd_chain_map[i]);
2381 if (rc != 0) {
2382 if_printf(ifp, "Could not allocate %dth RX descriptor "
2383 "chain DMA memory!\n", i);
2384 return rc;
2385 }
2386
2387 rc = bus_dmamap_load(sc->rx_bd_chain_tag,
2388 sc->rx_bd_chain_map[i],
2389 sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ,
2390 bce_dma_map_addr, &busaddr,
2391 BUS_DMA_WAITOK);
2392 if (rc != 0) {
2393 if_printf(ifp, "Could not map %dth RX descriptor "
2394 "chain DMA memory!\n", i);
2395 bus_dmamem_free(sc->rx_bd_chain_tag,
2396 sc->rx_bd_chain[i],
2397 sc->rx_bd_chain_map[i]);
2398 sc->rx_bd_chain[i] = NULL;
2399 return rc;
2400 }
2401
2402 sc->rx_bd_chain_paddr[i] = busaddr;
2403 /* DRC - Fix for 64 bit systems. */
2404 DBPRINT(sc, BCE_INFO, "rx_bd_chain_paddr[%d] = 0x%08X\n",
2405 i, (uint32_t)sc->rx_bd_chain_paddr[i]);
2406 }
2407
2408 /* Create a DMA tag for RX mbufs. */
2409 rc = bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY,
2410 sc->max_bus_addr, BUS_SPACE_MAXADDR,
2411 NULL, NULL,
2412 MCLBYTES, 1/* BCE_MAX_SEGMENTS */, MCLBYTES,
2413 0, &sc->rx_mbuf_tag);
2414 if (rc != 0) {
2415 if_printf(ifp, "Could not allocate RX mbuf DMA tag!\n");
2416 return rc;
2417 }
2418
2419 /* Create DMA maps for the RX mbuf clusters. */
2420 for (i = 0; i < TOTAL_RX_BD; i++) {
2421 rc = bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_WAITOK,
2422 &sc->rx_mbuf_map[i]);
2423 if (rc != 0) {
2424 for (j = 0; j < i; ++j) {
2425 bus_dmamap_destroy(sc->rx_mbuf_tag,
2426 sc->rx_mbuf_map[j]);
2427 }
2428 bus_dma_tag_destroy(sc->rx_mbuf_tag);
2429 sc->rx_mbuf_tag = NULL;
2430
2431 if_printf(ifp, "Unable to create "
2432 "%dth RX mbuf DMA map!\n", i);
2433 return rc;
2434 }
2435 }
2436 return 0;
2437 }
2438
2439
2440 /****************************************************************************/
2441 /* Firmware synchronization. */
2442 /* */
2443 /* Before performing certain events such as a chip reset, synchronize with */
2444 /* the firmware first. */
2445 /* */
2446 /* Returns: */
2447 /* 0 for success, positive value for failure. */
2448 /****************************************************************************/
2449 static int
2450 bce_fw_sync(struct bce_softc *sc, uint32_t msg_data)
2451 {
2452 int i, rc = 0;
2453 uint32_t val;
2454
2455 /* Don't waste any time if we've timed out before. */
2456 if (sc->bce_fw_timed_out)
2457 return EBUSY;
2458
2459 /* Increment the message sequence number. */
2460 sc->bce_fw_wr_seq++;
2461 msg_data |= sc->bce_fw_wr_seq;
2462
2463 DBPRINT(sc, BCE_VERBOSE, "bce_fw_sync(): msg_data = 0x%08X\n", msg_data);
2464
2465 /* Send the message to the bootcode driver mailbox. */
2466 REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_MB, msg_data);
2467
2468 /* Wait for the bootcode to acknowledge the message. */
2469 for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) {
2470 /* Check for a response in the bootcode firmware mailbox. */
2471 val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_FW_MB);
2472 if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ))
2473 break;
2474 DELAY(1000);
2475 }
2476
2477 /* If we've timed out, tell the bootcode that we've stopped waiting. */
2478 if ((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ) &&
2479 (msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0) {
2480 if_printf(&sc->arpcom.ac_if,
2481 "Firmware synchronization timeout! "
2482 "msg_data = 0x%08X\n", msg_data);
2483
2484 msg_data &= ~BCE_DRV_MSG_CODE;
2485 msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT;
2486
2487 REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_MB, msg_data);
2488
2489 sc->bce_fw_timed_out = 1;
2490 rc = EBUSY;
2491 }
2492 return rc;
2493 }
2494
2495
2496 /****************************************************************************/
2497 /* Load Receive Virtual 2 Physical (RV2P) processor firmware. */
2498 /* */
2499 /* Returns: */
2500 /* Nothing. */
2501 /****************************************************************************/
2502 static void
2503 bce_load_rv2p_fw(struct bce_softc *sc, uint32_t *rv2p_code,
2504 uint32_t rv2p_code_len, uint32_t rv2p_proc)
2505 {
2506 int i;
2507 uint32_t val;
2508
2509 for (i = 0; i < rv2p_code_len; i += 8) {
2510 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code);
2511 rv2p_code++;
2512 REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code);
2513 rv2p_code++;
2514
2515 if (rv2p_proc == RV2P_PROC1) {
2516 val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR;
2517 REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val);
2518 } else {
2519 val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR;
2520 REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val);
2521 }
2522 }
2523
2524 /* Reset the processor, un-stall is done later. */
2525 if (rv2p_proc == RV2P_PROC1)
2526 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET);
2527 else
2528 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET);
2529 }
2530
2531
2532 /****************************************************************************/
2533 /* Load RISC processor firmware. */
2534 /* */
2535 /* Loads firmware from the file if_bcefw.h into the scratchpad memory */
2536 /* associated with a particular processor. */
2537 /* */
2538 /* Returns: */
2539 /* Nothing. */
2540 /****************************************************************************/
2541 static void
2542 bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg,
2543 struct fw_info *fw)
2544 {
2545 uint32_t offset, val;
2546 int j;
2547
2548 /* Halt the CPU. */
2549 val = REG_RD_IND(sc, cpu_reg->mode);
2550 val |= cpu_reg->mode_value_halt;
2551 REG_WR_IND(sc, cpu_reg->mode, val);
2552 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
2553
2554 /* Load the Text area. */
2555 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
2556 if (fw->text) {
2557 for (j = 0; j < (fw->text_len / 4); j++, offset += 4)
2558 REG_WR_IND(sc, offset, fw->text[j]);
2559 }
2560
2561 /* Load the Data area. */
2562 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
2563 if (fw->data) {
2564 for (j = 0; j < (fw->data_len / 4); j++, offset += 4)
2565 REG_WR_IND(sc, offset, fw->data[j]);
2566 }
2567
2568 /* Load the SBSS area. */
2569 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
2570 if (fw->sbss) {
2571 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4)
2572 REG_WR_IND(sc, offset, fw->sbss[j]);
2573 }
2574
2575 /* Load the BSS area. */
2576 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
2577 if (fw->bss) {
2578 for (j = 0; j < (fw->bss_len/4); j++, offset += 4)
2579 REG_WR_IND(sc, offset, fw->bss[j]);
2580 }
2581
2582 /* Load the Read-Only area. */
2583 offset = cpu_reg->spad_base +
2584 (fw->rodata_addr - cpu_reg->mips_view_base);
2585 if (fw->rodata) {
2586 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4)
2587 REG_WR_IND(sc, offset, fw->rodata[j]);
2588 }
2589
2590 /* Clear the pre-fetch instruction. */
2591 REG_WR_IND(sc, cpu_reg->inst, 0);
2592 REG_WR_IND(sc, cpu_reg->pc, fw->start_addr);
2593
2594 /* Start the CPU. */
2595 val = REG_RD_IND(sc, cpu_reg->mode);
2596 val &= ~cpu_reg->mode_value_halt;
2597 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
2598 REG_WR_IND(sc, cpu_reg->mode, val);
2599 }
2600
2601
2602 /****************************************************************************/
2603 /* Initialize the RV2P, RX, TX, TPAT, and COM CPUs. */
2604 /* */
2605 /* Loads the firmware for each CPU and starts the CPU. */
2606 /* */
2607 /* Returns: */
2608 /* Nothing. */
2609 /****************************************************************************/
2610 static void
2611 bce_init_cpus(struct bce_softc *sc)
2612 {
2613 struct cpu_reg cpu_reg;
2614 struct fw_info fw;
2615
2616 /* Initialize the RV2P processor. */
2617 bce_load_rv2p_fw(sc, bce_rv2p_proc1, sizeof(bce_rv2p_proc1), RV2P_PROC1);
2618 bce_load_rv2p_fw(sc, bce_rv2p_proc2, sizeof(bce_rv2p_proc2), RV2P_PROC2);
2619
2620 /* Initialize the RX Processor. */
2621 cpu_reg.mode = BCE_RXP_CPU_MODE;
2622 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
2623 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
2624 cpu_reg.state = BCE_RXP_CPU_STATE;
2625 cpu_reg.state_value_clear = 0xffffff;
2626 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
2627 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
2628 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
2629 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
2630 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
2631 cpu_reg.spad_base = BCE_RXP_SCRATCH;
2632 cpu_reg.mips_view_base = 0x8000000;
2633
2634 fw.ver_major = bce_RXP_b06FwReleaseMajor;
2635 fw.ver_minor = bce_RXP_b06FwReleaseMinor;
2636 fw.ver_fix = bce_RXP_b06FwReleaseFix;
2637 fw.start_addr = bce_RXP_b06FwStartAddr;
2638
2639 fw.text_addr = bce_RXP_b06FwTextAddr;
2640 fw.text_len = bce_RXP_b06FwTextLen;
2641 fw.text_index = 0;
2642 fw.text = bce_RXP_b06FwText;
2643
2644 fw.data_addr = bce_RXP_b06FwDataAddr;
2645 fw.data_len = bce_RXP_b06FwDataLen;
2646 fw.data_index = 0;
2647 fw.data = bce_RXP_b06FwData;
2648
2649 fw.sbss_addr = bce_RXP_b06FwSbssAddr;
2650 fw.sbss_len = bce_RXP_b06FwSbssLen;
2651 fw.sbss_index = 0;
2652 fw.sbss = bce_RXP_b06FwSbss;
2653
2654 fw.bss_addr = bce_RXP_b06FwBssAddr;
2655 fw.bss_len = bce_RXP_b06FwBssLen;
2656 fw.bss_index = 0;
2657 fw.bss = bce_RXP_b06FwBss;
2658
2659 fw.rodata_addr = bce_RXP_b06FwRodataAddr;
2660 fw.rodata_len = bce_RXP_b06FwRodataLen;
2661 fw.rodata_index = 0;
2662 fw.rodata = bce_RXP_b06FwRodata;
2663
2664 DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n");
2665 bce_load_cpu_fw(sc, &cpu_reg, &fw);
2666
2667 /* Initialize the TX Processor. */
2668 cpu_reg.mode = BCE_TXP_CPU_MODE;
2669 cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT;
2670 cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA;
2671 cpu_reg.state = BCE_TXP_CPU_STATE;
2672 cpu_reg.state_value_clear = 0xffffff;
2673 cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE;
2674 cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK;
2675 cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER;
2676 cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION;
2677 cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT;
2678 cpu_reg.spad_base = BCE_TXP_SCRATCH;
2679 cpu_reg.mips_view_base = 0x8000000;
2680
2681 fw.ver_major = bce_TXP_b06FwReleaseMajor;
2682 fw.ver_minor = bce_TXP_b06FwReleaseMinor;
2683 fw.ver_fix = bce_TXP_b06FwReleaseFix;
2684 fw.start_addr = bce_TXP_b06FwStartAddr;
2685
2686 fw.text_addr = bce_TXP_b06FwTextAddr;
2687 fw.text_len = bce_TXP_b06FwTextLen;
2688 fw.text_index = 0;
2689 fw.text = bce_TXP_b06FwText;
2690
2691 fw.data_addr = bce_TXP_b06FwDataAddr;
2692 fw.data_len = bce_TXP_b06FwDataLen;
2693 fw.data_index = 0;
2694 fw.data = bce_TXP_b06FwData;
2695
2696 fw.sbss_addr = bce_TXP_b06FwSbssAddr;
2697 fw.sbss_len = bce_TXP_b06FwSbssLen;
2698 fw.sbss_index = 0;
2699 fw.sbss = bce_TXP_b06FwSbss;
2700
2701 fw.bss_addr = bce_TXP_b06FwBssAddr;
2702 fw.bss_len = bce_TXP_b06FwBssLen;
2703 fw.bss_index = 0;
2704 fw.bss = bce_TXP_b06FwBss;
2705
2706 fw.rodata_addr = bce_TXP_b06FwRodataAddr;
2707 fw.rodata_len = bce_TXP_b06FwRodataLen;
2708 fw.rodata_index = 0;
2709 fw.rodata = bce_TXP_b06FwRodata;
2710
2711 DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n");
2712 bce_load_cpu_fw(sc, &cpu_reg, &fw);
2713
2714 /* Initialize the TX Patch-up Processor. */
2715 cpu_reg.mode = BCE_TPAT_CPU_MODE;
2716 cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT;
2717 cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA;
2718 cpu_reg.state = BCE_TPAT_CPU_STATE;
2719 cpu_reg.state_value_clear = 0xffffff;
2720 cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE;
2721 cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK;
2722 cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER;
2723 cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION;
2724 cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT;
2725 cpu_reg.spad_base = BCE_TPAT_SCRATCH;
2726 cpu_reg.mips_view_base = 0x8000000;
2727
2728 fw.ver_major = bce_TPAT_b06FwReleaseMajor;
2729 fw.ver_minor = bce_TPAT_b06FwReleaseMinor;
2730 fw.ver_fix = bce_TPAT_b06FwReleaseFix;
2731 fw.start_addr = bce_TPAT_b06FwStartAddr;
2732
2733 fw.text_addr = bce_TPAT_b06FwTextAddr;
2734 fw.text_len = bce_TPAT_b06FwTextLen;
2735 fw.text_index = 0;
2736 fw.text = bce_TPAT_b06FwText;
2737
2738 fw.data_addr = bce_TPAT_b06FwDataAddr;
2739 fw.data_len = bce_TPAT_b06FwDataLen;
2740 fw.data_index = 0;
2741 fw.data = bce_TPAT_b06FwData;
2742
2743 fw.sbss_addr = bce_TPAT_b06FwSbssAddr;
2744 fw.sbss_len = bce_TPAT_b06FwSbssLen;
2745 fw.sbss_index = 0;
2746 fw.sbss = bce_TPAT_b06FwSbss;
2747
2748 fw.bss_addr = bce_TPAT_b06FwBssAddr;
2749 fw.bss_len = bce_TPAT_b06FwBssLen;
2750 fw.bss_index = 0;
2751 fw.bss = bce_TPAT_b06FwBss;
2752
2753 fw.rodata_addr = bce_TPAT_b06FwRodataAddr;
2754 fw.rodata_len = bce_TPAT_b06FwRodataLen;
2755 fw.rodata_index = 0;
2756 fw.rodata = bce_TPAT_b06FwRodata;
2757
2758 DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n");
2759 bce_load_cpu_fw(sc, &cpu_reg, &fw);
2760
2761 /* Initialize the Completion Processor. */
2762 cpu_reg.mode = BCE_COM_CPU_MODE;
2763 cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT;
2764 cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA;
2765 cpu_reg.state = BCE_COM_CPU_STATE;
2766 cpu_reg.state_value_clear = 0xffffff;
2767 cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE;
2768 cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK;
2769 cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER;
2770 cpu_reg.inst = BCE_COM_CPU_INSTRUCTION;
2771 cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT;
2772 cpu_reg.spad_base = BCE_COM_SCRATCH;
2773 cpu_reg.mips_view_base = 0x8000000;
2774
2775 fw.ver_major = bce_COM_b06FwReleaseMajor;
2776 fw.ver_minor = bce_COM_b06FwReleaseMinor;
2777 fw.ver_fix = bce_COM_b06FwReleaseFix;
2778 fw.start_addr = bce_COM_b06FwStartAddr;
2779
2780 fw.text_addr = bce_COM_b06FwTextAddr;
2781 fw.text_len = bce_COM_b06FwTextLen;
2782 fw.text_index = 0;
2783 fw.text = bce_COM_b06FwText;
2784
2785 fw.data_addr = bce_COM_b06FwDataAddr;
2786 fw.data_len = bce_COM_b06FwDataLen;
2787 fw.data_index = 0;
2788 fw.data = bce_COM_b06FwData;
2789
2790 fw.sbss_addr = bce_COM_b06FwSbssAddr;
2791 fw.sbss_len = bce_COM_b06FwSbssLen;
2792 fw.sbss_index = 0;
2793 fw.sbss = bce_COM_b06FwSbss;
2794
2795 fw.bss_addr = bce_COM_b06FwBssAddr;
2796 fw.bss_len = bce_COM_b06FwBssLen;
2797 fw.bss_index = 0;
2798 fw.bss = bce_COM_b06FwBss;
2799
2800 fw.rodata_addr = bce_COM_b06FwRodataAddr;
2801 fw.rodata_len = bce_COM_b06FwRodataLen;
2802 fw.rodata_index = 0;
2803 fw.rodata = bce_COM_b06FwRodata;
2804
2805 DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n");
2806 bce_load_cpu_fw(sc, &cpu_reg, &fw);
2807 }
2808
2809
2810 /****************************************************************************/
2811 /* Initialize context memory. */
2812 /* */
2813 /* Clears the memory associated with each Context ID (CID). */
2814 /* */
2815 /* Returns: */
2816 /* Nothing. */
2817 /****************************************************************************/
2818 static void
2819 bce_init_ctx(struct bce_softc *sc)
2820 {
2821 uint32_t vcid = 96;
2822
2823 while (vcid) {
2824 uint32_t vcid_addr, pcid_addr, offset;
2825 int i;
2826
2827 vcid--;
2828
2829 vcid_addr = GET_CID_ADDR(vcid);
2830 pcid_addr = vcid_addr;
2831
2832 for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) {
2833 vcid_addr += (i << PHY_CTX_SHIFT);
2834 pcid_addr += (i << PHY_CTX_SHIFT);
2835
2836 REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr);
2837 REG_WR(sc, BCE_CTX_PAGE_TBL, pcid_addr);
2838
2839 /* Zero out the context. */
2840 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
2841 CTX_WR(sc, vcid_addr, offset, 0);
2842 }
2843 }
2844 }
2845
2846
2847 /****************************************************************************/
2848 /* Fetch the permanent MAC address of the controller. */
2849 /* */
2850 /* Returns: */
2851 /* Nothing. */
2852 /****************************************************************************/
2853 static void
2854 bce_get_mac_addr(struct bce_softc *sc)
2855 {
2856 uint32_t mac_lo = 0, mac_hi = 0;
2857
2858 /*
2859 * The NetXtreme II bootcode populates various NIC
2860 * power-on and runtime configuration items in a
2861 * shared memory area. The factory configured MAC
2862 * address is available from both NVRAM and the
2863 * shared memory area so we'll read the value from
2864 * shared memory for speed.
2865 */
2866
2867 mac_hi = REG_RD_IND(sc, sc->bce_shmem_base + BCE_PORT_HW_CFG_MAC_UPPER);
2868 mac_lo = REG_RD_IND(sc, sc->bce_shmem_base + BCE_PORT_HW_CFG_MAC_LOWER);
2869
2870 if (mac_lo == 0 && mac_hi == 0) {
2871 if_printf(&sc->arpcom.ac_if, "Invalid Ethernet address!\n");
2872 } else {
2873 sc->eaddr[0] = (u_char)(mac_hi >> 8);
2874 sc->eaddr[1] = (u_char)(mac_hi >> 0);
2875 sc->eaddr[2] = (u_char)(mac_lo >> 24);
2876 sc->eaddr[3] = (u_char)(mac_lo >> 16);
2877 sc->eaddr[4] = (u_char)(mac_lo >> 8);
2878 sc->eaddr[5] = (u_char)(mac_lo >> 0);
2879 }
2880
2881 DBPRINT(sc, BCE_INFO, "Permanent Ethernet address = %6D\n", sc->eaddr, ":");
2882 }
2883
2884
2885 /****************************************************************************/
2886 /* Program the MAC address. */
2887 /* */
2888 /* Returns: */
2889 /* Nothing. */
2890 /****************************************************************************/
2891 static void
2892 bce_set_mac_addr(struct bce_softc *sc)
2893 {
2894 const uint8_t *mac_addr = sc->eaddr;
2895 uint32_t val;
2896
2897 DBPRINT(sc, BCE_INFO, "Setting Ethernet address = %6D\n",
2898 sc->eaddr, ":");
2899
2900 val = (mac_addr[0] << 8) | mac_addr[1];
2901 REG_WR(sc, BCE_EMAC_MAC_MATCH0, val);
2902
2903 val = (mac_addr[2] << 24) |
2904 (mac_addr[3] << 16) |
2905 (mac_addr[4] << 8) |
2906 mac_addr[5];
2907 REG_WR(sc, BCE_EMAC_MAC_MATCH1, val);
2908 }
2909
2910
2911 /****************************************************************************/
2912 /* Stop the controller. */
2913 /* */
2914 /* Returns: */
2915 /* Nothing. */
2916 /****************************************************************************/
2917 static void
2918 bce_stop(struct bce_softc *sc)
2919 {
2920 struct ifnet *ifp = &sc->arpcom.ac_if;
2921 struct mii_data *mii = device_get_softc(sc->bce_miibus);
2922 struct ifmedia_entry *ifm;
2923 int mtmp, itmp;
2924
2925 ASSERT_SERIALIZED(ifp->if_serializer);
2926
2927 callout_stop(&sc->bce_stat_ch);
2928
2929 /* Disable the transmit/receive blocks. */
2930 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, 0x5ffffff);
2931 REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
2932 DELAY(20);
2933
2934 bce_disable_intr(sc);
2935
2936 /* Tell firmware that the driver is going away. */
2937 bce_reset(sc, BCE_DRV_MSG_CODE_SUSPEND_NO_WOL);
2938
2939 /* Free the RX lists. */
2940 bce_free_rx_chain(sc);
2941
2942 /* Free TX buffers. */
2943 bce_free_tx_chain(sc);
2944
2945 /*
2946 * Isolate/power down the PHY, but leave the media selection
2947 * unchanged so that things will be put back to normal when
2948 * we bring the interface back up.
2949 *
2950 * 'mii' may be NULL if bce_stop() is called by bce_detach().
2951 */
2952 if (mii != NULL) {
2953 itmp = ifp->if_flags;
2954 ifp->if_flags |= IFF_UP;
2955 ifm = mii->mii_media.ifm_cur;
2956 mtmp = ifm->ifm_media;
2957 ifm->ifm_media = IFM_ETHER | IFM_NONE;
2958 mii_mediachg(mii);
2959 ifm->ifm_media = mtmp;
2960 ifp->if_flags = itmp;
2961 }
2962
2963 sc->bce_link = 0;
2964 sc->bce_coalchg_mask = 0;
2965
2966 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2967 ifp->if_timer = 0;
2968
2969 bce_mgmt_init(sc);
2970 }
2971
2972
2973 static int
2974 bce_reset(struct bce_softc *sc, uint32_t reset_code)
2975 {
2976 uint32_t val;
2977 int i, rc = 0;
2978
2979 /* Wait for pending PCI transactions to complete. */
2980 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS,
2981 BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
2982 BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
2983 BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
2984 BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
2985 val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
2986 DELAY(5);
2987
2988 /* Assume bootcode is running. */
2989 sc->bce_fw_timed_out = 0;
2990
2991 /* Give the firmware a chance to prepare for the reset. */
2992 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code);
2993 if (rc) {
2994 if_printf(&sc->arpcom.ac_if,
2995 "Firmware is not ready for reset\n");
2996 return rc;
2997 }
2998
2999 /* Set a firmware reminder that this is a soft reset. */
3000 REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_RESET_SIGNATURE,
3001 BCE_DRV_RESET_SIGNATURE_MAGIC);
3002
3003 /* Dummy read to force the chip to complete all current transactions. */
3004 val = REG_RD(sc, BCE_MISC_ID);
3005
3006 /* Chip reset. */
3007 val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3008 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3009 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3010 REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val);
3011
3012 /* Allow up to 30us for reset to complete. */
3013 for (i = 0; i < 10; i++) {
3014 val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG);
3015 if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3016 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) {
3017 break;
3018 }
3019 DELAY(10);
3020 }
3021
3022 /* Check that reset completed successfully. */
3023 if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3024 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
3025 if_printf(&sc->arpcom.ac_if, "Reset failed!\n");
3026 return EBUSY;
3027 }
3028
3029 /* Make sure byte swapping is properly configured. */
3030 val = REG_RD(sc, BCE_PCI_SWAP_DIAG0);
3031 if (val != 0x01020304) {
3032 if_printf(&sc->arpcom.ac_if, "Byte swap is incorrect!\n");
3033 return ENODEV;
3034 }
3035
3036 /* Just completed a reset, assume that firmware is running again. */
3037 sc->bce_fw_timed_out = 0;
3038
3039 /* Wait for the firmware to finish its initialization. */
3040 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code);
3041 if (rc) {
3042 if_printf(&sc->arpcom.ac_if,
3043 "Firmware did not complete initialization!\n");
3044 }
3045 return rc;
3046 }
3047
3048
3049 static int
3050 bce_chipinit(struct bce_softc *sc)
3051 {
3052 uint32_t val;
3053 int rc = 0;
3054
3055 /* Make sure the interrupt is not active. */
3056 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);
3057
3058 /*
3059 * Initialize DMA byte/word swapping, configure the number of DMA
3060 * channels and PCI clock compensation delay.
3061 */
3062 val = BCE_DMA_CONFIG_DATA_BYTE_SWAP |
3063 BCE_DMA_CONFIG_DATA_WORD_SWAP |
3064 #if BYTE_ORDER == BIG_ENDIAN
3065 BCE_DMA_CONFIG_CNTL_BYTE_SWAP |
3066 #endif
3067 BCE_DMA_CONFIG_CNTL_WORD_SWAP |
3068 DMA_READ_CHANS << 12 |
3069 DMA_WRITE_CHANS << 16;
3070
3071 val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY;
3072
3073 if ((sc->bce_flags & BCE_PCIX_FLAG) && sc->bus_speed_mhz == 133)
3074 val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP;
3075
3076 /*
3077 * This setting resolves a problem observed on certain Intel PCI
3078 * chipsets that cannot handle multiple outstanding DMA operations.
3079 * See errata E9_5706A1_65.
3080 */
3081 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706 &&
3082 BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0 &&
3083 !(sc->bce_flags & BCE_PCIX_FLAG))
3084 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA;
3085
3086 REG_WR(sc, BCE_DMA_CONFIG, val);
3087
3088 /* Clear the PCI-X relaxed ordering bit. See errata E3_5708CA0_570. */
3089 if (sc->bce_flags & BCE_PCIX_FLAG) {
3090 uint16_t cmd;
3091
3092 cmd = pci_read_config(sc->bce_dev, BCE_PCI_PCIX_CMD, 2);
3093 pci_write_config(sc->bce_dev, BCE_PCI_PCIX_CMD, cmd & ~0x2, 2);
3094 }
3095
3096 /* Enable the RX_V2P and Context state machines before access. */
3097 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
3098 BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
3099 BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
3100 BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
3101
3102 /* Initialize context mapping and zero out the quick contexts. */
3103 bce_init_ctx(sc);
3104
3105 /* Initialize the on-boards CPUs */
3106 bce_init_cpus(sc);
3107
3108 /* Prepare NVRAM for access. */
3109 rc = bce_init_nvram(sc);
3110 if (rc != 0)
3111 return rc;
3112
3113 /* Set the kernel bypass block size */
3114 val = REG_RD(sc, BCE_MQ_CONFIG);
3115 val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE;
3116 val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
3117 REG_WR(sc, BCE_MQ_CONFIG, val);
3118
3119 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
3120 REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val);
3121 REG_WR(sc, BCE_MQ_KNL_WIND_END, val);
3122
3123 /* Set the page size and clear the RV2P processor stall bits. */
3124 val = (BCM_PAGE_BITS - 8) << 24;
3125 REG_WR(sc, BCE_RV2P_CONFIG, val);
3126
3127 /* Configure page size. */
3128 val = REG_RD(sc, BCE_TBDR_CONFIG);
3129 val &= ~BCE_TBDR_CONFIG_PAGE_SIZE;
3130 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
3131 REG_WR(sc, BCE_TBDR_CONFIG, val);
3132
3133 return 0;
3134 }
3135
3136
3137 /****************************************************************************/
3138 /* Initialize the controller in preparation to send/receive traffic. */
3139 /* */
3140 /* Returns: */
3141 /* 0 for success, positive value for failure. */
3142 /****************************************************************************/
3143 static int
3144 bce_blockinit(struct bce_softc *sc)
3145 {
3146 uint32_t reg, val;
3147 int rc = 0;
3148
3149 /* Load the hardware default MAC address. */
3150 bce_set_mac_addr(sc);
3151
3152 /* Set the Ethernet backoff seed value */
3153 val = sc->eaddr[0] + (sc->eaddr[1] << 8) + (sc->eaddr[2] << 16) +
3154 sc->eaddr[3] + (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16);
3155 REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val);
3156
3157 sc->last_status_idx = 0;
3158 sc->rx_mode = BCE_EMAC_RX_MODE_SORT_MODE;
3159
3160 /* Set up link change interrupt generation. */
3161 REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK);
3162
3163 /* Program the physical address of the status block. */
3164 REG_WR(sc, BCE_HC_STATUS_ADDR_L, BCE_ADDR_LO(sc->status_block_paddr));
3165 REG_WR(sc, BCE_HC_STATUS_ADDR_H, BCE_ADDR_HI(sc->status_block_paddr));
3166
3167 /* Program the physical address of the statistics block. */
3168 REG_WR(sc, BCE_HC_STATISTICS_ADDR_L,
3169 BCE_ADDR_LO(sc->stats_block_paddr));
3170 REG_WR(sc, BCE_HC_STATISTICS_ADDR_H,
3171 BCE_ADDR_HI(sc->stats_block_paddr));
3172
3173 /* Program various host coalescing parameters. */
3174 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
3175 (sc->bce_tx_quick_cons_trip_int << 16) |
3176 sc->bce_tx_quick_cons_trip);
3177 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
3178 (sc->bce_rx_quick_cons_trip_int << 16) |
3179 sc->bce_rx_quick_cons_trip);
3180 REG_WR(sc, BCE_HC_COMP_PROD_TRIP,
3181 (sc->bce_comp_prod_trip_int << 16) | sc->bce_comp_prod_trip);
3182 REG_WR(sc, BCE_HC_TX_TICKS,
3183 (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks);
3184 REG_WR(sc, BCE_HC_RX_TICKS,
3185 (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks);
3186 REG_WR(sc, BCE_HC_COM_TICKS,
3187 (sc->bce_com_ticks_int << 16) | sc->bce_com_ticks);
3188 REG_WR(sc, BCE_HC_CMD_TICKS,
3189 (sc->bce_cmd_ticks_int << 16) | sc->bce_cmd_ticks);
3190 REG_WR(sc, BCE_HC_STATS_TICKS, (sc->bce_stats_ticks & 0xffff00));
3191 REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
3192 REG_WR(sc, BCE_HC_CONFIG,
3193 BCE_HC_CONFIG_RX_TMR_MODE |
3194 BCE_HC_CONFIG_TX_TMR_MODE |
3195 BCE_HC_CONFIG_COLLECT_STATS);
3196
3197 /* Clear the internal statistics counters. */
3198 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW);
3199
3200 /* Verify that bootcode is running. */
3201 reg = REG_RD_IND(sc, sc->bce_shmem_base + BCE_DEV_INFO_SIGNATURE);
3202
3203 DBRUNIF(DB_RANDOMTRUE(bce_debug_bootcode_running_failure),
3204 if_printf(&sc->arpcom.ac_if,
3205 "%s(%d): Simulating bootcode failure.\n",
3206 __FILE__, __LINE__);
3207 reg = 0);
3208
3209 if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
3210 BCE_DEV_INFO_SIGNATURE_MAGIC) {
3211 if_printf(&sc->arpcom.ac_if,
3212 "Bootcode not running! Found: 0x%08X, "
3213 "Expected: 08%08X\n",
3214 reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK,
3215 BCE_DEV_INFO_SIGNATURE_MAGIC);
3216 return ENODEV;
3217 }
3218
3219 /* Check if any management firmware is running. */
3220 reg = REG_RD_IND(sc, sc->bce_shmem_base + BCE_PORT_FEATURE);
3221 if (reg & (BCE_PORT_FEATURE_ASF_ENABLED |
3222 BCE_PORT_FEATURE_IMD_ENABLED)) {
3223 DBPRINT(sc, BCE_INFO, "Management F/W Enabled.\n");
3224 sc->bce_flags |= BCE_MFW_ENABLE_FLAG;
3225 }
3226
3227 sc->bce_fw_ver =
3228 REG_RD_IND(sc, sc->bce_shmem_base + BCE_DEV_INFO_BC_REV);
3229 DBPRINT(sc, BCE_INFO, "bootcode rev = 0x%08X\n", sc->bce_fw_ver);
3230
3231 /* Allow bootcode to apply any additional fixes before enabling MAC. */
3232 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT2 | BCE_DRV_MSG_CODE_RESET);
3233
3234 /* Enable link state change interrupt generation. */
3235 REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
3236
3237 /* Enable all remaining blocks in the MAC. */
3238 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 0x5ffffff);
3239 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
3240 DELAY(20);
3241
3242 return 0;
3243 }
3244
3245
3246 /****************************************************************************/
3247 /* Encapsulate an mbuf cluster into the rx_bd chain. */
3248 /* */
3249 /* The NetXtreme II can support Jumbo frames by using multiple rx_bd's. */
3250 /* This routine will map an mbuf cluster into 1 or more rx_bd's as */
3251 /* necessary. */
3252 /* */
3253 /* Returns: */
3254 /* 0 for success, positive value for failure. */
3255 /****************************************************************************/
3256 static int
3257 bce_newbuf_std(struct bce_softc *sc, struct mbuf *m,
3258 uint16_t *prod, uint16_t *chain_prod, uint32_t *prod_bseq)
3259 {
3260 bus_dmamap_t map;
3261 struct bce_dmamap_arg ctx;
3262 bus_dma_segment_t seg;
3263 struct mbuf *m_new;
3264 struct rx_bd *rxbd;
3265 int error;
3266 #ifdef BCE_DEBUG
3267 uint16_t debug_chain_prod = *chain_prod;
3268 #endif
3269
3270 /* Make sure the inputs are valid. */
3271 DBRUNIF((*chain_prod > MAX_RX_BD),
3272 if_printf(&sc->arpcom.ac_if, "%s(%d): "
3273 "RX producer out of range: 0x%04X > 0x%04X\n",
3274 __FILE__, __LINE__,
3275 *chain_prod, (uint16_t)MAX_RX_BD));
3276
3277 DBPRINT(sc, BCE_VERBOSE_RECV, "%s(enter): prod = 0x%04X, chain_prod = 0x%04X, "
3278 "prod_bseq = 0x%08X\n", __func__, *prod, *chain_prod, *prod_bseq);
3279
3280 if (m == NULL) {
3281 DBRUNIF(DB_RANDOMTRUE(bce_debug_mbuf_allocation_failure),
3282 if_printf(&sc->arpcom.ac_if, "%s(%d): "
3283 "Simulating mbuf allocation failure.\n",
3284 __FILE__, __LINE__);
3285 sc->mbuf_alloc_failed++;
3286 return ENOBUFS);
3287
3288 /* This is a new mbuf allocation. */
3289 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
3290 if (m_new == NULL)
3291 return ENOBUFS;
3292 DBRUNIF(1, sc->rx_mbuf_alloc++);
3293 } else {
3294 m_new = m;
3295 m_new->m_data = m_new->m_ext.ext_buf;
3296 }
3297 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
3298
3299 /* Map the mbuf cluster into device memory. */
3300 map = sc->rx_mbuf_map[*chain_prod];
3301
3302 ctx.bce_maxsegs = 1;
3303 ctx.bce_segs = &seg;
3304 error = bus_dmamap_load_mbuf(sc->rx_mbuf_tag, map, m_new,
3305 bce_dma_map_mbuf, &ctx, BUS_DMA_NOWAIT);
3306 if (error || ctx.bce_maxsegs == 0) {
3307 if_printf(&sc->arpcom.ac_if,
3308 "Error mapping mbuf into RX chain!\n");
3309
3310 if (m == NULL)
3311 m_freem(m_new);
3312
3313 DBRUNIF(1, sc->rx_mbuf_alloc--);
3314 return ENOBUFS;
3315 }
3316
3317 /* Watch for overflow. */
3318 DBRUNIF((sc->free_rx_bd > USABLE_RX_BD),
3319 if_printf(&sc->arpcom.ac_if, "%s(%d): "
3320 "Too many free rx_bd (0x%04X > 0x%04X)!\n",
3321 __FILE__, __LINE__, sc->free_rx_bd,
3322 (uint16_t)USABLE_RX_BD));
3323
3324 /* Update some debug statistic counters */
3325 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
3326 sc->rx_low_watermark = sc->free_rx_bd);
3327 DBRUNIF((sc->free_rx_bd == 0), sc->rx_empty_count++);
3328
3329 /* Setup the rx_bd for the first segment. */
3330 rxbd = &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)];
3331
3332 rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(seg.ds_addr));
3333 rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(seg.ds_addr));
3334 rxbd->rx_bd_len = htole32(seg.ds_len);
3335 rxbd->rx_bd_flags = htole32(RX_BD_FLAGS_START);
3336 *prod_bseq += seg.ds_len;
3337
3338 rxbd->rx_bd_flags |= htole32(RX_BD_FLAGS_END);
3339
3340 /* Save the mbuf and update our counter. */
3341 sc->rx_mbuf_ptr[*chain_prod] = m_new;
3342 sc->free_rx_bd--;
3343
3344 DBRUN(BCE_VERBOSE_RECV,
3345 bce_dump_rx_mbuf_chain(sc, debug_chain_prod, 1));
3346
3347 DBPRINT(sc, BCE_VERBOSE_RECV, "%s(exit): prod = 0x%04X, chain_prod = 0x%04X, "
3348 "prod_bseq = 0x%08X\n", __func__, *prod, *chain_prod, *prod_bseq);
3349
3350 return 0;
3351 }
3352
3353
3354 /****************************************************************************/
3355 /* Allocate memory and initialize the TX data structures. */
3356 /* */
3357 /* Returns: */
3358 /* 0 for success, positive value for failure. */
3359 /****************************************************************************/
3360 static int
3361 bce_init_tx_chain(struct bce_softc *sc)
3362 {
3363 struct tx_bd *txbd;
3364 uint32_t val;
3365 int i, rc = 0;
3366
3367 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
3368
3369 /* Set the initial TX producer/consumer indices. */
3370 sc->tx_prod = 0;
3371 sc->tx_cons = 0;
3372 sc->tx_prod_bseq = 0;
3373 sc->used_tx_bd = 0;
3374 sc->max_tx_bd = USABLE_TX_BD;
3375 DBRUNIF(1, sc->tx_hi_watermark = USABLE_TX_BD);
3376 DBRUNIF(1, sc->tx_full_count = 0);
3377
3378 /*
3379 * The NetXtreme II supports a linked-list structre called
3380 * a Buffer Descriptor Chain (or BD chain). A BD chain
3381 * consists of a series of 1 or more chain pages, each of which
3382 * consists of a fixed number of BD entries.
3383 * The last BD entry on each page is a pointer to the next page
3384 * in the chain, and the last pointer in the BD chain
3385 * points back to the beginning of the chain.
3386 */
3387
3388 /* Set the TX next pointer chain entries. */
3389 for (i = 0; i < TX_PAGES; i++) {
3390 int j;
3391
3392 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE];
3393
3394 /* Check if we've reached the last page. */
3395 if (i == (TX_PAGES - 1))
3396 j = 0;
3397 else
3398 j = i + 1;
3399
3400 txbd->tx_bd_haddr_hi =
3401 htole32(BCE_ADDR_HI(sc->tx_bd_chain_paddr[j]));
3402 txbd->tx_bd_haddr_lo =
3403 htole32(BCE_ADDR_LO(sc->tx_bd_chain_paddr[j]));
3404 }
3405
3406 for (i = 0; i < TX_PAGES; ++i) {
3407 bus_dmamap_sync(sc->tx_bd_chain_tag, sc->tx_bd_chain_map[i],
3408 BUS_DMASYNC_PREWRITE);
3409 }
3410
3411 /* Initialize the context ID for an L2 TX chain. */
3412 val = BCE_L2CTX_TYPE_TYPE_L2;
3413 val |= BCE_L2CTX_TYPE_SIZE_L2;
3414 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TYPE, val);
3415
3416 val = BCE_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
3417 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_CMD_TYPE, val);
3418
3419 /* Point the hardware to the first page in the chain. */
3420 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
3421 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TBDR_BHADDR_HI, val);
3422 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
3423 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TBDR_BHADDR_LO, val);
3424
3425 DBRUN(BCE_VERBOSE_SEND, bce_dump_tx_chain(sc, 0, TOTAL_TX_BD));
3426
3427 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
3428
3429 return(rc);
3430 }
3431
3432
3433 /****************************************************************************/
3434 /* Free memory and clear the TX data structures. */
3435 /* */
3436 /* Returns: */
3437 /* Nothing. */
3438 /****************************************************************************/
3439 static void
3440 bce_free_tx_chain(struct bce_softc *sc)
3441 {
3442 int i;
3443
3444 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
3445
3446 /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */
3447 for (i = 0; i < TOTAL_TX_BD; i++) {
3448 if (sc->tx_mbuf_ptr[i] != NULL) {
3449 bus_dmamap_sync(sc->tx_mbuf_tag, sc->tx_mbuf_map[i],
3450 BUS_DMASYNC_POSTWRITE);
3451 bus_dmamap_unload(sc->tx_mbuf_tag, sc->tx_mbuf_map[i]);
3452 m_freem(sc->tx_mbuf_ptr[i]);
3453 sc->tx_mbuf_ptr[i] = NULL;
3454 DBRUNIF(1, sc->tx_mbuf_alloc--);
3455 }
3456 }
3457
3458 /* Clear each TX chain page. */
3459 for (i = 0; i < TX_PAGES; i++)
3460 bzero(sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ);
3461 sc->used_tx_bd = 0;
3462
3463 /* Check if we lost any mbufs in the process. */
3464 DBRUNIF((sc->tx_mbuf_alloc),
3465 if_printf(&sc->arpcom.ac_if,
3466 "%s(%d): Memory leak! "
3467 "Lost %d mbufs from tx chain!\n",
3468 __FILE__, __LINE__, sc->tx_mbuf_alloc));
3469
3470 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
3471 }
3472
3473
3474 /****************************************************************************/
3475 /* Allocate memory and initialize the RX data structures. */
3476 /* */
3477 /* Returns: */
3478 /* 0 for success, positive value for failure. */
3479 /****************************************************************************/
3480 static int
3481 bce_init_rx_chain(struct bce_softc *sc)
3482 {
3483 struct rx_bd *rxbd;
3484 int i, rc = 0;
3485 uint16_t prod, chain_prod;
3486 uint32_t prod_bseq, val;
3487
3488 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
3489
3490 /* Initialize the RX producer and consumer indices. */
3491 sc->rx_prod = 0;
3492 sc->rx_cons = 0;
3493 sc->rx_prod_bseq = 0;
3494 sc->free_rx_bd = USABLE_RX_BD;
3495 sc->max_rx_bd = USABLE_RX_BD;
3496 DBRUNIF(1, sc->rx_low_watermark = USABLE_RX_BD);
3497 DBRUNIF(1, sc->rx_empty_count = 0);
3498
3499 /* Initialize the RX next pointer chain entries. */
3500 for (i = 0; i < RX_PAGES; i++) {
3501 int j;
3502
3503 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE];
3504
3505 /* Check if we've reached the last page. */
3506 if (i == (RX_PAGES - 1))
3507 j = 0;
3508 else
3509 j = i + 1;
3510
3511 /* Setup the chain page pointers. */
3512 rxbd->rx_bd_haddr_hi =
3513 htole32(BCE_ADDR_HI(sc->rx_bd_chain_paddr[j]));
3514 rxbd->rx_bd_haddr_lo =
3515 htole32(BCE_ADDR_LO(sc->rx_bd_chain_paddr[j]));
3516 }
3517
3518 /* Initialize the context ID for an L2 RX chain. */
3519 val = BCE_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
3520 val |= BCE_L2CTX_CTX_TYPE_SIZE_L2;
3521 val |= 0x02 << 8;
3522 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_CTX_TYPE, val);
3523
3524 /* Point the hardware to the first page in the chain. */
3525 /* XXX shouldn't this after RX descriptor initialization? */
3526 val = BCE_ADDR_HI(sc->rx_bd_chain_paddr[0]);
3527 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_NX_BDHADDR_HI, val);
3528 val = BCE_ADDR_LO(sc->rx_bd_chain_paddr[0]);
3529 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_NX_BDHADDR_LO, val);
3530
3531 /* Allocate mbuf clusters for the rx_bd chain. */
3532 prod = prod_bseq = 0;
3533 while (prod < TOTAL_RX_BD) {
3534 chain_prod = RX_CHAIN_IDX(prod);
3535 if (bce_newbuf_std(sc, NULL, &prod, &chain_prod, &prod_bseq)) {
3536 if_printf(&sc->arpcom.ac_if,
3537 "Error filling RX chain: rx_bd[0x%04X]!\n",
3538 chain_prod);
3539 rc = ENOBUFS;
3540 break;
3541 }
3542 prod = NEXT_RX_BD(prod);
3543 }
3544
3545 /* Save the RX chain producer index. */
3546 sc->rx_prod = prod;
3547 sc->rx_prod_bseq = prod_bseq;
3548
3549 for (i = 0; i < RX_PAGES; i++) {
3550 bus_dmamap_sync(sc->rx_bd_chain_tag, sc->rx_bd_chain_map[i],
3551 BUS_DMASYNC_PREWRITE);
3552 }
3553
3554 /* Tell the chip about the waiting rx_bd's. */
3555 REG_WR16(sc, MB_RX_CID_ADDR + BCE_L2CTX_HOST_BDIDX, sc->rx_prod);
3556 REG_WR(sc, MB_RX_CID_ADDR + BCE_L2CTX_HOST_BSEQ, sc->rx_prod_bseq);
3557
3558 DBRUN(BCE_VERBOSE_RECV, bce_dump_rx_chain(sc, 0, TOTAL_RX_BD));
3559
3560 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
3561
3562 return(rc);
3563 }
3564
3565
3566 /****************************************************************************/
3567 /* Free memory and clear the RX data structures. */
3568 /* */
3569 /* Returns: */
3570 /* Nothing. */
3571 /****************************************************************************/
3572 static void
3573 bce_free_rx_chain(struct bce_softc *sc)
3574 {
3575 int i;
3576
3577 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
3578
3579 /* Free any mbufs still in the RX mbuf chain. */
3580 for (i = 0; i < TOTAL_RX_BD; i++) {
3581 if (sc->rx_mbuf_ptr[i] != NULL) {
3582 bus_dmamap_sync(sc->rx_mbuf_tag, sc->rx_mbuf_map[i],
3583 BUS_DMASYNC_POSTREAD);
3584 bus_dmamap_unload(sc->rx_mbuf_tag, sc->rx_mbuf_map[i]);
3585 m_freem(sc->rx_mbuf_ptr[i]);
3586 sc->rx_mbuf_ptr[i] = NULL;
3587 DBRUNIF(1, sc->rx_mbuf_alloc--);
3588 }
3589 }
3590
3591 /* Clear each RX chain page. */
3592 for (i = 0; i < RX_PAGES; i++)
3593 bzero(sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ);
3594
3595 /* Check if we lost any mbufs in the process. */
3596 DBRUNIF((sc->rx_mbuf_alloc),
3597 if_printf(&sc->arpcom.ac_if,
3598 "%s(%d): Memory leak! "
3599 "Lost %d mbufs from rx chain!\n",
3600 __FILE__, __LINE__, sc->rx_mbuf_alloc));
3601
3602 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
3603 }
3604
3605
3606 /****************************************************************************/
3607 /* Set media options. */
3608 /* */
3609 /* Returns: */
3610 /* 0 for success, positive value for failure. */
3611 /****************************************************************************/
3612 static int
3613 bce_ifmedia_upd(struct ifnet *ifp)
3614 {
3615 struct bce_softc *sc = ifp->if_softc;
3616 struct mii_data *mii = device_get_softc(sc->bce_miibus);
3617
3618 /*
3619 * 'mii' will be NULL, when this function is called on following
3620 * code path: bce_attach() -> bce_mgmt_init()
3621 */
3622 if (mii != NULL) {
3623 /* Make sure the MII bus has been enumerated. */
3624 sc->bce_link = 0;
3625 if (mii->mii_instance) {
3626 struct mii_softc *miisc;
3627
3628 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
3629 mii_phy_reset(miisc);
3630 }
3631 mii_mediachg(mii);
3632 }
3633 return 0;
3634 }
3635
3636
3637 /****************************************************************************/
3638 /* Reports current media status. */
3639 /* */
3640 /* Returns: */
3641 /* Nothing. */
3642 /****************************************************************************/
3643 static void
3644 bce_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3645 {
3646 struct bce_softc *sc = ifp->if_softc;
3647 struct mii_data *mii = device_get_softc(sc->bce_miibus);
3648
3649 mii_pollstat(mii);
3650 ifmr->ifm_active = mii->mii_media_active;
3651 ifmr->ifm_status = mii->mii_media_status;
3652 }
3653
3654
3655 /****************************************************************************/
3656 /* Handles PHY generated interrupt events. */
3657 /* */
3658 /* Returns: */
3659 /* Nothing. */
3660 /****************************************************************************/
3661 static void
3662 bce_phy_intr(struct bce_softc *sc)
3663 {
3664 uint32_t new_link_state, old_link_state;
3665 struct ifnet *ifp = &sc->arpcom.ac_if;
3666
3667 ASSERT_SERIALIZED(ifp->if_serializer);
3668
3669 new_link_state = sc->status_block->status_attn_bits &
3670 STATUS_ATTN_BITS_LINK_STATE;
3671 old_link_state = sc->status_block->status_attn_bits_ack &
3672 STATUS_ATTN_BITS_LINK_STATE;
3673
3674 /* Handle any changes if the link state has changed. */
3675 if (new_link_state != old_link_state) { /* XXX redundant? */
3676 DBRUN(BCE_VERBOSE_INTR, bce_dump_status_block(sc));
3677
3678 sc->bce_link = 0;
3679 callout_stop(&sc->bce_stat_ch);
3680 bce_tick_serialized(sc);
3681
3682 /* Update the status_attn_bits_ack field in the status block. */
3683 if (new_link_state) {
3684 REG_WR(sc, BCE_PCICFG_STATUS_BIT_SET_CMD,
3685 STATUS_ATTN_BITS_LINK_STATE);
3686 if (bootverbose)
3687 if_printf(ifp, "Link is now UP.\n");
3688 } else {
3689 REG_WR(sc, BCE_PCICFG_STATUS_BIT_CLEAR_CMD,
3690 STATUS_ATTN_BITS_LINK_STATE);
3691 if (bootverbose)
3692 if_printf(ifp, "Link is now DOWN.\n");
3693 }
3694 }
3695
3696 /* Acknowledge the link change interrupt. */
3697 REG_WR(sc, BCE_EMAC_STATUS, BCE_EMAC_STATUS_LINK_CHANGE);
3698 }
3699
3700
3701 /****************************************************************************/
3702 /* Reads the receive consumer value from the status block (skipping over */
3703 /* chain page pointer if necessary). */
3704 /* */
3705 /* Returns: */
3706 /* hw_cons */
3707 /****************************************************************************/
3708 static __inline uint16_t
3709 bce_get_hw_rx_cons(struct bce_softc *sc)
3710 {
3711 uint16_t hw_cons = sc->status_block->status_rx_quick_consumer_index0;
3712
3713 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE)
3714 hw_cons++;
3715 return hw_cons;
3716 }
3717
3718
3719 /****************************************************************************/
3720 /* Handles received frame interrupt events. */
3721 /* */
3722 /* Returns: */
3723 /* Nothing. */
3724 /****************************************************************************/
3725 static void
3726 bce_rx_intr(struct bce_softc *sc, int count)
3727 {
3728 struct ifnet *ifp = &sc->arpcom.ac_if;
3729 uint16_t hw_cons, sw_cons, sw_chain_cons, sw_prod, sw_chain_prod;
3730 uint32_t sw_prod_bseq;
3731 int i;
3732
3733 ASSERT_SERIALIZED(ifp->if_serializer);
3734
3735 DBRUNIF(1, sc->rx_interrupts++);
3736
3737 /* Prepare the RX chain pages to be accessed by the host CPU. */
3738 for (i = 0; i < RX_PAGES; i++) {
3739 bus_dmamap_sync(sc->rx_bd_chain_tag,
3740 sc->rx_bd_chain_map[i], BUS_DMASYNC_POSTREAD);
3741 }
3742
3743 /* Get the hardware's view of the RX consumer index. */
3744 hw_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc);
3745
3746 /* Get working copies of the driver's view of the RX indices. */
3747 sw_cons = sc->rx_cons;
3748 sw_prod = sc->rx_prod;
3749 sw_prod_bseq = sc->rx_prod_bseq;
3750
3751 DBPRINT(sc, BCE_INFO_RECV, "%s(enter): sw_prod = 0x%04X, "
3752 "sw_cons = 0x%04X, sw_prod_bseq = 0x%08X\n",
3753 __func__, sw_prod, sw_cons, sw_prod_bseq);
3754
3755 /* Prevent speculative reads from getting ahead of the status block. */
3756 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
3757 BUS_SPACE_BARRIER_READ);
3758
3759 /* Update some debug statistics counters */
3760 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
3761 sc->rx_low_watermark = sc->free_rx_bd);
3762 DBRUNIF((sc->free_rx_bd == 0), sc->rx_empty_count++);
3763
3764 /* Scan through the receive chain as long as there is work to do. */
3765 while (sw_cons != hw_cons) {
3766 struct mbuf *m = NULL;
3767 struct l2_fhdr *l2fhdr = NULL;
3768 struct rx_bd *rxbd;
3769 unsigned int len;
3770 uint32_t status = 0;
3771
3772 #ifdef DEVICE_POLLING
3773 if (count >= 0 && count-- == 0) {
3774 sc->hw_rx_cons = sw_cons;
3775 break;
3776 }
3777 #endif
3778
3779 /*
3780 * Convert the producer/consumer indices
3781 * to an actual rx_bd index.
3782 */
3783 sw_chain_cons = RX_CHAIN_IDX(sw_cons);
3784 sw_chain_prod = RX_CHAIN_IDX(sw_prod);
3785
3786 /* Get the used rx_bd. */
3787 rxbd = &sc->rx_bd_chain[RX_PAGE(sw_chain_cons)]
3788 [RX_IDX(sw_chain_cons)];
3789 sc->free_rx_bd++;
3790
3791 DBRUN(BCE_VERBOSE_RECV,
3792 if_printf(ifp, "%s(): ", __func__);
3793 bce_dump_rxbd(sc, sw_chain_cons, rxbd));
3794
3795 /* The mbuf is stored with the last rx_bd entry of a packet. */
3796 if (sc->rx_mbuf_ptr[sw_chain_cons] != NULL) {
3797 /* Validate that this is the last rx_bd. */
3798 DBRUNIF((!(rxbd->rx_bd_flags & RX_BD_FLAGS_END)),
3799 if_printf(ifp, "%s(%d): "
3800 "Unexpected mbuf found in rx_bd[0x%04X]!\n",
3801 __FILE__, __LINE__, sw_chain_cons);
3802 bce_breakpoint(sc));
3803
3804 /*
3805 * ToDo: If the received packet is small enough
3806 * to fit into a single, non-M_EXT mbuf,
3807 * allocate a new mbuf here, copy the data to
3808 * that mbuf, and recycle the mapped jumbo frame.
3809 */
3810
3811 /* Unmap the mbuf from DMA space. */
3812 bus_dmamap_sync(sc->rx_mbuf_tag,
3813 sc->rx_mbuf_map[sw_chain_cons],
3814 BUS_DMASYNC_POSTREAD);
3815 bus_dmamap_unload(sc->rx_mbuf_tag,
3816 sc->rx_mbuf_map[sw_chain_cons]);
3817
3818 /* Remove the mbuf from the driver's chain. */
3819 m = sc->rx_mbuf_ptr[sw_chain_cons];
3820 sc->rx_mbuf_ptr[sw_chain_cons] = NULL;
3821
3822 /*
3823 * Frames received on the NetXteme II are prepended
3824 * with an l2_fhdr structure which provides status
3825 * information about the received frame (including
3826 * VLAN tags and checksum info). The frames are also
3827 * automatically adjusted to align the IP header
3828 * (i.e. two null bytes are inserted before the
3829 * Ethernet header).
3830 */
3831 l2fhdr = mtod(m, struct l2_fhdr *);
3832
3833 len = l2fhdr->l2_fhdr_pkt_len;
3834 status = l2fhdr->l2_fhdr_status;
3835
3836 DBRUNIF(DB_RANDOMTRUE(bce_debug_l2fhdr_status_check),
3837 if_printf(ifp,
3838 "Simulating l2_fhdr status error.\n");
3839 status = status | L2_FHDR_ERRORS_PHY_DECODE);
3840
3841 /* Watch for unusual sized frames. */
3842 DBRUNIF((len < BCE_MIN_MTU ||
3843 len > BCE_MAX_JUMBO_ETHER_MTU_VLAN),
3844 if_printf(ifp,
3845 "%s(%d): Unusual frame size found. "
3846 "Min(%d), Actual(%d), Max(%d)\n",
3847 __FILE__, __LINE__,
3848 (int)BCE_MIN_MTU, len,
3849 (int)BCE_MAX_JUMBO_ETHER_MTU_VLAN);
3850 bce_dump_mbuf(sc, m);
3851 bce_breakpoint(sc));
3852
3853 len -= ETHER_CRC_LEN;
3854
3855 /* Check the received frame for errors. */
3856 if (status & (L2_FHDR_ERRORS_BAD_CRC |
3857 L2_FHDR_ERRORS_PHY_DECODE |
3858 L2_FHDR_ERRORS_ALIGNMENT |
3859 L2_FHDR_ERRORS_TOO_SHORT |
3860 L2_FHDR_ERRORS_GIANT_FRAME)) {
3861 ifp->if_ierrors++;
3862 DBRUNIF(1, sc->l2fhdr_status_errors++);
3863
3864 /* Reuse the mbuf for a new frame. */
3865 if (bce_newbuf_std(sc, m, &sw_prod,
3866 &sw_chain_prod,
3867 &sw_prod_bseq)) {
3868 DBRUNIF(1, bce_breakpoint(sc));
3869 /* XXX */
3870 panic("%s: Can't reuse RX mbuf!\n",
3871 ifp->if_xname);
3872 }
3873 m = NULL;
3874 goto bce_rx_int_next_rx;
3875 }
3876
3877 /*
3878 * Get a new mbuf for the rx_bd. If no new
3879 * mbufs are available then reuse the current mbuf,
3880 * log an ierror on the interface, and generate
3881 * an error in the system log.
3882 */
3883 if (bce_newbuf_std(sc, NULL, &sw_prod, &sw_chain_prod,
3884 &sw_prod_bseq)) {
3885 DBRUN(BCE_WARN,
3886 if_printf(ifp,
3887 "%s(%d): Failed to allocate new mbuf, "
3888 "incoming frame dropped!\n",
3889 __FILE__, __LINE__));
3890
3891 ifp->if_ierrors++;
3892
3893 /* Try and reuse the exisitng mbuf. */
3894 if (bce_newbuf_std(sc, m, &sw_prod,
3895 &sw_chain_prod,
3896 &sw_prod_bseq)) {
3897 DBRUNIF(1, bce_breakpoint(sc));
3898 /* XXX */
3899 panic("%s: Double mbuf allocation "
3900 "failure!", ifp->if_xname);
3901 }
3902 m = NULL;
3903 goto bce_rx_int_next_rx;
3904 }
3905
3906 /*
3907 * Skip over the l2_fhdr when passing
3908 * the data up the stack.
3909 */
3910 m_adj(m, sizeof(struct l2_fhdr) + ETHER_ALIGN);
3911
3912 m->m_pkthdr.len = m->m_len = len;
3913 m->m_pkthdr.rcvif = ifp;
3914
3915 DBRUN(BCE_VERBOSE_RECV,
3916 struct ether_header *eh;
3917 eh = mtod(m, struct ether_header *);
3918 if_printf(ifp, "%s(): to: %6D, from: %6D, "
3919 "type: 0x%04X\n", __func__,
3920 eh->ether_dhost, ":",
3921 eh->ether_shost, ":",
3922 htons(eh->ether_type)));
3923
3924 /* Validate the checksum if offload enabled. */
3925 if (ifp->if_capenable & IFCAP_RXCSUM) {
3926 /* Check for an IP datagram. */
3927 if (status & L2_FHDR_STATUS_IP_DATAGRAM) {
3928 m->m_pkthdr.csum_flags |=
3929 CSUM_IP_CHECKED;
3930
3931 /* Check if the IP checksum is valid. */
3932 if ((l2fhdr->l2_fhdr_ip_xsum ^
3933 0xffff) == 0) {
3934 m->m_pkthdr.csum_flags |=
3935 CSUM_IP_VALID;
3936 } else {
3937 DBPRINT(sc, BCE_WARN_RECV,
3938 "%s(): Invalid IP checksum = 0x%04X!\n",
3939 __func__, l2fhdr->l2_fhdr_ip_xsum);
3940 }
3941 }
3942
3943 /* Check for a valid TCP/UDP frame. */
3944 if (status & (L2_FHDR_STATUS_TCP_SEGMENT |
3945 L2_FHDR_STATUS_UDP_DATAGRAM)) {
3946
3947 /* Check for a good TCP/UDP checksum. */
3948 if ((status &
3949 (L2_FHDR_ERRORS_TCP_XSUM |
3950 L2_FHDR_ERRORS_UDP_XSUM)) == 0) {
3951 m->m_pkthdr.csum_data =
3952 l2fhdr->l2_fhdr_tcp_udp_xsum;
3953 m->m_pkthdr.csum_flags |=
3954 CSUM_DATA_VALID |
3955 CSUM_PSEUDO_HDR;
3956 } else {
3957 DBPRINT(sc, BCE_WARN_RECV,
3958 "%s(): Invalid TCP/UDP checksum = 0x%04X!\n",
3959 __func__, l2fhdr->l2_fhdr_tcp_udp_xsum);
3960 }
3961 }
3962 }
3963
3964 ifp->if_ipackets++;
3965 bce_rx_int_next_rx:
3966 sw_prod = NEXT_RX_BD(sw_prod);
3967 }
3968
3969 sw_cons = NEXT_RX_BD(sw_cons);
3970
3971 /* If we have a packet, pass it up the stack */
3972 if (m) {
3973 DBPRINT(sc, BCE_VERBOSE_RECV,
3974 "%s(): Passing received frame up.\n", __func__);
3975
3976 if (status & L2_FHDR_STATUS_L2_VLAN_TAG) {
3977 m->m_flags |= M_VLANTAG;
3978 m->m_pkthdr.ether_vlantag =
3979 l2fhdr->l2_fhdr_vlan_tag;
3980 }
3981 ifp->if_input(ifp, m);
3982
3983 DBRUNIF(1, sc->rx_mbuf_alloc--);
3984 }
3985
3986 /*
3987 * If polling(4) is not enabled, refresh hw_cons to see
3988 * whether there's new work.
3989 *
3990 * If polling(4) is enabled, i.e count >= 0, refreshing
3991 * should not be performed, so that we would not spend
3992 * too much time in RX processing.
3993 */
3994 if (count < 0 && sw_cons == hw_cons)
3995 hw_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc);
3996
3997 /*
3998 * Prevent speculative reads from getting ahead
3999 * of the status block.
4000 */
4001 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
4002 BUS_SPACE_BARRIER_READ);
4003 }
4004
4005 for (i = 0; i < RX_PAGES; i++) {
4006 bus_dmamap_sync(sc->rx_bd_chain_tag,
4007 sc->rx_bd_chain_map[i], BUS_DMASYNC_PREWRITE);
4008 }
4009
4010 sc->rx_cons = sw_cons;
4011 sc->rx_prod = sw_prod;
4012 sc->rx_prod_bseq = sw_prod_bseq;
4013
4014 REG_WR16(sc, MB_RX_CID_ADDR + BCE_L2CTX_HOST_BDIDX, sc->rx_prod);
4015 REG_WR(sc, MB_RX_CID_ADDR + BCE_L2CTX_HOST_BSEQ, sc->rx_prod_bseq);
4016
4017 DBPRINT(sc, BCE_INFO_RECV, "%s(exit): rx_prod = 0x%04X, "
4018 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n",
4019 __func__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq);
4020 }
4021
4022
4023 /****************************************************************************/
4024 /* Reads the transmit consumer value from the status block (skipping over */
4025 /* chain page pointer if necessary). */
4026 /* */
4027 /* Returns: */
4028 /* hw_cons */
4029 /****************************************************************************/
4030 static __inline uint16_t
4031 bce_get_hw_tx_cons(struct bce_softc *sc)
4032 {
4033 uint16_t hw_cons = sc->status_block->status_tx_quick_consumer_index0;
4034
4035 if ((hw_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE)
4036 hw_cons++;
4037 return hw_cons;
4038 }
4039
4040
4041 /****************************************************************************/
4042 /* Handles transmit completion interrupt events. */
4043 /* */
4044 /* Returns: */
4045 /* Nothing. */
4046 /****************************************************************************/
4047 static void
4048 bce_tx_intr(struct bce_softc *sc)
4049 {
4050 struct ifnet *ifp = &sc->arpcom.ac_if;
4051 uint16_t hw_tx_cons, sw_tx_cons, sw_tx_chain_cons;
4052
4053 ASSERT_SERIALIZED(ifp->if_serializer);
4054
4055 DBRUNIF(1, sc->tx_interrupts++);
4056
4057 /* Get the hardware's view of the TX consumer index. */
4058 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc);
4059 sw_tx_cons = sc->tx_cons;
4060
4061 /* Prevent speculative reads from getting ahead of the status block. */
4062 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
4063 BUS_SPACE_BARRIER_READ);
4064
4065 /* Cycle through any completed TX chain page entries. */
4066 while (sw_tx_cons != hw_tx_cons) {
4067 #ifdef BCE_DEBUG
4068 struct tx_bd *txbd = NULL;
4069 #endif
4070 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons);
4071
4072 DBPRINT(sc, BCE_INFO_SEND,
4073 "%s(): hw_tx_cons = 0x%04X, sw_tx_cons = 0x%04X, "
4074 "sw_tx_chain_cons = 0x%04X\n",
4075 __func__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons);
4076
4077 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD),
4078 if_printf(ifp, "%s(%d): "
4079 "TX chain consumer out of range! "
4080 " 0x%04X > 0x%04X\n",
4081 __FILE__, __LINE__, sw_tx_chain_cons,
4082 (int)MAX_TX_BD);
4083 bce_breakpoint(sc));
4084
4085 DBRUNIF(1, txbd = &sc->tx_bd_chain[TX_PAGE(sw_tx_chain_cons)]
4086 [TX_IDX(sw_tx_chain_cons)]);
4087
4088 DBRUNIF((txbd == NULL),
4089 if_printf(ifp, "%s(%d): "
4090 "Unexpected NULL tx_bd[0x%04X]!\n",
4091 __FILE__, __LINE__, sw_tx_chain_cons);
4092 bce_breakpoint(sc));
4093
4094 DBRUN(BCE_INFO_SEND,
4095 if_printf(ifp, "%s(): ", __func__);
4096 bce_dump_txbd(sc, sw_tx_chain_cons, txbd));
4097
4098 /*
4099 * Free the associated mbuf. Remember
4100 * that only the last tx_bd of a packet
4101 * has an mbuf pointer and DMA map.
4102 */
4103 if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) {
4104 /* Validate that this is the last tx_bd. */
4105 DBRUNIF((!(txbd->tx_bd_flags & TX_BD_FLAGS_END)),
4106 if_printf(ifp, "%s(%d): "
4107 "tx_bd END flag not set but "
4108 "txmbuf == NULL!\n", __FILE__, __LINE__);
4109 bce_breakpoint(sc));
4110
4111 DBRUN(BCE_INFO_SEND,
4112 if_printf(ifp, "%s(): Unloading map/freeing mbuf "
4113 "from tx_bd[0x%04X]\n", __func__,
4114 sw_tx_chain_cons));
4115
4116 /* Unmap the mbuf. */
4117 bus_dmamap_unload(sc->tx_mbuf_tag,
4118 sc->tx_mbuf_map[sw_tx_chain_cons]);
4119
4120 /* Free the mbuf. */
4121 m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]);
4122 sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL;
4123 DBRUNIF(1, sc->tx_mbuf_alloc--);
4124
4125 ifp->if_opackets++;
4126 }
4127
4128 sc->used_tx_bd--;
4129 sw_tx_cons = NEXT_TX_BD(sw_tx_cons);
4130
4131 if (sw_tx_cons == hw_tx_cons) {
4132 /* Refresh hw_cons to see if there's new work. */
4133 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc);
4134 }
4135
4136 /*
4137 * Prevent speculative reads from getting
4138 * ahead of the status block.
4139 */
4140 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
4141 BUS_SPACE_BARRIER_READ);
4142 }
4143
4144 if (sc->used_tx_bd == 0) {
4145 /* Clear the TX timeout timer. */
4146 ifp->if_timer = 0;
4147 }
4148
4149 /* Clear the tx hardware queue full flag. */
4150 if (sc->max_tx_bd - sc->used_tx_bd >= BCE_TX_SPARE_SPACE) {
4151 DBRUNIF((ifp->if_flags & IFF_OACTIVE),
4152 DBPRINT(sc, BCE_WARN_SEND,
4153 "%s(): Open TX chain! %d/%d (used/total)\n",
4154 __func__, sc->used_tx_bd, sc->max_tx_bd));
4155 ifp->if_flags &= ~IFF_OACTIVE;
4156 }
4157 sc->tx_cons = sw_tx_cons;
4158 }
4159
4160
4161 /****************************************************************************/
4162 /* Disables interrupt generation. */
4163 /* */
4164 /* Returns: */
4165 /* Nothing. */
4166 /****************************************************************************/
4167 static void
4168 bce_disable_intr(struct bce_softc *sc)
4169 {
4170 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);
4171 REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
4172 lwkt_serialize_handler_disable(sc->arpcom.ac_if.if_serializer);
4173 }
4174
4175
4176 /****************************************************************************/
4177 /* Enables interrupt generation. */
4178 /* */
4179 /* Returns: */
4180 /* Nothing. */
4181 /****************************************************************************/
4182 static void
4183 bce_enable_intr(struct bce_softc *sc)
4184 {
4185 uint32_t val;
4186
4187 lwkt_serialize_handler_enable(sc->arpcom.ac_if.if_serializer);
4188
4189 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
4190 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID |
4191 BCE_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx);
4192
4193 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
4194 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx);
4195
4196 val = REG_RD(sc, BCE_HC_COMMAND);
4197 REG_WR(sc, BCE_HC_COMMAND, val | BCE_HC_COMMAND_COAL_NOW);
4198 }
4199
4200
4201 /****************************************************************************/
4202 /* Handles controller initialization. */
4203 /* */
4204 /* Returns: */
4205 /* Nothing. */
4206 /****************************************************************************/
4207 static void
4208 bce_init(void *xsc)
4209 {
4210 struct bce_softc *sc = xsc;
4211 struct ifnet *ifp = &sc->arpcom.ac_if;
4212 uint32_t ether_mtu;
4213 int error;
4214
4215 ASSERT_SERIALIZED(ifp->if_serializer);
4216
4217 /* Check if the driver is still running and bail out if it is. */
4218 if (ifp->if_flags & IFF_RUNNING)
4219 return;
4220
4221 bce_stop(sc);
4222
4223 error = bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
4224 if (error) {
4225 if_printf(ifp, "Controller reset failed!\n");
4226 goto back;
4227 }
4228
4229 error = bce_chipinit(sc);
4230 if (error) {
4231 if_printf(ifp, "Controller initialization failed!\n");
4232 goto back;
4233 }
4234
4235 error = bce_blockinit(sc);
4236 if (error) {
4237 if_printf(ifp, "Block initialization failed!\n");
4238 goto back;
4239 }
4240
4241 /* Load our MAC address. */
4242 bcopy(IF_LLADDR(ifp), sc->eaddr, ETHER_ADDR_LEN);
4243 bce_set_mac_addr(sc);
4244
4245 /* Calculate and program the Ethernet MTU size. */
4246 ether_mtu = ETHER_HDR_LEN + EVL_ENCAPLEN + ifp->if_mtu + ETHER_CRC_LEN;
4247
4248 DBPRINT(sc, BCE_INFO, "%s(): setting mtu = %d\n", __func__, ether_mtu);
4249
4250 /*
4251 * Program the mtu, enabling jumbo frame
4252 * support if necessary. Also set the mbuf
4253 * allocation count for RX frames.
4254 */
4255 if (ether_mtu > ETHER_MAX_LEN + EVL_ENCAPLEN) {
4256 #ifdef notyet
4257 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE,
4258 min(ether_mtu, BCE_MAX_JUMBO_ETHER_MTU) |
4259 BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA);
4260 sc->mbuf_alloc_size = MJUM9BYTES;
4261 #else
4262 panic("jumbo buffer is not supported yet\n");
4263 #endif
4264 } else {
4265 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu);
4266 sc->mbuf_alloc_size = MCLBYTES;
4267 }
4268
4269 /* Calculate the RX Ethernet frame size for rx_bd's. */
4270 sc->max_frame_size = sizeof(struct l2_fhdr) + 2 + ether_mtu + 8;
4271
4272 DBPRINT(sc, BCE_INFO,
4273 "%s(): mclbytes = %d, mbuf_alloc_size = %d, "
4274 "max_frame_size = %d\n",
4275 __func__, (int)MCLBYTES, sc->mbuf_alloc_size,
4276 sc->max_frame_size);
4277
4278 /* Program appropriate promiscuous/multicast filtering. */
4279 bce_set_rx_mode(sc);
4280
4281 /* Init RX buffer descriptor chain. */
4282 bce_init_rx_chain(sc); /* XXX return value */
4283
4284 /* Init TX buffer descriptor chain. */
4285 bce_init_tx_chain(sc); /* XXX return value */
4286
4287 #ifdef DEVICE_POLLING
4288 /* Disable interrupts if we are polling. */
4289 if (ifp->if_flags & IFF_POLLING) {
4290 bce_disable_intr(sc);
4291
4292 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
4293 (1 << 16) | sc->bce_rx_quick_cons_trip);
4294 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
4295 (1 << 16) | sc->bce_tx_quick_cons_trip);
4296 } else
4297 #endif
4298 /* Enable host interrupts. */
4299 bce_enable_intr(sc);
4300
4301 bce_ifmedia_upd(ifp);
4302
4303 ifp->if_flags |= IFF_RUNNING;
4304 ifp->if_flags &= ~IFF_OACTIVE;
4305
4306 callout_reset(&sc->bce_stat_ch, hz, bce_tick, sc);
4307 back:
4308 if (error)
4309 bce_stop(sc);
4310 }
4311
4312
4313 /****************************************************************************/
4314 /* Initialize the controller just enough so that any management firmware */
4315 /* running on the device will continue to operate corectly. */
4316 /* */
4317 /* Returns: */
4318 /* Nothing. */
4319 /****************************************************************************/
4320 static void
4321 bce_mgmt_init(struct bce_softc *sc)
4322 {
4323 struct ifnet *ifp = &sc->arpcom.ac_if;
4324 uint32_t val;
4325
4326 /* Check if the driver is still running and bail out if it is. */
4327 if (ifp->if_flags & IFF_RUNNING)
4328 return;
4329
4330 /* Initialize the on-boards CPUs */
4331 bce_init_cpus(sc);
4332
4333 /* Set the page size and clear the RV2P processor stall bits. */
4334 val = (BCM_PAGE_BITS - 8) << 24;
4335 REG_WR(sc, BCE_RV2P_CONFIG, val);
4336
4337 /* Enable all critical blocks in the MAC. */
4338 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
4339 BCE_MISC_ENABLE_SET_BITS_RX_V2P_ENABLE |
4340 BCE_MISC_ENABLE_SET_BITS_RX_DMA_ENABLE |
4341 BCE_MISC_ENABLE_SET_BITS_COMPLETION_ENABLE);
4342 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
4343 DELAY(20);
4344
4345 bce_ifmedia_upd(ifp);
4346 }
4347
4348
4349 /****************************************************************************/
4350 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */
4351 /* memory visible to the controller. */
4352 /* */
4353 /* Returns: */
4354 /* 0 for success, positive value for failure. */
4355 /****************************************************************************/
4356 static int
4357 bce_encap(struct bce_softc *sc, struct mbuf **m_head)
4358 {
4359 struct bce_dmamap_arg ctx;
4360 bus_dma_segment_t segs[BCE_MAX_SEGMENTS];
4361 bus_dmamap_t map, tmp_map;
4362 struct mbuf *m0 = *m_head;
4363 struct tx_bd *txbd = NULL;
4364 uint16_t vlan_tag = 0, flags = 0;
4365 uint16_t chain_prod, chain_prod_start, prod;
4366 uint32_t prod_bseq;
4367 int i, error, maxsegs;
4368 #ifdef BCE_DEBUG
4369 uint16_t debug_prod;
4370 #endif
4371
4372 /* Transfer any checksum offload flags to the bd. */
4373 if (m0->m_pkthdr.csum_flags) {
4374 if (m0->m_pkthdr.csum_flags & CSUM_IP)
4375 flags |= TX_BD_FLAGS_IP_CKSUM;
4376 if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
4377 flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
4378 }
4379
4380 /* Transfer any VLAN tags to the bd. */
4381 if (m0->m_flags & M_VLANTAG) {
4382 flags |= TX_BD_FLAGS_VLAN_TAG;
4383 vlan_tag = m0->m_pkthdr.ether_vlantag;
4384 }
4385
4386 prod = sc->tx_prod;
4387 chain_prod_start = chain_prod = TX_CHAIN_IDX(prod);
4388
4389 /* Map the mbuf into DMAable memory. */
4390 map = sc->tx_mbuf_map[chain_prod_start];
4391
4392 maxsegs = sc->max_tx_bd - sc->used_tx_bd;
4393 KASSERT(maxsegs >= BCE_TX_SPARE_SPACE,
4394 ("not enough segements %d\n", maxsegs));
4395 if (maxsegs > BCE_MAX_SEGMENTS)
4396 maxsegs = BCE_MAX_SEGMENTS;
4397
4398 /* Map the mbuf into our DMA address space. */
4399 ctx.bce_maxsegs = maxsegs;
4400 ctx.bce_segs = segs;
4401 error = bus_dmamap_load_mbuf(sc->tx_mbuf_tag, map, m0,
4402 bce_dma_map_mbuf, &ctx, BUS_DMA_NOWAIT);
4403 if (error == EFBIG || ctx.bce_maxsegs == 0) {
4404 DBPRINT(sc, BCE_WARN, "%s(): fragmented mbuf\n", __func__);
4405 DBRUNIF(1, bce_dump_mbuf(sc, m0););
4406
4407 m0 = m_defrag(*m_head, MB_DONTWAIT);
4408 if (m0 == NULL) {
4409 error = ENOBUFS;
4410 goto back;
4411 }
4412 *m_head = m0;
4413
4414 ctx.bce_maxsegs = maxsegs;
4415 ctx.bce_segs = segs;
4416 error = bus_dmamap_load_mbuf(sc->tx_mbuf_tag, map, m0,
4417 bce_dma_map_mbuf, &ctx,
4418 BUS_DMA_NOWAIT);
4419 if (error || ctx.bce_maxsegs == 0) {
4420 if_printf(&sc->arpcom.ac_if,
4421 "Error mapping mbuf into TX chain\n");
4422 if (error == 0)
4423 error = EFBIG;
4424 goto back;
4425 }
4426 } else if (error) {
4427 if_printf(&sc->arpcom.ac_if,
4428 "Error mapping mbuf into TX chain\n");
4429 goto back;
4430 }
4431
4432 /* prod points to an empty tx_bd at this point. */
4433 prod_bseq = sc->tx_prod_bseq;
4434
4435 #ifdef BCE_DEBUG
4436 debug_prod = chain_prod;
4437 #endif
4438
4439 DBPRINT(sc, BCE_INFO_SEND,
4440 "%s(): Start: prod = 0x%04X, chain_prod = %04X, "
4441 "prod_bseq = 0x%08X\n",
4442 __func__, prod, chain_prod, prod_bseq);
4443
4444 /*
4445 * Cycle through each mbuf segment that makes up
4446 * the outgoing frame, gathering the mapping info
4447 * for that segment and creating a tx_bd to for
4448 * the mbuf.
4449 */
4450 for (i = 0; i < ctx.bce_maxsegs; i++) {
4451 chain_prod = TX_CHAIN_IDX(prod);
4452 txbd= &sc->tx_bd_chain[TX_PAGE(chain_prod)][TX_IDX(chain_prod)];
4453
4454 txbd->tx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[i].ds_addr));
4455 txbd->tx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[i].ds_addr));
4456 txbd->tx_bd_mss_nbytes = htole16(segs[i].ds_len);
4457 txbd->tx_bd_vlan_tag = htole16(vlan_tag);
4458 txbd->tx_bd_flags = htole16(flags);
4459 prod_bseq += segs[i].ds_len;
4460 if (i == 0)
4461 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START);
4462 prod = NEXT_TX_BD(prod);
4463 }
4464
4465 /* Set the END flag on the last TX buffer descriptor. */
4466 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END);
4467
4468 DBRUN(BCE_EXCESSIVE_SEND,
4469 bce_dump_tx_chain(sc, debug_prod, ctx.bce_maxsegs));
4470
4471 DBPRINT(sc, BCE_INFO_SEND,
4472 "%s(): End: prod = 0x%04X, chain_prod = %04X, "
4473 "prod_bseq = 0x%08X\n",
4474 __func__, prod, chain_prod, prod_bseq);
4475
4476 bus_dmamap_sync(sc->tx_mbuf_tag, map, BUS_DMASYNC_PREWRITE);
4477
4478 /*
4479 * Ensure that the mbuf pointer for this transmission
4480 * is placed at the array index of the last
4481 * descriptor in this chain. This is done
4482 * because a single map is used for all
4483 * segments of the mbuf and we don't want to
4484 * unload the map before all of the segments
4485 * have been freed.
4486 */
4487 sc->tx_mbuf_ptr[chain_prod] = m0;
4488
4489 tmp_map = sc->tx_mbuf_map[chain_prod];
4490 sc->tx_mbuf_map[chain_prod] = map;
4491 sc->tx_mbuf_map[chain_prod_start] = tmp_map;
4492
4493 sc->used_tx_bd += ctx.bce_maxsegs;
4494
4495 /* Update some debug statistic counters */
4496 DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark),
4497 sc->tx_hi_watermark = sc->used_tx_bd);
4498 DBRUNIF((sc->used_tx_bd == sc->max_tx_bd), sc->tx_full_count++);
4499 DBRUNIF(1, sc->tx_mbuf_alloc++);
4500
4501 DBRUN(BCE_VERBOSE_SEND,
4502 bce_dump_tx_mbuf_chain(sc, chain_prod, ctx.bce_maxsegs));
4503
4504 /* prod points to the next free tx_bd at this point. */
4505 sc->tx_prod = prod;
4506 sc->tx_prod_bseq = prod_bseq;
4507 back:
4508 if (error) {
4509 m_freem(*m_head);
4510 *m_head = NULL;
4511 }
4512 return error;
4513 }
4514
4515
4516 /****************************************************************************/
4517 /* Main transmit routine when called from another routine with a lock. */
4518 /* */
4519 /* Returns: */
4520 /* Nothing. */
4521 /****************************************************************************/
4522 static void
4523 bce_start(struct ifnet *ifp)
4524 {
4525 struct bce_softc *sc = ifp->if_softc;
4526 int count = 0;
4527
4528 ASSERT_SERIALIZED(ifp->if_serializer);
4529
4530 /* If there's no link or the transmit queue is empty then just exit. */
4531 if (!sc->bce_link) {
4532 ifq_purge(&ifp->if_snd);
4533 return;
4534 }
4535
4536 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
4537 return;
4538
4539 DBPRINT(sc, BCE_INFO_SEND,
4540 "%s(): Start: tx_prod = 0x%04X, tx_chain_prod = %04X, "
4541 "tx_prod_bseq = 0x%08X\n",
4542 __func__,
4543 sc->tx_prod, TX_CHAIN_IDX(sc->tx_prod), sc->tx_prod_bseq);
4544
4545 for (;;) {
4546 struct mbuf *m_head;
4547
4548 /*
4549 * We keep BCE_TX_SPARE_SPACE entries, so bce_encap() is
4550 * unlikely to fail.
4551 */
4552 if (sc->max_tx_bd - sc->used_tx_bd < BCE_TX_SPARE_SPACE) {
4553 ifp->if_flags |= IFF_OACTIVE;
4554 break;
4555 }
4556
4557 /* Check for any frames to send. */
4558 m_head = ifq_dequeue(&ifp->if_snd, NULL);
4559 if (m_head == NULL)
4560 break;
4561
4562 /*
4563 * Pack the data into the transmit ring. If we
4564 * don't have room, place the mbuf back at the
4565 * head of the queue and set the OACTIVE flag
4566 * to wait for the NIC to drain the chain.
4567 */
4568 if (bce_encap(sc, &m_head)) {
4569 ifp->if_flags |= IFF_OACTIVE;
4570 DBPRINT(sc, BCE_INFO_SEND,
4571 "TX chain is closed for business! "
4572 "Total tx_bd used = %d\n",
4573 sc->used_tx_bd);
4574 break;
4575 }
4576
4577 count++;
4578
4579 /* Send a copy of the frame to any BPF listeners. */
4580 ETHER_BPF_MTAP(ifp, m_head);
4581 }
4582
4583 if (count == 0) {
4584 /* no packets were dequeued */
4585 DBPRINT(sc, BCE_VERBOSE_SEND,
4586 "%s(): No packets were dequeued\n", __func__);
4587 return;
4588 }
4589
4590 DBPRINT(sc, BCE_INFO_SEND,
4591 "%s(): End: tx_prod = 0x%04X, tx_chain_prod = 0x%04X, "
4592 "tx_prod_bseq = 0x%08X\n",
4593 __func__,
4594 sc->tx_prod, TX_CHAIN_IDX(sc->tx_prod), sc->tx_prod_bseq);
4595
4596 /* Start the transmit. */
4597 REG_WR16(sc, MB_TX_CID_ADDR + BCE_L2CTX_TX_HOST_BIDX, sc->tx_prod);
4598 REG_WR(sc, MB_TX_CID_ADDR + BCE_L2CTX_TX_HOST_BSEQ, sc->tx_prod_bseq);
4599
4600 /* Set the tx timeout. */
4601 ifp->if_timer = BCE_TX_TIMEOUT;
4602 }
4603
4604
4605 /****************************************************************************/
4606 /* Handles any IOCTL calls from the operating system. */
4607 /* */
4608 /* Returns: */
4609 /* 0 for success, positive value for failure. */
4610 /****************************************************************************/
4611 static int
4612 bce_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
4613 {
4614 struct bce_softc *sc = ifp->if_softc;
4615 struct ifreq *ifr = (struct ifreq *)data;
4616 struct mii_data *mii;
4617 int mask, error = 0;
4618
4619 ASSERT_SERIALIZED(ifp->if_serializer);
4620
4621 switch(command) {
4622 case SIOCSIFMTU:
4623 /* Check that the MTU setting is supported. */
4624 if (ifr->ifr_mtu < BCE_MIN_MTU ||
4625 #ifdef notyet
4626 ifr->ifr_mtu > BCE_MAX_JUMBO_MTU
4627 #else
4628 ifr->ifr_mtu > ETHERMTU
4629 #endif
4630 ) {
4631 error = EINVAL;
4632 break;
4633 }
4634
4635 DBPRINT(sc, BCE_INFO, "Setting new MTU of %d\n", ifr->ifr_mtu);
4636
4637 ifp->if_mtu = ifr->ifr_mtu;
4638 ifp->if_flags &= ~IFF_RUNNING; /* Force reinitialize */
4639 bce_init(sc);
4640 break;
4641
4642 case SIOCSIFFLAGS:
4643 if (ifp->if_flags & IFF_UP) {
4644 if (ifp->if_flags & IFF_RUNNING) {
4645 mask = ifp->if_flags ^ sc->bce_if_flags;
4646
4647 if (mask & (IFF_PROMISC | IFF_ALLMULTI))
4648 bce_set_rx_mode(sc);
4649 } else {
4650 bce_init(sc);
4651 }
4652 } else if (ifp->if_flags & IFF_RUNNING) {
4653 bce_stop(sc);
4654 }
4655 sc->bce_if_flags = ifp->if_flags;
4656 break;
4657
4658 case SIOCADDMULTI:
4659 case SIOCDELMULTI:
4660 if (ifp->if_flags & IFF_RUNNING)
4661 bce_set_rx_mode(sc);
4662 break;
4663
4664 case SIOCSIFMEDIA:
4665 case SIOCGIFMEDIA:
4666 DBPRINT(sc, BCE_VERBOSE, "bce_phy_flags = 0x%08X\n",
4667 sc->bce_phy_flags);
4668 DBPRINT(sc, BCE_VERBOSE, "Copper media set/get\n");
4669
4670 mii = device_get_softc(sc->bce_miibus);
4671 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
4672 break;
4673
4674 case SIOCSIFCAP:
4675 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
4676 DBPRINT(sc, BCE_INFO, "Received SIOCSIFCAP = 0x%08X\n",
4677 (uint32_t) mask);
4678
4679 if (mask & IFCAP_HWCSUM) {
4680 ifp->if_capenable ^= IFCAP_HWCSUM;
4681 if (IFCAP_HWCSUM & ifp->if_capenable)
4682 ifp->if_hwassist = BCE_IF_HWASSIST;
4683 else
4684 ifp->if_hwassist = 0;
4685 }
4686 break;
4687
4688 default:
4689 error = ether_ioctl(ifp, command, data);
4690 break;
4691 }
4692 return error;
4693 }
4694
4695
4696 /****************************************************************************/
4697 /* Transmit timeout handler. */
4698 /* */
4699 /* Returns: */
4700 /* Nothing. */
4701 /****************************************************************************/
4702 static void
4703 bce_watchdog(struct ifnet *ifp)
4704 {
4705 struct bce_softc *sc = ifp->if_softc;
4706
4707 ASSERT_SERIALIZED(ifp->if_serializer);
4708
4709 DBRUN(BCE_VERBOSE_SEND,
4710 bce_dump_driver_state(sc);
4711 bce_dump_status_block(sc));
4712
4713 /*
4714 * If we are in this routine because of pause frames, then
4715 * don't reset the hardware.
4716 */
4717 if (REG_RD(sc, BCE_EMAC_TX_STATUS) & BCE_EMAC_TX_STATUS_XOFFED)
4718 return;
4719
4720 if_printf(ifp, "Watchdog timeout occurred, resetting!\n");
4721
4722 /* DBRUN(BCE_FATAL, bce_breakpoint(sc)); */
4723
4724 ifp->if_flags &= ~IFF_RUNNING; /* Force reinitialize */
4725 bce_init(sc);
4726
4727 ifp->if_oerrors++;
4728
4729 if (!ifq_is_empty(&ifp->if_snd))
4730 if_devstart(ifp);
4731 }
4732
4733
4734 #ifdef DEVICE_POLLING
4735
4736 static void
4737 bce_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
4738 {
4739 struct bce_softc *sc = ifp->if_softc;
4740 struct status_block *sblk = sc->status_block;
4741 uint16_t hw_tx_cons, hw_rx_cons;
4742
4743 ASSERT_SERIALIZED(ifp->if_serializer);
4744
4745 switch (cmd) {
4746 case POLL_REGISTER:
4747 bce_disable_intr(sc);
4748
4749 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
4750 (1 << 16) | sc->bce_rx_quick_cons_trip);
4751 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
4752 (1 << 16) | sc->bce_tx_quick_cons_trip);
4753 return;
4754 case POLL_DEREGISTER:
4755 bce_enable_intr(sc);
4756
4757 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
4758 (sc->bce_tx_quick_cons_trip_int << 16) |
4759 sc->bce_tx_quick_cons_trip);
4760 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
4761 (sc->bce_rx_quick_cons_trip_int << 16) |
4762 sc->bce_rx_quick_cons_trip);
4763 return;
4764 default:
4765 break;
4766 }
4767
4768 bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_POSTREAD);
4769
4770 if (cmd == POLL_AND_CHECK_STATUS) {
4771 uint32_t status_attn_bits;
4772
4773 status_attn_bits = sblk->status_attn_bits;
4774
4775 DBRUNIF(DB_RANDOMTRUE(bce_debug_unexpected_attention),
4776 if_printf(ifp,
4777 "Simulating unexpected status attention bit set.");
4778 status_attn_bits |= STATUS_ATTN_BITS_PARITY_ERROR);
4779
4780 /* Was it a link change interrupt? */
4781 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) !=
4782 (sblk->status_attn_bits_ack & STATUS_ATTN_BITS_LINK_STATE))
4783 bce_phy_intr(sc);
4784
4785 /*
4786 * If any other attention is asserted then
4787 * the chip is toast.
4788 */
4789 if ((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) !=
4790 (sblk->status_attn_bits_ack &
4791 ~STATUS_ATTN_BITS_LINK_STATE)) {
4792 DBRUN(1, sc->unexpected_attentions++);
4793
4794 if_printf(ifp, "Fatal attention detected: 0x%08X\n",
4795 sblk->status_attn_bits);
4796
4797 DBRUN(BCE_FATAL,
4798 if (bce_debug_unexpected_attention == 0)
4799 bce_breakpoint(sc));
4800
4801 bce_init(sc);
4802 return;
4803 }
4804 }
4805
4806 hw_rx_cons = bce_get_hw_rx_cons(sc);
4807 hw_tx_cons = bce_get_hw_tx_cons(sc);
4808
4809 /* Check for any completed RX frames. */
4810 if (hw_rx_cons != sc->hw_rx_cons)
4811 bce_rx_intr(sc, count);
4812
4813 /* Check for any completed TX frames. */
4814 if (hw_tx_cons != sc->hw_tx_cons)
4815 bce_tx_intr(sc);
4816
4817 bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_PREWRITE);
4818
4819 /* Check for new frames to transmit. */
4820 if (!ifq_is_empty(&ifp->if_snd))
4821 if_devstart(ifp);
4822 }
4823
4824 #endif /* DEVICE_POLLING */
4825
4826
4827 /*
4828 * Interrupt handler.
4829 */
4830 /****************************************************************************/
4831 /* Main interrupt entry point. Verifies that the controller generated the */
4832 /* interrupt and then calls a separate routine for handle the various */
4833 /* interrupt causes (PHY, TX, RX). */
4834 /* */
4835 /* Returns: */
4836 /* 0 for success, positive value for failure. */
4837 /****************************************************************************/
4838 static void
4839 bce_intr(void *xsc)
4840 {
4841 struct bce_softc *sc = xsc;
4842 struct ifnet *ifp = &sc->arpcom.ac_if;
4843 struct status_block *sblk;
4844 uint16_t hw_rx_cons, hw_tx_cons;
4845
4846 ASSERT_SERIALIZED(ifp->if_serializer);
4847
4848 DBPRINT(sc, BCE_EXCESSIVE, "Entering %s()\n", __func__);
4849 DBRUNIF(1, sc->interrupts_generated++);
4850
4851 bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_POSTREAD);
4852 sblk = sc->status_block;
4853
4854 /*
4855 * If the hardware status block index matches the last value
4856 * read by the driver and we haven't asserted our interrupt
4857 * then there's nothing to do.
4858 */
4859 if (sblk->status_idx == sc->last_status_idx &&
4860 (REG_RD(sc, BCE_PCICFG_MISC_STATUS) &
4861 BCE_PCICFG_MISC_STATUS_INTA_VALUE))
4862 return;
4863
4864 /* Ack the interrupt and stop others from occuring. */
4865 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
4866 BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
4867 BCE_PCICFG_INT_ACK_CMD_MASK_INT);
4868
4869 /* Check if the hardware has finished any work. */
4870 hw_rx_cons = bce_get_hw_rx_cons(sc);
4871 hw_tx_cons = bce_get_hw_tx_cons(sc);
4872
4873 /* Keep processing data as long as there is work to do. */
4874 for (;;) {
4875 uint32_t status_attn_bits;
4876
4877 status_attn_bits = sblk->status_attn_bits;
4878
4879 DBRUNIF(DB_RANDOMTRUE(bce_debug_unexpected_attention),
4880 if_printf(ifp,
4881 "Simulating unexpected status attention bit set.");
4882 status_attn_bits |= STATUS_ATTN_BITS_PARITY_ERROR);
4883
4884 /* Was it a link change interrupt? */
4885 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) !=
4886 (sblk->status_attn_bits_ack & STATUS_ATTN_BITS_LINK_STATE))
4887 bce_phy_intr(sc);
4888
4889 /*
4890 * If any other attention is asserted then
4891 * the chip is toast.
4892 */
4893 if ((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) !=
4894 (sblk->status_attn_bits_ack &
4895 ~STATUS_ATTN_BITS_LINK_STATE)) {
4896 DBRUN(1, sc->unexpected_attentions++);
4897
4898 if_printf(ifp, "Fatal attention detected: 0x%08X\n",
4899 sblk->status_attn_bits);
4900
4901 DBRUN(BCE_FATAL,
4902 if (bce_debug_unexpected_attention == 0)
4903 bce_breakpoint(sc));
4904
4905 bce_init(sc);
4906 return;
4907 }
4908
4909 /* Check for any completed RX frames. */
4910 if (hw_rx_cons != sc->hw_rx_cons)
4911 bce_rx_intr(sc, -1);
4912
4913 /* Check for any completed TX frames. */
4914 if (hw_tx_cons != sc->hw_tx_cons)
4915 bce_tx_intr(sc);
4916
4917 /*
4918 * Save the status block index value
4919 * for use during the next interrupt.
4920 */
4921 sc->last_status_idx = sblk->status_idx;
4922
4923 /*
4924 * Prevent speculative reads from getting
4925 * ahead of the status block.
4926 */
4927 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
4928 BUS_SPACE_BARRIER_READ);
4929
4930 /*
4931 * If there's no work left then exit the
4932 * interrupt service routine.
4933 */
4934 hw_rx_cons = bce_get_hw_rx_cons(sc);
4935 hw_tx_cons = bce_get_hw_tx_cons(sc);
4936 if ((hw_rx_cons == sc->hw_rx_cons) && (hw_tx_cons == sc->hw_tx_cons))
4937 break;
4938 }
4939
4940 bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_PREWRITE);
4941
4942 /* Re-enable interrupts. */
4943 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
4944 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx |
4945 BCE_PCICFG_INT_ACK_CMD_MASK_INT);
4946 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
4947 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx);
4948
4949 if (sc->bce_coalchg_mask)
4950 bce_coal_change(sc);
4951
4952 /* Handle any frames that arrived while handling the interrupt. */
4953 if (!ifq_is_empty(&ifp->if_snd))
4954 if_devstart(ifp);
4955 }
4956
4957
4958 /****************************************************************************/
4959 /* Programs the various packet receive modes (broadcast and multicast). */
4960 /* */
4961 /* Returns: */
4962 /* Nothing. */
4963 /****************************************************************************/
4964 static void
4965 bce_set_rx_mode(struct bce_softc *sc)
4966 {
4967 struct ifnet *ifp = &sc->arpcom.ac_if;
4968 struct ifmultiaddr *ifma;
4969 uint32_t hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 };
4970 uint32_t rx_mode, sort_mode;
4971 int h, i;
4972
4973 ASSERT_SERIALIZED(ifp->if_serializer);
4974
4975 /* Initialize receive mode default settings. */
4976 rx_mode = sc->rx_mode &
4977 ~(BCE_EMAC_RX_MODE_PROMISCUOUS |
4978 BCE_EMAC_RX_MODE_KEEP_VLAN_TAG);
4979 sort_mode = 1 | BCE_RPM_SORT_USER0_BC_EN;
4980
4981 /*
4982 * ASF/IPMI/UMP firmware requires that VLAN tag stripping
4983 * be enbled.
4984 */
4985 if (!(BCE_IF_CAPABILITIES & IFCAP_VLAN_HWTAGGING) &&
4986 !(sc->bce_flags & BCE_MFW_ENABLE_FLAG))
4987 rx_mode |= BCE_EMAC_RX_MODE_KEEP_VLAN_TAG;
4988
4989 /*
4990 * Check for promiscuous, all multicast, or selected
4991 * multicast address filtering.
4992 */
4993 if (ifp->if_flags & IFF_PROMISC) {
4994 DBPRINT(sc, BCE_INFO, "Enabling promiscuous mode.\n");
4995
4996 /* Enable promiscuous mode. */
4997 rx_mode |= BCE_EMAC_RX_MODE_PROMISCUOUS;
4998 sort_mode |= BCE_RPM_SORT_USER0_PROM_EN;
4999 } else if (ifp->if_flags & IFF_ALLMULTI) {
5000 DBPRINT(sc, BCE_INFO, "Enabling all multicast mode.\n");
5001
5002 /* Enable all multicast addresses. */
5003 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
5004 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4),
5005 0xffffffff);
5006 }
5007 sort_mode |= BCE_RPM_SORT_USER0_MC_EN;
5008 } else {
5009 /* Accept one or more multicast(s). */
5010 DBPRINT(sc, BCE_INFO, "Enabling selective multicast mode.\n");
5011
5012 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
5013 if (ifma->ifma_addr->sa_family != AF_LINK)
5014 continue;
5015 h = ether_crc32_le(
5016 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
5017 ETHER_ADDR_LEN) & 0xFF;
5018 hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F);
5019 }
5020
5021 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
5022 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4),
5023 hashes[i]);
5024 }
5025 sort_mode |= BCE_RPM_SORT_USER0_MC_HSH_EN;
5026 }
5027
5028 /* Only make changes if the recive mode has actually changed. */
5029 if (rx_mode != sc->rx_mode) {
5030 DBPRINT(sc, BCE_VERBOSE, "Enabling new receive mode: 0x%08X\n",
5031 rx_mode);
5032
5033 sc->rx_mode = rx_mode;
5034 REG_WR(sc, BCE_EMAC_RX_MODE, rx_mode);
5035 }
5036
5037 /* Disable and clear the exisitng sort before enabling a new sort. */
5038 REG_WR(sc, BCE_RPM_SORT_USER0, 0x0);
5039 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode);
5040 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode | BCE_RPM_SORT_USER0_ENA);
5041 }
5042
5043
5044 /****************************************************************************/
5045 /* Called periodically to updates statistics from the controllers */
5046 /* statistics block. */
5047 /* */
5048 /* Returns: */
5049 /* Nothing. */
5050 /****************************************************************************/
5051 static void
5052 bce_stats_update(struct bce_softc *sc)
5053 {
5054 struct ifnet *ifp = &sc->arpcom.ac_if;
5055 struct statistics_block *stats = sc->stats_block;
5056
5057 DBPRINT(sc, BCE_EXCESSIVE, "Entering %s()\n", __func__);
5058
5059 ASSERT_SERIALIZED(ifp->if_serializer);
5060
5061 /*
5062 * Update the interface statistics from the hardware statistics.
5063 */
5064 ifp->if_collisions = (u_long)stats->stat_EtherStatsCollisions;
5065
5066 ifp->if_ierrors = (u_long)stats->stat_EtherStatsUndersizePkts +
5067 (u_long)stats->stat_EtherStatsOverrsizePkts +
5068 (u_long)stats->stat_IfInMBUFDiscards +
5069 (u_long)stats->stat_Dot3StatsAlignmentErrors +
5070 (u_long)stats->stat_Dot3StatsFCSErrors;
5071
5072 ifp->if_oerrors =
5073 (u_long)stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors +
5074 (u_long)stats->stat_Dot3StatsExcessiveCollisions +
5075 (u_long)stats->stat_Dot3StatsLateCollisions;
5076
5077 /*
5078 * Certain controllers don't report carrier sense errors correctly.
5079 * See errata E11_5708CA0_1165.
5080 */
5081 if (!(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) &&
5082 !(BCE_CHIP_ID(sc) == BCE_CHIP_ID_5708_A0)) {
5083 ifp->if_oerrors +=
5084 (u_long)stats->stat_Dot3StatsCarrierSenseErrors;
5085 }
5086
5087 /*
5088 * Update the sysctl statistics from the hardware statistics.
5089 */
5090 sc->stat_IfHCInOctets =
5091 ((uint64_t)stats->stat_IfHCInOctets_hi << 32) +
5092 (uint64_t)stats->stat_IfHCInOctets_lo;
5093
5094 sc->stat_IfHCInBadOctets =
5095 ((uint64_t)stats->stat_IfHCInBadOctets_hi << 32) +
5096 (uint64_t)stats->stat_IfHCInBadOctets_lo;
5097
5098 sc->stat_IfHCOutOctets =
5099 ((uint64_t)stats->stat_IfHCOutOctets_hi << 32) +
5100 (uint64_t)stats->stat_IfHCOutOctets_lo;
5101
5102 sc->stat_IfHCOutBadOctets =
5103 ((uint64_t)stats->stat_IfHCOutBadOctets_hi << 32) +
5104 (uint64_t)stats->stat_IfHCOutBadOctets_lo;
5105
5106 sc->stat_IfHCInUcastPkts =
5107 ((uint64_t)stats->stat_IfHCInUcastPkts_hi << 32) +
5108 (uint64_t)stats->stat_IfHCInUcastPkts_lo;
5109
5110 sc->stat_IfHCInMulticastPkts =
5111 ((uint64_t)stats->stat_IfHCInMulticastPkts_hi << 32) +
5112 (uint64_t)stats->stat_IfHCInMulticastPkts_lo;
5113
5114 sc->stat_IfHCInBroadcastPkts =
5115 ((uint64_t)stats->stat_IfHCInBroadcastPkts_hi << 32) +
5116 (uint64_t)stats->stat_IfHCInBroadcastPkts_lo;
5117
5118 sc->stat_IfHCOutUcastPkts =
5119 ((uint64_t)stats->stat_IfHCOutUcastPkts_hi << 32) +
5120 (uint64_t)stats->stat_IfHCOutUcastPkts_lo;
5121
5122 sc->stat_IfHCOutMulticastPkts =
5123 ((uint64_t)stats->stat_IfHCOutMulticastPkts_hi << 32) +
5124 (uint64_t)stats->stat_IfHCOutMulticastPkts_lo;
5125
5126 sc->stat_IfHCOutBroadcastPkts =
5127 ((uint64_t)stats->stat_IfHCOutBroadcastPkts_hi << 32) +
5128 (uint64_t)stats->stat_IfHCOutBroadcastPkts_lo;
5129
5130 sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors =
5131 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
5132
5133 sc->stat_Dot3StatsCarrierSenseErrors =
5134 stats->stat_Dot3StatsCarrierSenseErrors;
5135
5136 sc->stat_Dot3StatsFCSErrors =
5137 stats->stat_Dot3StatsFCSErrors;
5138
5139 sc->stat_Dot3StatsAlignmentErrors =
5140 stats->stat_Dot3StatsAlignmentErrors;
5141
5142 sc->stat_Dot3StatsSingleCollisionFrames =
5143 stats->stat_Dot3StatsSingleCollisionFrames;
5144
5145 sc->stat_Dot3StatsMultipleCollisionFrames =
5146 stats->stat_Dot3StatsMultipleCollisionFrames;
5147
5148 sc->stat_Dot3StatsDeferredTransmissions =
5149 stats->stat_Dot3StatsDeferredTransmissions;
5150
5151 sc->stat_Dot3StatsExcessiveCollisions =
5152 stats->stat_Dot3StatsExcessiveCollisions;
5153
5154 sc->stat_Dot3StatsLateCollisions =
5155 stats->stat_Dot3StatsLateCollisions;
5156
5157 sc->stat_EtherStatsCollisions =
5158 stats->stat_EtherStatsCollisions;
5159
5160 sc->stat_EtherStatsFragments =
5161 stats->stat_EtherStatsFragments;
5162
5163 sc->stat_EtherStatsJabbers =
5164 stats->stat_EtherStatsJabbers;
5165
5166 sc->stat_EtherStatsUndersizePkts =
5167 stats->stat_EtherStatsUndersizePkts;
5168
5169 sc->stat_EtherStatsOverrsizePkts =
5170 stats->stat_EtherStatsOverrsizePkts;
5171
5172 sc->stat_EtherStatsPktsRx64Octets =
5173 stats->stat_EtherStatsPktsRx64Octets;
5174
5175 sc->stat_EtherStatsPktsRx65Octetsto127Octets =
5176 stats->stat_EtherStatsPktsRx65Octetsto127Octets;
5177
5178 sc->stat_EtherStatsPktsRx128Octetsto255Octets =
5179 stats->stat_EtherStatsPktsRx128Octetsto255Octets;
5180
5181 sc->stat_EtherStatsPktsRx256Octetsto511Octets =
5182 stats->stat_EtherStatsPktsRx256Octetsto511Octets;
5183
5184 sc->stat_EtherStatsPktsRx512Octetsto1023Octets =
5185 stats->stat_EtherStatsPktsRx512Octetsto1023Octets;
5186
5187 sc->stat_EtherStatsPktsRx1024Octetsto1522Octets =
5188 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets;
5189
5190 sc->stat_EtherStatsPktsRx1523Octetsto9022Octets =
5191 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets;
5192
5193 sc->stat_EtherStatsPktsTx64Octets =
5194 stats->stat_EtherStatsPktsTx64Octets;
5195
5196 sc->stat_EtherStatsPktsTx65Octetsto127Octets =
5197 stats->stat_EtherStatsPktsTx65Octetsto127Octets;
5198
5199 sc->stat_EtherStatsPktsTx128Octetsto255Octets =
5200 stats->stat_EtherStatsPktsTx128Octetsto255Octets;
5201
5202 sc->stat_EtherStatsPktsTx256Octetsto511Octets =
5203 stats->stat_EtherStatsPktsTx256Octetsto511Octets;
5204
5205 sc->stat_EtherStatsPktsTx512Octetsto1023Octets =
5206 stats->stat_EtherStatsPktsTx512Octetsto1023Octets;
5207
5208 sc->stat_EtherStatsPktsTx1024Octetsto1522Octets =
5209 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets;
5210
5211 sc->stat_EtherStatsPktsTx1523Octetsto9022Octets =
5212 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets;
5213
5214 sc->stat_XonPauseFramesReceived =
5215 stats->stat_XonPauseFramesReceived;
5216
5217 sc->stat_XoffPauseFramesReceived =
5218 stats->stat_XoffPauseFramesReceived;
5219
5220 sc->stat_OutXonSent =
5221 stats->stat_OutXonSent;
5222
5223 sc->stat_OutXoffSent =
5224 stats->stat_OutXoffSent;
5225
5226 sc->stat_FlowControlDone =
5227 stats->stat_FlowControlDone;
5228
5229 sc->stat_MacControlFramesReceived =
5230 stats->stat_MacControlFramesReceived;
5231
5232 sc->stat_XoffStateEntered =
5233 stats->stat_XoffStateEntered;
5234
5235 sc->stat_IfInFramesL2FilterDiscards =
5236 stats->stat_IfInFramesL2FilterDiscards;
5237
5238 sc->stat_IfInRuleCheckerDiscards =
5239 stats->stat_IfInRuleCheckerDiscards;
5240
5241 sc->stat_IfInFTQDiscards =
5242 stats->stat_IfInFTQDiscards;
5243
5244 sc->stat_IfInMBUFDiscards =
5245 stats->stat_IfInMBUFDiscards;
5246
5247 sc->stat_IfInRuleCheckerP4Hit =
5248 stats->stat_IfInRuleCheckerP4Hit;
5249
5250 sc->stat_CatchupInRuleCheckerDiscards =
5251 stats->stat_CatchupInRuleCheckerDiscards;
5252
5253 sc->stat_CatchupInFTQDiscards =
5254 stats->stat_CatchupInFTQDiscards;
5255
5256 sc->stat_CatchupInMBUFDiscards =
5257 stats->stat_CatchupInMBUFDiscards;
5258
5259 sc->stat_CatchupInRuleCheckerP4Hit =
5260 stats->stat_CatchupInRuleCheckerP4Hit;
5261
5262 sc->com_no_buffers = REG_RD_IND(sc, 0x120084);
5263
5264 DBPRINT(sc, BCE_EXCESSIVE, "Exiting %s()\n", __func__);
5265 }
5266
5267
5268 /****************************************************************************/
5269 /* Periodic function to perform maintenance tasks. */
5270 /* */
5271 /* Returns: */
5272 /* Nothing. */
5273 /****************************************************************************/
5274 static void
5275 bce_tick_serialized(struct bce_softc *sc)
5276 {
5277 struct ifnet *ifp = &sc->arpcom.ac_if;
5278 struct mii_data *mii;
5279 uint32_t msg;
5280
5281 ASSERT_SERIALIZED(ifp->if_serializer);
5282
5283 /* Tell the firmware that the driver is still running. */
5284 #ifdef BCE_DEBUG
5285 msg = (uint32_t)BCE_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE;
5286 #else
5287 msg = (uint32_t)++sc->bce_fw_drv_pulse_wr_seq;
5288 #endif
5289 REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_PULSE_MB, msg);
5290
5291 /* Update the statistics from the hardware statistics block. */
5292 bce_stats_update(sc);
5293
5294 /* Schedule the next tick. */
5295 callout_reset(&sc->bce_stat_ch, hz, bce_tick, sc);
5296
5297 /* If link is up already up then we're done. */
5298 if (sc->bce_link)
5299 return;
5300
5301 mii = device_get_softc(sc->bce_miibus);
5302 mii_tick(mii);
5303
5304 /* Check if the link has come up. */
5305 if (!sc->bce_link && (mii->mii_media_status & IFM_ACTIVE) &&
5306 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
5307 sc->bce_link++;
5308 /* Now that link is up, handle any outstanding TX traffic. */
5309 if (!ifq_is_empty(&ifp->if_snd))
5310 if_devstart(ifp);
5311 }
5312 }
5313
5314
5315 static void
5316 bce_tick(void *xsc)
5317 {
5318 struct bce_softc *sc = xsc;
5319 struct ifnet *ifp = &sc->arpcom.ac_if;
5320
5321 lwkt_serialize_enter(ifp->if_serializer);
5322 bce_tick_serialized(sc);
5323 lwkt_serialize_exit(ifp->if_serializer);
5324 }
5325
5326
5327 #ifdef BCE_DEBUG
5328 /****************************************************************************/
5329 /* Allows the driver state to be dumped through the sysctl interface. */
5330 /* */
5331 /* Returns: */
5332 /* 0 for success, positive value for failure. */
5333 /****************************************************************************/
5334 static int
5335 bce_sysctl_driver_state(SYSCTL_HANDLER_ARGS)
5336 {
5337 int error;
5338 int result;
5339 struct bce_softc *sc;
5340
5341 result = -1;
5342 error = sysctl_handle_int(oidp, &result, 0, req);
5343
5344 if (error || !req->newptr)
5345 return (error);
5346
5347 if (result == 1) {
5348 sc = (struct bce_softc *)arg1;
5349 bce_dump_driver_state(sc);
5350 }
5351
5352 return error;
5353 }
5354
5355
5356 /****************************************************************************/
5357 /* Allows the hardware state to be dumped through the sysctl interface. */
5358 /* */
5359 /* Returns: */
5360 /* 0 for success, positive value for failure. */
5361 /****************************************************************************/
5362 static int
5363 bce_sysctl_hw_state(SYSCTL_HANDLER_ARGS)
5364 {
5365 int error;
5366 int result;
5367 struct bce_softc *sc;
5368
5369 result = -1;
5370 error = sysctl_handle_int(oidp, &result, 0, req);
5371
5372 if (error || !req->newptr)
5373 return (error);
5374
5375 if (result == 1) {
5376 sc = (struct bce_softc *)arg1;
5377 bce_dump_hw_state(sc);
5378 }
5379
5380 return error;
5381 }
5382
5383
5384 /****************************************************************************/
5385 /* Provides a sysctl interface to allows dumping the RX chain. */
5386 /* */
5387 /* Returns: */
5388 /* 0 for success, positive value for failure. */
5389 /****************************************************************************/
5390 static int
5391 bce_sysctl_dump_rx_chain(SYSCTL_HANDLER_ARGS)
5392 {
5393 int error;
5394 int result;
5395 struct bce_softc *sc;
5396
5397 result = -1;
5398 error = sysctl_handle_int(oidp, &result, 0, req);
5399
5400 if (error || !req->newptr)
5401 return (error);
5402
5403 if (result == 1) {
5404 sc = (struct bce_softc *)arg1;
5405 bce_dump_rx_chain(sc, 0, USABLE_RX_BD);
5406 }
5407
5408 return error;
5409 }
5410
5411
5412 /****************************************************************************/
5413 /* Provides a sysctl interface to allows dumping the TX chain. */
5414 /* */
5415 /* Returns: */
5416 /* 0 for success, positive value for failure. */
5417 /****************************************************************************/
5418 static int
5419 bce_sysctl_dump_tx_chain(SYSCTL_HANDLER_ARGS)
5420 {
5421 int error;
5422 int result;
5423 struct bce_softc *sc;
5424
5425 result = -1;
5426 error = sysctl_handle_int(oidp, &result, 0, req);
5427
5428 if (error || !req->newptr)
5429 return (error);
5430
5431 if (result == 1) {
5432 sc = (struct bce_softc *)arg1;
5433 bce_dump_tx_chain(sc, 0, USABLE_TX_BD);
5434 }
5435
5436 return error;
5437 }
5438
5439
5440 /****************************************************************************/
5441 /* Provides a sysctl interface to allow reading arbitrary registers in the */
5442 /* device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */
5443 /* */
5444 /* Returns: */
5445 /* 0 for success, positive value for failure. */
5446 /****************************************************************************/
5447 static int
5448 bce_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
5449 {
5450 struct bce_softc *sc;
5451 int error;
5452 uint32_t val, result;
5453
5454 result = -1;
5455 error = sysctl_handle_int(oidp, &result, 0, req);
5456 if (error || (req->newptr == NULL))
5457 return (error);
5458
5459 /* Make sure the register is accessible. */
5460 if (result < 0x8000) {
5461 sc = (struct bce_softc *)arg1;
5462 val = REG_RD(sc, result);
5463 if_printf(&sc->arpcom.ac_if, "reg 0x%08X = 0x%08X\n",
5464 result, val);
5465 } else if (result < 0x0280000) {
5466 sc = (struct bce_softc *)arg1;
5467 val = REG_RD_IND(sc, result);
5468 if_printf(&sc->arpcom.ac_if, "reg 0x%08X = 0x%08X\n",
5469 result, val);
5470 }
5471 return (error);
5472 }
5473
5474
5475 /****************************************************************************/
5476 /* Provides a sysctl interface to allow reading arbitrary PHY registers in */
5477 /* the device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */
5478 /* */
5479 /* Returns: */
5480 /* 0 for success, positive value for failure. */
5481 /****************************************************************************/
5482 static int
5483 bce_sysctl_phy_read(SYSCTL_HANDLER_ARGS)
5484 {
5485 struct bce_softc *sc;
5486 device_t dev;
5487 int error, result;
5488 uint16_t val;
5489
5490 result = -1;
5491 error = sysctl_handle_int(oidp, &result, 0, req);
5492 if (error || (req->newptr == NULL))
5493 return (error);
5494
5495 /* Make sure the register is accessible. */
5496 if (result < 0x20) {
5497 sc = (struct bce_softc *)arg1;
5498 dev = sc->bce_dev;
5499 val = bce_miibus_read_reg(dev, sc->bce_phy_addr, result);
5500 if_printf(&sc->arpcom.ac_if,
5501 "phy 0x%02X = 0x%04X\n", result, val);
5502 }
5503 return (error);
5504 }
5505
5506
5507 /****************************************************************************/
5508 /* Provides a sysctl interface to forcing the driver to dump state and */
5509 /* enter the debugger. DO NOT ENABLE ON PRODUCTION SYSTEMS! */
5510 /* */
5511 /* Returns: */
5512 /* 0 for success, positive value for failure. */
5513 /****************************************************************************/
5514 static int
5515 bce_sysctl_breakpoint(SYSCTL_HANDLER_ARGS)
5516 {
5517 int error;
5518 int result;
5519 struct bce_softc *sc;
5520
5521 result = -1;
5522 error = sysctl_handle_int(oidp, &result, 0, req);
5523
5524 if (error || !req->newptr)
5525 return (error);
5526
5527 if (result == 1) {
5528 sc = (struct bce_softc *)arg1;
5529 bce_breakpoint(sc);
5530 }
5531
5532 return error;
5533 }
5534 #endif
5535
5536
5537 /****************************************************************************/
5538 /* Adds any sysctl parameters for tuning or debugging purposes. */
5539 /* */
5540 /* Returns: */
5541 /* 0 for success, positive value for failure. */
5542 /****************************************************************************/
5543 static void
5544 bce_add_sysctls(struct bce_softc *sc)
5545 {
5546 struct sysctl_ctx_list *ctx;
5547 struct sysctl_oid_list *children;
5548
5549 sysctl_ctx_init(&sc->bce_sysctl_ctx);
5550 sc->bce_sysctl_tree = SYSCTL_ADD_NODE(&sc->bce_sysctl_ctx,
5551 SYSCTL_STATIC_CHILDREN(_hw),
5552 OID_AUTO,
5553 device_get_nameunit(sc->bce_dev),
5554 CTLFLAG_RD, 0, "");
5555 if (sc->bce_sysctl_tree == NULL) {
5556 device_printf(sc->bce_dev, "can't add sysctl node\n");
5557 return;
5558 }
5559
5560 ctx = &sc->bce_sysctl_ctx;
5561 children = SYSCTL_CHILDREN(sc->bce_sysctl_tree);
5562
5563 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_bds_int",
5564 CTLTYPE_INT | CTLFLAG_RW,
5565 sc, 0, bce_sysctl_tx_bds_int, "I",
5566 "Send max coalesced BD count during interrupt");
5567 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_bds",
5568 CTLTYPE_INT | CTLFLAG_RW,
5569 sc, 0, bce_sysctl_tx_bds, "I",
5570 "Send max coalesced BD count");
5571 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_ticks_int",
5572 CTLTYPE_INT | CTLFLAG_RW,
5573 sc, 0, bce_sysctl_tx_ticks_int, "I",
5574 "Send coalescing ticks during interrupt");
5575 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_ticks",
5576 CTLTYPE_INT | CTLFLAG_RW,
5577 sc, 0, bce_sysctl_tx_ticks, "I",
5578 "Send coalescing ticks");
5579
5580 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_bds_int",
5581 CTLTYPE_INT | CTLFLAG_RW,
5582 sc, 0, bce_sysctl_rx_bds_int, "I",
5583 "Receive max coalesced BD count during interrupt");
5584 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_bds",
5585 CTLTYPE_INT | CTLFLAG_RW,
5586 sc, 0, bce_sysctl_rx_bds, "I",
5587 "Receive max coalesced BD count");
5588 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_ticks_int",
5589 CTLTYPE_INT | CTLFLAG_RW,
5590 sc, 0, bce_sysctl_rx_ticks_int, "I",
5591 "Receive coalescing ticks during interrupt");
5592 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_ticks",
5593 CTLTYPE_INT | CTLFLAG_RW,
5594 sc, 0, bce_sysctl_rx_ticks, "I",
5595 "Receive coalescing ticks");
5596
5597 #ifdef BCE_DEBUG
5598 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
5599 "rx_low_watermark",
5600 CTLFLAG_RD, &sc->rx_low_watermark,
5601 0, "Lowest level of free rx_bd's");
5602
5603 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
5604 "rx_empty_count",
5605 CTLFLAG_RD, &sc->rx_empty_count,
5606 0, "Number of times the RX chain was empty");
5607
5608 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
5609 "tx_hi_watermark",
5610 CTLFLAG_RD, &sc->tx_hi_watermark,
5611 0, "Highest level of used tx_bd's");
5612
5613 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
5614 "tx_full_count",
5615 CTLFLAG_RD, &sc->tx_full_count,
5616 0, "Number of times the TX chain was full");
5617
5618 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
5619 "l2fhdr_status_errors",
5620 CTLFLAG_RD, &sc->l2fhdr_status_errors,
5621 0, "l2_fhdr status errors");
5622
5623 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
5624 "unexpected_attentions",
5625 CTLFLAG_RD, &sc->unexpected_attentions,
5626 0, "unexpected attentions");
5627
5628 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
5629 "lost_status_block_updates",
5630 CTLFLAG_RD, &sc->lost_status_block_updates,
5631 0, "lost status block updates");
5632
5633 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
5634 "mbuf_alloc_failed",
5635 CTLFLAG_RD, &sc->mbuf_alloc_failed,
5636 0, "mbuf cluster allocation failures");
5637 #endif
5638
5639 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
5640 "stat_IfHCInOctets",
5641 CTLFLAG_RD, &sc->stat_IfHCInOctets,
5642 "Bytes received");
5643
5644 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
5645 "stat_IfHCInBadOctets",
5646 CTLFLAG_RD, &sc->stat_IfHCInBadOctets,
5647 "Bad bytes received");
5648
5649 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
5650 "stat_IfHCOutOctets",
5651 CTLFLAG_RD, &sc->stat_IfHCOutOctets,
5652 "Bytes sent");
5653
5654 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
5655 "stat_IfHCOutBadOctets",
5656 CTLFLAG_RD, &sc->stat_IfHCOutBadOctets,
5657 "Bad bytes sent");
5658
5659 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
5660 "stat_IfHCInUcastPkts",
5661 CTLFLAG_RD, &sc->stat_IfHCInUcastPkts,
5662 "Unicast packets received");
5663
5664 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
5665 "stat_IfHCInMulticastPkts",
5666 CTLFLAG_RD, &sc->stat_IfHCInMulticastPkts,
5667 "Multicast packets received");
5668
5669 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
5670 "stat_IfHCInBroadcastPkts",
5671 CTLFLAG_RD, &sc->stat_IfHCInBroadcastPkts,
5672 "Broadcast packets received");
5673
5674 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
5675 "stat_IfHCOutUcastPkts",
5676 CTLFLAG_RD, &sc->stat_IfHCOutUcastPkts,
5677 "Unicast packets sent");
5678
5679 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
5680 "stat_IfHCOutMulticastPkts",
5681 CTLFLAG_RD, &sc->stat_IfHCOutMulticastPkts,
5682 "Multicast packets sent");
5683
5684 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
5685 "stat_IfHCOutBroadcastPkts",
5686 CTLFLAG_RD, &sc->stat_IfHCOutBroadcastPkts,
5687 "Broadcast packets sent");
5688
5689 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5690 "stat_emac_tx_stat_dot3statsinternalmactransmiterrors",
5691 CTLFLAG_RD, &sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors,
5692 0, "Internal MAC transmit errors");
5693
5694 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5695 "stat_Dot3StatsCarrierSenseErrors",
5696 CTLFLAG_RD, &sc->stat_Dot3StatsCarrierSenseErrors,
5697 0, "Carrier sense errors");
5698
5699 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5700 "stat_Dot3StatsFCSErrors",
5701 CTLFLAG_RD, &sc->stat_Dot3StatsFCSErrors,
5702 0, "Frame check sequence errors");
5703
5704 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5705 "stat_Dot3StatsAlignmentErrors",
5706 CTLFLAG_RD, &sc->stat_Dot3StatsAlignmentErrors,
5707 0, "Alignment errors");
5708
5709 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5710 "stat_Dot3StatsSingleCollisionFrames",
5711 CTLFLAG_RD, &sc->stat_Dot3StatsSingleCollisionFrames,
5712 0, "Single Collision Frames");
5713
5714 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5715 "stat_Dot3StatsMultipleCollisionFrames",
5716 CTLFLAG_RD, &sc->stat_Dot3StatsMultipleCollisionFrames,
5717 0, "Multiple Collision Frames");
5718
5719 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5720 "stat_Dot3StatsDeferredTransmissions",
5721 CTLFLAG_RD, &sc->stat_Dot3StatsDeferredTransmissions,
5722 0, "Deferred Transmissions");
5723
5724 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5725 "stat_Dot3StatsExcessiveCollisions",
5726 CTLFLAG_RD, &sc->stat_Dot3StatsExcessiveCollisions,
5727 0, "Excessive Collisions");
5728
5729 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5730 "stat_Dot3StatsLateCollisions",
5731 CTLFLAG_RD, &sc->stat_Dot3StatsLateCollisions,
5732 0, "Late Collisions");
5733
5734 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5735 "stat_EtherStatsCollisions",
5736 CTLFLAG_RD, &sc->stat_EtherStatsCollisions,
5737 0, "Collisions");
5738
5739 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5740 "stat_EtherStatsFragments",
5741 CTLFLAG_RD, &sc->stat_EtherStatsFragments,
5742 0, "Fragments");
5743
5744 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5745 "stat_EtherStatsJabbers",
5746 CTLFLAG_RD, &sc->stat_EtherStatsJabbers,
5747 0, "Jabbers");
5748
5749 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5750 "stat_EtherStatsUndersizePkts",
5751 CTLFLAG_RD, &sc->stat_EtherStatsUndersizePkts,
5752 0, "Undersize packets");
5753
5754 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5755 "stat_EtherStatsOverrsizePkts",
5756 CTLFLAG_RD, &sc->stat_EtherStatsOverrsizePkts,
5757 0, "stat_EtherStatsOverrsizePkts");
5758
5759 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5760 "stat_EtherStatsPktsRx64Octets",
5761 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx64Octets,
5762 0, "Bytes received in 64 byte packets");
5763
5764 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5765 "stat_EtherStatsPktsRx65Octetsto127Octets",
5766 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx65Octetsto127Octets,
5767 0, "Bytes received in 65 to 127 byte packets");
5768
5769 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5770 "stat_EtherStatsPktsRx128Octetsto255Octets",
5771 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx128Octetsto255Octets,
5772 0, "Bytes received in 128 to 255 byte packets");
5773
5774 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5775 "stat_EtherStatsPktsRx256Octetsto511Octets",
5776 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx256Octetsto511Octets,
5777 0, "Bytes received in 256 to 511 byte packets");
5778
5779 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5780 "stat_EtherStatsPktsRx512Octetsto1023Octets",
5781 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx512Octetsto1023Octets,
5782 0, "Bytes received in 512 to 1023 byte packets");
5783
5784 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5785 "stat_EtherStatsPktsRx1024Octetsto1522Octets",
5786 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1024Octetsto1522Octets,
5787 0, "Bytes received in 1024 t0 1522 byte packets");
5788
5789 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5790 "stat_EtherStatsPktsRx1523Octetsto9022Octets",
5791 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1523Octetsto9022Octets,
5792 0, "Bytes received in 1523 to 9022 byte packets");
5793
5794 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5795 "stat_EtherStatsPktsTx64Octets",
5796 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx64Octets,
5797 0, "Bytes sent in 64 byte packets");
5798
5799 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5800 "stat_EtherStatsPktsTx65Octetsto127Octets",
5801 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx65Octetsto127Octets,
5802 0, "Bytes sent in 65 to 127 byte packets");
5803
5804 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5805 "stat_EtherStatsPktsTx128Octetsto255Octets",
5806 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx128Octetsto255Octets,
5807 0, "Bytes sent in 128 to 255 byte packets");
5808
5809 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5810 "stat_EtherStatsPktsTx256Octetsto511Octets",
5811 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx256Octetsto511Octets,
5812 0, "Bytes sent in 256 to 511 byte packets");
5813
5814 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5815 "stat_EtherStatsPktsTx512Octetsto1023Octets",
5816 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx512Octetsto1023Octets,
5817 0, "Bytes sent in 512 to 1023 byte packets");
5818
5819 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5820 "stat_EtherStatsPktsTx1024Octetsto1522Octets",
5821 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1024Octetsto1522Octets,
5822 0, "Bytes sent in 1024 to 1522 byte packets");
5823
5824 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5825 "stat_EtherStatsPktsTx1523Octetsto9022Octets",
5826 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1523Octetsto9022Octets,
5827 0, "Bytes sent in 1523 to 9022 byte packets");
5828
5829 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5830 "stat_XonPauseFramesReceived",
5831 CTLFLAG_RD, &sc->stat_XonPauseFramesReceived,
5832 0, "XON pause frames receved");
5833
5834 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5835 "stat_XoffPauseFramesReceived",
5836 CTLFLAG_RD, &sc->stat_XoffPauseFramesReceived,
5837 0, "XOFF pause frames received");
5838
5839 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5840 "stat_OutXonSent",
5841 CTLFLAG_RD, &sc->stat_OutXonSent,
5842 0, "XON pause frames sent");
5843
5844 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5845 "stat_OutXoffSent",
5846 CTLFLAG_RD, &sc->stat_OutXoffSent,
5847 0, "XOFF pause frames sent");
5848
5849 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5850 "stat_FlowControlDone",
5851 CTLFLAG_RD, &sc->stat_FlowControlDone,
5852 0, "Flow control done");
5853
5854 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5855 "stat_MacControlFramesReceived",
5856 CTLFLAG_RD, &sc->stat_MacControlFramesReceived,
5857 0, "MAC control frames received");
5858
5859 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5860 "stat_XoffStateEntered",
5861 CTLFLAG_RD, &sc->stat_XoffStateEntered,
5862 0, "XOFF state entered");
5863
5864 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5865 "stat_IfInFramesL2FilterDiscards",
5866 CTLFLAG_RD, &sc->stat_IfInFramesL2FilterDiscards,
5867 0, "Received L2 packets discarded");
5868
5869 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5870 "stat_IfInRuleCheckerDiscards",
5871 CTLFLAG_RD, &sc->stat_IfInRuleCheckerDiscards,
5872 0, "Received packets discarded by rule");
5873
5874 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5875 "stat_IfInFTQDiscards",
5876 CTLFLAG_RD, &sc->stat_IfInFTQDiscards,
5877 0, "Received packet FTQ discards");
5878
5879 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5880 "stat_IfInMBUFDiscards",
5881 CTLFLAG_RD, &sc->stat_IfInMBUFDiscards,
5882 0, "Received packets discarded due to lack of controller buffer memory");
5883
5884 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5885 "stat_IfInRuleCheckerP4Hit",
5886 CTLFLAG_RD, &sc->stat_IfInRuleCheckerP4Hit,
5887 0, "Received packets rule checker hits");
5888
5889 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5890 "stat_CatchupInRuleCheckerDiscards",
5891 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerDiscards,
5892 0, "Received packets discarded in Catchup path");
5893
5894 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5895 "stat_CatchupInFTQDiscards",
5896 CTLFLAG_RD, &sc->stat_CatchupInFTQDiscards,
5897 0, "Received packets discarded in FTQ in Catchup path");
5898
5899 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5900 "stat_CatchupInMBUFDiscards",
5901 CTLFLAG_RD, &sc->stat_CatchupInMBUFDiscards,
5902 0, "Received packets discarded in controller buffer memory in Catchup path");
5903
5904 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5905 "stat_CatchupInRuleCheckerP4Hit",
5906 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerP4Hit,
5907 0, "Received packets rule checker hits in Catchup path");
5908
5909 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5910 "com_no_buffers",
5911 CTLFLAG_RD, &sc->com_no_buffers,
5912 0, "Valid packets received but no RX buffers available");
5913
5914 #ifdef BCE_DEBUG
5915 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
5916 "driver_state", CTLTYPE_INT | CTLFLAG_RW,
5917 (void *)sc, 0,
5918 bce_sysctl_driver_state, "I", "Drive state information");
5919
5920 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
5921 "hw_state", CTLTYPE_INT | CTLFLAG_RW,
5922 (void *)sc, 0,
5923 bce_sysctl_hw_state, "I", "Hardware state information");
5924
5925 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
5926 "dump_rx_chain", CTLTYPE_INT | CTLFLAG_RW,
5927 (void *)sc, 0,
5928 bce_sysctl_dump_rx_chain, "I", "Dump rx_bd chain");
5929
5930 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
5931 "dump_tx_chain", CTLTYPE_INT | CTLFLAG_RW,
5932 (void *)sc, 0,
5933 bce_sysctl_dump_tx_chain, "I", "Dump tx_bd chain");
5934
5935 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
5936 "breakpoint", CTLTYPE_INT | CTLFLAG_RW,
5937 (void *)sc, 0,
5938 bce_sysctl_breakpoint, "I", "Driver breakpoint");
5939
5940 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
5941 "reg_read", CTLTYPE_INT | CTLFLAG_RW,
5942 (void *)sc, 0,
5943 bce_sysctl_reg_read, "I", "Register read");
5944
5945 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
5946 "phy_read", CTLTYPE_INT | CTLFLAG_RW,
5947 (void *)sc, 0,
5948 bce_sysctl_phy_read, "I", "PHY register read");
5949
5950 #endif
5951
5952 }
5953
5954
5955 /****************************************************************************/
5956 /* BCE Debug Routines */
5957 /****************************************************************************/
5958 #ifdef BCE_DEBUG
5959
5960 /****************************************************************************/
5961 /* Freezes the controller to allow for a cohesive state dump. */
5962 /* */
5963 /* Returns: */
5964 /* Nothing. */
5965 /****************************************************************************/
5966 static void
5967 bce_freeze_controller(struct bce_softc *sc)
5968 {
5969 uint32_t val;
5970
5971 val = REG_RD(sc, BCE_MISC_COMMAND);
5972 val |= BCE_MISC_COMMAND_DISABLE_ALL;
5973 REG_WR(sc, BCE_MISC_COMMAND, val);
5974 }
5975
5976
5977 /****************************************************************************/
5978 /* Unfreezes the controller after a freeze operation. This may not always */
5979 /* work and the controller will require a reset! */
5980 /* */
5981 /* Returns: */
5982 /* Nothing. */
5983 /****************************************************************************/
5984 static void
5985 bce_unfreeze_controller(struct bce_softc *sc)
5986 {
5987 uint32_t val;
5988
5989 val = REG_RD(sc, BCE_MISC_COMMAND);
5990 val |= BCE_MISC_COMMAND_ENABLE_ALL;
5991 REG_WR(sc, BCE_MISC_COMMAND, val);
5992 }
5993
5994
5995 /****************************************************************************/
5996 /* Prints out information about an mbuf. */
5997 /* */
5998 /* Returns: */
5999 /* Nothing. */
6000 /****************************************************************************/
6001 static void
6002 bce_dump_mbuf(struct bce_softc *sc, struct mbuf *m)
6003 {
6004 struct ifnet *ifp = &sc->arpcom.ac_if;
6005 uint32_t val_hi, val_lo;
6006 struct mbuf *mp = m;
6007
6008 if (m == NULL) {
6009 /* Index out of range. */
6010 if_printf(ifp, "mbuf: null pointer\n");
6011 return;
6012 }
6013
6014 while (mp) {
6015 val_hi = BCE_ADDR_HI(mp);
6016 val_lo = BCE_ADDR_LO(mp);
6017 if_printf(ifp, "mbuf: vaddr = 0x%08X:%08X, m_len = %d, "
6018 "m_flags = ( ", val_hi, val_lo, mp->m_len);
6019
6020 if (mp->m_flags & M_EXT)
6021 kprintf("M_EXT ");
6022 if (mp->m_flags & M_PKTHDR)
6023 kprintf("M_PKTHDR ");
6024 if (mp->m_flags & M_EOR)
6025 kprintf("M_EOR ");
6026 #ifdef M_RDONLY
6027 if (mp->m_flags & M_RDONLY)
6028 kprintf("M_RDONLY ");
6029 #endif
6030
6031 val_hi = BCE_ADDR_HI(mp->m_data);
6032 val_lo = BCE_ADDR_LO(mp->m_data);
6033 kprintf(") m_data = 0x%08X:%08X\n", val_hi, val_lo);
6034
6035 if (mp->m_flags & M_PKTHDR) {
6036 if_printf(ifp, "- m_pkthdr: flags = ( ");
6037 if (mp->m_flags & M_BCAST)
6038 kprintf("M_BCAST ");
6039 if (mp->m_flags & M_MCAST)
6040 kprintf("M_MCAST ");
6041 if (mp->m_flags & M_FRAG)
6042 kprintf("M_FRAG ");
6043 if (mp->m_flags & M_FIRSTFRAG)
6044 kprintf("M_FIRSTFRAG ");
6045 if (mp->m_flags & M_LASTFRAG)
6046 kprintf("M_LASTFRAG ");
6047 #ifdef M_VLANTAG
6048 if (mp->m_flags & M_VLANTAG)
6049 kprintf("M_VLANTAG ");
6050 #endif
6051 #ifdef M_PROMISC
6052 if (mp->m_flags & M_PROMISC)
6053 kprintf("M_PROMISC ");
6054 #endif
6055 kprintf(") csum_flags = ( ");
6056 if (mp->m_pkthdr.csum_flags & CSUM_IP)
6057 kprintf("CSUM_IP ");
6058 if (mp->m_pkthdr.csum_flags & CSUM_TCP)
6059 kprintf("CSUM_TCP ");
6060 if (mp->m_pkthdr.csum_flags & CSUM_UDP)
6061 kprintf("CSUM_UDP ");
6062 if (mp->m_pkthdr.csum_flags & CSUM_IP_FRAGS)
6063 kprintf("CSUM_IP_FRAGS ");
6064 if (mp->m_pkthdr.csum_flags & CSUM_FRAGMENT)
6065 kprintf("CSUM_FRAGMENT ");
6066 #ifdef CSUM_TSO
6067 if (mp->m_pkthdr.csum_flags & CSUM_TSO)
6068 kprintf("CSUM_TSO ");
6069 #endif
6070 if (mp->m_pkthdr.csum_flags & CSUM_IP_CHECKED)
6071 kprintf("CSUM_IP_CHECKED ");
6072 if (mp->m_pkthdr.csum_flags & CSUM_IP_VALID)
6073 kprintf("CSUM_IP_VALID ");
6074 if (mp->m_pkthdr.csum_flags & CSUM_DATA_VALID)
6075 kprintf("CSUM_DATA_VALID ");
6076 kprintf(")\n");
6077 }
6078
6079 if (mp->m_flags & M_EXT) {
6080 val_hi = BCE_ADDR_HI(mp->m_ext.ext_buf);
6081 val_lo = BCE_ADDR_LO(mp->m_ext.ext_buf);
6082 if_printf(ifp, "- m_ext: vaddr = 0x%08X:%08X, "
6083 "ext_size = %d\n",
6084 val_hi, val_lo, mp->m_ext.ext_size);
6085 }
6086 mp = mp->m_next;
6087 }
6088 }
6089
6090
6091 /****************************************************************************/
6092 /* Prints out the mbufs in the TX mbuf chain. */
6093 /* */
6094 /* Returns: */
6095 /* Nothing. */
6096 /****************************************************************************/
6097 static void
6098 bce_dump_tx_mbuf_chain(struct bce_softc *sc, int chain_prod, int count)
6099 {
6100 struct ifnet *ifp = &sc->arpcom.ac_if;
6101 int i;
6102
6103 if_printf(ifp,
6104 "----------------------------"
6105 " tx mbuf data "
6106 "----------------------------\n");
6107
6108 for (i = 0; i < count; i++) {
6109 if_printf(ifp, "txmbuf[%d]\n", chain_prod);
6110 bce_dump_mbuf(sc, sc->tx_mbuf_ptr[chain_prod]);
6111 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod));
6112 }
6113
6114 if_printf(ifp,
6115 "----------------------------"
6116 "----------------"
6117 "----------------------------\n");
6118 }
6119
6120
6121 /****************************************************************************/
6122 /* Prints out the mbufs in the RX mbuf chain. */
6123 /* */
6124 /* Returns: */
6125 /* Nothing. */
6126 /****************************************************************************/
6127 static void
6128 bce_dump_rx_mbuf_chain(struct bce_softc *sc, int chain_prod, int count)
6129 {
6130 struct ifnet *ifp = &sc->arpcom.ac_if;
6131 int i;
6132
6133 if_printf(ifp,
6134 "----------------------------"
6135 " rx mbuf data "
6136 "----------------------------\n");
6137
6138 for (i = 0; i < count; i++) {
6139 if_printf(ifp, "rxmbuf[0x%04X]\n", chain_prod);
6140 bce_dump_mbuf(sc, sc->rx_mbuf_ptr[chain_prod]);
6141 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod));
6142 }
6143
6144 if_printf(ifp,
6145 "----------------------------"
6146 "----------------"
6147 "----------------------------\n");
6148 }
6149
6150
6151 /****************************************************************************/
6152 /* Prints out a tx_bd structure. */
6153 /* */
6154 /* Returns: */
6155 /* Nothing. */
6156 /****************************************************************************/
6157 static void
6158 bce_dump_txbd(struct bce_softc *sc, int idx, struct tx_bd *txbd)
6159 {
6160 struct ifnet *ifp = &sc->arpcom.ac_if;
6161
6162 if (idx > MAX_TX_BD) {
6163 /* Index out of range. */
6164 if_printf(ifp, "tx_bd[0x%04X]: Invalid tx_bd index!\n", idx);
6165 } else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) {
6166 /* TX Chain page pointer. */
6167 if_printf(ifp, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6168 "chain page pointer\n",
6169 idx, txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo);
6170 } else {
6171 /* Normal tx_bd entry. */
6172 if_printf(ifp, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6173 "nbytes = 0x%08X, "
6174 "vlan tag= 0x%04X, flags = 0x%04X (",
6175 idx, txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo,
6176 txbd->tx_bd_mss_nbytes,
6177 txbd->tx_bd_vlan_tag, txbd->tx_bd_flags);
6178
6179 if (txbd->tx_bd_flags & TX_BD_FLAGS_CONN_FAULT)
6180 kprintf(" CONN_FAULT");
6181
6182 if (txbd->tx_bd_flags & TX_BD_FLAGS_TCP_UDP_CKSUM)
6183 kprintf(" TCP_UDP_CKSUM");
6184
6185 if (txbd->tx_bd_flags & TX_BD_FLAGS_IP_CKSUM)
6186 kprintf(" IP_CKSUM");
6187
6188 if (txbd->tx_bd_flags & TX_BD_FLAGS_VLAN_TAG)
6189 kprintf(" VLAN");
6190
6191 if (txbd->tx_bd_flags & TX_BD_FLAGS_COAL_NOW)
6192 kprintf(" COAL_NOW");
6193
6194 if (txbd->tx_bd_flags & TX_BD_FLAGS_DONT_GEN_CRC)
6195 kprintf(" DONT_GEN_CRC");
6196
6197 if (txbd->tx_bd_flags & TX_BD_FLAGS_START)
6198 kprintf(" START");
6199
6200 if (txbd->tx_bd_flags & TX_BD_FLAGS_END)
6201 kprintf(" END");
6202
6203 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_LSO)
6204 kprintf(" LSO");
6205
6206 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_OPTION_WORD)
6207 kprintf(" OPTION_WORD");
6208
6209 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_FLAGS)
6210 kprintf(" FLAGS");
6211
6212 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_SNAP)
6213 kprintf(" SNAP");
6214
6215 kprintf(" )\n");
6216 }
6217 }
6218
6219
6220 /****************************************************************************/
6221 /* Prints out a rx_bd structure. */
6222 /* */
6223 /* Returns: */
6224 /* Nothing. */
6225 /****************************************************************************/
6226 static void
6227 bce_dump_rxbd(struct bce_softc *sc, int idx, struct rx_bd *rxbd)
6228 {
6229 struct ifnet *ifp = &sc->arpcom.ac_if;
6230
6231 if (idx > MAX_RX_BD) {
6232 /* Index out of range. */
6233 if_printf(ifp, "rx_bd[0x%04X]: Invalid rx_bd index!\n", idx);
6234 } else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) {
6235 /* TX Chain page pointer. */
6236 if_printf(ifp, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6237 "chain page pointer\n",
6238 idx, rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo);
6239 } else {
6240 /* Normal tx_bd entry. */
6241 if_printf(ifp, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6242 "nbytes = 0x%08X, flags = 0x%08X\n",
6243 idx, rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo,
6244 rxbd->rx_bd_len, rxbd->rx_bd_flags);
6245 }
6246 }
6247
6248
6249 /****************************************************************************/
6250 /* Prints out a l2_fhdr structure. */
6251 /* */
6252 /* Returns: */
6253 /* Nothing. */
6254 /****************************************************************************/
6255 static void
6256 bce_dump_l2fhdr(struct bce_softc *sc, int idx, struct l2_fhdr *l2fhdr)
6257 {
6258 if_printf(&sc->arpcom.ac_if, "l2_fhdr[0x%04X]: status = 0x%08X, "
6259 "pkt_len = 0x%04X, vlan = 0x%04x, "
6260 "ip_xsum = 0x%04X, tcp_udp_xsum = 0x%04X\n",
6261 idx, l2fhdr->l2_fhdr_status,
6262 l2fhdr->l2_fhdr_pkt_len, l2fhdr->l2_fhdr_vlan_tag,
6263 l2fhdr->l2_fhdr_ip_xsum, l2fhdr->l2_fhdr_tcp_udp_xsum);
6264 }
6265
6266
6267 /****************************************************************************/
6268 /* Prints out the tx chain. */
6269 /* */
6270 /* Returns: */
6271 /* Nothing. */
6272 /****************************************************************************/
6273 static void
6274 bce_dump_tx_chain(struct bce_softc *sc, int tx_prod, int count)
6275 {
6276 struct ifnet *ifp = &sc->arpcom.ac_if;
6277 int i;
6278
6279 /* First some info about the tx_bd chain structure. */
6280 if_printf(ifp,
6281 "----------------------------"
6282 " tx_bd chain "
6283 "----------------------------\n");
6284
6285 if_printf(ifp, "page size = 0x%08X, "
6286 "tx chain pages = 0x%08X\n",
6287 (uint32_t)BCM_PAGE_SIZE, (uint32_t)TX_PAGES);
6288
6289 if_printf(ifp, "tx_bd per page = 0x%08X, "
6290 "usable tx_bd per page = 0x%08X\n",
6291 (uint32_t)TOTAL_TX_BD_PER_PAGE,
6292 (uint32_t)USABLE_TX_BD_PER_PAGE);
6293
6294 if_printf(ifp, "total tx_bd = 0x%08X\n", (uint32_t)TOTAL_TX_BD);
6295
6296 if_printf(ifp,
6297 "----------------------------"
6298 " tx_bd data "
6299 "----------------------------\n");
6300
6301 /* Now print out the tx_bd's themselves. */
6302 for (i = 0; i < count; i++) {
6303 struct tx_bd *txbd;
6304
6305 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)];
6306 bce_dump_txbd(sc, tx_prod, txbd);
6307 tx_prod = TX_CHAIN_IDX(NEXT_TX_BD(tx_prod));
6308 }
6309
6310 if_printf(ifp,
6311 "----------------------------"
6312 "----------------"
6313 "----------------------------\n");
6314 }
6315
6316
6317 /****************************************************************************/
6318 /* Prints out the rx chain. */
6319 /* */
6320 /* Returns: */
6321 /* Nothing. */
6322 /****************************************************************************/
6323 static void
6324 bce_dump_rx_chain(struct bce_softc *sc, int rx_prod, int count)
6325 {
6326 struct ifnet *ifp = &sc->arpcom.ac_if;
6327 int i;
6328
6329 /* First some info about the tx_bd chain structure. */
6330 if_printf(ifp,
6331 "----------------------------"
6332 " rx_bd chain "
6333 "----------------------------\n");
6334
6335 if_printf(ifp, "page size = 0x%08X, "
6336 "rx chain pages = 0x%08X\n",
6337 (uint32_t)BCM_PAGE_SIZE, (uint32_t)RX_PAGES);
6338
6339 if_printf(ifp, "rx_bd per page = 0x%08X, "
6340 "usable rx_bd per page = 0x%08X\n",
6341 (uint32_t)TOTAL_RX_BD_PER_PAGE,
6342 (uint32_t)USABLE_RX_BD_PER_PAGE);
6343
6344 if_printf(ifp, "total rx_bd = 0x%08X\n", (uint32_t)TOTAL_RX_BD);
6345
6346 if_printf(ifp,
6347 "----------------------------"
6348 " rx_bd data "
6349 "----------------------------\n");
6350
6351 /* Now print out the rx_bd's themselves. */
6352 for (i = 0; i < count; i++) {
6353 struct rx_bd *rxbd;
6354
6355 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)];
6356 bce_dump_rxbd(sc, rx_prod, rxbd);
6357 rx_prod = RX_CHAIN_IDX(NEXT_RX_BD(rx_prod));
6358 }
6359
6360 if_printf(ifp,
6361 "----------------------------"
6362 "----------------"
6363 "----------------------------\n");
6364 }
6365
6366
6367 /****************************************************************************/
6368 /* Prints out the status block from host memory. */
6369 /* */
6370 /* Returns: */
6371 /* Nothing. */
6372 /****************************************************************************/
6373 static void
6374 bce_dump_status_block(struct bce_softc *sc)
6375 {
6376 struct status_block *sblk = sc->status_block;
6377 struct ifnet *ifp = &sc->arpcom.ac_if;
6378
6379 if_printf(ifp,
6380 "----------------------------"
6381 " Status Block "
6382 "----------------------------\n");
6383
6384 if_printf(ifp, " 0x%08X - attn_bits\n", sblk->status_attn_bits);
6385
6386 if_printf(ifp, " 0x%08X - attn_bits_ack\n",
6387 sblk->status_attn_bits_ack);
6388
6389 if_printf(ifp, "0x%04X(0x%04X) - rx_cons0\n",
6390 sblk->status_rx_quick_consumer_index0,
6391 (uint16_t)RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index0));
6392
6393 if_printf(ifp, "0x%04X(0x%04X) - tx_cons0\n",
6394 sblk->status_tx_quick_consumer_index0,
6395 (uint16_t)TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index0));
6396
6397 if_printf(ifp, " 0x%04X - status_idx\n", sblk->status_idx);
6398
6399 /* Theses indices are not used for normal L2 drivers. */
6400 if (sblk->status_rx_quick_consumer_index1) {
6401 if_printf(ifp, "0x%04X(0x%04X) - rx_cons1\n",
6402 sblk->status_rx_quick_consumer_index1,
6403 (uint16_t)RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index1));
6404 }
6405
6406 if (sblk->status_tx_quick_consumer_index1) {
6407 if_printf(ifp, "0x%04X(0x%04X) - tx_cons1\n",
6408 sblk->status_tx_quick_consumer_index1,
6409 (uint16_t)TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index1));
6410 }
6411
6412 if (sblk->status_rx_quick_consumer_index2) {
6413 if_printf(ifp, "0x%04X(0x%04X)- rx_cons2\n",
6414 sblk->status_rx_quick_consumer_index2,
6415 (uint16_t)RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index2));
6416 }
6417
6418 if (sblk->status_tx_quick_consumer_index2) {
6419 if_printf(ifp, "0x%04X(0x%04X) - tx_cons2\n",
6420 sblk->status_tx_quick_consumer_index2,
6421 (uint16_t)TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index2));
6422 }
6423
6424 if (sblk->status_rx_quick_consumer_index3) {
6425 if_printf(ifp, "0x%04X(0x%04X) - rx_cons3\n",
6426 sblk->status_rx_quick_consumer_index3,
6427 (uint16_t)RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index3));
6428 }
6429
6430 if (sblk->status_tx_quick_consumer_index3) {
6431 if_printf(ifp, "0x%04X(0x%04X) - tx_cons3\n",
6432 sblk->status_tx_quick_consumer_index3,
6433 (uint16_t)TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index3));
6434 }
6435
6436 if (sblk->status_rx_quick_consumer_index4 ||
6437 sblk->status_rx_quick_consumer_index5) {
6438 if_printf(ifp, "rx_cons4 = 0x%08X, rx_cons5 = 0x%08X\n",
6439 sblk->status_rx_quick_consumer_index4,
6440 sblk->status_rx_quick_consumer_index5);
6441 }
6442
6443 if (sblk->status_rx_quick_consumer_index6 ||
6444 sblk->status_rx_quick_consumer_index7) {
6445 if_printf(ifp, "rx_cons6 = 0x%08X, rx_cons7 = 0x%08X\n",
6446 sblk->status_rx_quick_consumer_index6,
6447 sblk->status_rx_quick_consumer_index7);
6448 }
6449
6450 if (sblk->status_rx_quick_consumer_index8 ||
6451 sblk->status_rx_quick_consumer_index9) {
6452 if_printf(ifp, "rx_cons8 = 0x%08X, rx_cons9 = 0x%08X\n",
6453 sblk->status_rx_quick_consumer_index8,
6454 sblk->status_rx_quick_consumer_index9);
6455 }
6456
6457 if (sblk->status_rx_quick_consumer_index10 ||
6458 sblk->status_rx_quick_consumer_index11) {
6459 if_printf(ifp, "rx_cons10 = 0x%08X, rx_cons11 = 0x%08X\n",
6460 sblk->status_rx_quick_consumer_index10,
6461 sblk->status_rx_quick_consumer_index11);
6462 }
6463
6464 if (sblk->status_rx_quick_consumer_index12 ||
6465 sblk->status_rx_quick_consumer_index13) {
6466 if_printf(ifp, "rx_cons12 = 0x%08X, rx_cons13 = 0x%08X\n",
6467 sblk->status_rx_quick_consumer_index12,
6468 sblk->status_rx_quick_consumer_index13);
6469 }
6470
6471 if (sblk->status_rx_quick_consumer_index14 ||
6472 sblk->status_rx_quick_consumer_index15) {
6473 if_printf(ifp, "rx_cons14 = 0x%08X, rx_cons15 = 0x%08X\n",
6474 sblk->status_rx_quick_consumer_index14,
6475 sblk->status_rx_quick_consumer_index15);
6476 }
6477
6478 if (sblk->status_completion_producer_index ||
6479 sblk->status_cmd_consumer_index) {
6480 if_printf(ifp, "com_prod = 0x%08X, cmd_cons = 0x%08X\n",
6481 sblk->status_completion_producer_index,
6482 sblk->status_cmd_consumer_index);
6483 }
6484
6485 if_printf(ifp,
6486 "----------------------------"
6487 "----------------"
6488 "----------------------------\n");
6489 }
6490
6491
6492 /****************************************************************************/
6493 /* Prints out the statistics block. */
6494 /* */
6495 /* Returns: */
6496 /* Nothing. */
6497 /****************************************************************************/
6498 static void
6499 bce_dump_stats_block(struct bce_softc *sc)
6500 {
6501 struct statistics_block *sblk = sc->stats_block;
6502 struct ifnet *ifp = &sc->arpcom.ac_if;
6503
6504 if_printf(ifp,
6505 "---------------"
6506 " Stats Block (All Stats Not Shown Are 0) "
6507 "---------------\n");
6508
6509 if (sblk->stat_IfHCInOctets_hi || sblk->stat_IfHCInOctets_lo) {
6510 if_printf(ifp, "0x%08X:%08X : IfHcInOctets\n",
6511 sblk->stat_IfHCInOctets_hi,
6512 sblk->stat_IfHCInOctets_lo);
6513 }
6514
6515 if (sblk->stat_IfHCInBadOctets_hi || sblk->stat_IfHCInBadOctets_lo) {
6516 if_printf(ifp, "0x%08X:%08X : IfHcInBadOctets\n",
6517 sblk->stat_IfHCInBadOctets_hi,
6518 sblk->stat_IfHCInBadOctets_lo);
6519 }
6520
6521 if (sblk->stat_IfHCOutOctets_hi || sblk->stat_IfHCOutOctets_lo) {
6522 if_printf(ifp, "0x%08X:%08X : IfHcOutOctets\n",
6523 sblk->stat_IfHCOutOctets_hi,
6524 sblk->stat_IfHCOutOctets_lo);
6525 }
6526
6527 if (sblk->stat_IfHCOutBadOctets_hi || sblk->stat_IfHCOutBadOctets_lo) {
6528 if_printf(ifp, "0x%08X:%08X : IfHcOutBadOctets\n",
6529 sblk->stat_IfHCOutBadOctets_hi,
6530 sblk->stat_IfHCOutBadOctets_lo);
6531 }
6532
6533 if (sblk->stat_IfHCInUcastPkts_hi || sblk->stat_IfHCInUcastPkts_lo) {
6534 if_printf(ifp, "0x%08X:%08X : IfHcInUcastPkts\n",
6535 sblk->stat_IfHCInUcastPkts_hi,
6536 sblk->stat_IfHCInUcastPkts_lo);
6537 }
6538
6539 if (sblk->stat_IfHCInBroadcastPkts_hi ||
6540 sblk->stat_IfHCInBroadcastPkts_lo) {
6541 if_printf(ifp, "0x%08X:%08X : IfHcInBroadcastPkts\n",
6542 sblk->stat_IfHCInBroadcastPkts_hi,
6543 sblk->stat_IfHCInBroadcastPkts_lo);
6544 }
6545
6546 if (sblk->stat_IfHCInMulticastPkts_hi ||
6547 sblk->stat_IfHCInMulticastPkts_lo) {
6548 if_printf(ifp, "0x%08X:%08X : IfHcInMulticastPkts\n",
6549 sblk->stat_IfHCInMulticastPkts_hi,
6550 sblk->stat_IfHCInMulticastPkts_lo);
6551 }
6552
6553 if (sblk->stat_IfHCOutUcastPkts_hi || sblk->stat_IfHCOutUcastPkts_lo) {
6554 if_printf(ifp, "0x%08X:%08X : IfHcOutUcastPkts\n",
6555 sblk->stat_IfHCOutUcastPkts_hi,
6556 sblk->stat_IfHCOutUcastPkts_lo);
6557 }
6558
6559 if (sblk->stat_IfHCOutBroadcastPkts_hi ||
6560 sblk->stat_IfHCOutBroadcastPkts_lo) {
6561 if_printf(ifp, "0x%08X:%08X : IfHcOutBroadcastPkts\n",
6562 sblk->stat_IfHCOutBroadcastPkts_hi,
6563 sblk->stat_IfHCOutBroadcastPkts_lo);
6564 }
6565
6566 if (sblk->stat_IfHCOutMulticastPkts_hi ||
6567 sblk->stat_IfHCOutMulticastPkts_lo) {
6568 if_printf(ifp, "0x%08X:%08X : IfHcOutMulticastPkts\n",
6569 sblk->stat_IfHCOutMulticastPkts_hi,
6570 sblk->stat_IfHCOutMulticastPkts_lo);
6571 }
6572
6573 if (sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors) {
6574 if_printf(ifp, " 0x%08X : "
6575 "emac_tx_stat_dot3statsinternalmactransmiterrors\n",
6576 sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors);
6577 }
6578
6579 if (sblk->stat_Dot3StatsCarrierSenseErrors) {
6580 if_printf(ifp, " 0x%08X : "
6581 "Dot3StatsCarrierSenseErrors\n",
6582 sblk->stat_Dot3StatsCarrierSenseErrors);
6583 }
6584
6585 if (sblk->stat_Dot3StatsFCSErrors) {
6586 if_printf(ifp, " 0x%08X : Dot3StatsFCSErrors\n",
6587 sblk->stat_Dot3StatsFCSErrors);
6588 }
6589
6590 if (sblk->stat_Dot3StatsAlignmentErrors) {
6591 if_printf(ifp, " 0x%08X : Dot3StatsAlignmentErrors\n",
6592 sblk->stat_Dot3StatsAlignmentErrors);
6593 }
6594
6595 if (sblk->stat_Dot3StatsSingleCollisionFrames) {
6596 if_printf(ifp, " 0x%08X : "
6597 "Dot3StatsSingleCollisionFrames\n",
6598 sblk->stat_Dot3StatsSingleCollisionFrames);
6599 }
6600
6601 if (sblk->stat_Dot3StatsMultipleCollisionFrames) {
6602 if_printf(ifp, " 0x%08X : "
6603 "Dot3StatsMultipleCollisionFrames\n",
6604 sblk->stat_Dot3StatsMultipleCollisionFrames);
6605 }
6606
6607 if (sblk->stat_Dot3StatsDeferredTransmissions) {
6608 if_printf(ifp, " 0x%08X : "
6609 "Dot3StatsDeferredTransmissions\n",
6610 sblk->stat_Dot3StatsDeferredTransmissions);
6611 }
6612
6613 if (sblk->stat_Dot3StatsExcessiveCollisions) {
6614 if_printf(ifp, " 0x%08X : "
6615 "Dot3StatsExcessiveCollisions\n",
6616 sblk->stat_Dot3StatsExcessiveCollisions);
6617 }
6618
6619 if (sblk->stat_Dot3StatsLateCollisions) {
6620 if_printf(ifp, " 0x%08X : Dot3StatsLateCollisions\n",
6621 sblk->stat_Dot3StatsLateCollisions);
6622 }
6623
6624 if (sblk->stat_EtherStatsCollisions) {
6625 if_printf(ifp, " 0x%08X : EtherStatsCollisions\n",
6626 sblk->stat_EtherStatsCollisions);
6627 }
6628
6629 if (sblk->stat_EtherStatsFragments) {
6630 if_printf(ifp, " 0x%08X : EtherStatsFragments\n",
6631 sblk->stat_EtherStatsFragments);
6632 }
6633
6634 if (sblk->stat_EtherStatsJabbers) {
6635 if_printf(ifp, " 0x%08X : EtherStatsJabbers\n",
6636 sblk->stat_EtherStatsJabbers);
6637 }
6638
6639 if (sblk->stat_EtherStatsUndersizePkts) {
6640 if_printf(ifp, " 0x%08X : EtherStatsUndersizePkts\n",
6641 sblk->stat_EtherStatsUndersizePkts);
6642 }
6643
6644 if (sblk->stat_EtherStatsOverrsizePkts) {
6645 if_printf(ifp, " 0x%08X : EtherStatsOverrsizePkts\n",
6646 sblk->stat_EtherStatsOverrsizePkts);
6647 }
6648
6649 if (sblk->stat_EtherStatsPktsRx64Octets) {
6650 if_printf(ifp, " 0x%08X : EtherStatsPktsRx64Octets\n",
6651 sblk->stat_EtherStatsPktsRx64Octets);
6652 }
6653
6654 if (sblk->stat_EtherStatsPktsRx65Octetsto127Octets) {
6655 if_printf(ifp, " 0x%08X : "
6656 "EtherStatsPktsRx65Octetsto127Octets\n",
6657 sblk->stat_EtherStatsPktsRx65Octetsto127Octets);
6658 }
6659
6660 if (sblk->stat_EtherStatsPktsRx128Octetsto255Octets) {
6661 if_printf(ifp, " 0x%08X : "
6662 "EtherStatsPktsRx128Octetsto255Octets\n",
6663 sblk->stat_EtherStatsPktsRx128Octetsto255Octets);
6664 }
6665
6666 if (sblk->stat_EtherStatsPktsRx256Octetsto511Octets) {
6667 if_printf(ifp, " 0x%08X : "
6668 "EtherStatsPktsRx256Octetsto511Octets\n",
6669 sblk->stat_EtherStatsPktsRx256Octetsto511Octets);
6670 }
6671
6672 if (sblk->stat_EtherStatsPktsRx512Octetsto1023Octets) {
6673 if_printf(ifp, " 0x%08X : "
6674 "EtherStatsPktsRx512Octetsto1023Octets\n",
6675 sblk->stat_EtherStatsPktsRx512Octetsto1023Octets);
6676 }
6677
6678 if (sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets) {
6679 if_printf(ifp, " 0x%08X : "
6680 "EtherStatsPktsRx1024Octetsto1522Octets\n",
6681 sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets);
6682 }
6683
6684 if (sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets) {
6685 if_printf(ifp, " 0x%08X : "
6686 "EtherStatsPktsRx1523Octetsto9022Octets\n",
6687 sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets);
6688 }
6689
6690 if (sblk->stat_EtherStatsPktsTx64Octets) {
6691 if_printf(ifp, " 0x%08X : EtherStatsPktsTx64Octets\n",
6692 sblk->stat_EtherStatsPktsTx64Octets);
6693 }
6694
6695 if (sblk->stat_EtherStatsPktsTx65Octetsto127Octets) {
6696 if_printf(ifp, " 0x%08X : "
6697 "EtherStatsPktsTx65Octetsto127Octets\n",
6698 sblk->stat_EtherStatsPktsTx65Octetsto127Octets);
6699 }
6700
6701 if (sblk->stat_EtherStatsPktsTx128Octetsto255Octets) {
6702 if_printf(ifp, " 0x%08X : "
6703 "EtherStatsPktsTx128Octetsto255Octets\n",
6704 sblk->stat_EtherStatsPktsTx128Octetsto255Octets);
6705 }
6706
6707 if (sblk->stat_EtherStatsPktsTx256Octetsto511Octets) {
6708 if_printf(ifp, " 0x%08X : "
6709 "EtherStatsPktsTx256Octetsto511Octets\n",
6710 sblk->stat_EtherStatsPktsTx256Octetsto511Octets);
6711 }
6712
6713 if (sblk->stat_EtherStatsPktsTx512Octetsto1023Octets) {
6714 if_printf(ifp, " 0x%08X : "
6715 "EtherStatsPktsTx512Octetsto1023Octets\n",
6716 sblk->stat_EtherStatsPktsTx512Octetsto1023Octets);
6717 }
6718
6719 if (sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets) {
6720 if_printf(ifp, " 0x%08X : "
6721 "EtherStatsPktsTx1024Octetsto1522Octets\n",
6722 sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets);
6723 }
6724
6725 if (sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets) {
6726 if_printf(ifp, " 0x%08X : "
6727 "EtherStatsPktsTx1523Octetsto9022Octets\n",
6728 sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets);
6729 }
6730
6731 if (sblk->stat_XonPauseFramesReceived) {
6732 if_printf(ifp, " 0x%08X : XonPauseFramesReceived\n",
6733 sblk->stat_XonPauseFramesReceived);
6734 }
6735
6736 if (sblk->stat_XoffPauseFramesReceived) {
6737 if_printf(ifp, " 0x%08X : XoffPauseFramesReceived\n",
6738 sblk->stat_XoffPauseFramesReceived);
6739 }
6740
6741 if (sblk->stat_OutXonSent) {
6742 if_printf(ifp, " 0x%08X : OutXoffSent\n",
6743 sblk->stat_OutXonSent);
6744 }
6745
6746 if (sblk->stat_OutXoffSent) {
6747 if_printf(ifp, " 0x%08X : OutXoffSent\n",
6748 sblk->stat_OutXoffSent);
6749 }
6750
6751 if (sblk->stat_FlowControlDone) {
6752 if_printf(ifp, " 0x%08X : FlowControlDone\n",
6753 sblk->stat_FlowControlDone);
6754 }
6755
6756 if (sblk->stat_MacControlFramesReceived) {
6757 if_printf(ifp, " 0x%08X : MacControlFramesReceived\n",
6758 sblk->stat_MacControlFramesReceived);
6759 }
6760
6761 if (sblk->stat_XoffStateEntered) {
6762 if_printf(ifp, " 0x%08X : XoffStateEntered\n",
6763 sblk->stat_XoffStateEntered);
6764 }
6765
6766 if (sblk->stat_IfInFramesL2FilterDiscards) {
6767 if_printf(ifp, " 0x%08X : IfInFramesL2FilterDiscards\n", sblk->stat_IfInFramesL2FilterDiscards);
6768 }
6769
6770 if (sblk->stat_IfInRuleCheckerDiscards) {
6771 if_printf(ifp, " 0x%08X : IfInRuleCheckerDiscards\n",
6772 sblk->stat_IfInRuleCheckerDiscards);
6773 }
6774
6775 if (sblk->stat_IfInFTQDiscards) {
6776 if_printf(ifp, " 0x%08X : IfInFTQDiscards\n",
6777 sblk->stat_IfInFTQDiscards);
6778 }
6779
6780 if (sblk->stat_IfInMBUFDiscards) {
6781 if_printf(ifp, " 0x%08X : IfInMBUFDiscards\n",
6782 sblk->stat_IfInMBUFDiscards);
6783 }
6784
6785 if (sblk->stat_IfInRuleCheckerP4Hit) {
6786 if_printf(ifp, " 0x%08X : IfInRuleCheckerP4Hit\n",
6787 sblk->stat_IfInRuleCheckerP4Hit);
6788 }
6789
6790 if (sblk->stat_CatchupInRuleCheckerDiscards) {
6791 if_printf(ifp, " 0x%08X : "
6792 "CatchupInRuleCheckerDiscards\n",
6793 sblk->stat_CatchupInRuleCheckerDiscards);
6794 }
6795
6796 if (sblk->stat_CatchupInFTQDiscards) {
6797 if_printf(ifp, " 0x%08X : CatchupInFTQDiscards\n",
6798 sblk->stat_CatchupInFTQDiscards);
6799 }
6800
6801 if (sblk->stat_CatchupInMBUFDiscards) {
6802 if_printf(ifp, " 0x%08X : CatchupInMBUFDiscards\n",
6803 sblk->stat_CatchupInMBUFDiscards);
6804 }
6805
6806 if (sblk->stat_CatchupInRuleCheckerP4Hit) {
6807 if_printf(ifp, " 0x%08X : CatchupInRuleCheckerP4Hit\n",
6808 sblk->stat_CatchupInRuleCheckerP4Hit);
6809 }
6810
6811 if_printf(ifp,
6812 "----------------------------"
6813 "----------------"
6814 "----------------------------\n");
6815 }
6816
6817
6818 /****************************************************************************/
6819 /* Prints out a summary of the driver state. */
6820 /* */
6821 /* Returns: */
6822 /* Nothing. */
6823 /****************************************************************************/
6824 static void
6825 bce_dump_driver_state(struct bce_softc *sc)
6826 {
6827 struct ifnet *ifp = &sc->arpcom.ac_if;
6828 uint32_t val_hi, val_lo;
6829
6830 if_printf(ifp,
6831 "-----------------------------"
6832 " Driver State "
6833 "-----------------------------\n");
6834
6835 val_hi = BCE_ADDR_HI(sc);
6836 val_lo = BCE_ADDR_LO(sc);
6837 if_printf(ifp, "0x%08X:%08X - (sc) driver softc structure "
6838 "virtual address\n", val_hi, val_lo);
6839
6840 val_hi = BCE_ADDR_HI(sc->status_block);
6841 val_lo = BCE_ADDR_LO(sc->status_block);
6842 if_printf(ifp, "0x%08X:%08X - (sc->status_block) status block "
6843 "virtual address\n", val_hi, val_lo);
6844
6845 val_hi = BCE_ADDR_HI(sc->stats_block);
6846 val_lo = BCE_ADDR_LO(sc->stats_block);
6847 if_printf(ifp, "0x%08X:%08X - (sc->stats_block) statistics block "
6848 "virtual address\n", val_hi, val_lo);
6849
6850 val_hi = BCE_ADDR_HI(sc->tx_bd_chain);
6851 val_lo = BCE_ADDR_LO(sc->tx_bd_chain);
6852 if_printf(ifp, "0x%08X:%08X - (sc->tx_bd_chain) tx_bd chain "
6853 "virtual adddress\n", val_hi, val_lo);
6854
6855 val_hi = BCE_ADDR_HI(sc->rx_bd_chain);
6856 val_lo = BCE_ADDR_LO(sc->rx_bd_chain);
6857 if_printf(ifp, "0x%08X:%08X - (sc->rx_bd_chain) rx_bd chain "
6858 "virtual address\n", val_hi, val_lo);
6859
6860 val_hi = BCE_ADDR_HI(sc->tx_mbuf_ptr);
6861 val_lo = BCE_ADDR_LO(sc->tx_mbuf_ptr);
6862 if_printf(ifp, "0x%08X:%08X - (sc->tx_mbuf_ptr) tx mbuf chain "
6863 "virtual address\n", val_hi, val_lo);
6864
6865 val_hi = BCE_ADDR_HI(sc->rx_mbuf_ptr);
6866 val_lo = BCE_ADDR_LO(sc->rx_mbuf_ptr);
6867 if_printf(ifp, "0x%08X:%08X - (sc->rx_mbuf_ptr) rx mbuf chain "
6868 "virtual address\n", val_hi, val_lo);
6869
6870 if_printf(ifp, " 0x%08X - (sc->interrupts_generated) "
6871 "h/w intrs\n", sc->interrupts_generated);
6872
6873 if_printf(ifp, " 0x%08X - (sc->rx_interrupts) "
6874 "rx interrupts handled\n", sc->rx_interrupts);
6875
6876 if_printf(ifp, " 0x%08X - (sc->tx_interrupts) "
6877 "tx interrupts handled\n", sc->tx_interrupts);
6878
6879 if_printf(ifp, " 0x%08X - (sc->last_status_idx) "
6880 "status block index\n", sc->last_status_idx);
6881
6882 if_printf(ifp, " 0x%04X(0x%04X) - (sc->tx_prod) "
6883 "tx producer index\n",
6884 sc->tx_prod, (uint16_t)TX_CHAIN_IDX(sc->tx_prod));
6885
6886 if_printf(ifp, " 0x%04X(0x%04X) - (sc->tx_cons) "
6887 "tx consumer index\n",
6888 sc->tx_cons, (uint16_t)TX_CHAIN_IDX(sc->tx_cons));
6889
6890 if_printf(ifp, " 0x%08X - (sc->tx_prod_bseq) "
6891 "tx producer bseq index\n", sc->tx_prod_bseq);
6892
6893 if_printf(ifp, " 0x%04X(0x%04X) - (sc->rx_prod) "
6894 "rx producer index\n",
6895 sc->rx_prod, (uint16_t)RX_CHAIN_IDX(sc->rx_prod));
6896
6897 if_printf(ifp, " 0x%04X(0x%04X) - (sc->rx_cons) "
6898 "rx consumer index\n",
6899 sc->rx_cons, (uint16_t)RX_CHAIN_IDX(sc->rx_cons));
6900
6901 if_printf(ifp, " 0x%08X - (sc->rx_prod_bseq) "
6902 "rx producer bseq index\n", sc->rx_prod_bseq);
6903
6904 if_printf(ifp, " 0x%08X - (sc->rx_mbuf_alloc) "
6905 "rx mbufs allocated\n", sc->rx_mbuf_alloc);
6906
6907 if_printf(ifp, " 0x%08X - (sc->free_rx_bd) "
6908 "free rx_bd's\n", sc->free_rx_bd);
6909
6910 if_printf(ifp, "0x%08X/%08X - (sc->rx_low_watermark) rx "
6911 "low watermark\n", sc->rx_low_watermark, sc->max_rx_bd);
6912
6913 if_printf(ifp, " 0x%08X - (sc->txmbuf_alloc) "
6914 "tx mbufs allocated\n", sc->tx_mbuf_alloc);
6915
6916 if_printf(ifp, " 0x%08X - (sc->rx_mbuf_alloc) "
6917 "rx mbufs allocated\n", sc->rx_mbuf_alloc);
6918
6919 if_printf(ifp, " 0x%08X - (sc->used_tx_bd) used tx_bd's\n",
6920 sc->used_tx_bd);
6921
6922 if_printf(ifp, "0x%08X/%08X - (sc->tx_hi_watermark) tx hi watermark\n",
6923 sc->tx_hi_watermark, sc->max_tx_bd);
6924
6925 if_printf(ifp, " 0x%08X - (sc->mbuf_alloc_failed) "
6926 "failed mbuf alloc\n", sc->mbuf_alloc_failed);
6927
6928 if_printf(ifp,
6929 "----------------------------"
6930 "----------------"
6931 "----------------------------\n");
6932 }
6933
6934
6935 /****************************************************************************/
6936 /* Prints out the hardware state through a summary of important registers, */
6937 /* followed by a complete register dump. */
6938 /* */
6939 /* Returns: */
6940 /* Nothing. */
6941 /****************************************************************************/
6942 static void
6943 bce_dump_hw_state(struct bce_softc *sc)
6944 {
6945 struct ifnet *ifp = &sc->arpcom.ac_if;
6946 uint32_t val1;
6947 int i;
6948
6949 if_printf(ifp,
6950 "----------------------------"
6951 " Hardware State "
6952 "----------------------------\n");
6953
6954 if_printf(ifp, "0x%08X - bootcode version\n", sc->bce_fw_ver);
6955
6956 val1 = REG_RD(sc, BCE_MISC_ENABLE_STATUS_BITS);
6957 if_printf(ifp, "0x%08X - (0x%06X) misc_enable_status_bits\n",
6958 val1, BCE_MISC_ENABLE_STATUS_BITS);
6959
6960 val1 = REG_RD(sc, BCE_DMA_STATUS);
6961 if_printf(ifp, "0x%08X - (0x%04X) dma_status\n", val1, BCE_DMA_STATUS);
6962
6963 val1 = REG_RD(sc, BCE_CTX_STATUS);
6964 if_printf(ifp, "0x%08X - (0x%04X) ctx_status\n", val1, BCE_CTX_STATUS);
6965
6966 val1 = REG_RD(sc, BCE_EMAC_STATUS);
6967 if_printf(ifp, "0x%08X - (0x%04X) emac_status\n",
6968 val1, BCE_EMAC_STATUS);
6969
6970 val1 = REG_RD(sc, BCE_RPM_STATUS);
6971 if_printf(ifp, "0x%08X - (0x%04X) rpm_status\n", val1, BCE_RPM_STATUS);
6972
6973 val1 = REG_RD(sc, BCE_TBDR_STATUS);
6974 if_printf(ifp, "0x%08X - (0x%04X) tbdr_status\n",
6975 val1, BCE_TBDR_STATUS);
6976
6977 val1 = REG_RD(sc, BCE_TDMA_STATUS);
6978 if_printf(ifp, "0x%08X - (0x%04X) tdma_status\n",
6979 val1, BCE_TDMA_STATUS);
6980
6981 val1 = REG_RD(sc, BCE_HC_STATUS);
6982 if_printf(ifp, "0x%08X - (0x%06X) hc_status\n", val1, BCE_HC_STATUS);
6983
6984 val1 = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
6985 if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_state\n",
6986 val1, BCE_TXP_CPU_STATE);
6987
6988 val1 = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
6989 if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_state\n",
6990 val1, BCE_TPAT_CPU_STATE);
6991
6992 val1 = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
6993 if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_state\n",
6994 val1, BCE_RXP_CPU_STATE);
6995
6996 val1 = REG_RD_IND(sc, BCE_COM_CPU_STATE);
6997 if_printf(ifp, "0x%08X - (0x%06X) com_cpu_state\n",
6998 val1, BCE_COM_CPU_STATE);
6999
7000 val1 = REG_RD_IND(sc, BCE_MCP_CPU_STATE);
7001 if_printf(ifp, "0x%08X - (0x%06X) mcp_cpu_state\n",
7002 val1, BCE_MCP_CPU_STATE);
7003
7004 val1 = REG_RD_IND(sc, BCE_CP_CPU_STATE);
7005 if_printf(ifp, "0x%08X - (0x%06X) cp_cpu_state\n",
7006 val1, BCE_CP_CPU_STATE);
7007
7008 if_printf(ifp,
7009 "----------------------------"
7010 "----------------"
7011 "----------------------------\n");
7012
7013 if_printf(ifp,
7014 "----------------------------"
7015 " Register Dump "
7016 "----------------------------\n");
7017
7018 for (i = 0x400; i < 0x8000; i += 0x10) {
7019 if_printf(ifp, "0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7020 REG_RD(sc, i),
7021 REG_RD(sc, i + 0x4),
7022 REG_RD(sc, i + 0x8),
7023 REG_RD(sc, i + 0xc));
7024 }
7025
7026 if_printf(ifp,
7027 "----------------------------"
7028 "----------------"
7029 "----------------------------\n");
7030 }
7031
7032
7033 /****************************************************************************/
7034 /* Prints out the TXP state. */
7035 /* */
7036 /* Returns: */
7037 /* Nothing. */
7038 /****************************************************************************/
7039 static void
7040 bce_dump_txp_state(struct bce_softc *sc)
7041 {
7042 struct ifnet *ifp = &sc->arpcom.ac_if;
7043 uint32_t val1;
7044 int i;
7045
7046 if_printf(ifp,
7047 "----------------------------"
7048 " TXP State "
7049 "----------------------------\n");
7050
7051 val1 = REG_RD_IND(sc, BCE_TXP_CPU_MODE);
7052 if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_mode\n",
7053 val1, BCE_TXP_CPU_MODE);
7054
7055 val1 = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
7056 if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_state\n",
7057 val1, BCE_TXP_CPU_STATE);
7058
7059 val1 = REG_RD_IND(sc, BCE_TXP_CPU_EVENT_MASK);
7060 if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_event_mask\n",
7061 val1, BCE_TXP_CPU_EVENT_MASK);
7062
7063 if_printf(ifp,
7064 "----------------------------"
7065 " Register Dump "
7066 "----------------------------\n");
7067
7068 for (i = BCE_TXP_CPU_MODE; i < 0x68000; i += 0x10) {
7069 /* Skip the big blank spaces */
7070 if (i < 0x454000 && i > 0x5ffff) {
7071 if_printf(ifp, "0x%04X: "
7072 "0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7073 REG_RD_IND(sc, i),
7074 REG_RD_IND(sc, i + 0x4),
7075 REG_RD_IND(sc, i + 0x8),
7076 REG_RD_IND(sc, i + 0xc));
7077 }
7078 }
7079
7080 if_printf(ifp,
7081 "----------------------------"
7082 "----------------"
7083 "----------------------------\n");
7084 }
7085
7086
7087 /****************************************************************************/
7088 /* Prints out the RXP state. */
7089 /* */
7090 /* Returns: */
7091 /* Nothing. */
7092 /****************************************************************************/
7093 static void
7094 bce_dump_rxp_state(struct bce_softc *sc)
7095 {
7096 struct ifnet *ifp = &sc->arpcom.ac_if;
7097 uint32_t val1;
7098 int i;
7099
7100 if_printf(ifp,
7101 "----------------------------"
7102 " RXP State "
7103 "----------------------------\n");
7104
7105 val1 = REG_RD_IND(sc, BCE_RXP_CPU_MODE);
7106 if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_mode\n",
7107 val1, BCE_RXP_CPU_MODE);
7108
7109 val1 = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
7110 if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_state\n",
7111 val1, BCE_RXP_CPU_STATE);
7112
7113 val1 = REG_RD_IND(sc, BCE_RXP_CPU_EVENT_MASK);
7114 if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_event_mask\n",
7115 val1, BCE_RXP_CPU_EVENT_MASK);
7116
7117 if_printf(ifp,
7118 "----------------------------"
7119 " Register Dump "
7120 "----------------------------\n");
7121
7122 for (i = BCE_RXP_CPU_MODE; i < 0xe8fff; i += 0x10) {
7123 /* Skip the big blank sapces */
7124 if (i < 0xc5400 && i > 0xdffff) {
7125 if_printf(ifp, "0x%04X: "
7126 "0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7127 REG_RD_IND(sc, i),
7128 REG_RD_IND(sc, i + 0x4),
7129 REG_RD_IND(sc, i + 0x8),
7130 REG_RD_IND(sc, i + 0xc));
7131 }
7132 }
7133
7134 if_printf(ifp,
7135 "----------------------------"
7136 "----------------"
7137 "----------------------------\n");
7138 }
7139
7140
7141 /****************************************************************************/
7142 /* Prints out the TPAT state. */
7143 /* */
7144 /* Returns: */
7145 /* Nothing. */
7146 /****************************************************************************/
7147 static void
7148 bce_dump_tpat_state(struct bce_softc *sc)
7149 {
7150 struct ifnet *ifp = &sc->arpcom.ac_if;
7151 uint32_t val1;
7152 int i;
7153
7154 if_printf(ifp,
7155 "----------------------------"
7156 " TPAT State "
7157 "----------------------------\n");
7158
7159 val1 = REG_RD_IND(sc, BCE_TPAT_CPU_MODE);
7160 if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_mode\n",
7161 val1, BCE_TPAT_CPU_MODE);
7162
7163 val1 = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
7164 if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_state\n",
7165 val1, BCE_TPAT_CPU_STATE);
7166
7167 val1 = REG_RD_IND(sc, BCE_TPAT_CPU_EVENT_MASK);
7168 if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_event_mask\n",
7169 val1, BCE_TPAT_CPU_EVENT_MASK);
7170
7171 if_printf(ifp,
7172 "----------------------------"
7173 " Register Dump "
7174 "----------------------------\n");
7175
7176 for (i = BCE_TPAT_CPU_MODE; i < 0xa3fff; i += 0x10) {
7177 /* Skip the big blank spaces */
7178 if (i < 0x854000 && i > 0x9ffff) {
7179 if_printf(ifp, "0x%04X: "
7180 "0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7181 REG_RD_IND(sc, i),
7182 REG_RD_IND(sc, i + 0x4),
7183 REG_RD_IND(sc, i + 0x8),
7184 REG_RD_IND(sc, i + 0xc));
7185 }
7186 }
7187
7188 if_printf(ifp,
7189 "----------------------------"
7190 "----------------"
7191 "----------------------------\n");
7192 }
7193
7194
7195 /****************************************************************************/
7196 /* Prints out the driver state and then enters the debugger. */
7197 /* */
7198 /* Returns: */
7199 /* Nothing. */
7200 /****************************************************************************/
7201 static void
7202 bce_breakpoint(struct bce_softc *sc)
7203 {
7204 #if 0
7205 bce_freeze_controller(sc);
7206 #endif
7207
7208 bce_dump_driver_state(sc);
7209 bce_dump_status_block(sc);
7210 bce_dump_tx_chain(sc, 0, TOTAL_TX_BD);
7211 bce_dump_hw_state(sc);
7212 bce_dump_txp_state(sc);
7213
7214 #if 0
7215 bce_unfreeze_controller(sc);
7216 #endif
7217
7218 /* Call the debugger. */
7219 breakpoint();
7220 }
7221
7222 #endif /* BCE_DEBUG */
7223
7224 static int
7225 bce_sysctl_tx_bds_int(SYSCTL_HANDLER_ARGS)
7226 {
7227 struct bce_softc *sc = arg1;
7228
7229 return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7230 &sc->bce_tx_quick_cons_trip_int,
7231 BCE_COALMASK_TX_BDS_INT);
7232 }
7233
7234 static int
7235 bce_sysctl_tx_bds(SYSCTL_HANDLER_ARGS)
7236 {
7237 struct bce_softc *sc = arg1;
7238
7239 return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7240 &sc->bce_tx_quick_cons_trip,
7241 BCE_COALMASK_TX_BDS);
7242 }
7243
7244 static int
7245 bce_sysctl_tx_ticks_int(SYSCTL_HANDLER_ARGS)
7246 {
7247 struct bce_softc *sc = arg1;
7248
7249 return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7250 &sc->bce_tx_ticks_int,
7251 BCE_COALMASK_TX_TICKS_INT);
7252 }
7253
7254 static int
7255 bce_sysctl_tx_ticks(SYSCTL_HANDLER_ARGS)
7256 {
7257 struct bce_softc *sc = arg1;
7258
7259 return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7260 &sc->bce_tx_ticks,
7261 BCE_COALMASK_TX_TICKS);
7262 }
7263
7264 static int
7265 bce_sysctl_rx_bds_int(SYSCTL_HANDLER_ARGS)
7266 {
7267 struct bce_softc *sc = arg1;
7268
7269 return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7270 &sc->bce_rx_quick_cons_trip_int,
7271 BCE_COALMASK_RX_BDS_INT);
7272 }
7273
7274 static int
7275 bce_sysctl_rx_bds(SYSCTL_HANDLER_ARGS)
7276 {
7277 struct bce_softc *sc = arg1;
7278
7279 return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7280 &sc->bce_rx_quick_cons_trip,
7281 BCE_COALMASK_RX_BDS);
7282 }
7283
7284 static int
7285 bce_sysctl_rx_ticks_int(SYSCTL_HANDLER_ARGS)
7286 {
7287 struct bce_softc *sc = arg1;
7288
7289 return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7290 &sc->bce_rx_ticks_int,
7291 BCE_COALMASK_RX_TICKS_INT);
7292 }
7293
7294 static int
7295 bce_sysctl_rx_ticks(SYSCTL_HANDLER_ARGS)
7296 {
7297 struct bce_softc *sc = arg1;
7298
7299 return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7300 &sc->bce_rx_ticks,
7301 BCE_COALMASK_RX_TICKS);
7302 }
7303
7304 static int
7305 bce_sysctl_coal_change(SYSCTL_HANDLER_ARGS, uint32_t *coal,
7306 uint32_t coalchg_mask)
7307 {
7308 struct bce_softc *sc = arg1;
7309 struct ifnet *ifp = &sc->arpcom.ac_if;
7310 int error = 0, v;
7311
7312 lwkt_serialize_enter(ifp->if_serializer);
7313
7314 v = *coal;
7315 error = sysctl_handle_int(oidp, &v, 0, req);
7316 if (!error && req->newptr != NULL) {
7317 if (v < 0) {
7318 error = EINVAL;
7319 } else {
7320 *coal = v;
7321 sc->bce_coalchg_mask |= coalchg_mask;
7322 }
7323 }
7324
7325 lwkt_serialize_exit(ifp->if_serializer);
7326 return error;
7327 }
7328
7329 static void
7330 bce_coal_change(struct bce_softc *sc)
7331 {
7332 struct ifnet *ifp = &sc->arpcom.ac_if;
7333
7334 ASSERT_SERIALIZED(ifp->if_serializer);
7335
7336 if ((ifp->if_flags & IFF_RUNNING) == 0) {
7337 sc->bce_coalchg_mask = 0;
7338 return;
7339 }
7340
7341 if (sc->bce_coalchg_mask &
7342 (BCE_COALMASK_TX_BDS | BCE_COALMASK_TX_BDS_INT)) {
7343 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
7344 (sc->bce_tx_quick_cons_trip_int << 16) |
7345 sc->bce_tx_quick_cons_trip);
7346 if (bootverbose) {
7347 if_printf(ifp, "tx_bds %u, tx_bds_int %u\n",
7348 sc->bce_tx_quick_cons_trip,
7349 sc->bce_tx_quick_cons_trip_int);
7350 }
7351 }
7352
7353 if (sc->bce_coalchg_mask &
7354 (BCE_COALMASK_TX_TICKS | BCE_COALMASK_TX_TICKS_INT)) {
7355 REG_WR(sc, BCE_HC_TX_TICKS,
7356 (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks);
7357 if (bootverbose) {
7358 if_printf(ifp, "tx_ticks %u, tx_ticks_int %u\n",
7359 sc->bce_tx_ticks, sc->bce_tx_ticks_int);
7360 }
7361 }
7362
7363 if (sc->bce_coalchg_mask &
7364 (BCE_COALMASK_RX_BDS | BCE_COALMASK_RX_BDS_INT)) {
7365 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
7366 (sc->bce_rx_quick_cons_trip_int << 16) |
7367 sc->bce_rx_quick_cons_trip);
7368 if (bootverbose) {
7369 if_printf(ifp, "rx_bds %u, rx_bds_int %u\n",
7370 sc->bce_rx_quick_cons_trip,
7371 sc->bce_rx_quick_cons_trip_int);
7372 }
7373 }
7374
7375 if (sc->bce_coalchg_mask &
7376 (BCE_COALMASK_RX_TICKS | BCE_COALMASK_RX_TICKS_INT)) {
7377 REG_WR(sc, BCE_HC_RX_TICKS,
7378 (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks);
7379 if (bootverbose) {
7380 if_printf(ifp, "rx_ticks %u, rx_ticks_int %u\n",
7381 sc->bce_rx_ticks, sc->bce_rx_ticks_int);
7382 }
7383 }
7384
7385 sc->bce_coalchg_mask = 0;
7386 }
DragonFly BSD