sbin/hammer: Have consistent naming for buffer variables
[dragonfly.git] / sys / bus / firewire / firewire.h
blob2c4e22898b370521f72be4f43324f7560498aecd
1 /*
2 * Copyright (c) 2003 Hidetoshi Shimokawa
3 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa
4 * All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the acknowledgement as bellow:
17 * This product includes software developed by K. Kobayashi and H. Shimokawa
19 * 4. The name of the author may not be used to endorse or promote products
20 * derived from this software without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32 * POSSIBILITY OF SUCH DAMAGE.
34 * $FreeBSD: src/sys/dev/firewire/firewire.h,v 1.17 2003/11/07 09:01:41 simokawa Exp $
37 #ifndef _FIREWIRE_H
38 #define _FIREWIRE_H 1
40 #include <sys/ioccom.h>
42 #define DEV_DEF 0
43 #define DEV_DV 2
45 struct fw_isochreq {
46 unsigned char ch:6,
47 tag:2;
50 struct fw_isobufreq {
51 struct fw_bufspec {
52 unsigned int nchunk;
53 unsigned int npacket;
54 unsigned int psize;
55 } tx, rx;
58 struct fw_addr {
59 unsigned long hi;
60 unsigned long lo;
63 struct fw_asybindreq {
64 struct fw_addr start;
65 unsigned long len;
68 struct fw_reg_req_t {
69 unsigned long addr;
70 unsigned long data;
73 #define MAXREC(x) (2 << (x))
74 #define FWPMAX_S400 (2048 + 20) /* MAXREC plus space for control data */
75 #define FWMAXQUEUE 128
77 #define FWLOCALBUS 0xffc0
79 #define FWTCODE_WREQQ 0
80 #define FWTCODE_WREQB 1
81 #define FWTCODE_WRES 2
82 #define FWTCODE_RREQQ 4
83 #define FWTCODE_RREQB 5
84 #define FWTCODE_RRESQ 6
85 #define FWTCODE_RRESB 7
86 #define FWTCODE_CYCS 8
87 #define FWTCODE_LREQ 9
88 #define FWTCODE_STREAM 0xa
89 #define FWTCODE_LRES 0xb
90 #define FWTCODE_PHY 0xe
92 #define FWRETRY_1 0
93 #define FWRETRY_X 1
94 #define FWRETRY_A 2
95 #define FWRETRY_B 3
97 #define FWRCODE_COMPLETE 0
98 #define FWRCODE_ER_CONFL 4
99 #define FWRCODE_ER_DATA 5
100 #define FWRCODE_ER_TYPE 6
101 #define FWRCODE_ER_ADDR 7
103 #define FWSPD_S100 0
104 #define FWSPD_S200 1
105 #define FWSPD_S400 2
107 #define FWP_TL_VALID (1 << 7)
109 struct fw_isohdr {
110 u_int32_t hdr[1];
113 struct fw_asyhdr {
114 u_int32_t hdr[4];
117 #if BYTE_ORDER == BIG_ENDIAN
118 #define BIT4x2(x,y) u_int8_t x:4, y:4
119 #define BIT16x2(x,y) u_int32_t x:16, y:16
120 #else
121 #define BIT4x2(x,y) u_int8_t y:4, x:4
122 #define BIT16x2(x,y) u_int32_t y:16, x:16
123 #endif
126 #if BYTE_ORDER == BIG_ENDIAN
127 #define COMMON_HDR(a,b,c,d) u_int32_t a:16,b:8,c:4,d:4
128 #define COMMON_RES(a,b,c,d) u_int32_t a:16,b:4,c:4,d:8
129 #else
130 #define COMMON_HDR(a,b,c,d) u_int32_t d:4,c:4,b:8,a:16
131 #define COMMON_RES(a,b,c,d) u_int32_t d:8,c:4,b:4,a:16
132 #endif
134 struct fw_pkt {
135 union {
136 u_int32_t ld[0];
137 struct {
138 COMMON_HDR(, , tcode, );
139 } common;
140 struct {
141 COMMON_HDR(len, chtag, tcode, sy);
142 u_int32_t payload[0];
143 } stream;
144 struct {
145 COMMON_HDR(dst, tlrt, tcode, pri);
146 BIT16x2(src, );
147 } hdr;
148 struct {
149 COMMON_HDR(dst, tlrt, tcode, pri);
150 BIT16x2(src, dest_hi);
151 u_int32_t dest_lo;
152 } rreqq;
153 struct {
154 COMMON_HDR(dst, tlrt, tcode, pri);
155 COMMON_RES(src, rtcode, , );
156 u_int32_t :32;
157 } wres;
158 struct {
159 COMMON_HDR(dst, tlrt, tcode, pri);
160 BIT16x2(src, dest_hi);
161 u_int32_t dest_lo;
162 BIT16x2(len, extcode);
163 } rreqb;
164 struct {
165 COMMON_HDR(dst, tlrt, tcode, pri);
166 BIT16x2(src, dest_hi);
167 u_int32_t dest_lo;
168 u_int32_t data;
169 } wreqq;
170 struct {
171 COMMON_HDR(dst, tlrt, tcode, pri);
172 BIT16x2(src, dest_hi);
173 u_int32_t dest_lo;
174 u_int32_t data;
175 } cyc;
176 struct {
177 COMMON_HDR(dst, tlrt, tcode, pri);
178 COMMON_RES(src, rtcode, , );
179 u_int32_t :32;
180 u_int32_t data;
181 } rresq;
182 struct {
183 COMMON_HDR(dst, tlrt, tcode, pri);
184 BIT16x2(src, dest_hi);
185 u_int32_t dest_lo;
186 BIT16x2(len, extcode);
187 u_int32_t payload[0];
188 } wreqb;
189 struct {
190 COMMON_HDR(dst, tlrt, tcode, pri);
191 BIT16x2(src, dest_hi);
192 u_int32_t dest_lo;
193 BIT16x2(len, extcode);
194 u_int32_t payload[0];
195 } lreq;
196 struct {
197 COMMON_HDR(dst, tlrt, tcode, pri);
198 COMMON_RES(src, rtcode, , );
199 u_int32_t :32;
200 BIT16x2(len, extcode);
201 u_int32_t payload[0];
202 } rresb;
203 struct {
204 COMMON_HDR(dst, tlrt, tcode, pri);
205 COMMON_RES(src, rtcode, , );
206 u_int32_t :32;
207 BIT16x2(len, extcode);
208 u_int32_t payload[0];
209 } lres;
210 } mode;
214 * Response code (rtcode)
216 /* The node has successfully completed the command. */
217 #define RESP_CMP 0
218 /* A resource conflict was detected. The request may be retried. */
219 #define RESP_CONFLICT_ERROR 4
220 /* Hardware error, data is unavailable. */
221 #define RESP_DATA_ERROR 5
222 /* A field in the request packet header was set to an unsupported or incorrect
223 * value, or an invalid transaction was attempted (e.g., a write to a read-only
224 * address). */
225 #define RESP_TYPE_ERROR 6
226 /* The destination offset field in the request was set to an address not
227 * accessible in the destination node. */
228 #define RESP_ADDRESS_ERROR 7
231 * Extended transaction code (extcode)
233 #define EXTCODE_MASK_SWAP 1
234 #define EXTCODE_CMP_SWAP 2
235 #define EXTCODE_FETCH_ADD 3
236 #define EXTCODE_LITTLE_ADD 4
237 #define EXTCODE_BOUNDED_ADD 5
238 #define EXTCODE_WRAP_ADD 6
240 struct fw_eui64 {
241 u_int32_t hi, lo;
243 #define FW_EUI64_BYTE(eui, x) \
244 ((((x)<4)? \
245 ((eui)->hi >> (8*(3-(x)))): \
246 ((eui)->lo >> (8*(7-(x)))) \
247 ) & 0xff)
248 #define FW_EUI64_EQUAL(x, y) \
249 ((x).hi == (y).hi && (x).lo == (y).lo)
251 struct fw_asyreq {
252 struct fw_asyreq_t{
253 unsigned char sped;
254 unsigned int type;
255 #define FWASREQNODE 0
256 #define FWASREQEUI 1
257 #define FWASRESTL 2
258 #define FWASREQSTREAM 3
259 unsigned short len;
260 union {
261 struct fw_eui64 eui;
262 }dst;
263 }req;
264 struct fw_pkt pkt;
265 u_int32_t data[512];
268 struct fw_devinfo {
269 struct fw_eui64 eui;
270 u_int16_t dst;
271 u_int16_t status;
274 #define FW_MAX_DEVLST 70
275 struct fw_devlstreq {
276 u_int16_t n;
277 u_int16_t info_len;
278 struct fw_devinfo dev[FW_MAX_DEVLST];
281 #define FW_SELF_ID_PORT_CONNECTED_TO_CHILD 3
282 #define FW_SELF_ID_PORT_CONNECTED_TO_PARENT 2
283 #define FW_SELF_ID_PORT_NOT_CONNECTED 1
284 #define FW_SELF_ID_PORT_NOT_EXISTS 0
285 #if BYTE_ORDER == BIG_ENDIAN
286 union fw_self_id {
287 struct {
288 u_int32_t id:2,
289 phy_id:6,
290 sequel:1,
291 link_active:1,
292 gap_count:6,
293 phy_speed:2,
294 phy_delay:2,
295 contender:1,
296 power_class:3,
297 port0:2,
298 port1:2,
299 port2:2,
300 initiated_reset:1,
301 more_packets:1;
302 } p0;
303 struct {
304 u_int32_t
305 id:2,
306 phy_id:6,
307 sequel:1,
308 sequence_num:3,
310 porta:2,
311 portb:2,
312 portc:2,
313 portd:2,
314 porte:2,
315 portf:2,
316 portg:2,
317 porth:2,
319 more_packets:1;
320 } p1;
322 #else
323 union fw_self_id {
324 struct {
325 u_int32_t more_packets:1,
326 initiated_reset:1,
327 port2:2,
328 port1:2,
329 port0:2,
330 power_class:3,
331 contender:1,
332 phy_delay:2,
333 phy_speed:2,
334 gap_count:6,
335 link_active:1,
336 sequel:1,
337 phy_id:6,
338 id:2;
339 } p0;
340 struct {
341 u_int32_t more_packets:1,
342 reserved1:1,
343 porth:2,
344 portg:2,
345 portf:2,
346 porte:2,
347 portd:2,
348 portc:2,
349 portb:2,
350 porta:2,
351 reserved2:2,
352 sequence_num:3,
353 sequel:1,
354 phy_id:6,
355 id:2;
356 } p1;
358 #endif
361 struct fw_topology_map {
362 u_int32_t crc:16,
363 crc_len:16;
364 u_int32_t generation;
365 u_int32_t self_id_count:16,
366 node_count:16;
367 union fw_self_id self_id[4*64];
370 struct fw_speed_map {
371 u_int32_t crc:16,
372 crc_len:16;
373 u_int32_t generation;
374 u_int8_t speed[64][64];
377 struct fw_crom_buf {
378 struct fw_eui64 eui;
379 int len;
380 void *ptr;
384 * FireWire specific system requests.
386 #define FW_SSTBUF _IOWR('S', 86, struct fw_isobufreq)
387 #define FW_GSTBUF _IOWR('S', 87, struct fw_isobufreq)
388 #define FW_SRSTREAM _IOWR('S', 88, struct fw_isochreq)
389 #define FW_GRSTREAM _IOWR('S', 89, struct fw_isochreq)
390 #define FW_STSTREAM _IOWR('S', 90, struct fw_isochreq)
391 #define FW_GTSTREAM _IOWR('S', 91, struct fw_isochreq)
393 #define FW_ASYREQ _IOWR('S', 92, struct fw_asyreq)
394 #define FW_IBUSRST _IOR('S', 1, unsigned int)
395 #define FW_GDEVLST _IOWR('S', 2, struct fw_devlstreq)
396 #define FW_SBINDADDR _IOWR('S', 3, struct fw_asybindreq)
397 #define FW_CBINDADDR _IOWR('S', 4, struct fw_asybindreq)
398 #define FW_GTPMAP _IOR('S', 5, struct fw_topology_map)
399 #define FW_GCROM _IOWR('S', 7, struct fw_crom_buf)
401 #define FW_SDEUI64 _IOW('S', 20, struct fw_eui64)
402 #define FW_GDEUI64 _IOR('S', 21, struct fw_eui64)
404 #define FWOHCI_RDREG _IOWR('S', 80, struct fw_reg_req_t)
405 #define FWOHCI_WRREG _IOWR('S', 81, struct fw_reg_req_t)
406 #define FWOHCI_RDPHYREG _IOWR('S', 82, struct fw_reg_req_t)
407 #define FWOHCI_WRPHYREG _IOWR('S', 83, struct fw_reg_req_t)
409 #define DUMPDMA _IOWR('S', 82, u_int32_t)
411 #ifdef _KERNEL
413 #define FWMAXNDMA 0x100 /* 8 bits DMA channel id. in device No. */
415 #define unit2minor(x) (((x) & 0xff) | (((x) << 8) & ~0xffff))
417 #define MAKEMINOR(f, u, s) \
418 unit2minor((f) | (((u) & 0xff) << 8) | (s & 0xff))
419 #define DEV2UNIT(x) ((dev2unit(x) & 0xff00) >> 8)
420 #define DEV2SUB(x) (dev2unit(x) & 0xff)
422 #define FW_UNITMASK MAKEMINOR(0, -1, 0)
423 #define FW_UNIT(unit) MAKEMINOR(0, unit, 0)
425 #define FWMEM_FLAG 0x10000
426 #define DEV_FWMEM(x) (dev2unit(x) & FWMEM_FLAG)
427 #endif
428 #endif