sys/dev/video/meteor/meteor_reg.h

   1 /*
   2  * Copyright (c) 1995 Mark Tinguely and Jim Lowe
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  * 3. All advertising materials mentioning features or use of this software
  14  *    must display the following acknowledgement:
  15  *      This product includes software developed by Mark Tinguely and Jim Lowe
  16  * 4. The name of the author may not be used to endorse or promote products
  17  *    derived from this software without specific prior written permission.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  20  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  21  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  22  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  23  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  24  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  25  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  27  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
  28  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29  * POSSIBILITY OF SUCH DAMAGE.
  30  *
  31  * $FreeBSD: src/sys/pci/meteor_reg.h,v 1.5.2.1 2000/08/03 01:09:11 peter Exp $
  32  * $DragonFly: src/sys/dev/video/meteor/meteor_reg.h,v 1.2 2003/06/17 04:28:57 dillon Exp $
  33  */
  34 #ifndef PCI_LATENCY_TIMER
  35 #define PCI_LATENCY_TIMER               0x0c    /* pci timer register */
  36 #endif
  37
  38 /*
  39  * Definitions for the Philips SAA7116 digital video to pci interface.
  40  */
  41 #define SAA7116_PHILIPS_ID                      0x12238086ul
  42 #define SAA7116_I2C_WRITE                       0x00
  43 #define SAA7116_I2C_READ                        0x01
  44 #define SAA7116_IIC_NEW_CYCLE                   0x1000000L
  45 #define SAA7116_IIC_DIRECT_TRANSFER_ABORTED     0x0000200L
  46
  47 typedef volatile u_int  mreg_t;
  48 struct saa7116_regs {
  49         mreg_t  dma1e;          /* Base address for even field dma chn 1 */
  50         mreg_t  dma2e;          /* Base address for even field dma chn 2 */
  51         mreg_t  dma3e;          /* Base address for even field dma chn 3 */
  52         mreg_t  dma1o;          /* Base address for odd field dma chn 1 */
  53         mreg_t  dma2o;          /* Base address for odd field dma chn 2 */
  54         mreg_t  dma3o;          /* Base address for odd field dma chn 3 */
  55         mreg_t  stride1e;       /* Address stride for even field dma chn 1 */
  56         mreg_t  stride2e;       /* Address stride for even field dma chn 2 */
  57         mreg_t  stride3e;       /* Address stride for even field dma chn 3 */
  58         mreg_t  stride1o;       /* Address stride for odd field dma chn 1 */
  59         mreg_t  stride2o;       /* Address stride for odd field dma chn 2 */
  60         mreg_t  stride3o;       /* Address stride for odd field dma chn 3 */
  61         mreg_t  routee;         /* Route/mode even */
  62         mreg_t  routeo;         /* Route/mode odd */
  63         mreg_t  fifo_t;         /* FIFO trigger for PCI int */
  64         mreg_t  field_t;        /* Field toggle */
  65         mreg_t  cap_cntl;       /* Capture control */
  66         mreg_t  retry_wait_cnt; /* Clks for master to wait after disconnect */
  67         mreg_t  irq_stat;       /* IRQ mask and status reg */
  68         mreg_t  fme;            /* Field Mask even */
  69         mreg_t  fmo;            /* Field mask odd */
  70         mreg_t  fml;            /* Field mask length */
  71         mreg_t  fifo_t_err;     /* FIFO almost empty/almost full ptrs */
  72         mreg_t  i2c_phase;      /* i2c phase register */
  73         mreg_t  i2c_read;       /* i2c read register */
  74         mreg_t  i2c_write;      /* i2c write register */
  75         mreg_t  i2c_auto_a_e;   /* i2c auto register a, even */
  76         mreg_t  i2c_auto_b_e;   /* i2c auto register b, even */
  77         mreg_t  i2c_auto_c_e;   /* i2c auto register c, even */
  78         mreg_t  i2c_auto_d_e;   /* i2c auto register d, even */
  79         mreg_t  i2c_auto_a_o;   /* i2c auto register a, odd */
  80         mreg_t  i2c_auto_b_o;   /* i2c auto register b, odd */
  81         mreg_t  i2c_auto_c_o;   /* i2c auto register c, odd */
  82         mreg_t  i2c_auto_d_o;   /* i2c auto register d, odd */
  83         mreg_t  i2c_auto_enable;/* enable above auto registers */
  84         mreg_t  dma_end_e;      /* DMA end even (range) */
  85         mreg_t  dma_end_o;      /* DMA end odd (range) */
  86 };
  87
  88
  89 /*
  90  * Definitions for the Philips SAA7196 digital video decoder,
  91  * scalar, and clock generator circuit (DESCpro).
  92  */
  93 #define NUM_SAA7196_I2C_REGS    49
  94 #define SAA7196_I2C_ADDR        0x40
  95 #define SAA7196_WRITE(mtr, reg, data) \
  96         i2c_write(mtr, SAA7196_I2C_ADDR, SAA7116_I2C_WRITE, reg, data), \
  97         mtr->saa7196_i2c[reg] = data
  98 #define SAA7196_REG(mtr, reg) mtr->saa7196_i2c[reg]
  99 #define SAA7196_READ(mtr) \
 100         i2c_write(mtr, SAA7196_I2C_ADDR, SAA7116_I2C_READ, 0x0, 0x0)
 101
 102 #define SAA7196_IDEL    0x00    /* Increment delay */
 103 #define SAA7196_HSB5    0x01    /* H-sync begin; 50 hz */
 104 #define SAA7196_HSS5    0x02    /* H-sync stop; 50 hz */
 105 #define SAA7196_HCB5    0x03    /* H-clamp begin; 50 hz */
 106 #define SAA7196_HCS5    0x04    /* H-clamp stop; 50 hz */
 107 #define SAA7196_HSP5    0x05    /* H-sync after PHI1; 50 hz */
 108 #define SAA7196_LUMC    0x06    /* Luminance control */
 109 #define SAA7196_HUEC    0x07    /* Hue control */
 110 #define SAA7196_CKTQ    0x08    /* Colour Killer Threshold QAM (PAL, NTSC) */
 111 #define SAA7196_CKTS    0x09    /* Colour Killer Threshold SECAM */
 112 #define SAA7196_PALS    0x0a    /* PAL switch sensitivity */
 113 #define SAA7196_SECAMS  0x0b    /* SECAM switch sensitivity */
 114 #define SAA7196_CGAINC  0x0c    /* Chroma gain control */
 115 #define SAA7196_STDC    0x0d    /* Standard/Mode control */
 116 #define SAA7196_IOCC    0x0e    /* I/O and Clock Control */
 117 #define SAA7196_CTRL1   0x0f    /* Control #1 */
 118 #define SAA7196_CTRL2   0x10    /* Control #2 */
 119 #define SAA7196_CGAINR  0x11    /* Chroma Gain Reference */
 120 #define SAA7196_CSAT    0x12    /* Chroma Saturation */
 121 #define SAA7196_CONT    0x13    /* Luminance Contrast */
 122 #define SAA7196_HSB6    0x14    /* H-sync begin; 60 hz */
 123 #define SAA7196_HSS6    0x15    /* H-sync stop; 60 hz */
 124 #define SAA7196_HCB6    0x16    /* H-clamp begin; 60 hz */
 125 #define SAA7196_HCS6    0x17    /* H-clamp stop; 60 hz */
 126 #define SAA7196_HSP6    0x18    /* H-sync after PHI1; 60 hz */
 127 #define SAA7196_BRIG    0x19    /* Luminance Brightness */
 128 #define SAA7196_FMTS    0x20    /* Formats and sequence */
 129 #define SAA7196_OUTPIX  0x21    /* Output data pixel/line */
 130 #define SAA7196_INPIX   0x22    /* Input data pixel/line */
 131 #define SAA7196_HWS     0x23    /* Horiz. window start */
 132 #define SAA7196_HFILT   0x24    /* Horiz. filter */
 133 #define SAA7196_OUTLINE 0x25    /* Output data lines/field */
 134 #define SAA7196_INLINE  0x26    /* Input data lines/field */
 135 #define SAA7196_VWS     0x27    /* Vertical window start */
 136 #define SAA7196_VYP     0x28    /* AFS/vertical Y processing */
 137 #define SAA7196_VBS     0x29    /* Vertical Bypass start */
 138 #define SAA7196_VBCNT   0x2a    /* Vertical Bypass count */
 139 #define SAA7196_VBP     0x2b    /* veritcal Bypass Polarity */
 140 #define SAA7196_VLOW    0x2c    /* Colour-keying lower V limit */
 141 #define SAA7196_VHIGH   0x2d    /* Colour-keying upper V limit */
 142 #define SAA7196_ULOW    0x2e    /* Colour-keying lower U limit */
 143 #define SAA7196_UHIGH   0x2f    /* Colour-keying upper U limit */
 144 #define SAA7196_DPATH   0x30    /* Data path setting  */
 145
 146 /*
 147  * Defines for the PCF8574.
 148  */
 149 #define NUM_PCF8574_I2C_REGS    2
 150 #define PCF8574_CTRL_I2C_ADDR   0x70
 151 #define PCF8574_DATA_I2C_ADDR   0x72
 152 #define PCF8574_CTRL_WRITE(mtr, data) \
 153         i2c_write(mtr,  PCF8574_CTRL_I2C_ADDR, SAA7116_I2C_WRITE, data, data), \
 154         mtr->pcf_i2c[0] = data
 155 #define PCF8574_DATA_WRITE(mtr, data) \
 156         i2c_write(mtr,  PCF8574_DATA_I2C_ADDR, SAA7116_I2C_WRITE, data, data), \
 157         mtr->pcf_i2c[1] = data
 158 #define PCF8574_CTRL_REG(mtr) mtr->pcf_i2c[0]
 159 #define PCF8574_DATA_REG(mtr) mtr->pcf_i2c[1]
 160
 161
 162 /*
 163  * Defines for the BT254.
 164  */
 165 #define NUM_BT254_REGS  7
 166
 167 #define BT254_COMMAND   0
 168 #define BT254_IOUT1     1
 169 #define BT254_IOUT2     2
 170 #define BT254_IOUT3     3
 171 #define BT254_IOUT4     4
 172 #define BT254_IOUT5     5
 173 #define BT254_IOUT6     6
 174
 175 /*
 176  * Meteor info structure, one per meteor card installed.
 177  */
 178 typedef struct meteor_softc {
 179     struct saa7116_regs *base;  /* saa7116 register virtual address */
 180     vm_offset_t phys_base;      /* saa7116 register physical address */
 181     pcici_t     tag;            /* PCI tag, for doing PCI commands */
 182     vm_offset_t bigbuf;         /* buffer that holds the captured image */
 183     int         alloc_pages;    /* number of pages in bigbuf */
 184     struct proc *proc;          /* process to receive raised signal */
 185     int         signal;         /* signal to send to process */
 186 #define METEOR_SIG_MODE_MASK    0xffff0000
 187 #define METEOR_SIG_FIELD_MODE   0x00010000
 188 #define METEOR_SIG_FRAME_MODE   0x00000000
 189     struct meteor_mem *mem;     /* used to control sync. multi-frame output */
 190     u_long      synch_wait;     /* wait for free buffer before continuing */
 191     short       current;        /* frame number in buffer (1-frames) */
 192     short       rows;           /* number of rows in a frame */
 193     short       cols;           /* number of columns in a frame */
 194     short       depth;          /* number of byte per pixel */
 195     short       frames;         /* number of frames allocated */
 196     int         frame_size;     /* number of bytes in a frame */
 197     u_long      fifo_errors;    /* number of fifo capture errors since open */
 198     u_long      dma_errors;     /* number of DMA capture errors since open */
 199     u_long      frames_captured;/* number of frames captured since open */
 200     u_long      even_fields_captured; /* number of even fields captured */
 201     u_long      odd_fields_captured; /* number of odd fields captured */
 202     u_long      range_enable;   /* enable range checking ?? */
 203     unsigned    flags;
 204 #define METEOR_INITALIZED       0x00000001
 205 #define METEOR_OPEN             0x00000002
 206 #define METEOR_MMAP             0x00000004
 207 #define METEOR_INTR             0x00000008
 208 #define METEOR_READ             0x00000010      /* XXX never gets referenced */
 209 #define METEOR_SINGLE           0x00000020      /* get single frame */
 210 #define METEOR_CONTIN           0x00000040      /* continuously get frames */
 211 #define METEOR_SYNCAP           0x00000080      /* synchronously get frames */
 212 #define METEOR_CAP_MASK         0x000000f0
 213 #define METEOR_NTSC             0x00000100
 214 #define METEOR_PAL              0x00000200
 215 #define METEOR_SECAM            0x00000400
 216 #define METEOR_AUTOMODE         0x00000800
 217 #define METEOR_FORM_MASK        0x00000f00
 218 #define METEOR_DEV0             0x00001000
 219 #define METEOR_DEV1             0x00002000
 220 #define METEOR_DEV2             0x00004000
 221 #define METEOR_DEV3             0x00008000
 222 #define METEOR_DEV_SVIDEO       0x00006000
 223 #define METEOR_DEV_RGB          0x0000a000
 224 #define METEOR_DEV_MASK         0x0000f000
 225 #define METEOR_RGB16            0x00010000
 226 #define METEOR_RGB24            0x00020000
 227 #define METEOR_YUV_PACKED       0x00040000
 228 #define METEOR_YUV_PLANAR       0x00080000
 229 #define METEOR_WANT_EVEN        0x00100000      /* want even frame */
 230 #define METEOR_WANT_ODD         0x00200000      /* want odd frame */
 231 #define METEOR_WANT_MASK        0x00300000
 232 #define METEOR_ONLY_EVEN_FIELDS 0x01000000
 233 #define METEOR_ONLY_ODD_FIELDS  0x02000000
 234 #define METEOR_ONLY_FIELDS_MASK 0x03000000
 235 #define METEOR_YUV_422          0x04000000
 236 #define METEOR_OUTPUT_FMT_MASK  0x040f0000
 237 #define METEOR_WANT_TS          0x08000000      /* time-stamp a frame */
 238 #define METEOR_RGB              0x20000000      /* meteor rgb unit */
 239 #define METEOR_FIELD_MODE       0x80000000
 240     u_char      saa7196_i2c[NUM_SAA7196_I2C_REGS]; /* saa7196 register values */
 241     u_char      pcf_i2c[NUM_PCF8574_I2C_REGS];  /* PCF8574 register values */
 242     u_char      bt254_reg[NUM_BT254_REGS];      /* BT254 register values */
 243     u_short     fps;            /* frames per second */
 244 #ifdef METEOR_TEST_VIDEO
 245     struct meteor_video video;
 246 #endif
 247 } meteor_reg_t;