?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Merge commit 'crater/master'
[dragonfly.git] / sys / dev / drm / i915_dma.c
blob8d321d4b613c6ebf1eabc31ff35131b72906651d
1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
2 */
3 /*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29 #include "dev/drm/drmP.h"
30 #include "dev/drm/drm.h"
31 #include "dev/drm/i915_drm.h"
32 #include "dev/drm/i915_drv.h"
33
34 /* Really want an OS-independent resettable timer. Would like to have
35 * this loop run for (eg) 3 sec, but have the timer reset every time
36 * the head pointer changes, so that EBUSY only happens if the ring
37 * actually stalls for (eg) 3 seconds.
38 */
39 int i915_wait_ring(struct drm_device * dev, int n, const char *caller)
40 {
41 drm_i915_private_t *dev_priv = dev->dev_private;
42 drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
43 u32 last_head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
44 u32 acthd_reg = IS_I965G(dev) ? ACTHD_I965 : ACTHD;
45 u32 last_acthd = I915_READ(acthd_reg);
46 u32 acthd;
47 int i;
48
49 for (i = 0; i < 100000; i++) {
50 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
51 acthd = I915_READ(acthd_reg);
52 ring->space = ring->head - (ring->tail + 8);
53 if (ring->space < 0)
54 ring->space += ring->Size;
55 if (ring->space >= n)
56 return 0;
57
58 if (dev_priv->sarea_priv)
59 dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
60
61 if (ring->head != last_head)
62 i = 0;
63
64 if (acthd != last_acthd)
65 i = 0;
66
67 last_head = ring->head;
68 last_acthd = acthd;
69 DRM_UDELAY(10 * 1000);
70 }
71
72 return -EBUSY;
73 }
74
75 /**
76 * Sets up the hardware status page for devices that need a physical address
77 * in the register.
78 */
79 static int i915_init_phys_hws(struct drm_device *dev)
80 {
81 drm_i915_private_t *dev_priv = dev->dev_private;
82
83 /* Program Hardware Status Page */
84 DRM_UNLOCK();
85 dev_priv->status_page_dmah =
86 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff);
87 DRM_LOCK();
88 if (!dev_priv->status_page_dmah) {
89 DRM_ERROR("Can not allocate hardware status page\n");
90 return -ENOMEM;
91 }
92 dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr;
93 dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
94
95 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
96
97 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
98 DRM_DEBUG("Enabled hardware status page\n");
99 return 0;
100 }
101
102 /**
103 * Frees the hardware status page, whether it's a physical address or a virtual
104 * address set up by the X Server.
105 */
106 static void i915_free_hws(struct drm_device *dev)
107 {
108 drm_i915_private_t *dev_priv = dev->dev_private;
109 if (dev_priv->status_page_dmah) {
110 drm_pci_free(dev, dev_priv->status_page_dmah);
111 dev_priv->status_page_dmah = NULL;
112 }
113
114 if (dev_priv->status_gfx_addr) {
115 dev_priv->status_gfx_addr = 0;
116 drm_core_ioremapfree(&dev_priv->hws_map, dev);
117 }
118
119 /* Need to rewrite hardware status page */
120 I915_WRITE(HWS_PGA, 0x1ffff000);
121 }
122
123 void i915_kernel_lost_context(struct drm_device * dev)
124 {
125 drm_i915_private_t *dev_priv = dev->dev_private;
126 drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
127
128 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
129 ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
130 ring->space = ring->head - (ring->tail + 8);
131 if (ring->space < 0)
132 ring->space += ring->Size;
133
134 if (ring->head == ring->tail && dev_priv->sarea_priv)
135 dev_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
136 }
137
138 static int i915_dma_cleanup(struct drm_device * dev)
139 {
140 drm_i915_private_t *dev_priv = dev->dev_private;
141 /* Make sure interrupts are disabled here because the uninstall ioctl
142 * may not have been called from userspace and after dev_private
143 * is freed, it's too late.
144 */
145 if (dev->irq_enabled)
146 drm_irq_uninstall(dev);
147
148 if (dev_priv->ring.virtual_start) {
149 drm_core_ioremapfree(&dev_priv->ring.map, dev);
150 dev_priv->ring.virtual_start = NULL;
151 dev_priv->ring.map.handle = NULL;
152 dev_priv->ring.map.size = 0;
153 }
154
155 /* Clear the HWS virtual address at teardown */
156 if (I915_NEED_GFX_HWS(dev))
157 i915_free_hws(dev);
158
159 return 0;
160 }
161
162 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
163 {
164 drm_i915_private_t *dev_priv = dev->dev_private;
165
166 dev_priv->sarea = drm_getsarea(dev);
167 if (!dev_priv->sarea) {
168 DRM_ERROR("can not find sarea!\n");
169 i915_dma_cleanup(dev);
170 return -EINVAL;
171 }
172
173 dev_priv->sarea_priv = (drm_i915_sarea_t *)
174 ((u8 *) dev_priv->sarea->handle + init->sarea_priv_offset);
175
176 if (init->ring_size != 0) {
177 if (dev_priv->ring.ring_obj != NULL) {
178 i915_dma_cleanup(dev);
179 DRM_ERROR("Client tried to initialize ringbuffer in "
180 "GEM mode\n");
181 return -EINVAL;
182 }
183
184 dev_priv->ring.Size = init->ring_size;
185 dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
186
187 dev_priv->ring.map.offset = init->ring_start;
188 dev_priv->ring.map.size = init->ring_size;
189 dev_priv->ring.map.type = 0;
190 dev_priv->ring.map.flags = 0;
191 dev_priv->ring.map.mtrr = 0;
192
193 drm_core_ioremap_wc(&dev_priv->ring.map, dev);
194
195 if (dev_priv->ring.map.handle == NULL) {
196 i915_dma_cleanup(dev);
197 DRM_ERROR("can not ioremap virtual address for"
198 " ring buffer\n");
199 return -ENOMEM;
200 }
201 }
202
203 dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
204
205 dev_priv->cpp = init->cpp;
206 dev_priv->back_offset = init->back_offset;
207 dev_priv->front_offset = init->front_offset;
208 dev_priv->current_page = 0;
209 dev_priv->sarea_priv->pf_current_page = 0;
210
211 /* Allow hardware batchbuffers unless told otherwise.
212 */
213 dev_priv->allow_batchbuffer = 1;
214
215 return 0;
216 }
217
218 static int i915_dma_resume(struct drm_device * dev)
219 {
220 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
221
222 DRM_DEBUG("\n");
223
224 if (!dev_priv->sarea) {
225 DRM_ERROR("can not find sarea!\n");
226 return -EINVAL;
227 }
228
229 if (dev_priv->ring.map.handle == NULL) {
230 DRM_ERROR("can not ioremap virtual address for"
231 " ring buffer\n");
232 return -ENOMEM;
233 }
234
235 /* Program Hardware Status Page */
236 if (!dev_priv->hw_status_page) {
237 DRM_ERROR("Can not find hardware status page\n");
238 return -EINVAL;
239 }
240 DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
241
242 if (dev_priv->status_gfx_addr != 0)
243 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
244 else
245 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
246 DRM_DEBUG("Enabled hardware status page\n");
247
248 return 0;
249 }
250
251 static int i915_dma_init(struct drm_device *dev, void *data,
252 struct drm_file *file_priv)
253 {
254 drm_i915_init_t *init = data;
255 int retcode = 0;
256
257 switch (init->func) {
258 case I915_INIT_DMA:
259 retcode = i915_initialize(dev, init);
260 break;
261 case I915_CLEANUP_DMA:
262 retcode = i915_dma_cleanup(dev);
263 break;
264 case I915_RESUME_DMA:
265 retcode = i915_dma_resume(dev);
266 break;
267 default:
268 retcode = -EINVAL;
269 break;
270 }
271
272 return retcode;
273 }
274
275 /* Implement basically the same security restrictions as hardware does
276 * for MI_BATCH_NON_SECURE. These can be made stricter at any time.
277 *
278 * Most of the calculations below involve calculating the size of a
279 * particular instruction. It's important to get the size right as
280 * that tells us where the next instruction to check is. Any illegal
281 * instruction detected will be given a size of zero, which is a
282 * signal to abort the rest of the buffer.
283 */
284 static int do_validate_cmd(int cmd)
285 {
286 switch (((cmd >> 29) & 0x7)) {
287 case 0x0:
288 switch ((cmd >> 23) & 0x3f) {
289 case 0x0:
290 return 1; /* MI_NOOP */
291 case 0x4:
292 return 1; /* MI_FLUSH */
293 default:
294 return 0; /* disallow everything else */
295 }
296 break;
297 case 0x1:
298 return 0; /* reserved */
299 case 0x2:
300 return (cmd & 0xff) + 2; /* 2d commands */
301 case 0x3:
302 if (((cmd >> 24) & 0x1f) <= 0x18)
303 return 1;
304
305 switch ((cmd >> 24) & 0x1f) {
306 case 0x1c:
307 return 1;
308 case 0x1d:
309 switch ((cmd >> 16) & 0xff) {
310 case 0x3:
311 return (cmd & 0x1f) + 2;
312 case 0x4:
313 return (cmd & 0xf) + 2;
314 default:
315 return (cmd & 0xffff) + 2;
316 }
317 case 0x1e:
318 if (cmd & (1 << 23))
319 return (cmd & 0xffff) + 1;
320 else
321 return 1;
322 case 0x1f:
323 if ((cmd & (1 << 23)) == 0) /* inline vertices */
324 return (cmd & 0x1ffff) + 2;
325 else if (cmd & (1 << 17)) /* indirect random */
326 if ((cmd & 0xffff) == 0)
327 return 0; /* unknown length, too hard */
328 else
329 return (((cmd & 0xffff) + 1) / 2) + 1;
330 else
331 return 2; /* indirect sequential */
332 default:
333 return 0;
334 }
335 default:
336 return 0;
337 }
338
339 return 0;
340 }
341
342 static int validate_cmd(int cmd)
343 {
344 int ret = do_validate_cmd(cmd);
345
346 /* printk("validate_cmd( %x ): %d\n", cmd, ret); */
347
348 return ret;
349 }
350
351 static int i915_emit_cmds(struct drm_device *dev, int __user *buffer,
352 int dwords)
353 {
354 drm_i915_private_t *dev_priv = dev->dev_private;
355 int i;
356 RING_LOCALS;
357
358 if ((dwords+1) * sizeof(int) >= dev_priv->ring.Size - 8)
359 return -EINVAL;
360
361 BEGIN_LP_RING((dwords+1)&~1);
362
363 for (i = 0; i < dwords;) {
364 int cmd, sz;
365
366 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd)))
367 return -EINVAL;
368
369 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
370 return -EINVAL;
371
372 OUT_RING(cmd);
373
374 while (++i, --sz) {
375 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i],
376 sizeof(cmd))) {
377 return -EINVAL;
378 }
379 OUT_RING(cmd);
380 }
381 }
382
383 if (dwords & 1)
384 OUT_RING(0);
385
386 ADVANCE_LP_RING();
387
388 return 0;
389 }
390
391 int i915_emit_box(struct drm_device * dev,
392 struct drm_clip_rect __user * boxes,
393 int i, int DR1, int DR4)
394 {
395 drm_i915_private_t *dev_priv = dev->dev_private;
396 struct drm_clip_rect box;
397 RING_LOCALS;
398
399 if (DRM_COPY_FROM_USER_UNCHECKED(&box, &boxes[i], sizeof(box))) {
400 return -EFAULT;
401 }
402
403 if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
404 DRM_ERROR("Bad box %d,%d..%d,%d\n",
405 box.x1, box.y1, box.x2, box.y2);
406 return -EINVAL;
407 }
408
409 if (IS_I965G(dev)) {
410 BEGIN_LP_RING(4);
411 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
412 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
413 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
414 OUT_RING(DR4);
415 ADVANCE_LP_RING();
416 } else {
417 BEGIN_LP_RING(6);
418 OUT_RING(GFX_OP_DRAWRECT_INFO);
419 OUT_RING(DR1);
420 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
421 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
422 OUT_RING(DR4);
423 OUT_RING(0);
424 ADVANCE_LP_RING();
425 }
426
427 return 0;
428 }
429
430 /* XXX: Emitting the counter should really be moved to part of the IRQ
431 * emit. For now, do it in both places:
432 */
433
434 static void i915_emit_breadcrumb(struct drm_device *dev)
435 {
436 drm_i915_private_t *dev_priv = dev->dev_private;
437 RING_LOCALS;
438
439 if (++dev_priv->counter > 0x7FFFFFFFUL)
440 dev_priv->counter = 0;
441 if (dev_priv->sarea_priv)
442 dev_priv->sarea_priv->last_enqueue = dev_priv->counter;
443
444 BEGIN_LP_RING(4);
445 OUT_RING(MI_STORE_DWORD_INDEX);
446 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
447 OUT_RING(dev_priv->counter);
448 OUT_RING(0);
449 ADVANCE_LP_RING();
450 }
451
452 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
453 drm_i915_cmdbuffer_t * cmd)
454 {
455 int nbox = cmd->num_cliprects;
456 int i = 0, count, ret;
457
458 if (cmd->sz & 0x3) {
459 DRM_ERROR("alignment\n");
460 return -EINVAL;
461 }
462
463 i915_kernel_lost_context(dev);
464
465 count = nbox ? nbox : 1;
466
467 for (i = 0; i < count; i++) {
468 if (i < nbox) {
469 ret = i915_emit_box(dev, cmd->cliprects, i,
470 cmd->DR1, cmd->DR4);
471 if (ret)
472 return ret;
473 }
474
475 ret = i915_emit_cmds(dev, (int __user *)cmd->buf, cmd->sz / 4);
476 if (ret)
477 return ret;
478 }
479
480 i915_emit_breadcrumb(dev);
481 return 0;
482 }
483
484 static int i915_dispatch_batchbuffer(struct drm_device * dev,
485 drm_i915_batchbuffer_t * batch)
486 {
487 drm_i915_private_t *dev_priv = dev->dev_private;
488 struct drm_clip_rect __user *boxes = batch->cliprects;
489 int nbox = batch->num_cliprects;
490 int i = 0, count;
491 RING_LOCALS;
492
493 if ((batch->start | batch->used) & 0x7) {
494 DRM_ERROR("alignment\n");
495 return -EINVAL;
496 }
497
498 i915_kernel_lost_context(dev);
499
500 count = nbox ? nbox : 1;
501
502 for (i = 0; i < count; i++) {
503 if (i < nbox) {
504 int ret = i915_emit_box(dev, boxes, i,
505 batch->DR1, batch->DR4);
506 if (ret)
507 return ret;
508 }
509
510 if (!IS_I830(dev) && !IS_845G(dev)) {
511 BEGIN_LP_RING(2);
512 if (IS_I965G(dev)) {
513 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
514 OUT_RING(batch->start);
515 } else {
516 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
517 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
518 }
519 ADVANCE_LP_RING();
520 } else {
521 BEGIN_LP_RING(4);
522 OUT_RING(MI_BATCH_BUFFER);
523 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
524 OUT_RING(batch->start + batch->used - 4);
525 OUT_RING(0);
526 ADVANCE_LP_RING();
527 }
528 }
529
530 i915_emit_breadcrumb(dev);
531
532 return 0;
533 }
534
535 static int i915_dispatch_flip(struct drm_device * dev)
536 {
537 drm_i915_private_t *dev_priv = dev->dev_private;
538 RING_LOCALS;
539
540 if (!dev_priv->sarea_priv)
541 return -EINVAL;
542
543 DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n",
544 __func__,
545 dev_priv->current_page,
546 dev_priv->sarea_priv->pf_current_page);
547
548 i915_kernel_lost_context(dev);
549
550 BEGIN_LP_RING(2);
551 OUT_RING(MI_FLUSH | MI_READ_FLUSH);
552 OUT_RING(0);
553 ADVANCE_LP_RING();
554
555 BEGIN_LP_RING(6);
556 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
557 OUT_RING(0);
558 if (dev_priv->current_page == 0) {
559 OUT_RING(dev_priv->back_offset);
560 dev_priv->current_page = 1;
561 } else {
562 OUT_RING(dev_priv->front_offset);
563 dev_priv->current_page = 0;
564 }
565 OUT_RING(0);
566 ADVANCE_LP_RING();
567
568 BEGIN_LP_RING(2);
569 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
570 OUT_RING(0);
571 ADVANCE_LP_RING();
572
573 if (++dev_priv->counter > 0x7FFFFFFFUL)
574 dev_priv->counter = 0;
575 if (dev_priv->sarea_priv)
576 dev_priv->sarea_priv->last_enqueue = dev_priv->counter;
577
578 BEGIN_LP_RING(4);
579 OUT_RING(MI_STORE_DWORD_INDEX);
580 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
581 OUT_RING(dev_priv->counter);
582 OUT_RING(0);
583 ADVANCE_LP_RING();
584
585 dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
586 return 0;
587 }
588
589 static int i915_quiescent(struct drm_device * dev)
590 {
591 drm_i915_private_t *dev_priv = dev->dev_private;
592
593 i915_kernel_lost_context(dev);
594 return i915_wait_ring(dev, dev_priv->ring.Size - 8, __func__);
595 }
596
597 static int i915_flush_ioctl(struct drm_device *dev, void *data,
598 struct drm_file *file_priv)
599 {
600 int ret;
601
602 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
603
604 ret = i915_quiescent(dev);
605
606 return ret;
607 }
608
609 static int i915_batchbuffer(struct drm_device *dev, void *data,
610 struct drm_file *file_priv)
611 {
612 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
613 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
614 dev_priv->sarea_priv;
615 drm_i915_batchbuffer_t *batch = data;
616 size_t cliplen;
617 int ret;
618
619 if (!dev_priv->allow_batchbuffer) {
620 DRM_ERROR("Batchbuffer ioctl disabled\n");
621 return -EINVAL;
622 }
623
624 DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n",
625 batch->start, batch->used, batch->num_cliprects);
626
627 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
628
629 DRM_UNLOCK();
630 cliplen = batch->num_cliprects * sizeof(struct drm_clip_rect);
631 if (batch->num_cliprects && DRM_VERIFYAREA_READ(batch->cliprects,
632 cliplen)) {
633 DRM_LOCK();
634 return -EFAULT;
635 }
636 if (batch->num_cliprects) {
637 vslock((caddr_t)batch->cliprects, cliplen);
638 }
639
640 ret = i915_dispatch_batchbuffer(dev, batch);
641
642 if (batch->num_cliprects)
643 vsunlock((caddr_t)batch->cliprects, cliplen);
644
645 if (sarea_priv)
646 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
647
648 return ret;
649 }
650
651 static int i915_cmdbuffer(struct drm_device *dev, void *data,
652 struct drm_file *file_priv)
653 {
654 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
655 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
656 dev_priv->sarea_priv;
657 drm_i915_cmdbuffer_t *cmdbuf = data;
658 size_t cliplen;
659 int ret;
660
661 DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
662 cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
663
664 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
665
666 DRM_UNLOCK();
667 cliplen = cmdbuf->num_cliprects * sizeof(struct drm_clip_rect);
668 if (cmdbuf->num_cliprects && DRM_VERIFYAREA_READ(cmdbuf->cliprects,
669 cliplen)) {
670 DRM_ERROR("Fault accessing cliprects\n");
671 DRM_LOCK();
672 return -EFAULT;
673 }
674 if (cmdbuf->num_cliprects) {
675 vslock((caddr_t)cmdbuf->cliprects, cliplen);
676 vslock((caddr_t)cmdbuf->buf, cmdbuf->sz);
677 }
678
679 ret = i915_dispatch_cmdbuffer(dev, cmdbuf);
680
681 if (cmdbuf->num_cliprects) {
682 vsunlock((caddr_t)cmdbuf->buf, cmdbuf->sz);
683 vsunlock((caddr_t)cmdbuf->cliprects, cliplen);
684 }
685 DRM_LOCK();
686 if (ret) {
687 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
688 return ret;
689 }
690
691 if (sarea_priv)
692 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
693 return 0;
694 }
695
696 static int i915_flip_bufs(struct drm_device *dev, void *data,
697 struct drm_file *file_priv)
698 {
699 int ret;
700
701 DRM_DEBUG("%s\n", __func__);
702
703 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
704
705 ret = i915_dispatch_flip(dev);
706
707 return ret;
708 }
709
710 static int i915_getparam(struct drm_device *dev, void *data,
711 struct drm_file *file_priv)
712 {
713 drm_i915_private_t *dev_priv = dev->dev_private;
714 drm_i915_getparam_t *param = data;
715 int value;
716
717 if (!dev_priv) {
718 DRM_ERROR("called with no initialization\n");
719 return -EINVAL;
720 }
721
722 switch (param->param) {
723 case I915_PARAM_IRQ_ACTIVE:
724 value = dev->irq_enabled ? 1 : 0;
725 break;
726 case I915_PARAM_ALLOW_BATCHBUFFER:
727 value = dev_priv->allow_batchbuffer ? 1 : 0;
728 break;
729 case I915_PARAM_LAST_DISPATCH:
730 value = READ_BREADCRUMB(dev_priv);
731 break;
732 case I915_PARAM_CHIPSET_ID:
733 value = dev->pci_device;
734 break;
735 case I915_PARAM_HAS_GEM:
736 /* We need to reset this to 1 once we have GEM */
737 value = 0;
738 break;
739 default:
740 DRM_DEBUG("Unknown parameter %d\n", param->param);
741 return -EINVAL;
742 }
743
744 if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
745 DRM_ERROR("DRM_COPY_TO_USER failed\n");
746 return -EFAULT;
747 }
748
749 return 0;
750 }
751
752 static int i915_setparam(struct drm_device *dev, void *data,
753 struct drm_file *file_priv)
754 {
755 drm_i915_private_t *dev_priv = dev->dev_private;
756 drm_i915_setparam_t *param = data;
757
758 if (!dev_priv) {
759 DRM_ERROR("called with no initialization\n");
760 return -EINVAL;
761 }
762
763 switch (param->param) {
764 case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
765 break;
766 case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
767 dev_priv->tex_lru_log_granularity = param->value;
768 break;
769 case I915_SETPARAM_ALLOW_BATCHBUFFER:
770 dev_priv->allow_batchbuffer = param->value;
771 break;
772 default:
773 DRM_DEBUG("unknown parameter %d\n", param->param);
774 return -EINVAL;
775 }
776
777 return 0;
778 }
779
780 static int i915_set_status_page(struct drm_device *dev, void *data,
781 struct drm_file *file_priv)
782 {
783 drm_i915_private_t *dev_priv = dev->dev_private;
784 drm_i915_hws_addr_t *hws = data;
785
786 if (!I915_NEED_GFX_HWS(dev))
787 return -EINVAL;
788
789 if (!dev_priv) {
790 DRM_ERROR("called with no initialization\n");
791 return -EINVAL;
792 }
793
794 DRM_DEBUG("set status page addr 0x%08x\n", (u32)hws->addr);
795
796 dev_priv->status_gfx_addr = hws->addr & (0x1ffff<<12);
797
798 dev_priv->hws_map.offset = dev->agp->base + hws->addr;
799 dev_priv->hws_map.size = 4*1024;
800 dev_priv->hws_map.type = 0;
801 dev_priv->hws_map.flags = 0;
802 dev_priv->hws_map.mtrr = 0;
803
804 drm_core_ioremap_wc(&dev_priv->hws_map, dev);
805 if (dev_priv->hws_map.handle == NULL) {
806 i915_dma_cleanup(dev);
807 dev_priv->status_gfx_addr = 0;
808 DRM_ERROR("can not ioremap virtual address for"
809 " G33 hw status page\n");
810 return -ENOMEM;
811 }
812 dev_priv->hw_status_page = dev_priv->hws_map.handle;
813
814 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
815 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
816 DRM_DEBUG("load hws HWS_PGA with gfx mem 0x%x\n",
817 dev_priv->status_gfx_addr);
818 DRM_DEBUG("load hws at %p\n", dev_priv->hw_status_page);
819 return 0;
820 }
821
822 int i915_driver_load(struct drm_device *dev, unsigned long flags)
823 {
824 struct drm_i915_private *dev_priv = dev->dev_private;
825 unsigned long base, size;
826 int ret = 0, mmio_bar = IS_I9XX(dev) ? 0 : 1;
827
828 /* i915 has 4 more counters */
829 dev->counters += 4;
830 dev->types[6] = _DRM_STAT_IRQ;
831 dev->types[7] = _DRM_STAT_PRIMARY;
832 dev->types[8] = _DRM_STAT_SECONDARY;
833 dev->types[9] = _DRM_STAT_DMA;
834
835 dev_priv = drm_alloc(sizeof(drm_i915_private_t), DRM_MEM_DRIVER);
836 if (dev_priv == NULL)
837 return -ENOMEM;
838
839 memset(dev_priv, 0, sizeof(drm_i915_private_t));
840
841 dev->dev_private = (void *)dev_priv;
842 dev_priv->dev = dev;
843
844 /* Add register map (needed for suspend/resume) */
845 base = drm_get_resource_start(dev, mmio_bar);
846 size = drm_get_resource_len(dev, mmio_bar);
847
848 ret = drm_addmap(dev, base, size, _DRM_REGISTERS,
849 _DRM_KERNEL | _DRM_DRIVER, &dev_priv->mmio_map);
850
851 if (IS_G4X(dev)) {
852 dev->driver->get_vblank_counter = g45_get_vblank_counter;
853 dev->max_vblank_count = 0xffffffff; /* 32 bits of frame count */
854 } else {
855 dev->driver->get_vblank_counter = i915_get_vblank_counter;
856 dev->max_vblank_count = 0x00ffffff; /* 24 bits of frame count */
857 }
858
859 #ifdef I915_HAVE_GEM
860 i915_gem_load(dev);
861 #endif
862 /* Init HWS */
863 if (!I915_NEED_GFX_HWS(dev)) {
864 ret = i915_init_phys_hws(dev);
865 if (ret != 0) {
866 drm_rmmap(dev, dev_priv->mmio_map);
867 drm_free(dev_priv, sizeof(struct drm_i915_private),
868 DRM_MEM_DRIVER);
869 return ret;
870 }
871 }
872 #ifdef __linux__
873 /* On the 945G/GM, the chipset reports the MSI capability on the
874 * integrated graphics even though the support isn't actually there
875 * according to the published specs. It doesn't appear to function
876 * correctly in testing on 945G.
877 * This may be a side effect of MSI having been made available for PEG
878 * and the registers being closely associated.
879 *
880 * According to chipset errata, on the 965GM, MSI interrupts may
881 * be lost or delayed
882 */
883 if (!IS_I945G(dev) && !IS_I945GM(dev) && !IS_I965GM(dev))
884 if (pci_enable_msi(dev->pdev))
885 DRM_ERROR("failed to enable MSI\n");
886
887 intel_opregion_init(dev);
888 #endif
889 DRM_SPININIT(&dev_priv->user_irq_lock, "userirq");
890 dev_priv->user_irq_refcount = 0;
891
892 ret = drm_vblank_init(dev, I915_NUM_PIPE);
893
894 if (ret) {
895 (void) i915_driver_unload(dev);
896 return ret;
897 }
898
899 return ret;
900 }
901
902 int i915_driver_unload(struct drm_device *dev)
903 {
904 struct drm_i915_private *dev_priv = dev->dev_private;
905
906 i915_free_hws(dev);
907
908 drm_rmmap(dev, dev_priv->mmio_map);
909 #ifdef __linux__
910 intel_opregion_free(dev);
911 #endif
912 DRM_SPINUNINIT(&dev_priv->user_irq_lock);
913
914 drm_free(dev->dev_private, sizeof(drm_i915_private_t),
915 DRM_MEM_DRIVER);
916
917 return 0;
918 }
919
920 int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv)
921 {
922 struct drm_i915_file_private *i915_file_priv;
923
924 DRM_DEBUG("\n");
925 i915_file_priv = (struct drm_i915_file_private *)
926 drm_alloc(sizeof(*i915_file_priv), DRM_MEM_FILES);
927
928 if (!i915_file_priv)
929 return -ENOMEM;
930
931 file_priv->driver_priv = i915_file_priv;
932
933 i915_file_priv->mm.last_gem_seqno = 0;
934 i915_file_priv->mm.last_gem_throttle_seqno = 0;
935
936 return 0;
937 }
938
939 void i915_driver_lastclose(struct drm_device * dev)
940 {
941 drm_i915_private_t *dev_priv = dev->dev_private;
942
943 if (!dev_priv)
944 return;
945 #ifdef I915_HAVE_GEM
946 i915_gem_lastclose(dev);
947 #endif
948 if (dev_priv->agp_heap)
949 i915_mem_takedown(&(dev_priv->agp_heap));
950
951 i915_dma_cleanup(dev);
952 }
953
954 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
955 {
956 drm_i915_private_t *dev_priv = dev->dev_private;
957 i915_mem_release(dev, file_priv, dev_priv->agp_heap);
958 }
959
960 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file_priv)
961 {
962 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
963
964 drm_free(i915_file_priv, sizeof(*i915_file_priv), DRM_MEM_FILES);
965 }
966
967 struct drm_ioctl_desc i915_ioctls[] = {
968 DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
969 DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
970 DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH),
971 DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
972 DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
973 DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
974 DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH),
975 DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
976 DRM_IOCTL_DEF(DRM_I915_ALLOC, i915_mem_alloc, DRM_AUTH),
977 DRM_IOCTL_DEF(DRM_I915_FREE, i915_mem_free, DRM_AUTH),
978 DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
979 DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
980 DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP, i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
981 DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE, i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
982 DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH ),
983 DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
984 DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
985 #ifdef I915_HAVE_GEM
986 DRM_IOCTL_DEF(DRM_I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
987 DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
988 DRM_IOCTL_DEF(DRM_I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
989 DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
990 DRM_IOCTL_DEF(DRM_I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH),
991 DRM_IOCTL_DEF(DRM_I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH),
992 DRM_IOCTL_DEF(DRM_I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
993 DRM_IOCTL_DEF(DRM_I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
994 DRM_IOCTL_DEF(DRM_I915_GEM_CREATE, i915_gem_create_ioctl, 0),
995 DRM_IOCTL_DEF(DRM_I915_GEM_PREAD, i915_gem_pread_ioctl, 0),
996 DRM_IOCTL_DEF(DRM_I915_GEM_PWRITE, i915_gem_pwrite_ioctl, 0),
997 DRM_IOCTL_DEF(DRM_I915_GEM_MMAP, i915_gem_mmap_ioctl, 0),
998 DRM_IOCTL_DEF(DRM_I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, 0),
999 DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, 0),
1000 DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, 0),
1001 DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, 0),
1002 #endif
1003 };
1004
1005 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
1006
1007 /**
1008 * Determine if the device really is AGP or not.
1009 *
1010 * All Intel graphics chipsets are treated as AGP, even if they are really
1011 * PCI-e.
1012 *
1013 * \param dev The device to be tested.
1014 *
1015 * \returns
1016 * A value of 1 is always retured to indictate every i9x5 is AGP.
1017 */
1018 int i915_driver_device_is_agp(struct drm_device * dev)
1019 {
1020 return 1;
1021 }
DragonFly BSD