sys/dev/crypto/ubsec/ubsecreg.h

   1 /* $FreeBSD: src/sys/dev/ubsec/ubsecreg.h,v 1.2.2.4 2003/06/04 17:05:11 sam Exp $ */
   2 /* $DragonFly: src/sys/dev/crypto/ubsec/ubsecreg.h,v 1.2 2003/06/17 04:28:32 dillon Exp $ */
   3 /*      $OpenBSD: ubsecreg.h,v 1.27 2002/09/11 22:40:31 jason Exp $     */
   4
   5 /*
   6  * Copyright (c) 2000 Theo de Raadt
   7  * Copyright (c) 2001 Patrik Lindergren (patrik@ipunplugged.com)
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  *
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  * 3. The name of the author may not be used to endorse or promote products
  19  *    derived from this software without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  22  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  23  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  24  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  25  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  26  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  27  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  28  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  30  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  *
  32  * Effort sponsored in part by the Defense Advanced Research Projects
  33  * Agency (DARPA) and Air Force Research Laboratory, Air Force
  34  * Materiel Command, USAF, under agreement number F30602-01-2-0537.
  35  *
  36  */
  37
  38 /*
  39  * Register definitions for 5601 BlueSteel Networks Ubiquitous Broadband
  40  * Security "uBSec" chip.  Definitions from revision 2.8 of the product
  41  * datasheet.
  42  */
  43
  44 #define BS_BAR                  0x10    /* DMA base address register */
  45 #define BS_TRDY_TIMEOUT         0x40    /* TRDY timeout */
  46 #define BS_RETRY_TIMEOUT        0x41    /* DMA retry timeout */
  47
  48 #define PCI_VENDOR_BROADCOM     0x14e4          /* Broadcom */
  49 #define PCI_VENDOR_BLUESTEEL    0x15ab          /* Bluesteel Networks */
  50 #define PCI_VENDOR_SUN          0x108e          /* Sun Microsystems */
  51
  52 /* Bluesteel Networks */
  53 #define PCI_PRODUCT_BLUESTEEL_5501      0x0000          /* 5501 */
  54 #define PCI_PRODUCT_BLUESTEEL_5601      0x5601          /* 5601 */
  55
  56 /* Broadcom */
  57 #define PCI_PRODUCT_BROADCOM_BCM5700    0x1644          /* BCM5700 */
  58 #define PCI_PRODUCT_BROADCOM_BCM5701    0x1645          /* BCM5701 */
  59 #define PCI_PRODUCT_BROADCOM_5801       0x5801          /* 5801 */
  60 #define PCI_PRODUCT_BROADCOM_5802       0x5802          /* 5802 */
  61 #define PCI_PRODUCT_BROADCOM_5805       0x5805          /* 5805 */
  62 #define PCI_PRODUCT_BROADCOM_5820       0x5820          /* 5820 */
  63 #define PCI_PRODUCT_BROADCOM_5821       0x5821          /* 5821 */
  64 #define PCI_PRODUCT_BROADCOM_5822       0x5822          /* 5822 */
  65 #define PCI_PRODUCT_BROADCOM_5823       0x5823          /* 5823 */
  66
  67 /* Sun Microsystems */
  68 #define PCI_PRODUCT_SUN_5821            0x5454          /* Crypto 5821 */
  69 #define PCI_PRODUCT_SUN_SCA1K           0x5455          /* Crypto 1K */
  70
  71 #define UBS_PCI_RTY_SHIFT                       8
  72 #define UBS_PCI_RTY_MASK                        0xff
  73 #define UBS_PCI_RTY(misc) \
  74     (((misc) >> UBS_PCI_RTY_SHIFT) & UBS_PCI_RTY_MASK)
  75
  76 #define UBS_PCI_TOUT_SHIFT                      0
  77 #define UBS_PCI_TOUT_MASK                       0xff
  78 #define UBS_PCI_TOUT(misc) \
  79     (((misc) >> PCI_TOUT_SHIFT) & PCI_TOUT_MASK)
  80
  81 /*
  82  * DMA Control & Status Registers (offset from BS_BAR)
  83  */
  84 #define BS_MCR1         0x00    /* DMA Master Command Record 1 */
  85 #define BS_CTRL         0x04    /* DMA Control */
  86 #define BS_STAT         0x08    /* DMA Status */
  87 #define BS_ERR          0x0c    /* DMA Error Address */
  88 #define BS_MCR2         0x10    /* DMA Master Command Record 2 */
  89
  90 /* BS_CTRL - DMA Control */
  91 #define BS_CTRL_RESET           0x80000000      /* hardware reset, 5805/5820 */
  92 #define BS_CTRL_MCR2INT         0x40000000      /* enable intr MCR for MCR2 */
  93 #define BS_CTRL_MCR1INT         0x20000000      /* enable intr MCR for MCR1 */
  94 #define BS_CTRL_OFM             0x10000000      /* Output fragment mode */
  95 #define BS_CTRL_BE32            0x08000000      /* big-endian, 32bit bytes */
  96 #define BS_CTRL_BE64            0x04000000      /* big-endian, 64bit bytes */
  97 #define BS_CTRL_DMAERR          0x02000000      /* enable intr DMA error */
  98 #define BS_CTRL_RNG_M           0x01800000      /* RNG mode */
  99 #define BS_CTRL_RNG_1           0x00000000      /* 1bit rn/one slow clock */
 100 #define BS_CTRL_RNG_4           0x00800000      /* 1bit rn/four slow clocks */
 101 #define BS_CTRL_RNG_8           0x01000000      /* 1bit rn/eight slow clocks */
 102 #define BS_CTRL_RNG_16          0x01800000      /* 1bit rn/16 slow clocks */
 103 #define BS_CTRL_SWNORM          0x00400000      /* 582[01], sw normalization */
 104 #define BS_CTRL_FRAG_M          0x0000ffff      /* output fragment size mask */
 105 #define BS_CTRL_LITTLE_ENDIAN   (BS_CTRL_BE32 | BS_CTRL_BE64)
 106
 107 /* BS_STAT - DMA Status */
 108 #define BS_STAT_MCR1_BUSY       0x80000000      /* MCR1 is busy */
 109 #define BS_STAT_MCR1_FULL       0x40000000      /* MCR1 is full */
 110 #define BS_STAT_MCR1_DONE       0x20000000      /* MCR1 is done */
 111 #define BS_STAT_DMAERR          0x10000000      /* DMA error */
 112 #define BS_STAT_MCR2_FULL       0x08000000      /* MCR2 is full */
 113 #define BS_STAT_MCR2_DONE       0x04000000      /* MCR2 is done */
 114 #define BS_STAT_MCR1_ALLEMPTY   0x02000000      /* 5821, MCR1 is empty */
 115 #define BS_STAT_MCR2_ALLEMPTY   0x01000000      /* 5821, MCR2 is empty */
 116
 117 /* BS_ERR - DMA Error Address */
 118 #define BS_ERR_ADDR             0xfffffffc      /* error address mask */
 119 #define BS_ERR_READ             0x00000002      /* fault was on read */
 120
 121 struct ubsec_pktctx {
 122         u_int32_t       pc_deskey[6];           /* 3DES key */
 123         u_int32_t       pc_hminner[5];          /* hmac inner state */
 124         u_int32_t       pc_hmouter[5];          /* hmac outer state */
 125         u_int32_t       pc_iv[2];               /* [3]DES iv */
 126         u_int16_t       pc_flags;               /* flags, below */
 127         u_int16_t       pc_offset;              /* crypto offset */
 128 };
 129 #define UBS_PKTCTX_ENC_3DES     0x8000          /* use 3des */
 130 #define UBS_PKTCTX_ENC_NONE     0x0000          /* no encryption */
 131 #define UBS_PKTCTX_INBOUND      0x4000          /* inbound packet */
 132 #define UBS_PKTCTX_AUTH         0x3000          /* authentication mask */
 133 #define UBS_PKTCTX_AUTH_NONE    0x0000          /* no authentication */
 134 #define UBS_PKTCTX_AUTH_MD5     0x1000          /* use hmac-md5 */
 135 #define UBS_PKTCTX_AUTH_SHA1    0x2000          /* use hmac-sha1 */
 136
 137 struct ubsec_pktctx_long {
 138         volatile u_int16_t      pc_len;         /* length of ctx struct */
 139         volatile u_int16_t      pc_type;        /* context type, 0 */
 140         volatile u_int16_t      pc_flags;       /* flags, same as above */
 141         volatile u_int16_t      pc_offset;      /* crypto/auth offset */
 142         volatile u_int32_t      pc_deskey[6];   /* 3DES key */
 143         volatile u_int32_t      pc_iv[2];       /* [3]DES iv */
 144         volatile u_int32_t      pc_hminner[5];  /* hmac inner state */
 145         volatile u_int32_t      pc_hmouter[5];  /* hmac outer state */
 146 };
 147 #define UBS_PKTCTX_TYPE_IPSEC   0x0000
 148
 149 struct ubsec_pktbuf {
 150         volatile u_int32_t      pb_addr;        /* address of buffer start */
 151         volatile u_int32_t      pb_next;        /* pointer to next pktbuf */
 152         volatile u_int32_t      pb_len;         /* packet length */
 153 };
 154 #define UBS_PKTBUF_LEN          0x0000ffff      /* length mask */
 155
 156 struct ubsec_mcr {
 157         volatile u_int16_t      mcr_pkts;       /* #pkts in this mcr */
 158         volatile u_int16_t      mcr_flags;      /* mcr flags (below) */
 159         volatile u_int32_t      mcr_cmdctxp;    /* command ctx pointer */
 160         struct ubsec_pktbuf     mcr_ipktbuf;    /* input chain header */
 161         volatile u_int16_t      mcr_reserved;
 162         volatile u_int16_t      mcr_pktlen;
 163         struct ubsec_pktbuf     mcr_opktbuf;    /* output chain header */
 164 };
 165
 166 struct ubsec_mcr_add {
 167         volatile u_int32_t      mcr_cmdctxp;    /* command ctx pointer */
 168         struct ubsec_pktbuf     mcr_ipktbuf;    /* input chain header */
 169         volatile u_int16_t      mcr_reserved;
 170         volatile u_int16_t      mcr_pktlen;
 171         struct ubsec_pktbuf     mcr_opktbuf;    /* output chain header */
 172 };
 173
 174 #define UBS_MCR_DONE            0x0001          /* mcr has been processed */
 175 #define UBS_MCR_ERROR           0x0002          /* error in processing */
 176 #define UBS_MCR_ERRORCODE       0xff00          /* error type */
 177
 178 struct ubsec_ctx_keyop {
 179         volatile u_int16_t      ctx_len;        /* command length */
 180         volatile u_int16_t      ctx_op;         /* operation code */
 181         volatile u_int8_t       ctx_pad[60];    /* padding */
 182 };
 183 #define UBS_CTXOP_DHPKGEN       0x01            /* dh public key generation */
 184 #define UBS_CTXOP_DHSSGEN       0x02            /* dh shared secret gen. */
 185 #define UBS_CTXOP_RSAPUB        0x03            /* rsa public key op */
 186 #define UBS_CTXOP_RSAPRIV       0x04            /* rsa private key op */
 187 #define UBS_CTXOP_DSASIGN       0x05            /* dsa signing op */
 188 #define UBS_CTXOP_DSAVRFY       0x06            /* dsa verification */
 189 #define UBS_CTXOP_RNGBYPASS     0x41            /* rng direct test mode */
 190 #define UBS_CTXOP_RNGSHA1       0x42            /* rng sha1 test mode */
 191 #define UBS_CTXOP_MODADD        0x43            /* modular addition */
 192 #define UBS_CTXOP_MODSUB        0x44            /* modular subtraction */
 193 #define UBS_CTXOP_MODMUL        0x45            /* modular multiplication */
 194 #define UBS_CTXOP_MODRED        0x46            /* modular reduction */
 195 #define UBS_CTXOP_MODEXP        0x47            /* modular exponentiation */
 196 #define UBS_CTXOP_MODINV        0x48            /* modular inverse */
 197
 198 struct ubsec_ctx_rngbypass {
 199         volatile u_int16_t      rbp_len;        /* command length, 64 */
 200         volatile u_int16_t      rbp_op;         /* rng bypass, 0x41 */
 201         volatile u_int8_t       rbp_pad[60];    /* padding */
 202 };
 203
 204 /* modexp: C = (M ^ E) mod N */
 205 struct ubsec_ctx_modexp {
 206         volatile u_int16_t      me_len;         /* command length */
 207         volatile u_int16_t      me_op;          /* modexp, 0x47 */
 208         volatile u_int16_t      me_E_len;       /* E (bits) */
 209         volatile u_int16_t      me_N_len;       /* N (bits) */
 210         u_int8_t                me_N[2048/8];   /* N */
 211 };
 212
 213 struct ubsec_ctx_rsapriv {
 214         volatile u_int16_t      rpr_len;        /* command length */
 215         volatile u_int16_t      rpr_op;         /* rsaprivate, 0x04 */
 216         volatile u_int16_t      rpr_q_len;      /* q (bits) */
 217         volatile u_int16_t      rpr_p_len;      /* p (bits) */
 218         u_int8_t                rpr_buf[5 * 1024 / 8];  /* parameters: */
 219                                                 /* p, q, dp, dq, pinv */
 220 };