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Merge commit 'crater/master'
[dragonfly.git] / sys / dev / crypto / ubsec / ubsec.c
blob933f9bbbad524eee74e7fe9edb7c11727a4eaf74
1 /* $FreeBSD: src/sys/dev/ubsec/ubsec.c,v 1.6.2.12 2003/06/04 17:56:59 sam Exp $ */
2 /* $DragonFly: src/sys/dev/crypto/ubsec/ubsec.c,v 1.13 2006/12/22 23:26:15 swildner Exp $ */
3 /* $OpenBSD: ubsec.c,v 1.115 2002/09/24 18:33:26 jason Exp $ */
4
5 /*
6 * Copyright (c) 2000 Jason L. Wright (jason@thought.net)
7 * Copyright (c) 2000 Theo de Raadt (deraadt@openbsd.org)
8 * Copyright (c) 2001 Patrik Lindergren (patrik@ipunplugged.com)
9 *
10 * All rights reserved.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 * 3. All advertising materials mentioning features or use of this software
21 * must display the following acknowledgement:
22 * This product includes software developed by Jason L. Wright
23 * 4. The name of the author may not be used to endorse or promote products
24 * derived from this software without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
27 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
28 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
29 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
30 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
31 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
32 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
34 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
35 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 * POSSIBILITY OF SUCH DAMAGE.
37 *
38 * Effort sponsored in part by the Defense Advanced Research Projects
39 * Agency (DARPA) and Air Force Research Laboratory, Air Force
40 * Materiel Command, USAF, under agreement number F30602-01-2-0537.
41 *
42 */
43
44 /*
45 * uBsec 5[56]01, 58xx hardware crypto accelerator
46 */
47
48 #include "opt_ubsec.h"
49
50 #include <sys/param.h>
51 #include <sys/systm.h>
52 #include <sys/proc.h>
53 #include <sys/errno.h>
54 #include <sys/malloc.h>
55 #include <sys/kernel.h>
56 #include <sys/mbuf.h>
57 #include <sys/sysctl.h>
58 #include <sys/endian.h>
59 #include <sys/bus.h>
60 #include <sys/rman.h>
61 #include <sys/md5.h>
62 #include <sys/random.h>
63 #include <sys/thread2.h>
64
65 #include <vm/vm.h>
66 #include <vm/pmap.h>
67
68 #include <machine/clock.h>
69
70 #include <crypto/sha1.h>
71 #include <opencrypto/cryptodev.h>
72 #include <opencrypto/cryptosoft.h>
73
74 #include <bus/pci/pcivar.h>
75 #include <bus/pci/pcireg.h>
76
77 /* grr, #defines for gratuitous incompatibility in queue.h */
78 #define SIMPLEQ_HEAD STAILQ_HEAD
79 #define SIMPLEQ_ENTRY STAILQ_ENTRY
80 #define SIMPLEQ_INIT STAILQ_INIT
81 #define SIMPLEQ_INSERT_TAIL STAILQ_INSERT_TAIL
82 #define SIMPLEQ_EMPTY STAILQ_EMPTY
83 #define SIMPLEQ_FIRST STAILQ_FIRST
84 #define SIMPLEQ_REMOVE_HEAD STAILQ_REMOVE_HEAD
85 #define SIMPLEQ_FOREACH STAILQ_FOREACH
86 /* ditto for endian.h */
87 #define letoh16(x) le16toh(x)
88 #define letoh32(x) le32toh(x)
89
90 #ifdef UBSEC_RNDTEST
91 #include "../rndtest/rndtest.h"
92 #endif
93 #include "ubsecreg.h"
94 #include "ubsecvar.h"
95
96 /*
97 * Prototypes and count for the pci_device structure
98 */
99 static int ubsec_probe(device_t);
100 static int ubsec_attach(device_t);
101 static int ubsec_detach(device_t);
102 static int ubsec_suspend(device_t);
103 static int ubsec_resume(device_t);
104 static void ubsec_shutdown(device_t);
105
106 static device_method_t ubsec_methods[] = {
107 /* Device interface */
108 DEVMETHOD(device_probe, ubsec_probe),
109 DEVMETHOD(device_attach, ubsec_attach),
110 DEVMETHOD(device_detach, ubsec_detach),
111 DEVMETHOD(device_suspend, ubsec_suspend),
112 DEVMETHOD(device_resume, ubsec_resume),
113 DEVMETHOD(device_shutdown, ubsec_shutdown),
114
115 /* bus interface */
116 DEVMETHOD(bus_print_child, bus_generic_print_child),
117 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
118
119 { 0, 0 }
120 };
121 static driver_t ubsec_driver = {
122 "ubsec",
123 ubsec_methods,
124 sizeof (struct ubsec_softc)
125 };
126 static devclass_t ubsec_devclass;
127
128 DECLARE_DUMMY_MODULE(ubsec);
129 DRIVER_MODULE(ubsec, pci, ubsec_driver, ubsec_devclass, 0, 0);
130 MODULE_DEPEND(ubsec, crypto, 1, 1, 1);
131 #ifdef UBSEC_RNDTEST
132 MODULE_DEPEND(ubsec, rndtest, 1, 1, 1);
133 #endif
134
135 static void ubsec_intr(void *);
136 static int ubsec_newsession(void *, u_int32_t *, struct cryptoini *);
137 static int ubsec_freesession(void *, u_int64_t);
138 static int ubsec_process(void *, struct cryptop *, int);
139 static void ubsec_callback(struct ubsec_softc *, struct ubsec_q *);
140 static void ubsec_feed(struct ubsec_softc *);
141 static void ubsec_mcopy(struct mbuf *, struct mbuf *, int, int);
142 static void ubsec_callback2(struct ubsec_softc *, struct ubsec_q2 *);
143 static int ubsec_feed2(struct ubsec_softc *);
144 static void ubsec_rng(void *);
145 static int ubsec_dma_malloc(struct ubsec_softc *, bus_size_t,
146 struct ubsec_dma_alloc *, int);
147 #define ubsec_dma_sync(_dma, _flags) \
148 bus_dmamap_sync((_dma)->dma_tag, (_dma)->dma_map, (_flags))
149 static void ubsec_dma_free(struct ubsec_softc *, struct ubsec_dma_alloc *);
150 static int ubsec_dmamap_aligned(struct ubsec_operand *op);
151
152 static void ubsec_reset_board(struct ubsec_softc *sc);
153 static void ubsec_init_board(struct ubsec_softc *sc);
154 static void ubsec_init_pciregs(device_t dev);
155 static void ubsec_totalreset(struct ubsec_softc *sc);
156
157 static int ubsec_free_q(struct ubsec_softc *sc, struct ubsec_q *q);
158
159 static int ubsec_kprocess(void*, struct cryptkop *, int);
160 static int ubsec_kprocess_modexp_hw(struct ubsec_softc *, struct cryptkop *, int);
161 static int ubsec_kprocess_modexp_sw(struct ubsec_softc *, struct cryptkop *, int);
162 static int ubsec_kprocess_rsapriv(struct ubsec_softc *, struct cryptkop *, int);
163 static void ubsec_kfree(struct ubsec_softc *, struct ubsec_q2 *);
164 static int ubsec_ksigbits(struct crparam *);
165 static void ubsec_kshift_r(u_int, u_int8_t *, u_int, u_int8_t *, u_int);
166 static void ubsec_kshift_l(u_int, u_int8_t *, u_int, u_int8_t *, u_int);
167
168 SYSCTL_NODE(_hw, OID_AUTO, ubsec, CTLFLAG_RD, 0, "Broadcom driver parameters");
169
170 #ifdef UBSEC_DEBUG
171 static void ubsec_dump_pb(volatile struct ubsec_pktbuf *);
172 static void ubsec_dump_mcr(struct ubsec_mcr *);
173 static void ubsec_dump_ctx2(struct ubsec_ctx_keyop *);
174
175 static int ubsec_debug = 0;
176 SYSCTL_INT(_hw_ubsec, OID_AUTO, debug, CTLFLAG_RW, &ubsec_debug,
177 0, "control debugging msgs");
178 #endif
179
180 #define READ_REG(sc,r) \
181 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (r))
182
183 #define WRITE_REG(sc,reg,val) \
184 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, reg, val)
185
186 #define SWAP32(x) (x) = htole32(ntohl((x)))
187 #define HTOLE32(x) (x) = htole32(x)
188
189
190 struct ubsec_stats ubsecstats;
191 SYSCTL_STRUCT(_hw_ubsec, OID_AUTO, stats, CTLFLAG_RD, &ubsecstats,
192 ubsec_stats, "driver statistics");
193
194 static int
195 ubsec_probe(device_t dev)
196 {
197 if (pci_get_vendor(dev) == PCI_VENDOR_SUN &&
198 (pci_get_device(dev) == PCI_PRODUCT_SUN_5821 ||
199 pci_get_device(dev) == PCI_PRODUCT_SUN_SCA1K))
200 return (0);
201 if (pci_get_vendor(dev) == PCI_VENDOR_BLUESTEEL &&
202 (pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5501 ||
203 pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5601))
204 return (0);
205 if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM &&
206 (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5801 ||
207 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5802 ||
208 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5805 ||
209 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5820 ||
210 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5821 ||
211 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5822 ||
212 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5823
213 ))
214 return (0);
215 return (ENXIO);
216 }
217
218 static const char*
219 ubsec_partname(struct ubsec_softc *sc)
220 {
221 /* XXX sprintf numbers when not decoded */
222 switch (pci_get_vendor(sc->sc_dev)) {
223 case PCI_VENDOR_BROADCOM:
224 switch (pci_get_device(sc->sc_dev)) {
225 case PCI_PRODUCT_BROADCOM_5801: return "Broadcom 5801";
226 case PCI_PRODUCT_BROADCOM_5802: return "Broadcom 5802";
227 case PCI_PRODUCT_BROADCOM_5805: return "Broadcom 5805";
228 case PCI_PRODUCT_BROADCOM_5820: return "Broadcom 5820";
229 case PCI_PRODUCT_BROADCOM_5821: return "Broadcom 5821";
230 case PCI_PRODUCT_BROADCOM_5822: return "Broadcom 5822";
231 case PCI_PRODUCT_BROADCOM_5823: return "Broadcom 5823";
232 }
233 return "Broadcom unknown-part";
234 case PCI_VENDOR_BLUESTEEL:
235 switch (pci_get_device(sc->sc_dev)) {
236 case PCI_PRODUCT_BLUESTEEL_5601: return "Bluesteel 5601";
237 }
238 return "Bluesteel unknown-part";
239 case PCI_VENDOR_SUN:
240 switch (pci_get_device(sc->sc_dev)) {
241 case PCI_PRODUCT_SUN_5821: return "Sun Crypto 5821";
242 case PCI_PRODUCT_SUN_SCA1K: return "Sun Crypto 1K";
243 }
244 return "Sun unknown-part";
245 }
246 return "Unknown-vendor unknown-part";
247 }
248
249 static void
250 default_harvest(struct rndtest_state *rsp, void *buf, u_int count)
251 {
252 u_int32_t *p = (u_int32_t *)buf;
253 for (count /= sizeof (u_int32_t); count; count--)
254 add_true_randomness(*p++);
255 }
256
257 static int
258 ubsec_attach(device_t dev)
259 {
260 struct ubsec_softc *sc = device_get_softc(dev);
261 struct ubsec_dma *dmap;
262 u_int32_t cmd, i;
263 int rid;
264
265 KASSERT(sc != NULL, ("ubsec_attach: null software carrier!"));
266 bzero(sc, sizeof (*sc));
267 sc->sc_dev = dev;
268
269 SIMPLEQ_INIT(&sc->sc_queue);
270 SIMPLEQ_INIT(&sc->sc_qchip);
271 SIMPLEQ_INIT(&sc->sc_queue2);
272 SIMPLEQ_INIT(&sc->sc_qchip2);
273 SIMPLEQ_INIT(&sc->sc_q2free);
274
275 /* XXX handle power management */
276
277 sc->sc_statmask = BS_STAT_MCR1_DONE | BS_STAT_DMAERR;
278
279 if (pci_get_vendor(dev) == PCI_VENDOR_BLUESTEEL &&
280 pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5601)
281 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG;
282
283 if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM &&
284 (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5802 ||
285 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5805))
286 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG;
287
288 if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM &&
289 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5820)
290 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG |
291 UBS_FLAGS_LONGCTX | UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY;
292
293 if ((pci_get_vendor(dev) == PCI_VENDOR_BROADCOM &&
294 (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5821 ||
295 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5822 ||
296 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5823)) ||
297 (pci_get_vendor(dev) == PCI_VENDOR_SUN &&
298 (pci_get_device(dev) == PCI_PRODUCT_SUN_SCA1K ||
299 pci_get_device(dev) == PCI_PRODUCT_SUN_5821))) {
300 /* NB: the 5821/5822 defines some additional status bits */
301 sc->sc_statmask |= BS_STAT_MCR1_ALLEMPTY |
302 BS_STAT_MCR2_ALLEMPTY;
303 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG |
304 UBS_FLAGS_LONGCTX | UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY;
305 }
306
307 cmd = pci_read_config(dev, PCIR_COMMAND, 4);
308 cmd |= PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN;
309 pci_write_config(dev, PCIR_COMMAND, cmd, 4);
310 cmd = pci_read_config(dev, PCIR_COMMAND, 4);
311
312 if (!(cmd & PCIM_CMD_MEMEN)) {
313 device_printf(dev, "failed to enable memory mapping\n");
314 goto bad;
315 }
316
317 if (!(cmd & PCIM_CMD_BUSMASTEREN)) {
318 device_printf(dev, "failed to enable bus mastering\n");
319 goto bad;
320 }
321
322 /*
323 * Setup memory-mapping of PCI registers.
324 */
325 rid = BS_BAR;
326 sc->sc_sr = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
327 0, ~0, 1, RF_ACTIVE);
328 if (sc->sc_sr == NULL) {
329 device_printf(dev, "cannot map register space\n");
330 goto bad;
331 }
332 sc->sc_st = rman_get_bustag(sc->sc_sr);
333 sc->sc_sh = rman_get_bushandle(sc->sc_sr);
334
335 /*
336 * Arrange interrupt line.
337 */
338 rid = 0;
339 sc->sc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid,
340 0, ~0, 1, RF_SHAREABLE|RF_ACTIVE);
341 if (sc->sc_irq == NULL) {
342 device_printf(dev, "could not map interrupt\n");
343 goto bad1;
344 }
345 /*
346 * NB: Network code assumes we are blocked with splimp()
347 * so make sure the IRQ is mapped appropriately.
348 */
349 if (bus_setup_intr(dev, sc->sc_irq, 0,
350 ubsec_intr, sc,
351 &sc->sc_ih, NULL)) {
352 device_printf(dev, "could not establish interrupt\n");
353 goto bad2;
354 }
355
356 sc->sc_cid = crypto_get_driverid(0);
357 if (sc->sc_cid < 0) {
358 device_printf(dev, "could not get crypto driver id\n");
359 goto bad3;
360 }
361
362 /*
363 * Setup DMA descriptor area.
364 */
365 if (bus_dma_tag_create(NULL, /* parent */
366 1, 0, /* alignment, bounds */
367 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
368 BUS_SPACE_MAXADDR, /* highaddr */
369 NULL, NULL, /* filter, filterarg */
370 0x3ffff, /* maxsize */
371 UBS_MAX_SCATTER, /* nsegments */
372 0xffff, /* maxsegsize */
373 BUS_DMA_ALLOCNOW, /* flags */
374 &sc->sc_dmat)) {
375 device_printf(dev, "cannot allocate DMA tag\n");
376 goto bad4;
377 }
378 SIMPLEQ_INIT(&sc->sc_freequeue);
379 dmap = sc->sc_dmaa;
380 for (i = 0; i < UBS_MAX_NQUEUE; i++, dmap++) {
381 struct ubsec_q *q;
382
383 q = kmalloc(sizeof(struct ubsec_q), M_DEVBUF, M_WAITOK);
384 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_dmachunk),
385 &dmap->d_alloc, 0)) {
386 device_printf(dev, "cannot allocate dma buffers\n");
387 kfree(q, M_DEVBUF);
388 break;
389 }
390 dmap->d_dma = (struct ubsec_dmachunk *)dmap->d_alloc.dma_vaddr;
391
392 q->q_dma = dmap;
393 sc->sc_queuea[i] = q;
394
395 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next);
396 }
397
398 device_printf(sc->sc_dev, "%s\n", ubsec_partname(sc));
399
400 crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0,
401 ubsec_newsession, ubsec_freesession, ubsec_process, sc);
402 crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0,
403 ubsec_newsession, ubsec_freesession, ubsec_process, sc);
404 crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0,
405 ubsec_newsession, ubsec_freesession, ubsec_process, sc);
406 crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0,
407 ubsec_newsession, ubsec_freesession, ubsec_process, sc);
408
409 /*
410 * Reset Broadcom chip
411 */
412 ubsec_reset_board(sc);
413
414 /*
415 * Init Broadcom specific PCI settings
416 */
417 ubsec_init_pciregs(dev);
418
419 /*
420 * Init Broadcom chip
421 */
422 ubsec_init_board(sc);
423
424 #ifndef UBSEC_NO_RNG
425 if (sc->sc_flags & UBS_FLAGS_RNG) {
426 sc->sc_statmask |= BS_STAT_MCR2_DONE;
427 #ifdef UBSEC_RNDTEST
428 sc->sc_rndtest = rndtest_attach(dev);
429 if (sc->sc_rndtest)
430 sc->sc_harvest = rndtest_harvest;
431 else
432 sc->sc_harvest = default_harvest;
433 #else
434 sc->sc_harvest = default_harvest;
435 #endif
436
437 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr),
438 &sc->sc_rng.rng_q.q_mcr, 0))
439 goto skip_rng;
440
441 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rngbypass),
442 &sc->sc_rng.rng_q.q_ctx, 0)) {
443 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr);
444 goto skip_rng;
445 }
446
447 if (ubsec_dma_malloc(sc, sizeof(u_int32_t) *
448 UBSEC_RNG_BUFSIZ, &sc->sc_rng.rng_buf, 0)) {
449 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_ctx);
450 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr);
451 goto skip_rng;
452 }
453
454 if (hz >= 100)
455 sc->sc_rnghz = hz / 100;
456 else
457 sc->sc_rnghz = 1;
458 callout_init(&sc->sc_rngto);
459 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc);
460 skip_rng:
461 ;
462 }
463 #endif /* UBSEC_NO_RNG */
464
465 if (sc->sc_flags & UBS_FLAGS_KEY) {
466 sc->sc_statmask |= BS_STAT_MCR2_DONE;
467
468 crypto_kregister(sc->sc_cid, CRK_MOD_EXP, 0,
469 ubsec_kprocess, sc);
470 #if 0
471 crypto_kregister(sc->sc_cid, CRK_MOD_EXP_CRT, 0,
472 ubsec_kprocess, sc);
473 #endif
474 }
475 return (0);
476 bad4:
477 crypto_unregister_all(sc->sc_cid);
478 bad3:
479 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih);
480 bad2:
481 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq);
482 bad1:
483 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr);
484 bad:
485 return (ENXIO);
486 }
487
488 /*
489 * Detach a device that successfully probed.
490 */
491 static int
492 ubsec_detach(device_t dev)
493 {
494 struct ubsec_softc *sc = device_get_softc(dev);
495
496 KASSERT(sc != NULL, ("ubsec_detach: null software carrier"));
497
498 /* XXX wait/abort active ops */
499
500 crit_enter();
501
502 callout_stop(&sc->sc_rngto);
503
504 crypto_unregister_all(sc->sc_cid);
505
506 #ifdef UBSEC_RNDTEST
507 if (sc->sc_rndtest)
508 rndtest_detach(sc->sc_rndtest);
509 #endif
510
511 while (!SIMPLEQ_EMPTY(&sc->sc_freequeue)) {
512 struct ubsec_q *q;
513
514 q = SIMPLEQ_FIRST(&sc->sc_freequeue);
515 SIMPLEQ_REMOVE_HEAD(&sc->sc_freequeue, q_next);
516 ubsec_dma_free(sc, &q->q_dma->d_alloc);
517 kfree(q, M_DEVBUF);
518 }
519 #ifndef UBSEC_NO_RNG
520 if (sc->sc_flags & UBS_FLAGS_RNG) {
521 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr);
522 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_ctx);
523 ubsec_dma_free(sc, &sc->sc_rng.rng_buf);
524 }
525 #endif /* UBSEC_NO_RNG */
526
527 bus_generic_detach(dev);
528 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih);
529 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq);
530
531 bus_dma_tag_destroy(sc->sc_dmat);
532 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr);
533
534 crit_exit();
535
536 return (0);
537 }
538
539 /*
540 * Stop all chip i/o so that the kernel's probe routines don't
541 * get confused by errant DMAs when rebooting.
542 */
543 static void
544 ubsec_shutdown(device_t dev)
545 {
546 #ifdef notyet
547 ubsec_stop(device_get_softc(dev));
548 #endif
549 }
550
551 /*
552 * Device suspend routine.
553 */
554 static int
555 ubsec_suspend(device_t dev)
556 {
557 struct ubsec_softc *sc = device_get_softc(dev);
558
559 KASSERT(sc != NULL, ("ubsec_suspend: null software carrier"));
560 #ifdef notyet
561 /* XXX stop the device and save PCI settings */
562 #endif
563 sc->sc_suspended = 1;
564
565 return (0);
566 }
567
568 static int
569 ubsec_resume(device_t dev)
570 {
571 struct ubsec_softc *sc = device_get_softc(dev);
572
573 KASSERT(sc != NULL, ("ubsec_resume: null software carrier"));
574 #ifdef notyet
575 /* XXX retore PCI settings and start the device */
576 #endif
577 sc->sc_suspended = 0;
578 return (0);
579 }
580
581 /*
582 * UBSEC Interrupt routine
583 */
584 static void
585 ubsec_intr(void *arg)
586 {
587 struct ubsec_softc *sc = arg;
588 volatile u_int32_t stat;
589 struct ubsec_q *q;
590 struct ubsec_dma *dmap;
591 int npkts = 0, i;
592
593 stat = READ_REG(sc, BS_STAT);
594 stat &= sc->sc_statmask;
595 if (stat == 0) {
596 return;
597 }
598
599 WRITE_REG(sc, BS_STAT, stat); /* IACK */
600
601 /*
602 * Check to see if we have any packets waiting for us
603 */
604 if ((stat & BS_STAT_MCR1_DONE)) {
605 while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) {
606 q = SIMPLEQ_FIRST(&sc->sc_qchip);
607 dmap = q->q_dma;
608
609 if ((dmap->d_dma->d_mcr.mcr_flags & htole16(UBS_MCR_DONE)) == 0)
610 break;
611
612 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q_next);
613
614 npkts = q->q_nstacked_mcrs;
615 sc->sc_nqchip -= 1+npkts;
616 /*
617 * search for further sc_qchip ubsec_q's that share
618 * the same MCR, and complete them too, they must be
619 * at the top.
620 */
621 for (i = 0; i < npkts; i++) {
622 if(q->q_stacked_mcr[i]) {
623 ubsec_callback(sc, q->q_stacked_mcr[i]);
624 } else {
625 break;
626 }
627 }
628 ubsec_callback(sc, q);
629 }
630
631 /*
632 * Don't send any more packet to chip if there has been
633 * a DMAERR.
634 */
635 if (!(stat & BS_STAT_DMAERR))
636 ubsec_feed(sc);
637 }
638
639 /*
640 * Check to see if we have any key setups/rng's waiting for us
641 */
642 if ((sc->sc_flags & (UBS_FLAGS_KEY|UBS_FLAGS_RNG)) &&
643 (stat & BS_STAT_MCR2_DONE)) {
644 struct ubsec_q2 *q2;
645 struct ubsec_mcr *mcr;
646
647 while (!SIMPLEQ_EMPTY(&sc->sc_qchip2)) {
648 q2 = SIMPLEQ_FIRST(&sc->sc_qchip2);
649
650 ubsec_dma_sync(&q2->q_mcr,
651 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
652
653 mcr = (struct ubsec_mcr *)q2->q_mcr.dma_vaddr;
654 if ((mcr->mcr_flags & htole16(UBS_MCR_DONE)) == 0) {
655 ubsec_dma_sync(&q2->q_mcr,
656 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
657 break;
658 }
659 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip2, q_next);
660 ubsec_callback2(sc, q2);
661 /*
662 * Don't send any more packet to chip if there has been
663 * a DMAERR.
664 */
665 if (!(stat & BS_STAT_DMAERR))
666 ubsec_feed2(sc);
667 }
668 }
669
670 /*
671 * Check to see if we got any DMA Error
672 */
673 if (stat & BS_STAT_DMAERR) {
674 #ifdef UBSEC_DEBUG
675 if (ubsec_debug) {
676 volatile u_int32_t a = READ_REG(sc, BS_ERR);
677
678 kprintf("dmaerr %s@%08x\n",
679 (a & BS_ERR_READ) ? "read" : "write",
680 a & BS_ERR_ADDR);
681 }
682 #endif /* UBSEC_DEBUG */
683 ubsecstats.hst_dmaerr++;
684 ubsec_totalreset(sc);
685 ubsec_feed(sc);
686 }
687
688 if (sc->sc_needwakeup) { /* XXX check high watermark */
689 int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ);
690 #ifdef UBSEC_DEBUG
691 if (ubsec_debug)
692 device_printf(sc->sc_dev, "wakeup crypto (%x)\n",
693 sc->sc_needwakeup);
694 #endif /* UBSEC_DEBUG */
695 sc->sc_needwakeup &= ~wakeup;
696 crypto_unblock(sc->sc_cid, wakeup);
697 }
698 }
699
700 /*
701 * ubsec_feed() - aggregate and post requests to chip
702 */
703 static void
704 ubsec_feed(struct ubsec_softc *sc)
705 {
706 struct ubsec_q *q, *q2;
707 int npkts, i;
708 void *v;
709 u_int32_t stat;
710
711 /*
712 * Decide how many ops to combine in a single MCR. We cannot
713 * aggregate more than UBS_MAX_AGGR because this is the number
714 * of slots defined in the data structure. Note that
715 * aggregation only happens if ops are marked batch'able.
716 * Aggregating ops reduces the number of interrupts to the host
717 * but also (potentially) increases the latency for processing
718 * completed ops as we only get an interrupt when all aggregated
719 * ops have completed.
720 */
721 if (sc->sc_nqueue == 0)
722 return;
723 if (sc->sc_nqueue > 1) {
724 npkts = 0;
725 SIMPLEQ_FOREACH(q, &sc->sc_queue, q_next) {
726 npkts++;
727 if ((q->q_crp->crp_flags & CRYPTO_F_BATCH) == 0)
728 break;
729 }
730 } else
731 npkts = 1;
732 /*
733 * Check device status before going any further.
734 */
735 if ((stat = READ_REG(sc, BS_STAT)) & (BS_STAT_MCR1_FULL | BS_STAT_DMAERR)) {
736 if (stat & BS_STAT_DMAERR) {
737 ubsec_totalreset(sc);
738 ubsecstats.hst_dmaerr++;
739 } else
740 ubsecstats.hst_mcr1full++;
741 return;
742 }
743 if (sc->sc_nqueue > ubsecstats.hst_maxqueue)
744 ubsecstats.hst_maxqueue = sc->sc_nqueue;
745 if (npkts > UBS_MAX_AGGR)
746 npkts = UBS_MAX_AGGR;
747 if (npkts < 2) /* special case 1 op */
748 goto feed1;
749
750 ubsecstats.hst_totbatch += npkts-1;
751 #ifdef UBSEC_DEBUG
752 if (ubsec_debug)
753 kprintf("merging %d records\n", npkts);
754 #endif /* UBSEC_DEBUG */
755
756 q = SIMPLEQ_FIRST(&sc->sc_queue);
757 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q_next);
758 --sc->sc_nqueue;
759
760 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_PREWRITE);
761 if (q->q_dst_map != NULL)
762 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, BUS_DMASYNC_PREREAD);
763
764 q->q_nstacked_mcrs = npkts - 1; /* Number of packets stacked */
765
766 for (i = 0; i < q->q_nstacked_mcrs; i++) {
767 q2 = SIMPLEQ_FIRST(&sc->sc_queue);
768 bus_dmamap_sync(sc->sc_dmat, q2->q_src_map,
769 BUS_DMASYNC_PREWRITE);
770 if (q2->q_dst_map != NULL)
771 bus_dmamap_sync(sc->sc_dmat, q2->q_dst_map,
772 BUS_DMASYNC_PREREAD);
773 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q_next);
774 --sc->sc_nqueue;
775
776 v = (void*)(((char *)&q2->q_dma->d_dma->d_mcr) + sizeof(struct ubsec_mcr) -
777 sizeof(struct ubsec_mcr_add));
778 bcopy(v, &q->q_dma->d_dma->d_mcradd[i], sizeof(struct ubsec_mcr_add));
779 q->q_stacked_mcr[i] = q2;
780 }
781 q->q_dma->d_dma->d_mcr.mcr_pkts = htole16(npkts);
782 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next);
783 sc->sc_nqchip += npkts;
784 if (sc->sc_nqchip > ubsecstats.hst_maxqchip)
785 ubsecstats.hst_maxqchip = sc->sc_nqchip;
786 ubsec_dma_sync(&q->q_dma->d_alloc,
787 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
788 WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr +
789 offsetof(struct ubsec_dmachunk, d_mcr));
790 return;
791
792 feed1:
793 q = SIMPLEQ_FIRST(&sc->sc_queue);
794
795 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_PREWRITE);
796 if (q->q_dst_map != NULL)
797 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, BUS_DMASYNC_PREREAD);
798 ubsec_dma_sync(&q->q_dma->d_alloc,
799 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
800
801 WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr +
802 offsetof(struct ubsec_dmachunk, d_mcr));
803 #ifdef UBSEC_DEBUG
804 if (ubsec_debug)
805 kprintf("feed1: q->chip %p %08x stat %08x\n",
806 q, (u_int32_t)vtophys(&q->q_dma->d_dma->d_mcr),
807 stat);
808 #endif /* UBSEC_DEBUG */
809 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q_next);
810 --sc->sc_nqueue;
811 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next);
812 sc->sc_nqchip++;
813 if (sc->sc_nqchip > ubsecstats.hst_maxqchip)
814 ubsecstats.hst_maxqchip = sc->sc_nqchip;
815 return;
816 }
817
818 /*
819 * Allocate a new 'session' and return an encoded session id. 'sidp'
820 * contains our registration id, and should contain an encoded session
821 * id on successful allocation.
822 */
823 static int
824 ubsec_newsession(void *arg, u_int32_t *sidp, struct cryptoini *cri)
825 {
826 struct cryptoini *c, *encini = NULL, *macini = NULL;
827 struct ubsec_softc *sc = arg;
828 struct ubsec_session *ses = NULL;
829 MD5_CTX md5ctx;
830 SHA1_CTX sha1ctx;
831 int i, sesn;
832
833 KASSERT(sc != NULL, ("ubsec_newsession: null softc"));
834 if (sidp == NULL || cri == NULL || sc == NULL)
835 return (EINVAL);
836
837 for (c = cri; c != NULL; c = c->cri_next) {
838 if (c->cri_alg == CRYPTO_MD5_HMAC ||
839 c->cri_alg == CRYPTO_SHA1_HMAC) {
840 if (macini)
841 return (EINVAL);
842 macini = c;
843 } else if (c->cri_alg == CRYPTO_DES_CBC ||
844 c->cri_alg == CRYPTO_3DES_CBC) {
845 if (encini)
846 return (EINVAL);
847 encini = c;
848 } else
849 return (EINVAL);
850 }
851 if (encini == NULL && macini == NULL)
852 return (EINVAL);
853
854 if (sc->sc_sessions == NULL) {
855 ses = sc->sc_sessions = kmalloc(sizeof(struct ubsec_session),
856 M_DEVBUF, M_INTWAIT);
857 sesn = 0;
858 sc->sc_nsessions = 1;
859 } else {
860 for (sesn = 0; sesn < sc->sc_nsessions; sesn++) {
861 if (sc->sc_sessions[sesn].ses_used == 0) {
862 ses = &sc->sc_sessions[sesn];
863 break;
864 }
865 }
866
867 if (ses == NULL) {
868 sesn = sc->sc_nsessions;
869 ses = kmalloc((sesn + 1) * sizeof(struct ubsec_session),
870 M_DEVBUF, M_INTWAIT);
871 bcopy(sc->sc_sessions, ses, sesn *
872 sizeof(struct ubsec_session));
873 bzero(sc->sc_sessions, sesn *
874 sizeof(struct ubsec_session));
875 kfree(sc->sc_sessions, M_DEVBUF);
876 sc->sc_sessions = ses;
877 ses = &sc->sc_sessions[sesn];
878 sc->sc_nsessions++;
879 }
880 }
881
882 bzero(ses, sizeof(struct ubsec_session));
883 ses->ses_used = 1;
884 if (encini) {
885 /* get an IV, network byte order */
886 /* XXX may read fewer than requested */
887 read_random(ses->ses_iv, sizeof(ses->ses_iv));
888
889 /* Go ahead and compute key in ubsec's byte order */
890 if (encini->cri_alg == CRYPTO_DES_CBC) {
891 bcopy(encini->cri_key, &ses->ses_deskey[0], 8);
892 bcopy(encini->cri_key, &ses->ses_deskey[2], 8);
893 bcopy(encini->cri_key, &ses->ses_deskey[4], 8);
894 } else
895 bcopy(encini->cri_key, ses->ses_deskey, 24);
896
897 SWAP32(ses->ses_deskey[0]);
898 SWAP32(ses->ses_deskey[1]);
899 SWAP32(ses->ses_deskey[2]);
900 SWAP32(ses->ses_deskey[3]);
901 SWAP32(ses->ses_deskey[4]);
902 SWAP32(ses->ses_deskey[5]);
903 }
904
905 if (macini) {
906 for (i = 0; i < macini->cri_klen / 8; i++)
907 macini->cri_key[i] ^= HMAC_IPAD_VAL;
908
909 if (macini->cri_alg == CRYPTO_MD5_HMAC) {
910 MD5Init(&md5ctx);
911 MD5Update(&md5ctx, macini->cri_key,
912 macini->cri_klen / 8);
913 MD5Update(&md5ctx, hmac_ipad_buffer,
914 HMAC_BLOCK_LEN - (macini->cri_klen / 8));
915 bcopy(md5ctx.state, ses->ses_hminner,
916 sizeof(md5ctx.state));
917 } else {
918 SHA1Init(&sha1ctx);
919 SHA1Update(&sha1ctx, macini->cri_key,
920 macini->cri_klen / 8);
921 SHA1Update(&sha1ctx, hmac_ipad_buffer,
922 HMAC_BLOCK_LEN - (macini->cri_klen / 8));
923 bcopy(sha1ctx.h.b32, ses->ses_hminner,
924 sizeof(sha1ctx.h.b32));
925 }
926
927 for (i = 0; i < macini->cri_klen / 8; i++)
928 macini->cri_key[i] ^= (HMAC_IPAD_VAL ^ HMAC_OPAD_VAL);
929
930 if (macini->cri_alg == CRYPTO_MD5_HMAC) {
931 MD5Init(&md5ctx);
932 MD5Update(&md5ctx, macini->cri_key,
933 macini->cri_klen / 8);
934 MD5Update(&md5ctx, hmac_opad_buffer,
935 HMAC_BLOCK_LEN - (macini->cri_klen / 8));
936 bcopy(md5ctx.state, ses->ses_hmouter,
937 sizeof(md5ctx.state));
938 } else {
939 SHA1Init(&sha1ctx);
940 SHA1Update(&sha1ctx, macini->cri_key,
941 macini->cri_klen / 8);
942 SHA1Update(&sha1ctx, hmac_opad_buffer,
943 HMAC_BLOCK_LEN - (macini->cri_klen / 8));
944 bcopy(sha1ctx.h.b32, ses->ses_hmouter,
945 sizeof(sha1ctx.h.b32));
946 }
947
948 for (i = 0; i < macini->cri_klen / 8; i++)
949 macini->cri_key[i] ^= HMAC_OPAD_VAL;
950 }
951
952 *sidp = UBSEC_SID(device_get_unit(sc->sc_dev), sesn);
953 return (0);
954 }
955
956 /*
957 * Deallocate a session.
958 */
959 static int
960 ubsec_freesession(void *arg, u_int64_t tid)
961 {
962 struct ubsec_softc *sc = arg;
963 int session;
964 u_int32_t sid = ((u_int32_t) tid) & 0xffffffff;
965
966 KASSERT(sc != NULL, ("ubsec_freesession: null softc"));
967 if (sc == NULL)
968 return (EINVAL);
969
970 session = UBSEC_SESSION(sid);
971 if (session >= sc->sc_nsessions)
972 return (EINVAL);
973
974 bzero(&sc->sc_sessions[session], sizeof(sc->sc_sessions[session]));
975 return (0);
976 }
977
978 static void
979 ubsec_op_cb(void *arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, int error)
980 {
981 struct ubsec_operand *op = arg;
982
983 KASSERT(nsegs <= UBS_MAX_SCATTER,
984 ("Too many DMA segments returned when mapping operand"));
985 #ifdef UBSEC_DEBUG
986 if (ubsec_debug)
987 kprintf("ubsec_op_cb: mapsize %u nsegs %d\n",
988 (u_int) mapsize, nsegs);
989 #endif
990 op->mapsize = mapsize;
991 op->nsegs = nsegs;
992 bcopy(seg, op->segs, nsegs * sizeof (seg[0]));
993 }
994
995 static int
996 ubsec_process(void *arg, struct cryptop *crp, int hint)
997 {
998 struct ubsec_q *q = NULL;
999 int err = 0, i, j, nicealign;
1000 struct ubsec_softc *sc = arg;
1001 struct cryptodesc *crd1, *crd2, *maccrd, *enccrd;
1002 int encoffset = 0, macoffset = 0, cpskip, cpoffset;
1003 int sskip, dskip, stheend, dtheend;
1004 int16_t coffset;
1005 struct ubsec_session *ses;
1006 struct ubsec_pktctx ctx;
1007 struct ubsec_dma *dmap = NULL;
1008
1009 if (crp == NULL || crp->crp_callback == NULL || sc == NULL) {
1010 ubsecstats.hst_invalid++;
1011 return (EINVAL);
1012 }
1013 if (UBSEC_SESSION(crp->crp_sid) >= sc->sc_nsessions) {
1014 ubsecstats.hst_badsession++;
1015 return (EINVAL);
1016 }
1017
1018 crit_enter();
1019
1020 if (SIMPLEQ_EMPTY(&sc->sc_freequeue)) {
1021 ubsecstats.hst_queuefull++;
1022 sc->sc_needwakeup |= CRYPTO_SYMQ;
1023 crit_exit();
1024 return (ERESTART);
1025 }
1026 q = SIMPLEQ_FIRST(&sc->sc_freequeue);
1027 SIMPLEQ_REMOVE_HEAD(&sc->sc_freequeue, q_next);
1028 crit_exit();
1029
1030 dmap = q->q_dma; /* Save dma pointer */
1031 bzero(q, sizeof(struct ubsec_q));
1032 bzero(&ctx, sizeof(ctx));
1033
1034 q->q_sesn = UBSEC_SESSION(crp->crp_sid);
1035 q->q_dma = dmap;
1036 ses = &sc->sc_sessions[q->q_sesn];
1037
1038 if (crp->crp_flags & CRYPTO_F_IMBUF) {
1039 q->q_src_m = (struct mbuf *)crp->crp_buf;
1040 q->q_dst_m = (struct mbuf *)crp->crp_buf;
1041 } else if (crp->crp_flags & CRYPTO_F_IOV) {
1042 q->q_src_io = (struct uio *)crp->crp_buf;
1043 q->q_dst_io = (struct uio *)crp->crp_buf;
1044 } else {
1045 ubsecstats.hst_badflags++;
1046 err = EINVAL;
1047 goto errout; /* XXX we don't handle contiguous blocks! */
1048 }
1049
1050 bzero(&dmap->d_dma->d_mcr, sizeof(struct ubsec_mcr));
1051
1052 dmap->d_dma->d_mcr.mcr_pkts = htole16(1);
1053 dmap->d_dma->d_mcr.mcr_flags = 0;
1054 q->q_crp = crp;
1055
1056 crd1 = crp->crp_desc;
1057 if (crd1 == NULL) {
1058 ubsecstats.hst_nodesc++;
1059 err = EINVAL;
1060 goto errout;
1061 }
1062 crd2 = crd1->crd_next;
1063
1064 if (crd2 == NULL) {
1065 if (crd1->crd_alg == CRYPTO_MD5_HMAC ||
1066 crd1->crd_alg == CRYPTO_SHA1_HMAC) {
1067 maccrd = crd1;
1068 enccrd = NULL;
1069 } else if (crd1->crd_alg == CRYPTO_DES_CBC ||
1070 crd1->crd_alg == CRYPTO_3DES_CBC) {
1071 maccrd = NULL;
1072 enccrd = crd1;
1073 } else {
1074 ubsecstats.hst_badalg++;
1075 err = EINVAL;
1076 goto errout;
1077 }
1078 } else {
1079 if ((crd1->crd_alg == CRYPTO_MD5_HMAC ||
1080 crd1->crd_alg == CRYPTO_SHA1_HMAC) &&
1081 (crd2->crd_alg == CRYPTO_DES_CBC ||
1082 crd2->crd_alg == CRYPTO_3DES_CBC) &&
1083 ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) {
1084 maccrd = crd1;
1085 enccrd = crd2;
1086 } else if ((crd1->crd_alg == CRYPTO_DES_CBC ||
1087 crd1->crd_alg == CRYPTO_3DES_CBC) &&
1088 (crd2->crd_alg == CRYPTO_MD5_HMAC ||
1089 crd2->crd_alg == CRYPTO_SHA1_HMAC) &&
1090 (crd1->crd_flags & CRD_F_ENCRYPT)) {
1091 enccrd = crd1;
1092 maccrd = crd2;
1093 } else {
1094 /*
1095 * We cannot order the ubsec as requested
1096 */
1097 ubsecstats.hst_badalg++;
1098 err = EINVAL;
1099 goto errout;
1100 }
1101 }
1102
1103 if (enccrd) {
1104 encoffset = enccrd->crd_skip;
1105 ctx.pc_flags |= htole16(UBS_PKTCTX_ENC_3DES);
1106
1107 if (enccrd->crd_flags & CRD_F_ENCRYPT) {
1108 q->q_flags |= UBSEC_QFLAGS_COPYOUTIV;
1109
1110 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT)
1111 bcopy(enccrd->crd_iv, ctx.pc_iv, 8);
1112 else {
1113 ctx.pc_iv[0] = ses->ses_iv[0];
1114 ctx.pc_iv[1] = ses->ses_iv[1];
1115 }
1116
1117 if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) {
1118 if (crp->crp_flags & CRYPTO_F_IMBUF)
1119 m_copyback(q->q_src_m,
1120 enccrd->crd_inject,
1121 8, (caddr_t)ctx.pc_iv);
1122 else if (crp->crp_flags & CRYPTO_F_IOV)
1123 cuio_copyback(q->q_src_io,
1124 enccrd->crd_inject,
1125 8, (caddr_t)ctx.pc_iv);
1126 }
1127 } else {
1128 ctx.pc_flags |= htole16(UBS_PKTCTX_INBOUND);
1129
1130 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT)
1131 bcopy(enccrd->crd_iv, ctx.pc_iv, 8);
1132 else if (crp->crp_flags & CRYPTO_F_IMBUF)
1133 m_copydata(q->q_src_m, enccrd->crd_inject,
1134 8, (caddr_t)ctx.pc_iv);
1135 else if (crp->crp_flags & CRYPTO_F_IOV)
1136 cuio_copydata(q->q_src_io,
1137 enccrd->crd_inject, 8,
1138 (caddr_t)ctx.pc_iv);
1139 }
1140
1141 ctx.pc_deskey[0] = ses->ses_deskey[0];
1142 ctx.pc_deskey[1] = ses->ses_deskey[1];
1143 ctx.pc_deskey[2] = ses->ses_deskey[2];
1144 ctx.pc_deskey[3] = ses->ses_deskey[3];
1145 ctx.pc_deskey[4] = ses->ses_deskey[4];
1146 ctx.pc_deskey[5] = ses->ses_deskey[5];
1147 SWAP32(ctx.pc_iv[0]);
1148 SWAP32(ctx.pc_iv[1]);
1149 }
1150
1151 if (maccrd) {
1152 macoffset = maccrd->crd_skip;
1153
1154 if (maccrd->crd_alg == CRYPTO_MD5_HMAC)
1155 ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_MD5);
1156 else
1157 ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_SHA1);
1158
1159 for (i = 0; i < 5; i++) {
1160 ctx.pc_hminner[i] = ses->ses_hminner[i];
1161 ctx.pc_hmouter[i] = ses->ses_hmouter[i];
1162
1163 HTOLE32(ctx.pc_hminner[i]);
1164 HTOLE32(ctx.pc_hmouter[i]);
1165 }
1166 }
1167
1168 if (enccrd && maccrd) {
1169 /*
1170 * ubsec cannot handle packets where the end of encryption
1171 * and authentication are not the same, or where the
1172 * encrypted part begins before the authenticated part.
1173 */
1174 if ((encoffset + enccrd->crd_len) !=
1175 (macoffset + maccrd->crd_len)) {
1176 ubsecstats.hst_lenmismatch++;
1177 err = EINVAL;
1178 goto errout;
1179 }
1180 if (enccrd->crd_skip < maccrd->crd_skip) {
1181 ubsecstats.hst_skipmismatch++;
1182 err = EINVAL;
1183 goto errout;
1184 }
1185 sskip = maccrd->crd_skip;
1186 cpskip = dskip = enccrd->crd_skip;
1187 stheend = maccrd->crd_len;
1188 dtheend = enccrd->crd_len;
1189 coffset = enccrd->crd_skip - maccrd->crd_skip;
1190 cpoffset = cpskip + dtheend;
1191 #ifdef UBSEC_DEBUG
1192 if (ubsec_debug) {
1193 kprintf("mac: skip %d, len %d, inject %d\n",
1194 maccrd->crd_skip, maccrd->crd_len, maccrd->crd_inject);
1195 kprintf("enc: skip %d, len %d, inject %d\n",
1196 enccrd->crd_skip, enccrd->crd_len, enccrd->crd_inject);
1197 kprintf("src: skip %d, len %d\n", sskip, stheend);
1198 kprintf("dst: skip %d, len %d\n", dskip, dtheend);
1199 kprintf("ubs: coffset %d, pktlen %d, cpskip %d, cpoffset %d\n",
1200 coffset, stheend, cpskip, cpoffset);
1201 }
1202 #endif
1203 } else {
1204 cpskip = dskip = sskip = macoffset + encoffset;
1205 dtheend = stheend = (enccrd)?enccrd->crd_len:maccrd->crd_len;
1206 cpoffset = cpskip + dtheend;
1207 coffset = 0;
1208 }
1209 ctx.pc_offset = htole16(coffset >> 2);
1210
1211 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &q->q_src_map)) {
1212 ubsecstats.hst_nomap++;
1213 err = ENOMEM;
1214 goto errout;
1215 }
1216 if (crp->crp_flags & CRYPTO_F_IMBUF) {
1217 if (bus_dmamap_load_mbuf(sc->sc_dmat, q->q_src_map,
1218 q->q_src_m, ubsec_op_cb, &q->q_src, BUS_DMA_NOWAIT) != 0) {
1219 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map);
1220 q->q_src_map = NULL;
1221 ubsecstats.hst_noload++;
1222 err = ENOMEM;
1223 goto errout;
1224 }
1225 } else if (crp->crp_flags & CRYPTO_F_IOV) {
1226 if (bus_dmamap_load_uio(sc->sc_dmat, q->q_src_map,
1227 q->q_src_io, ubsec_op_cb, &q->q_src, BUS_DMA_NOWAIT) != 0) {
1228 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map);
1229 q->q_src_map = NULL;
1230 ubsecstats.hst_noload++;
1231 err = ENOMEM;
1232 goto errout;
1233 }
1234 }
1235 nicealign = ubsec_dmamap_aligned(&q->q_src);
1236
1237 dmap->d_dma->d_mcr.mcr_pktlen = htole16(stheend);
1238
1239 #ifdef UBSEC_DEBUG
1240 if (ubsec_debug)
1241 kprintf("src skip: %d nicealign: %u\n", sskip, nicealign);
1242 #endif
1243 for (i = j = 0; i < q->q_src_nsegs; i++) {
1244 struct ubsec_pktbuf *pb;
1245 bus_size_t packl = q->q_src_segs[i].ds_len;
1246 bus_addr_t packp = q->q_src_segs[i].ds_addr;
1247
1248 if (sskip >= packl) {
1249 sskip -= packl;
1250 continue;
1251 }
1252
1253 packl -= sskip;
1254 packp += sskip;
1255 sskip = 0;
1256
1257 if (packl > 0xfffc) {
1258 err = EIO;
1259 goto errout;
1260 }
1261
1262 if (j == 0)
1263 pb = &dmap->d_dma->d_mcr.mcr_ipktbuf;
1264 else
1265 pb = &dmap->d_dma->d_sbuf[j - 1];
1266
1267 pb->pb_addr = htole32(packp);
1268
1269 if (stheend) {
1270 if (packl > stheend) {
1271 pb->pb_len = htole32(stheend);
1272 stheend = 0;
1273 } else {
1274 pb->pb_len = htole32(packl);
1275 stheend -= packl;
1276 }
1277 } else
1278 pb->pb_len = htole32(packl);
1279
1280 if ((i + 1) == q->q_src_nsegs)
1281 pb->pb_next = 0;
1282 else
1283 pb->pb_next = htole32(dmap->d_alloc.dma_paddr +
1284 offsetof(struct ubsec_dmachunk, d_sbuf[j]));
1285 j++;
1286 }
1287
1288 if (enccrd == NULL && maccrd != NULL) {
1289 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr = 0;
1290 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len = 0;
1291 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next = htole32(dmap->d_alloc.dma_paddr +
1292 offsetof(struct ubsec_dmachunk, d_macbuf[0]));
1293 #ifdef UBSEC_DEBUG
1294 if (ubsec_debug)
1295 kprintf("opkt: %x %x %x\n",
1296 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr,
1297 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len,
1298 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next);
1299 #endif
1300 } else {
1301 if (crp->crp_flags & CRYPTO_F_IOV) {
1302 if (!nicealign) {
1303 ubsecstats.hst_iovmisaligned++;
1304 err = EINVAL;
1305 goto errout;
1306 }
1307 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT,
1308 &q->q_dst_map)) {
1309 ubsecstats.hst_nomap++;
1310 err = ENOMEM;
1311 goto errout;
1312 }
1313 if (bus_dmamap_load_uio(sc->sc_dmat, q->q_dst_map,
1314 q->q_dst_io, ubsec_op_cb, &q->q_dst, BUS_DMA_NOWAIT) != 0) {
1315 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map);
1316 q->q_dst_map = NULL;
1317 ubsecstats.hst_noload++;
1318 err = ENOMEM;
1319 goto errout;
1320 }
1321 } else if (crp->crp_flags & CRYPTO_F_IMBUF) {
1322 if (nicealign) {
1323 q->q_dst = q->q_src;
1324 } else {
1325 int totlen, len;
1326 struct mbuf *m, *top, **mp;
1327
1328 ubsecstats.hst_unaligned++;
1329 totlen = q->q_src_mapsize;
1330 if (q->q_src_m->m_flags & M_PKTHDR) {
1331 len = MHLEN;
1332 MGETHDR(m, MB_DONTWAIT, MT_DATA);
1333 if (m && !m_dup_pkthdr(m, q->q_src_m, MB_DONTWAIT)) {
1334 m_free(m);
1335 m = NULL;
1336 }
1337 } else {
1338 len = MLEN;
1339 MGET(m, MB_DONTWAIT, MT_DATA);
1340 }
1341 if (m == NULL) {
1342 ubsecstats.hst_nombuf++;
1343 err = sc->sc_nqueue ? ERESTART : ENOMEM;
1344 goto errout;
1345 }
1346 if (totlen >= MINCLSIZE) {
1347 MCLGET(m, MB_DONTWAIT);
1348 if ((m->m_flags & M_EXT) == 0) {
1349 m_free(m);
1350 ubsecstats.hst_nomcl++;
1351 err = sc->sc_nqueue ? ERESTART : ENOMEM;
1352 goto errout;
1353 }
1354 len = MCLBYTES;
1355 }
1356 m->m_len = len;
1357 top = NULL;
1358 mp = &top;
1359
1360 while (totlen > 0) {
1361 if (top) {
1362 MGET(m, MB_DONTWAIT, MT_DATA);
1363 if (m == NULL) {
1364 m_freem(top);
1365 ubsecstats.hst_nombuf++;
1366 err = sc->sc_nqueue ? ERESTART : ENOMEM;
1367 goto errout;
1368 }
1369 len = MLEN;
1370 }
1371 if (top && totlen >= MINCLSIZE) {
1372 MCLGET(m, MB_DONTWAIT);
1373 if ((m->m_flags & M_EXT) == 0) {
1374 *mp = m;
1375 m_freem(top);
1376 ubsecstats.hst_nomcl++;
1377 err = sc->sc_nqueue ? ERESTART : ENOMEM;
1378 goto errout;
1379 }
1380 len = MCLBYTES;
1381 }
1382 m->m_len = len = min(totlen, len);
1383 totlen -= len;
1384 *mp = m;
1385 mp = &m->m_next;
1386 }
1387 q->q_dst_m = top;
1388 ubsec_mcopy(q->q_src_m, q->q_dst_m,
1389 cpskip, cpoffset);
1390 if (bus_dmamap_create(sc->sc_dmat,
1391 BUS_DMA_NOWAIT, &q->q_dst_map) != 0) {
1392 ubsecstats.hst_nomap++;
1393 err = ENOMEM;
1394 goto errout;
1395 }
1396 if (bus_dmamap_load_mbuf(sc->sc_dmat,
1397 q->q_dst_map, q->q_dst_m,
1398 ubsec_op_cb, &q->q_dst,
1399 BUS_DMA_NOWAIT) != 0) {
1400 bus_dmamap_destroy(sc->sc_dmat,
1401 q->q_dst_map);
1402 q->q_dst_map = NULL;
1403 ubsecstats.hst_noload++;
1404 err = ENOMEM;
1405 goto errout;
1406 }
1407 }
1408 } else {
1409 ubsecstats.hst_badflags++;
1410 err = EINVAL;
1411 goto errout;
1412 }
1413
1414 #ifdef UBSEC_DEBUG
1415 if (ubsec_debug)
1416 kprintf("dst skip: %d\n", dskip);
1417 #endif
1418 for (i = j = 0; i < q->q_dst_nsegs; i++) {
1419 struct ubsec_pktbuf *pb;
1420 bus_size_t packl = q->q_dst_segs[i].ds_len;
1421 bus_addr_t packp = q->q_dst_segs[i].ds_addr;
1422
1423 if (dskip >= packl) {
1424 dskip -= packl;
1425 continue;
1426 }
1427
1428 packl -= dskip;
1429 packp += dskip;
1430 dskip = 0;
1431
1432 if (packl > 0xfffc) {
1433 err = EIO;
1434 goto errout;
1435 }
1436
1437 if (j == 0)
1438 pb = &dmap->d_dma->d_mcr.mcr_opktbuf;
1439 else
1440 pb = &dmap->d_dma->d_dbuf[j - 1];
1441
1442 pb->pb_addr = htole32(packp);
1443
1444 if (dtheend) {
1445 if (packl > dtheend) {
1446 pb->pb_len = htole32(dtheend);
1447 dtheend = 0;
1448 } else {
1449 pb->pb_len = htole32(packl);
1450 dtheend -= packl;
1451 }
1452 } else
1453 pb->pb_len = htole32(packl);
1454
1455 if ((i + 1) == q->q_dst_nsegs) {
1456 if (maccrd)
1457 pb->pb_next = htole32(dmap->d_alloc.dma_paddr +
1458 offsetof(struct ubsec_dmachunk, d_macbuf[0]));
1459 else
1460 pb->pb_next = 0;
1461 } else
1462 pb->pb_next = htole32(dmap->d_alloc.dma_paddr +
1463 offsetof(struct ubsec_dmachunk, d_dbuf[j]));
1464 j++;
1465 }
1466 }
1467
1468 dmap->d_dma->d_mcr.mcr_cmdctxp = htole32(dmap->d_alloc.dma_paddr +
1469 offsetof(struct ubsec_dmachunk, d_ctx));
1470
1471 if (sc->sc_flags & UBS_FLAGS_LONGCTX) {
1472 struct ubsec_pktctx_long *ctxl;
1473
1474 ctxl = (struct ubsec_pktctx_long *)(dmap->d_alloc.dma_vaddr +
1475 offsetof(struct ubsec_dmachunk, d_ctx));
1476
1477 /* transform small context into long context */
1478 ctxl->pc_len = htole16(sizeof(struct ubsec_pktctx_long));
1479 ctxl->pc_type = htole16(UBS_PKTCTX_TYPE_IPSEC);
1480 ctxl->pc_flags = ctx.pc_flags;
1481 ctxl->pc_offset = ctx.pc_offset;
1482 for (i = 0; i < 6; i++)
1483 ctxl->pc_deskey[i] = ctx.pc_deskey[i];
1484 for (i = 0; i < 5; i++)
1485 ctxl->pc_hminner[i] = ctx.pc_hminner[i];
1486 for (i = 0; i < 5; i++)
1487 ctxl->pc_hmouter[i] = ctx.pc_hmouter[i];
1488 ctxl->pc_iv[0] = ctx.pc_iv[0];
1489 ctxl->pc_iv[1] = ctx.pc_iv[1];
1490 } else
1491 bcopy(&ctx, dmap->d_alloc.dma_vaddr +
1492 offsetof(struct ubsec_dmachunk, d_ctx),
1493 sizeof(struct ubsec_pktctx));
1494
1495 crit_enter();
1496 SIMPLEQ_INSERT_TAIL(&sc->sc_queue, q, q_next);
1497 sc->sc_nqueue++;
1498 ubsecstats.hst_ipackets++;
1499 ubsecstats.hst_ibytes += dmap->d_alloc.dma_size;
1500 if ((hint & CRYPTO_HINT_MORE) == 0 || sc->sc_nqueue >= UBS_MAX_AGGR)
1501 ubsec_feed(sc);
1502 crit_exit();
1503 return (0);
1504
1505 errout:
1506 if (q != NULL) {
1507 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m))
1508 m_freem(q->q_dst_m);
1509
1510 if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) {
1511 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map);
1512 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map);
1513 }
1514 if (q->q_src_map != NULL) {
1515 bus_dmamap_unload(sc->sc_dmat, q->q_src_map);
1516 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map);
1517 }
1518
1519 crit_enter();
1520 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next);
1521 crit_exit();
1522 }
1523 if (err != ERESTART) {
1524 crp->crp_etype = err;
1525 crypto_done(crp);
1526 } else {
1527 sc->sc_needwakeup |= CRYPTO_SYMQ;
1528 }
1529 return (err);
1530 }
1531
1532 static void
1533 ubsec_callback(struct ubsec_softc *sc, struct ubsec_q *q)
1534 {
1535 struct cryptop *crp = (struct cryptop *)q->q_crp;
1536 struct cryptodesc *crd;
1537 struct ubsec_dma *dmap = q->q_dma;
1538
1539 ubsecstats.hst_opackets++;
1540 ubsecstats.hst_obytes += dmap->d_alloc.dma_size;
1541
1542 ubsec_dma_sync(&dmap->d_alloc,
1543 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1544 if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) {
1545 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map,
1546 BUS_DMASYNC_POSTREAD);
1547 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map);
1548 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map);
1549 }
1550 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_POSTWRITE);
1551 bus_dmamap_unload(sc->sc_dmat, q->q_src_map);
1552 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map);
1553
1554 if ((crp->crp_flags & CRYPTO_F_IMBUF) && (q->q_src_m != q->q_dst_m)) {
1555 m_freem(q->q_src_m);
1556 crp->crp_buf = (caddr_t)q->q_dst_m;
1557 }
1558 ubsecstats.hst_obytes += ((struct mbuf *)crp->crp_buf)->m_len;
1559
1560 /* copy out IV for future use */
1561 if (q->q_flags & UBSEC_QFLAGS_COPYOUTIV) {
1562 for (crd = crp->crp_desc; crd; crd = crd->crd_next) {
1563 if (crd->crd_alg != CRYPTO_DES_CBC &&
1564 crd->crd_alg != CRYPTO_3DES_CBC)
1565 continue;
1566 if (crp->crp_flags & CRYPTO_F_IMBUF)
1567 m_copydata((struct mbuf *)crp->crp_buf,
1568 crd->crd_skip + crd->crd_len - 8, 8,
1569 (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv);
1570 else if (crp->crp_flags & CRYPTO_F_IOV) {
1571 cuio_copydata((struct uio *)crp->crp_buf,
1572 crd->crd_skip + crd->crd_len - 8, 8,
1573 (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv);
1574 }
1575 break;
1576 }
1577 }
1578
1579 for (crd = crp->crp_desc; crd; crd = crd->crd_next) {
1580 if (crd->crd_alg != CRYPTO_MD5_HMAC &&
1581 crd->crd_alg != CRYPTO_SHA1_HMAC)
1582 continue;
1583 if (crp->crp_flags & CRYPTO_F_IMBUF)
1584 m_copyback((struct mbuf *)crp->crp_buf,
1585 crd->crd_inject, 12,
1586 (caddr_t)dmap->d_dma->d_macbuf);
1587 else if (crp->crp_flags & CRYPTO_F_IOV && crp->crp_mac)
1588 bcopy((caddr_t)dmap->d_dma->d_macbuf,
1589 crp->crp_mac, 12);
1590 break;
1591 }
1592 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next);
1593 crypto_done(crp);
1594 }
1595
1596 static void
1597 ubsec_mcopy(struct mbuf *srcm, struct mbuf *dstm, int hoffset, int toffset)
1598 {
1599 int i, j, dlen, slen;
1600 caddr_t dptr, sptr;
1601
1602 j = 0;
1603 sptr = srcm->m_data;
1604 slen = srcm->m_len;
1605 dptr = dstm->m_data;
1606 dlen = dstm->m_len;
1607
1608 while (1) {
1609 for (i = 0; i < min(slen, dlen); i++) {
1610 if (j < hoffset || j >= toffset)
1611 *dptr++ = *sptr++;
1612 slen--;
1613 dlen--;
1614 j++;
1615 }
1616 if (slen == 0) {
1617 srcm = srcm->m_next;
1618 if (srcm == NULL)
1619 return;
1620 sptr = srcm->m_data;
1621 slen = srcm->m_len;
1622 }
1623 if (dlen == 0) {
1624 dstm = dstm->m_next;
1625 if (dstm == NULL)
1626 return;
1627 dptr = dstm->m_data;
1628 dlen = dstm->m_len;
1629 }
1630 }
1631 }
1632
1633 /*
1634 * feed the key generator, must be called at splimp() or higher.
1635 */
1636 static int
1637 ubsec_feed2(struct ubsec_softc *sc)
1638 {
1639 struct ubsec_q2 *q;
1640
1641 while (!SIMPLEQ_EMPTY(&sc->sc_queue2)) {
1642 if (READ_REG(sc, BS_STAT) & BS_STAT_MCR2_FULL)
1643 break;
1644 q = SIMPLEQ_FIRST(&sc->sc_queue2);
1645
1646 ubsec_dma_sync(&q->q_mcr,
1647 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1648 ubsec_dma_sync(&q->q_ctx, BUS_DMASYNC_PREWRITE);
1649
1650 WRITE_REG(sc, BS_MCR2, q->q_mcr.dma_paddr);
1651 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue2, q_next);
1652 --sc->sc_nqueue2;
1653 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip2, q, q_next);
1654 }
1655 return (0);
1656 }
1657
1658 /*
1659 * Callback for handling random numbers
1660 */
1661 static void
1662 ubsec_callback2(struct ubsec_softc *sc, struct ubsec_q2 *q)
1663 {
1664 struct cryptkop *krp;
1665 struct ubsec_ctx_keyop *ctx;
1666
1667 ctx = (struct ubsec_ctx_keyop *)q->q_ctx.dma_vaddr;
1668 ubsec_dma_sync(&q->q_ctx, BUS_DMASYNC_POSTWRITE);
1669
1670 switch (q->q_type) {
1671 #ifndef UBSEC_NO_RNG
1672 case UBS_CTXOP_RNGBYPASS: {
1673 struct ubsec_q2_rng *rng = (struct ubsec_q2_rng *)q;
1674
1675 ubsec_dma_sync(&rng->rng_buf, BUS_DMASYNC_POSTREAD);
1676 (*sc->sc_harvest)(sc->sc_rndtest,
1677 rng->rng_buf.dma_vaddr,
1678 UBSEC_RNG_BUFSIZ*sizeof (u_int32_t));
1679 rng->rng_used = 0;
1680 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc);
1681 break;
1682 }
1683 #endif
1684 case UBS_CTXOP_MODEXP: {
1685 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q;
1686 u_int rlen, clen;
1687
1688 krp = me->me_krp;
1689 rlen = (me->me_modbits + 7) / 8;
1690 clen = (krp->krp_param[krp->krp_iparams].crp_nbits + 7) / 8;
1691
1692 ubsec_dma_sync(&me->me_M, BUS_DMASYNC_POSTWRITE);
1693 ubsec_dma_sync(&me->me_E, BUS_DMASYNC_POSTWRITE);
1694 ubsec_dma_sync(&me->me_C, BUS_DMASYNC_POSTREAD);
1695 ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_POSTWRITE);
1696
1697 if (clen < rlen)
1698 krp->krp_status = E2BIG;
1699 else {
1700 if (sc->sc_flags & UBS_FLAGS_HWNORM) {
1701 bzero(krp->krp_param[krp->krp_iparams].crp_p,
1702 (krp->krp_param[krp->krp_iparams].crp_nbits
1703 + 7) / 8);
1704 bcopy(me->me_C.dma_vaddr,
1705 krp->krp_param[krp->krp_iparams].crp_p,
1706 (me->me_modbits + 7) / 8);
1707 } else
1708 ubsec_kshift_l(me->me_shiftbits,
1709 me->me_C.dma_vaddr, me->me_normbits,
1710 krp->krp_param[krp->krp_iparams].crp_p,
1711 krp->krp_param[krp->krp_iparams].crp_nbits);
1712 }
1713
1714 crypto_kdone(krp);
1715
1716 /* bzero all potentially sensitive data */
1717 bzero(me->me_E.dma_vaddr, me->me_E.dma_size);
1718 bzero(me->me_M.dma_vaddr, me->me_M.dma_size);
1719 bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
1720 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size);
1721
1722 /* Can't free here, so put us on the free list. */
1723 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &me->me_q, q_next);
1724 break;
1725 }
1726 case UBS_CTXOP_RSAPRIV: {
1727 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q;
1728 u_int len;
1729
1730 krp = rp->rpr_krp;
1731 ubsec_dma_sync(&rp->rpr_msgin, BUS_DMASYNC_POSTWRITE);
1732 ubsec_dma_sync(&rp->rpr_msgout, BUS_DMASYNC_POSTREAD);
1733
1734 len = (krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_nbits + 7) / 8;
1735 bcopy(rp->rpr_msgout.dma_vaddr,
1736 krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_p, len);
1737
1738 crypto_kdone(krp);
1739
1740 bzero(rp->rpr_msgin.dma_vaddr, rp->rpr_msgin.dma_size);
1741 bzero(rp->rpr_msgout.dma_vaddr, rp->rpr_msgout.dma_size);
1742 bzero(rp->rpr_q.q_ctx.dma_vaddr, rp->rpr_q.q_ctx.dma_size);
1743
1744 /* Can't free here, so put us on the free list. */
1745 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &rp->rpr_q, q_next);
1746 break;
1747 }
1748 default:
1749 device_printf(sc->sc_dev, "unknown ctx op: %x\n",
1750 letoh16(ctx->ctx_op));
1751 break;
1752 }
1753 }
1754
1755 #ifndef UBSEC_NO_RNG
1756 static void
1757 ubsec_rng(void *vsc)
1758 {
1759 struct ubsec_softc *sc = vsc;
1760 struct ubsec_q2_rng *rng = &sc->sc_rng;
1761 struct ubsec_mcr *mcr;
1762 struct ubsec_ctx_rngbypass *ctx;
1763
1764 crit_enter();
1765 if (rng->rng_used) {
1766 crit_exit();
1767 return;
1768 }
1769 sc->sc_nqueue2++;
1770 if (sc->sc_nqueue2 >= UBS_MAX_NQUEUE)
1771 goto out;
1772
1773 mcr = (struct ubsec_mcr *)rng->rng_q.q_mcr.dma_vaddr;
1774 ctx = (struct ubsec_ctx_rngbypass *)rng->rng_q.q_ctx.dma_vaddr;
1775
1776 mcr->mcr_pkts = htole16(1);
1777 mcr->mcr_flags = 0;
1778 mcr->mcr_cmdctxp = htole32(rng->rng_q.q_ctx.dma_paddr);
1779 mcr->mcr_ipktbuf.pb_addr = mcr->mcr_ipktbuf.pb_next = 0;
1780 mcr->mcr_ipktbuf.pb_len = 0;
1781 mcr->mcr_reserved = mcr->mcr_pktlen = 0;
1782 mcr->mcr_opktbuf.pb_addr = htole32(rng->rng_buf.dma_paddr);
1783 mcr->mcr_opktbuf.pb_len = htole32(((sizeof(u_int32_t) * UBSEC_RNG_BUFSIZ)) &
1784 UBS_PKTBUF_LEN);
1785 mcr->mcr_opktbuf.pb_next = 0;
1786
1787 ctx->rbp_len = htole16(sizeof(struct ubsec_ctx_rngbypass));
1788 ctx->rbp_op = htole16(UBS_CTXOP_RNGBYPASS);
1789 rng->rng_q.q_type = UBS_CTXOP_RNGBYPASS;
1790
1791 ubsec_dma_sync(&rng->rng_buf, BUS_DMASYNC_PREREAD);
1792
1793 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rng->rng_q, q_next);
1794 rng->rng_used = 1;
1795 ubsec_feed2(sc);
1796 ubsecstats.hst_rng++;
1797 crit_exit();
1798
1799 return;
1800
1801 out:
1802 /*
1803 * Something weird happened, generate our own call back.
1804 */
1805 sc->sc_nqueue2--;
1806 crit_exit();
1807 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc);
1808 }
1809 #endif /* UBSEC_NO_RNG */
1810
1811 static void
1812 ubsec_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1813 {
1814 bus_addr_t *paddr = (bus_addr_t*) arg;
1815 *paddr = segs->ds_addr;
1816 }
1817
1818 static int
1819 ubsec_dma_malloc(
1820 struct ubsec_softc *sc,
1821 bus_size_t size,
1822 struct ubsec_dma_alloc *dma,
1823 int mapflags
1824 )
1825 {
1826 int r;
1827
1828 /* XXX could specify sc_dmat as parent but that just adds overhead */
1829 r = bus_dma_tag_create(NULL, /* parent */
1830 1, 0, /* alignment, bounds */
1831 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1832 BUS_SPACE_MAXADDR, /* highaddr */
1833 NULL, NULL, /* filter, filterarg */
1834 size, /* maxsize */
1835 1, /* nsegments */
1836 size, /* maxsegsize */
1837 BUS_DMA_ALLOCNOW, /* flags */
1838 &dma->dma_tag);
1839 if (r != 0) {
1840 device_printf(sc->sc_dev, "ubsec_dma_malloc: "
1841 "bus_dma_tag_create failed; error %u\n", r);
1842 goto fail_0;
1843 }
1844
1845 r = bus_dmamap_create(dma->dma_tag, BUS_DMA_NOWAIT, &dma->dma_map);
1846 if (r != 0) {
1847 device_printf(sc->sc_dev, "ubsec_dma_malloc: "
1848 "bus_dmamap_create failed; error %u\n", r);
1849 goto fail_1;
1850 }
1851
1852 r = bus_dmamem_alloc(dma->dma_tag, (void**) &dma->dma_vaddr,
1853 BUS_DMA_NOWAIT, &dma->dma_map);
1854 if (r != 0) {
1855 device_printf(sc->sc_dev, "ubsec_dma_malloc: "
1856 "bus_dmammem_alloc failed; size %ju, error %u\n",
1857 (intmax_t)size, r);
1858 goto fail_2;
1859 }
1860
1861 r = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr,
1862 size,
1863 ubsec_dmamap_cb,
1864 &dma->dma_paddr,
1865 mapflags | BUS_DMA_NOWAIT);
1866 if (r != 0) {
1867 device_printf(sc->sc_dev, "ubsec_dma_malloc: "
1868 "bus_dmamap_load failed; error %u\n", r);
1869 goto fail_3;
1870 }
1871
1872 dma->dma_size = size;
1873 return (0);
1874
1875 fail_3:
1876 bus_dmamap_unload(dma->dma_tag, dma->dma_map);
1877 fail_2:
1878 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
1879 fail_1:
1880 bus_dmamap_destroy(dma->dma_tag, dma->dma_map);
1881 bus_dma_tag_destroy(dma->dma_tag);
1882 fail_0:
1883 dma->dma_map = NULL;
1884 dma->dma_tag = NULL;
1885 return (r);
1886 }
1887
1888 static void
1889 ubsec_dma_free(struct ubsec_softc *sc, struct ubsec_dma_alloc *dma)
1890 {
1891 bus_dmamap_unload(dma->dma_tag, dma->dma_map);
1892 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
1893 bus_dmamap_destroy(dma->dma_tag, dma->dma_map);
1894 bus_dma_tag_destroy(dma->dma_tag);
1895 }
1896
1897 /*
1898 * Resets the board. Values in the regesters are left as is
1899 * from the reset (i.e. initial values are assigned elsewhere).
1900 */
1901 static void
1902 ubsec_reset_board(struct ubsec_softc *sc)
1903 {
1904 volatile u_int32_t ctrl;
1905
1906 ctrl = READ_REG(sc, BS_CTRL);
1907 ctrl |= BS_CTRL_RESET;
1908 WRITE_REG(sc, BS_CTRL, ctrl);
1909
1910 /*
1911 * Wait aprox. 30 PCI clocks = 900 ns = 0.9 us
1912 */
1913 DELAY(10);
1914 }
1915
1916 /*
1917 * Init Broadcom registers
1918 */
1919 static void
1920 ubsec_init_board(struct ubsec_softc *sc)
1921 {
1922 u_int32_t ctrl;
1923
1924 ctrl = READ_REG(sc, BS_CTRL);
1925 ctrl &= ~(BS_CTRL_BE32 | BS_CTRL_BE64);
1926 ctrl |= BS_CTRL_LITTLE_ENDIAN | BS_CTRL_MCR1INT;
1927
1928 if (sc->sc_flags & (UBS_FLAGS_KEY|UBS_FLAGS_RNG))
1929 ctrl |= BS_CTRL_MCR2INT;
1930 else
1931 ctrl &= ~BS_CTRL_MCR2INT;
1932
1933 if (sc->sc_flags & UBS_FLAGS_HWNORM)
1934 ctrl &= ~BS_CTRL_SWNORM;
1935
1936 WRITE_REG(sc, BS_CTRL, ctrl);
1937 }
1938
1939 /*
1940 * Init Broadcom PCI registers
1941 */
1942 static void
1943 ubsec_init_pciregs(device_t dev)
1944 {
1945 #if 0
1946 u_int32_t misc;
1947
1948 misc = pci_conf_read(pc, pa->pa_tag, BS_RTY_TOUT);
1949 misc = (misc & ~(UBS_PCI_RTY_MASK << UBS_PCI_RTY_SHIFT))
1950 | ((UBS_DEF_RTY & 0xff) << UBS_PCI_RTY_SHIFT);
1951 misc = (misc & ~(UBS_PCI_TOUT_MASK << UBS_PCI_TOUT_SHIFT))
1952 | ((UBS_DEF_TOUT & 0xff) << UBS_PCI_TOUT_SHIFT);
1953 pci_conf_write(pc, pa->pa_tag, BS_RTY_TOUT, misc);
1954 #endif
1955
1956 /*
1957 * This will set the cache line size to 1, this will
1958 * force the BCM58xx chip just to do burst read/writes.
1959 * Cache line read/writes are to slow
1960 */
1961 pci_write_config(dev, PCIR_CACHELNSZ, UBS_DEF_CACHELINE, 1);
1962 }
1963
1964 /*
1965 * Clean up after a chip crash.
1966 * It is assumed that the caller in splimp()
1967 */
1968 static void
1969 ubsec_cleanchip(struct ubsec_softc *sc)
1970 {
1971 struct ubsec_q *q;
1972
1973 while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) {
1974 q = SIMPLEQ_FIRST(&sc->sc_qchip);
1975 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q_next);
1976 ubsec_free_q(sc, q);
1977 }
1978 sc->sc_nqchip = 0;
1979 }
1980
1981 /*
1982 * free a ubsec_q
1983 * It is assumed that the caller is within spimp()
1984 */
1985 static int
1986 ubsec_free_q(struct ubsec_softc *sc, struct ubsec_q *q)
1987 {
1988 struct ubsec_q *q2;
1989 struct cryptop *crp;
1990 int npkts;
1991 int i;
1992
1993 npkts = q->q_nstacked_mcrs;
1994
1995 for (i = 0; i < npkts; i++) {
1996 if(q->q_stacked_mcr[i]) {
1997 q2 = q->q_stacked_mcr[i];
1998
1999 if ((q2->q_dst_m != NULL) && (q2->q_src_m != q2->q_dst_m))
2000 m_freem(q2->q_dst_m);
2001
2002 crp = (struct cryptop *)q2->q_crp;
2003
2004 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q2, q_next);
2005
2006 crp->crp_etype = EFAULT;
2007 crypto_done(crp);
2008 } else {
2009 break;
2010 }
2011 }
2012
2013 /*
2014 * Free header MCR
2015 */
2016 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m))
2017 m_freem(q->q_dst_m);
2018
2019 crp = (struct cryptop *)q->q_crp;
2020
2021 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next);
2022
2023 crp->crp_etype = EFAULT;
2024 crypto_done(crp);
2025 return(0);
2026 }
2027
2028 /*
2029 * Routine to reset the chip and clean up.
2030 * It is assumed that the caller is in splimp()
2031 */
2032 static void
2033 ubsec_totalreset(struct ubsec_softc *sc)
2034 {
2035 ubsec_reset_board(sc);
2036 ubsec_init_board(sc);
2037 ubsec_cleanchip(sc);
2038 }
2039
2040 static int
2041 ubsec_dmamap_aligned(struct ubsec_operand *op)
2042 {
2043 int i;
2044
2045 for (i = 0; i < op->nsegs; i++) {
2046 if (op->segs[i].ds_addr & 3)
2047 return (0);
2048 if ((i != (op->nsegs - 1)) &&
2049 (op->segs[i].ds_len & 3))
2050 return (0);
2051 }
2052 return (1);
2053 }
2054
2055 static void
2056 ubsec_kfree(struct ubsec_softc *sc, struct ubsec_q2 *q)
2057 {
2058 switch (q->q_type) {
2059 case UBS_CTXOP_MODEXP: {
2060 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q;
2061
2062 ubsec_dma_free(sc, &me->me_q.q_mcr);
2063 ubsec_dma_free(sc, &me->me_q.q_ctx);
2064 ubsec_dma_free(sc, &me->me_M);
2065 ubsec_dma_free(sc, &me->me_E);
2066 ubsec_dma_free(sc, &me->me_C);
2067 ubsec_dma_free(sc, &me->me_epb);
2068 kfree(me, M_DEVBUF);
2069 break;
2070 }
2071 case UBS_CTXOP_RSAPRIV: {
2072 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q;
2073
2074 ubsec_dma_free(sc, &rp->rpr_q.q_mcr);
2075 ubsec_dma_free(sc, &rp->rpr_q.q_ctx);
2076 ubsec_dma_free(sc, &rp->rpr_msgin);
2077 ubsec_dma_free(sc, &rp->rpr_msgout);
2078 kfree(rp, M_DEVBUF);
2079 break;
2080 }
2081 default:
2082 device_printf(sc->sc_dev, "invalid kfree 0x%x\n", q->q_type);
2083 break;
2084 }
2085 }
2086
2087 static int
2088 ubsec_kprocess(void *arg, struct cryptkop *krp, int hint)
2089 {
2090 struct ubsec_softc *sc = arg;
2091 int r;
2092
2093 if (krp == NULL || krp->krp_callback == NULL)
2094 return (EINVAL);
2095
2096 while (!SIMPLEQ_EMPTY(&sc->sc_q2free)) {
2097 struct ubsec_q2 *q;
2098
2099 q = SIMPLEQ_FIRST(&sc->sc_q2free);
2100 SIMPLEQ_REMOVE_HEAD(&sc->sc_q2free, q_next);
2101 ubsec_kfree(sc, q);
2102 }
2103
2104 switch (krp->krp_op) {
2105 case CRK_MOD_EXP:
2106 if (sc->sc_flags & UBS_FLAGS_HWNORM)
2107 r = ubsec_kprocess_modexp_hw(sc, krp, hint);
2108 else
2109 r = ubsec_kprocess_modexp_sw(sc, krp, hint);
2110 break;
2111 case CRK_MOD_EXP_CRT:
2112 return (ubsec_kprocess_rsapriv(sc, krp, hint));
2113 default:
2114 device_printf(sc->sc_dev, "kprocess: invalid op 0x%x\n",
2115 krp->krp_op);
2116 krp->krp_status = EOPNOTSUPP;
2117 crypto_kdone(krp);
2118 return (0);
2119 }
2120 return (0); /* silence compiler */
2121 }
2122
2123 /*
2124 * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (sw normalization)
2125 */
2126 static int
2127 ubsec_kprocess_modexp_sw(struct ubsec_softc *sc, struct cryptkop *krp, int hint)
2128 {
2129 struct ubsec_q2_modexp *me;
2130 struct ubsec_mcr *mcr;
2131 struct ubsec_ctx_modexp *ctx;
2132 struct ubsec_pktbuf *epb;
2133 int err = 0;
2134 u_int nbits, normbits, mbits, shiftbits, ebits;
2135
2136 me = kmalloc(sizeof *me, M_DEVBUF, M_INTWAIT | M_ZERO);
2137 me->me_krp = krp;
2138 me->me_q.q_type = UBS_CTXOP_MODEXP;
2139
2140 nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]);
2141 if (nbits <= 512)
2142 normbits = 512;
2143 else if (nbits <= 768)
2144 normbits = 768;
2145 else if (nbits <= 1024)
2146 normbits = 1024;
2147 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536)
2148 normbits = 1536;
2149 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048)
2150 normbits = 2048;
2151 else {
2152 err = E2BIG;
2153 goto errout;
2154 }
2155
2156 shiftbits = normbits - nbits;
2157
2158 me->me_modbits = nbits;
2159 me->me_shiftbits = shiftbits;
2160 me->me_normbits = normbits;
2161
2162 /* Sanity check: result bits must be >= true modulus bits. */
2163 if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) {
2164 err = ERANGE;
2165 goto errout;
2166 }
2167
2168 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr),
2169 &me->me_q.q_mcr, 0)) {
2170 err = ENOMEM;
2171 goto errout;
2172 }
2173 mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr;
2174
2175 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp),
2176 &me->me_q.q_ctx, 0)) {
2177 err = ENOMEM;
2178 goto errout;
2179 }
2180
2181 mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]);
2182 if (mbits > nbits) {
2183 err = E2BIG;
2184 goto errout;
2185 }
2186 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) {
2187 err = ENOMEM;
2188 goto errout;
2189 }
2190 ubsec_kshift_r(shiftbits,
2191 krp->krp_param[UBS_MODEXP_PAR_M].crp_p, mbits,
2192 me->me_M.dma_vaddr, normbits);
2193
2194 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) {
2195 err = ENOMEM;
2196 goto errout;
2197 }
2198 bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
2199
2200 ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]);
2201 if (ebits > nbits) {
2202 err = E2BIG;
2203 goto errout;
2204 }
2205 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) {
2206 err = ENOMEM;
2207 goto errout;
2208 }
2209 ubsec_kshift_r(shiftbits,
2210 krp->krp_param[UBS_MODEXP_PAR_E].crp_p, ebits,
2211 me->me_E.dma_vaddr, normbits);
2212
2213 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf),
2214 &me->me_epb, 0)) {
2215 err = ENOMEM;
2216 goto errout;
2217 }
2218 epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr;
2219 epb->pb_addr = htole32(me->me_E.dma_paddr);
2220 epb->pb_next = 0;
2221 epb->pb_len = htole32(normbits / 8);
2222
2223 #ifdef UBSEC_DEBUG
2224 if (ubsec_debug) {
2225 kprintf("Epb ");
2226 ubsec_dump_pb(epb);
2227 }
2228 #endif
2229
2230 mcr->mcr_pkts = htole16(1);
2231 mcr->mcr_flags = 0;
2232 mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr);
2233 mcr->mcr_reserved = 0;
2234 mcr->mcr_pktlen = 0;
2235
2236 mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr);
2237 mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8);
2238 mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr);
2239
2240 mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr);
2241 mcr->mcr_opktbuf.pb_next = 0;
2242 mcr->mcr_opktbuf.pb_len = htole32(normbits / 8);
2243
2244 #ifdef DIAGNOSTIC
2245 /* Misaligned output buffer will hang the chip. */
2246 if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0)
2247 panic("%s: modexp invalid addr 0x%x\n",
2248 device_get_nameunit(sc->sc_dev),
2249 letoh32(mcr->mcr_opktbuf.pb_addr));
2250 if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0)
2251 panic("%s: modexp invalid len 0x%x\n",
2252 device_get_nameunit(sc->sc_dev),
2253 letoh32(mcr->mcr_opktbuf.pb_len));
2254 #endif
2255
2256 ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr;
2257 bzero(ctx, sizeof(*ctx));
2258 ubsec_kshift_r(shiftbits,
2259 krp->krp_param[UBS_MODEXP_PAR_N].crp_p, nbits,
2260 ctx->me_N, normbits);
2261 ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t)));
2262 ctx->me_op = htole16(UBS_CTXOP_MODEXP);
2263 ctx->me_E_len = htole16(nbits);
2264 ctx->me_N_len = htole16(nbits);
2265
2266 #ifdef UBSEC_DEBUG
2267 if (ubsec_debug) {
2268 ubsec_dump_mcr(mcr);
2269 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx);
2270 }
2271 #endif
2272
2273 /*
2274 * ubsec_feed2 will sync mcr and ctx, we just need to sync
2275 * everything else.
2276 */
2277 ubsec_dma_sync(&me->me_M, BUS_DMASYNC_PREWRITE);
2278 ubsec_dma_sync(&me->me_E, BUS_DMASYNC_PREWRITE);
2279 ubsec_dma_sync(&me->me_C, BUS_DMASYNC_PREREAD);
2280 ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_PREWRITE);
2281
2282 /* Enqueue and we're done... */
2283 crit_enter();
2284 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next);
2285 ubsec_feed2(sc);
2286 ubsecstats.hst_modexp++;
2287 crit_exit();
2288
2289 return (0);
2290
2291 errout:
2292 if (me != NULL) {
2293 if (me->me_q.q_mcr.dma_map != NULL)
2294 ubsec_dma_free(sc, &me->me_q.q_mcr);
2295 if (me->me_q.q_ctx.dma_map != NULL) {
2296 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size);
2297 ubsec_dma_free(sc, &me->me_q.q_ctx);
2298 }
2299 if (me->me_M.dma_map != NULL) {
2300 bzero(me->me_M.dma_vaddr, me->me_M.dma_size);
2301 ubsec_dma_free(sc, &me->me_M);
2302 }
2303 if (me->me_E.dma_map != NULL) {
2304 bzero(me->me_E.dma_vaddr, me->me_E.dma_size);
2305 ubsec_dma_free(sc, &me->me_E);
2306 }
2307 if (me->me_C.dma_map != NULL) {
2308 bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
2309 ubsec_dma_free(sc, &me->me_C);
2310 }
2311 if (me->me_epb.dma_map != NULL)
2312 ubsec_dma_free(sc, &me->me_epb);
2313 kfree(me, M_DEVBUF);
2314 }
2315 krp->krp_status = err;
2316 crypto_kdone(krp);
2317 return (0);
2318 }
2319
2320 /*
2321 * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (hw normalization)
2322 */
2323 static int
2324 ubsec_kprocess_modexp_hw(struct ubsec_softc *sc, struct cryptkop *krp, int hint)
2325 {
2326 struct ubsec_q2_modexp *me;
2327 struct ubsec_mcr *mcr;
2328 struct ubsec_ctx_modexp *ctx;
2329 struct ubsec_pktbuf *epb;
2330 int err = 0;
2331 u_int nbits, normbits, mbits, shiftbits, ebits;
2332
2333 me = kmalloc(sizeof *me, M_DEVBUF, M_INTWAIT | M_ZERO);
2334 me->me_krp = krp;
2335 me->me_q.q_type = UBS_CTXOP_MODEXP;
2336
2337 nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]);
2338 if (nbits <= 512)
2339 normbits = 512;
2340 else if (nbits <= 768)
2341 normbits = 768;
2342 else if (nbits <= 1024)
2343 normbits = 1024;
2344 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536)
2345 normbits = 1536;
2346 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048)
2347 normbits = 2048;
2348 else {
2349 err = E2BIG;
2350 goto errout;
2351 }
2352
2353 shiftbits = normbits - nbits;
2354
2355 /* XXX ??? */
2356 me->me_modbits = nbits;
2357 me->me_shiftbits = shiftbits;
2358 me->me_normbits = normbits;
2359
2360 /* Sanity check: result bits must be >= true modulus bits. */
2361 if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) {
2362 err = ERANGE;
2363 goto errout;
2364 }
2365
2366 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr),
2367 &me->me_q.q_mcr, 0)) {
2368 err = ENOMEM;
2369 goto errout;
2370 }
2371 mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr;
2372
2373 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp),
2374 &me->me_q.q_ctx, 0)) {
2375 err = ENOMEM;
2376 goto errout;
2377 }
2378
2379 mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]);
2380 if (mbits > nbits) {
2381 err = E2BIG;
2382 goto errout;
2383 }
2384 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) {
2385 err = ENOMEM;
2386 goto errout;
2387 }
2388 bzero(me->me_M.dma_vaddr, normbits / 8);
2389 bcopy(krp->krp_param[UBS_MODEXP_PAR_M].crp_p,
2390 me->me_M.dma_vaddr, (mbits + 7) / 8);
2391
2392 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) {
2393 err = ENOMEM;
2394 goto errout;
2395 }
2396 bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
2397
2398 ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]);
2399 if (ebits > nbits) {
2400 err = E2BIG;
2401 goto errout;
2402 }
2403 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) {
2404 err = ENOMEM;
2405 goto errout;
2406 }
2407 bzero(me->me_E.dma_vaddr, normbits / 8);
2408 bcopy(krp->krp_param[UBS_MODEXP_PAR_E].crp_p,
2409 me->me_E.dma_vaddr, (ebits + 7) / 8);
2410
2411 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf),
2412 &me->me_epb, 0)) {
2413 err = ENOMEM;
2414 goto errout;
2415 }
2416 epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr;
2417 epb->pb_addr = htole32(me->me_E.dma_paddr);
2418 epb->pb_next = 0;
2419 epb->pb_len = htole32((ebits + 7) / 8);
2420
2421 #ifdef UBSEC_DEBUG
2422 if (ubsec_debug) {
2423 kprintf("Epb ");
2424 ubsec_dump_pb(epb);
2425 }
2426 #endif
2427
2428 mcr->mcr_pkts = htole16(1);
2429 mcr->mcr_flags = 0;
2430 mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr);
2431 mcr->mcr_reserved = 0;
2432 mcr->mcr_pktlen = 0;
2433
2434 mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr);
2435 mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8);
2436 mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr);
2437
2438 mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr);
2439 mcr->mcr_opktbuf.pb_next = 0;
2440 mcr->mcr_opktbuf.pb_len = htole32(normbits / 8);
2441
2442 #ifdef DIAGNOSTIC
2443 /* Misaligned output buffer will hang the chip. */
2444 if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0)
2445 panic("%s: modexp invalid addr 0x%x\n",
2446 device_get_nameunit(sc->sc_dev),
2447 letoh32(mcr->mcr_opktbuf.pb_addr));
2448 if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0)
2449 panic("%s: modexp invalid len 0x%x\n",
2450 device_get_nameunit(sc->sc_dev),
2451 letoh32(mcr->mcr_opktbuf.pb_len));
2452 #endif
2453
2454 ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr;
2455 bzero(ctx, sizeof(*ctx));
2456 bcopy(krp->krp_param[UBS_MODEXP_PAR_N].crp_p, ctx->me_N,
2457 (nbits + 7) / 8);
2458 ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t)));
2459 ctx->me_op = htole16(UBS_CTXOP_MODEXP);
2460 ctx->me_E_len = htole16(ebits);
2461 ctx->me_N_len = htole16(nbits);
2462
2463 #ifdef UBSEC_DEBUG
2464 if (ubsec_debug) {
2465 ubsec_dump_mcr(mcr);
2466 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx);
2467 }
2468 #endif
2469
2470 /*
2471 * ubsec_feed2 will sync mcr and ctx, we just need to sync
2472 * everything else.
2473 */
2474 ubsec_dma_sync(&me->me_M, BUS_DMASYNC_PREWRITE);
2475 ubsec_dma_sync(&me->me_E, BUS_DMASYNC_PREWRITE);
2476 ubsec_dma_sync(&me->me_C, BUS_DMASYNC_PREREAD);
2477 ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_PREWRITE);
2478
2479 /* Enqueue and we're done... */
2480 crit_enter();
2481 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next);
2482 ubsec_feed2(sc);
2483 crit_exit();
2484
2485 return (0);
2486
2487 errout:
2488 if (me != NULL) {
2489 if (me->me_q.q_mcr.dma_map != NULL)
2490 ubsec_dma_free(sc, &me->me_q.q_mcr);
2491 if (me->me_q.q_ctx.dma_map != NULL) {
2492 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size);
2493 ubsec_dma_free(sc, &me->me_q.q_ctx);
2494 }
2495 if (me->me_M.dma_map != NULL) {
2496 bzero(me->me_M.dma_vaddr, me->me_M.dma_size);
2497 ubsec_dma_free(sc, &me->me_M);
2498 }
2499 if (me->me_E.dma_map != NULL) {
2500 bzero(me->me_E.dma_vaddr, me->me_E.dma_size);
2501 ubsec_dma_free(sc, &me->me_E);
2502 }
2503 if (me->me_C.dma_map != NULL) {
2504 bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
2505 ubsec_dma_free(sc, &me->me_C);
2506 }
2507 if (me->me_epb.dma_map != NULL)
2508 ubsec_dma_free(sc, &me->me_epb);
2509 kfree(me, M_DEVBUF);
2510 }
2511 krp->krp_status = err;
2512 crypto_kdone(krp);
2513 return (0);
2514 }
2515
2516 static int
2517 ubsec_kprocess_rsapriv(struct ubsec_softc *sc, struct cryptkop *krp, int hint)
2518 {
2519 struct ubsec_q2_rsapriv *rp = NULL;
2520 struct ubsec_mcr *mcr;
2521 struct ubsec_ctx_rsapriv *ctx;
2522 int err = 0;
2523 u_int padlen, msglen;
2524
2525 msglen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_P]);
2526 padlen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_Q]);
2527 if (msglen > padlen)
2528 padlen = msglen;
2529
2530 if (padlen <= 256)
2531 padlen = 256;
2532 else if (padlen <= 384)
2533 padlen = 384;
2534 else if (padlen <= 512)
2535 padlen = 512;
2536 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 768)
2537 padlen = 768;
2538 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 1024)
2539 padlen = 1024;
2540 else {
2541 err = E2BIG;
2542 goto errout;
2543 }
2544
2545 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DP]) > padlen) {
2546 err = E2BIG;
2547 goto errout;
2548 }
2549
2550 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DQ]) > padlen) {
2551 err = E2BIG;
2552 goto errout;
2553 }
2554
2555 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_PINV]) > padlen) {
2556 err = E2BIG;
2557 goto errout;
2558 }
2559
2560 rp = kmalloc(sizeof *rp, M_DEVBUF, M_INTWAIT | M_ZERO);
2561 rp->rpr_krp = krp;
2562 rp->rpr_q.q_type = UBS_CTXOP_RSAPRIV;
2563
2564 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr),
2565 &rp->rpr_q.q_mcr, 0)) {
2566 err = ENOMEM;
2567 goto errout;
2568 }
2569 mcr = (struct ubsec_mcr *)rp->rpr_q.q_mcr.dma_vaddr;
2570
2571 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rsapriv),
2572 &rp->rpr_q.q_ctx, 0)) {
2573 err = ENOMEM;
2574 goto errout;
2575 }
2576 ctx = (struct ubsec_ctx_rsapriv *)rp->rpr_q.q_ctx.dma_vaddr;
2577 bzero(ctx, sizeof *ctx);
2578
2579 /* Copy in p */
2580 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_P].crp_p,
2581 &ctx->rpr_buf[0 * (padlen / 8)],
2582 (krp->krp_param[UBS_RSAPRIV_PAR_P].crp_nbits + 7) / 8);
2583
2584 /* Copy in q */
2585 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_p,
2586 &ctx->rpr_buf[1 * (padlen / 8)],
2587 (krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_nbits + 7) / 8);
2588
2589 /* Copy in dp */
2590 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_p,
2591 &ctx->rpr_buf[2 * (padlen / 8)],
2592 (krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_nbits + 7) / 8);
2593
2594 /* Copy in dq */
2595 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_p,
2596 &ctx->rpr_buf[3 * (padlen / 8)],
2597 (krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_nbits + 7) / 8);
2598
2599 /* Copy in pinv */
2600 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_p,
2601 &ctx->rpr_buf[4 * (padlen / 8)],
2602 (krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_nbits + 7) / 8);
2603
2604 msglen = padlen * 2;
2605
2606 /* Copy in input message (aligned buffer/length). */
2607 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGIN]) > msglen) {
2608 /* Is this likely? */
2609 err = E2BIG;
2610 goto errout;
2611 }
2612 if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgin, 0)) {
2613 err = ENOMEM;
2614 goto errout;
2615 }
2616 bzero(rp->rpr_msgin.dma_vaddr, (msglen + 7) / 8);
2617 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_p,
2618 rp->rpr_msgin.dma_vaddr,
2619 (krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_nbits + 7) / 8);
2620
2621 /* Prepare space for output message (aligned buffer/length). */
2622 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT]) < msglen) {
2623 /* Is this likely? */
2624 err = E2BIG;
2625 goto errout;
2626 }
2627 if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgout, 0)) {
2628 err = ENOMEM;
2629 goto errout;
2630 }
2631 bzero(rp->rpr_msgout.dma_vaddr, (msglen + 7) / 8);
2632
2633 mcr->mcr_pkts = htole16(1);
2634 mcr->mcr_flags = 0;
2635 mcr->mcr_cmdctxp = htole32(rp->rpr_q.q_ctx.dma_paddr);
2636 mcr->mcr_ipktbuf.pb_addr = htole32(rp->rpr_msgin.dma_paddr);
2637 mcr->mcr_ipktbuf.pb_next = 0;
2638 mcr->mcr_ipktbuf.pb_len = htole32(rp->rpr_msgin.dma_size);
2639 mcr->mcr_reserved = 0;
2640 mcr->mcr_pktlen = htole16(msglen);
2641 mcr->mcr_opktbuf.pb_addr = htole32(rp->rpr_msgout.dma_paddr);
2642 mcr->mcr_opktbuf.pb_next = 0;
2643 mcr->mcr_opktbuf.pb_len = htole32(rp->rpr_msgout.dma_size);
2644
2645 #ifdef DIAGNOSTIC
2646 if (rp->rpr_msgin.dma_paddr & 3 || rp->rpr_msgin.dma_size & 3) {
2647 panic("%s: rsapriv: invalid msgin %x(0x%x)",
2648 device_get_nameunit(sc->sc_dev),
2649 rp->rpr_msgin.dma_paddr, rp->rpr_msgin.dma_size);
2650 }
2651 if (rp->rpr_msgout.dma_paddr & 3 || rp->rpr_msgout.dma_size & 3) {
2652 panic("%s: rsapriv: invalid msgout %x(0x%x)",
2653 device_get_nameunit(sc->sc_dev),
2654 rp->rpr_msgout.dma_paddr, rp->rpr_msgout.dma_size);
2655 }
2656 #endif
2657
2658 ctx->rpr_len = (sizeof(u_int16_t) * 4) + (5 * (padlen / 8));
2659 ctx->rpr_op = htole16(UBS_CTXOP_RSAPRIV);
2660 ctx->rpr_q_len = htole16(padlen);
2661 ctx->rpr_p_len = htole16(padlen);
2662
2663 /*
2664 * ubsec_feed2 will sync mcr and ctx, we just need to sync
2665 * everything else.
2666 */
2667 ubsec_dma_sync(&rp->rpr_msgin, BUS_DMASYNC_PREWRITE);
2668 ubsec_dma_sync(&rp->rpr_msgout, BUS_DMASYNC_PREREAD);
2669
2670 /* Enqueue and we're done... */
2671 crit_enter();
2672 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rp->rpr_q, q_next);
2673 ubsec_feed2(sc);
2674 ubsecstats.hst_modexpcrt++;
2675 crit_exit();
2676 return (0);
2677
2678 errout:
2679 if (rp != NULL) {
2680 if (rp->rpr_q.q_mcr.dma_map != NULL)
2681 ubsec_dma_free(sc, &rp->rpr_q.q_mcr);
2682 if (rp->rpr_msgin.dma_map != NULL) {
2683 bzero(rp->rpr_msgin.dma_vaddr, rp->rpr_msgin.dma_size);
2684 ubsec_dma_free(sc, &rp->rpr_msgin);
2685 }
2686 if (rp->rpr_msgout.dma_map != NULL) {
2687 bzero(rp->rpr_msgout.dma_vaddr, rp->rpr_msgout.dma_size);
2688 ubsec_dma_free(sc, &rp->rpr_msgout);
2689 }
2690 kfree(rp, M_DEVBUF);
2691 }
2692 krp->krp_status = err;
2693 crypto_kdone(krp);
2694 return (0);
2695 }
2696
2697 #ifdef UBSEC_DEBUG
2698 static void
2699 ubsec_dump_pb(volatile struct ubsec_pktbuf *pb)
2700 {
2701 kprintf("addr 0x%x (0x%x) next 0x%x\n",
2702 pb->pb_addr, pb->pb_len, pb->pb_next);
2703 }
2704
2705 static void
2706 ubsec_dump_ctx2(struct ubsec_ctx_keyop *c)
2707 {
2708 kprintf("CTX (0x%x):\n", c->ctx_len);
2709 switch (letoh16(c->ctx_op)) {
2710 case UBS_CTXOP_RNGBYPASS:
2711 case UBS_CTXOP_RNGSHA1:
2712 break;
2713 case UBS_CTXOP_MODEXP:
2714 {
2715 struct ubsec_ctx_modexp *cx = (void *)c;
2716 int i, len;
2717
2718 kprintf(" Elen %u, Nlen %u\n",
2719 letoh16(cx->me_E_len), letoh16(cx->me_N_len));
2720 len = (cx->me_N_len + 7)/8;
2721 for (i = 0; i < len; i++)
2722 kprintf("%s%02x", (i == 0) ? " N: " : ":", cx->me_N[i]);
2723 kprintf("\n");
2724 break;
2725 }
2726 default:
2727 kprintf("unknown context: %x\n", c->ctx_op);
2728 }
2729 kprintf("END CTX\n");
2730 }
2731
2732 static void
2733 ubsec_dump_mcr(struct ubsec_mcr *mcr)
2734 {
2735 volatile struct ubsec_mcr_add *ma;
2736 int i;
2737
2738 kprintf("MCR:\n");
2739 kprintf(" pkts: %u, flags 0x%x\n",
2740 letoh16(mcr->mcr_pkts), letoh16(mcr->mcr_flags));
2741 ma = (volatile struct ubsec_mcr_add *)&mcr->mcr_cmdctxp;
2742 for (i = 0; i < letoh16(mcr->mcr_pkts); i++) {
2743 kprintf(" %d: ctx 0x%x len 0x%x rsvd 0x%x\n", i,
2744 letoh32(ma->mcr_cmdctxp), letoh16(ma->mcr_pktlen),
2745 letoh16(ma->mcr_reserved));
2746 kprintf(" %d: ipkt ", i);
2747 ubsec_dump_pb(&ma->mcr_ipktbuf);
2748 kprintf(" %d: opkt ", i);
2749 ubsec_dump_pb(&ma->mcr_opktbuf);
2750 ma++;
2751 }
2752 kprintf("END MCR\n");
2753 }
2754 #endif /* UBSEC_DEBUG */
2755
2756 /*
2757 * Return the number of significant bits of a big number.
2758 */
2759 static int
2760 ubsec_ksigbits(struct crparam *cr)
2761 {
2762 u_int plen = (cr->crp_nbits + 7) / 8;
2763 int i, sig = plen * 8;
2764 u_int8_t c, *p = cr->crp_p;
2765
2766 for (i = plen - 1; i >= 0; i--) {
2767 c = p[i];
2768 if (c != 0) {
2769 while ((c & 0x80) == 0) {
2770 sig--;
2771 c <<= 1;
2772 }
2773 break;
2774 }
2775 sig -= 8;
2776 }
2777 return (sig);
2778 }
2779
2780 static void
2781 ubsec_kshift_r(
2782 u_int shiftbits,
2783 u_int8_t *src, u_int srcbits,
2784 u_int8_t *dst, u_int dstbits)
2785 {
2786 u_int slen, dlen;
2787 int i, si, di, n;
2788
2789 slen = (srcbits + 7) / 8;
2790 dlen = (dstbits + 7) / 8;
2791
2792 for (i = 0; i < slen; i++)
2793 dst[i] = src[i];
2794 for (i = 0; i < dlen - slen; i++)
2795 dst[slen + i] = 0;
2796
2797 n = shiftbits / 8;
2798 if (n != 0) {
2799 si = dlen - n - 1;
2800 di = dlen - 1;
2801 while (si >= 0)
2802 dst[di--] = dst[si--];
2803 while (di >= 0)
2804 dst[di--] = 0;
2805 }
2806
2807 n = shiftbits % 8;
2808 if (n != 0) {
2809 for (i = dlen - 1; i > 0; i--)
2810 dst[i] = (dst[i] << n) |
2811 (dst[i - 1] >> (8 - n));
2812 dst[0] = dst[0] << n;
2813 }
2814 }
2815
2816 static void
2817 ubsec_kshift_l(
2818 u_int shiftbits,
2819 u_int8_t *src, u_int srcbits,
2820 u_int8_t *dst, u_int dstbits)
2821 {
2822 int slen, dlen, i, n;
2823
2824 slen = (srcbits + 7) / 8;
2825 dlen = (dstbits + 7) / 8;
2826
2827 n = shiftbits / 8;
2828 for (i = 0; i < slen; i++)
2829 dst[i] = src[i + n];
2830 for (i = 0; i < dlen - slen; i++)
2831 dst[slen + i] = 0;
2832
2833 n = shiftbits % 8;
2834 if (n != 0) {
2835 for (i = 0; i < (dlen - 1); i++)
2836 dst[i] = (dst[i] >> n) | (dst[i + 1] << (8 - n));
2837 dst[dlen - 1] = dst[dlen - 1] >> n;
2838 }
2839 }
DragonFly BSD