2 * Copyright (c) 2007 Yahoo!, Inc.
4 * Written by: John Baldwin <jhb@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. Neither the name of the author nor the names of any co-contributors
15 * may be used to endorse or promote products derived from this software
16 * without specific prior written permission.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * $FreeBSD: src/usr.sbin/pciconf/cap.c,v 1.11 2010/09/16 16:03:12 jhb Exp $
33 #include <sys/types.h>
37 #include <sys/agpio.h>
38 #include <sys/pciio.h>
40 #include <dev/agp/agpreg.h>
41 #include <bus/pci/pcireg.h>
45 static void list_ecaps(int fd
, struct pci_conf
*p
);
46 static const char *aspm_string(uint8_t aspm
);
47 static int slot_power(uint32_t cap
);
50 cap_power(int fd
, struct pci_conf
*p
, uint8_t ptr
)
54 cap
= read_config(fd
, &p
->pc_sel
, ptr
+ PCIR_POWER_CAP
, 2);
55 status
= read_config(fd
, &p
->pc_sel
, ptr
+ PCIR_POWER_STATUS
, 2);
56 printf("powerspec %d supports D0%s%s D3 current D%d",
58 cap
& PCIM_PCAP_D1SUPP
? " D1" : "",
59 cap
& PCIM_PCAP_D2SUPP
? " D2" : "",
60 status
& PCIM_PSTAT_DMASK
);
64 cap_agp(int fd
, struct pci_conf
*p
, uint8_t ptr
)
66 uint32_t status
, command
;
68 status
= read_config(fd
, &p
->pc_sel
, ptr
+ AGP_STATUS
, 4);
69 command
= read_config(fd
, &p
->pc_sel
, ptr
+ AGP_CAPID
, 4);
71 if (AGP_MODE_GET_MODE_3(status
)) {
73 if (AGP_MODE_GET_RATE(status
) & AGP_MODE_V3_RATE_8x
)
75 if (AGP_MODE_GET_RATE(status
) & AGP_MODE_V3_RATE_4x
)
78 if (AGP_MODE_GET_RATE(status
) & AGP_MODE_V2_RATE_4x
)
80 if (AGP_MODE_GET_RATE(status
) & AGP_MODE_V2_RATE_2x
)
82 if (AGP_MODE_GET_RATE(status
) & AGP_MODE_V2_RATE_1x
)
85 if (AGP_MODE_GET_SBA(status
))
87 if (AGP_MODE_GET_AGP(command
)) {
88 printf("enabled at ");
89 if (AGP_MODE_GET_MODE_3(command
)) {
91 switch (AGP_MODE_GET_RATE(command
)) {
92 case AGP_MODE_V3_RATE_8x
:
95 case AGP_MODE_V3_RATE_4x
:
100 switch (AGP_MODE_GET_RATE(command
)) {
101 case AGP_MODE_V2_RATE_4x
:
104 case AGP_MODE_V2_RATE_2x
:
107 case AGP_MODE_V2_RATE_1x
:
111 if (AGP_MODE_GET_SBA(command
))
118 cap_vpd(int fd __unused
, struct pci_conf
*p __unused
, uint8_t ptr __unused
)
125 cap_msi(int fd
, struct pci_conf
*p
, uint8_t ptr
)
130 ctrl
= read_config(fd
, &p
->pc_sel
, ptr
+ PCIR_MSI_CTRL
, 2);
131 msgnum
= 1 << ((ctrl
& PCIM_MSICTRL_MMC_MASK
) >> 1);
132 printf("MSI supports %d message%s%s%s ", msgnum
,
133 (msgnum
== 1) ? "" : "s",
134 (ctrl
& PCIM_MSICTRL_64BIT
) ? ", 64 bit" : "",
135 (ctrl
& PCIM_MSICTRL_VECTOR
) ? ", vector masks" : "");
136 if (ctrl
& PCIM_MSICTRL_MSI_ENABLE
) {
137 msgnum
= 1 << ((ctrl
& PCIM_MSICTRL_MME_MASK
) >> 4);
138 printf("enabled with %d message%s", msgnum
,
139 (msgnum
== 1) ? "" : "s");
144 cap_pcix(int fd
, struct pci_conf
*p
, uint8_t ptr
)
147 int comma
, max_splits
= 0, max_burst_read
= 0;
149 status
= read_config(fd
, &p
->pc_sel
, ptr
+ PCIXR_STATUS
, 4);
151 if (status
& PCIXM_STATUS_64BIT
)
153 if ((p
->pc_hdr
& PCIM_HDRTYPE
) == 1)
155 if ((p
->pc_hdr
& PCIM_HDRTYPE
) != 1 || (status
& (PCIXM_STATUS_133CAP
|
156 PCIXM_STATUS_266CAP
| PCIXM_STATUS_533CAP
)) != 0)
159 if (status
& PCIXM_STATUS_133CAP
) {
160 printf("%s 133MHz", comma
? "," : "");
163 if (status
& PCIXM_STATUS_266CAP
) {
164 printf("%s 266MHz", comma
? "," : "");
167 if (status
& PCIXM_STATUS_533CAP
) {
168 printf("%s 533MHz", comma
? "," : "");
171 if ((p
->pc_hdr
& PCIM_HDRTYPE
) == 1)
173 switch (status
& PCIXM_STATUS_MAX_READ
) {
174 case PCIXM_STATUS_MAX_READ_512
:
175 max_burst_read
= 512;
177 case PCIXM_STATUS_MAX_READ_1024
:
178 max_burst_read
= 1024;
180 case PCIXM_STATUS_MAX_READ_2048
:
181 max_burst_read
= 2048;
183 case PCIXM_STATUS_MAX_READ_4096
:
184 max_burst_read
= 4096;
187 switch (status
& PCIXM_STATUS_MAX_SPLITS
) {
188 case PCIXM_STATUS_MAX_SPLITS_1
:
191 case PCIXM_STATUS_MAX_SPLITS_2
:
194 case PCIXM_STATUS_MAX_SPLITS_3
:
197 case PCIXM_STATUS_MAX_SPLITS_4
:
200 case PCIXM_STATUS_MAX_SPLITS_8
:
203 case PCIXM_STATUS_MAX_SPLITS_12
:
206 case PCIXM_STATUS_MAX_SPLITS_16
:
209 case PCIXM_STATUS_MAX_SPLITS_32
:
213 printf("%s %d burst read, %d split transaction%s", comma
? "," : "",
214 max_burst_read
, max_splits
, max_splits
== 1 ? "" : "s");
218 cap_ht(int fd
, struct pci_conf
*p
, uint8_t ptr
)
223 command
= read_config(fd
, &p
->pc_sel
, ptr
+ PCIR_HT_COMMAND
, 2);
225 if ((command
& 0xe000) == PCIM_HTCAP_SLAVE
)
227 else if ((command
& 0xe000) == PCIM_HTCAP_HOST
)
230 switch (command
& PCIM_HTCMD_CAP_MASK
) {
231 case PCIM_HTCAP_SWITCH
:
234 case PCIM_HTCAP_INTERRUPT
:
237 case PCIM_HTCAP_REVISION_ID
:
238 printf("revision ID");
240 case PCIM_HTCAP_UNITID_CLUMPING
:
241 printf("unit ID clumping");
243 case PCIM_HTCAP_EXT_CONFIG_SPACE
:
244 printf("extended config space");
246 case PCIM_HTCAP_ADDRESS_MAPPING
:
247 printf("address mapping");
249 case PCIM_HTCAP_MSI_MAPPING
:
250 printf("MSI %saddress window %s at 0x",
251 command
& PCIM_HTCMD_MSI_FIXED
? "fixed " : "",
252 command
& PCIM_HTCMD_MSI_ENABLE
? "enabled" :
254 if (command
& PCIM_HTCMD_MSI_FIXED
)
257 reg
= read_config(fd
, &p
->pc_sel
,
258 ptr
+ PCIR_HTMSI_ADDRESS_HI
, 4);
261 reg
= read_config(fd
, &p
->pc_sel
,
262 ptr
+ PCIR_HTMSI_ADDRESS_LO
, 4);
266 case PCIM_HTCAP_DIRECT_ROUTE
:
267 printf("direct route");
269 case PCIM_HTCAP_VCSET
:
272 case PCIM_HTCAP_RETRY_MODE
:
273 printf("retry mode");
275 case PCIM_HTCAP_X86_ENCODING
:
276 printf("X86 encoding");
279 printf("unknown %02x", command
);
285 cap_vendor(int fd
, struct pci_conf
*p
, uint8_t ptr
)
289 length
= read_config(fd
, &p
->pc_sel
, ptr
+ PCIR_VENDOR_LENGTH
, 1);
290 printf("vendor (length %d)", length
);
291 if (p
->pc_vendor
== 0x8086) {
295 version
= read_config(fd
, &p
->pc_sel
, ptr
+ PCIR_VENDOR_DATA
,
297 printf(" Intel cap %d version %d", version
>> 4, version
& 0xf);
298 if (version
>> 4 == 1 && length
== 12) {
299 /* Feature Detection */
304 fvec
= read_config(fd
, &p
->pc_sel
, ptr
+
305 PCIR_VENDOR_DATA
+ 5, 4);
306 printf("\n\t\t features:");
307 if (fvec
& (1 << 0)) {
311 fvec
= read_config(fd
, &p
->pc_sel
, ptr
+
312 PCIR_VENDOR_DATA
+ 1, 4);
313 if (fvec
& (1 << 21)) {
314 printf("%s Quick Resume", comma
? "," : "");
317 if (fvec
& (1 << 18)) {
318 printf("%s SATA RAID-5", comma
? "," : "");
321 if (fvec
& (1 << 9)) {
322 printf("%s Mobile", comma
? "," : "");
325 if (fvec
& (1 << 7)) {
326 printf("%s 6 PCI-e x1 slots", comma
? "," : "");
329 printf("%s 4 PCI-e x1 slots", comma
? "," : "");
332 if (fvec
& (1 << 5)) {
333 printf("%s SATA RAID-0/1/10", comma
? "," : "");
336 if (fvec
& (1 << 3)) {
337 printf("%s SATA AHCI", comma
? "," : "");
345 cap_debug(int fd
, struct pci_conf
*p
, uint8_t ptr
)
349 debug_port
= read_config(fd
, &p
->pc_sel
, ptr
+ PCIR_DEBUG_PORT
, 2);
350 printf("EHCI Debug Port at offset 0x%x in map 0x%x", debug_port
&
351 PCIM_DEBUG_PORT_OFFSET
, PCIR_BAR(debug_port
>> 13));
355 cap_subvendor(int fd
, struct pci_conf
*p
, uint8_t ptr
)
359 id
= read_config(fd
, &p
->pc_sel
, ptr
+ PCIR_SUBVENDCAP_ID
, 4);
360 printf("PCI Bridge card=0x%08x", id
);
363 #define MAX_PAYLOAD(field) (128 << (field))
366 cap_express(int fd
, struct pci_conf
*p
, uint8_t ptr
)
369 uint16_t ctl
, flags
, sta
;
370 unsigned int version
;
372 flags
= read_config(fd
, &p
->pc_sel
, ptr
+ PCIER_CAPABILITY
, 2);
373 version
= flags
& PCIEM_CAP_VER_MASK
;
374 printf("PCI-Express %u ", version
);
375 switch (flags
& PCIEM_CAP_PORT_TYPE
) {
379 case PCIE_LEG_END_POINT
:
380 printf("legacy endpoint");
385 case PCIE_UP_STREAM_PORT
:
386 printf("upstream port");
388 case PCIE_DOWN_STREAM_PORT
:
389 printf("downstream port");
391 case PCIE_PCIE2PCI_BRIDGE
:
392 printf("PCI bridge");
394 case PCIE_PCI2PCIE_BRIDGE
:
395 printf("PCI to PCIe bridge");
397 case PCIE_ROOT_END_POINT
:
398 printf("root endpoint");
400 case PCIE_ROOT_EVT_COLL
:
401 printf("event collector");
404 printf("type %d", (flags
& PCIEM_CAP_PORT_TYPE
) >> 8);
407 if (flags
& PCIEM_CAP_IRQ_MSGNO
)
408 printf(" IRQ %d", (flags
& PCIEM_CAP_IRQ_MSGNO
) >> 8);
409 cap
= read_config(fd
, &p
->pc_sel
, ptr
+ PCIER_DEVCAP
, 4);
410 ctl
= read_config(fd
, &p
->pc_sel
, ptr
+ PCIER_DEVCTRL
, 2);
411 printf(" max data %d(%d)",
412 MAX_PAYLOAD((ctl
& PCIEM_DEVCAP_MAX_PAYLOAD
) >> 5),
413 MAX_PAYLOAD(cap
& PCIEM_DEVCAP_MAX_PAYLOAD
));
414 if ((cap
& PCIEM_CAP_FLR
) != 0)
416 if (ctl
& PCIEM_DEVCTL_RELAX_ORDER
)
418 if (ctl
& PCIEM_DEVCTL_NOSNOOP
)
420 if (ctl
& PCIEM_DEVCTL_COR_ENABLE
)
422 if (ctl
& PCIEM_DEVCTL_NFER_ENABLE
)
424 if (ctl
& PCIEM_DEVCTL_FER_ENABLE
)
426 if (ctl
& PCIEM_DEVCTL_URR_ENABLE
)
429 cap
= read_config(fd
, &p
->pc_sel
, ptr
+ PCIER_DEVCAP2
, 4);
430 if ((cap
& PCIEM_DEVCAP2_ALT_RID_SUPP
) != 0) {
431 ctl
= read_config(fd
, &p
->pc_sel
,
432 ptr
+ PCIER_DEVCTRL2
, 4);
434 (ctl
& PCIEM_DEVCTL2_ALT_RID_ENABLE
) ?
435 "enabled" : "disabled");
438 if ((cap
& PCIEM_DEVCAP2_LTR_SUPP
) != 0) {
440 (ctl
& PCIEM_DEVCTL2_LTR_ENABLE
) ?
441 "enabled" : "disabled");
445 cap
= read_config(fd
, &p
->pc_sel
, ptr
+ PCIER_LINKCAP
, 4);
446 sta
= read_config(fd
, &p
->pc_sel
, ptr
+ PCIER_LINKSTAT
, 2);
448 printf(" link x%d(x%d)", (sta
& PCIEM_LNKSTAT_WIDTH
) >> 4,
449 (cap
& PCIEM_LNKCAP_MAXW_MASK
) >> 4);
451 if (cap
& PCIEM_LNKCAP_ASPM_MASK
) {
452 ctl
= read_config(fd
, &p
->pc_sel
, ptr
+ PCIER_LINKCTRL
, 2);
453 printf(" ASPM %s(%s)",
454 aspm_string(ctl
& PCIEM_LNKCTL_ASPM_MASK
),
455 aspm_string((cap
& PCIEM_LNKCAP_ASPM_MASK
) >> 10));
457 if (flags
& PCIEM_CAP_SLOT_IMPL
) {
458 cap
= read_config(fd
, &p
->pc_sel
, ptr
+ PCIER_SLOTCAP
, 4);
459 sta
= read_config(fd
, &p
->pc_sel
, ptr
+ PCIER_SLOTSTA
, 2);
460 ctl
= read_config(fd
, &p
->pc_sel
, ptr
+ PCIER_SLOTCTL
, 2);
462 printf(" slot %d", (cap
& PCIEM_SLOTCAP_PSN
) >> 19);
463 printf(" power limit %d mW", slot_power(cap
));
464 if (cap
& PCIEM_SLOTCAP_HP_CAP
)
465 printf(" HotPlug(%s)", sta
& PCIEM_SLOTSTA_PDS
?
466 "present" : "empty");
467 if (cap
& PCIEM_SLOTCAP_HP_SURP
)
469 if (cap
& PCIEM_SLOTCAP_ATTEN_BTN
)
470 printf(" Attn Button");
471 if (cap
& PCIEM_SLOTCAP_PWR_CTRL
)
472 printf(" PC(%s)", ctl
& PCIEM_SLOTCTL_PCC
?
474 if (cap
& PCIEM_SLOTCAP_MRL_SNS
)
475 printf(" MRL(%s)", sta
& PCIEM_SLOTSTA_MRLSS
?
477 if (cap
& PCIEM_SLOTCAP_EIP
)
478 printf(" EI(%s)", sta
& PCIEM_SLOTSTA_EIS
?
479 "engaged" : "disengaged");
484 cap_msix(int fd
, struct pci_conf
*p
, uint8_t ptr
)
488 int msgnum
, table_bar
, pba_bar
;
490 ctrl
= read_config(fd
, &p
->pc_sel
, ptr
+ PCIR_MSIX_CTRL
, 2);
491 msgnum
= (ctrl
& PCIM_MSIXCTRL_TABLE_SIZE
) + 1;
492 val
= read_config(fd
, &p
->pc_sel
, ptr
+ PCIR_MSIX_TABLE
, 4);
493 table_bar
= PCIR_BAR(val
& PCIM_MSIX_BIR_MASK
);
494 val
= read_config(fd
, &p
->pc_sel
, ptr
+ PCIR_MSIX_PBA
, 4);
495 pba_bar
= PCIR_BAR(val
& PCIM_MSIX_BIR_MASK
);
496 printf("MSI-X supports %d message%s ", msgnum
,
497 (msgnum
== 1) ? "" : "s");
498 if (table_bar
== pba_bar
)
499 printf("in map 0x%x", table_bar
);
501 printf("in maps 0x%x and 0x%x", table_bar
, pba_bar
);
502 if (ctrl
& PCIM_MSIXCTRL_MSIX_ENABLE
)
507 cap_sata(__unused
int fd
, __unused
struct pci_conf
*p
, __unused
uint8_t ptr
)
510 printf("SATA Index-Data Pair");
514 cap_pciaf(int fd
, struct pci_conf
*p
, uint8_t ptr
)
518 cap
= read_config(fd
, &p
->pc_sel
, ptr
+ PCIR_PCIAF_CAP
, 1);
519 printf("PCI Advanced Features:%s%s",
520 cap
& PCIM_PCIAFCAP_FLR
? " FLR" : "",
521 cap
& PCIM_PCIAFCAP_TP
? " TP" : "");
525 list_caps(int fd
, struct pci_conf
*p
)
531 /* Are capabilities present for this device? */
532 sta
= read_config(fd
, &p
->pc_sel
, PCIR_STATUS
, 2);
533 if (!(sta
& PCIM_STATUS_CAPPRESENT
))
536 switch (p
->pc_hdr
& PCIM_HDRTYPE
) {
537 case PCIM_HDRTYPE_NORMAL
:
538 case PCIM_HDRTYPE_BRIDGE
:
541 case PCIM_HDRTYPE_CARDBUS
:
542 ptr
= PCIR_CAP_PTR_2
;
545 errx(1, "list_caps: bad header type");
548 /* Walk the capability list. */
550 ptr
= read_config(fd
, &p
->pc_sel
, ptr
, 1);
551 while (ptr
!= 0 && ptr
!= 0xff) {
552 cap
= read_config(fd
, &p
->pc_sel
, ptr
+ PCICAP_ID
, 1);
553 printf(" cap %02x[%02x] = ", cap
, ptr
);
556 cap_power(fd
, p
, ptr
);
568 cap_pcix(fd
, p
, ptr
);
574 cap_vendor(fd
, p
, ptr
);
577 cap_debug(fd
, p
, ptr
);
580 cap_subvendor(fd
, p
, ptr
);
584 cap_express(fd
, p
, ptr
);
587 cap_msix(fd
, p
, ptr
);
590 cap_sata(fd
, p
, ptr
);
593 cap_pciaf(fd
, p
, ptr
);
600 ptr
= read_config(fd
, &p
->pc_sel
, ptr
+ PCICAP_NEXTPTR
, 1);
607 /* From <sys/systm.h>. */
608 static __inline
uint32_t
609 bitcount32(uint32_t x
)
612 x
= (x
& 0x55555555) + ((x
& 0xaaaaaaaa) >> 1);
613 x
= (x
& 0x33333333) + ((x
& 0xcccccccc) >> 2);
614 x
= (x
+ (x
>> 4)) & 0x0f0f0f0f;
616 x
= (x
+ (x
>> 16)) & 0x000000ff;
621 ecap_aer(int fd
, struct pci_conf
*p
, uint16_t ptr
, uint8_t ver
)
625 printf("AER %d", ver
);
628 sta
= read_config(fd
, &p
->pc_sel
, ptr
+ PCIR_AER_UC_STATUS
, 4);
629 mask
= read_config(fd
, &p
->pc_sel
, ptr
+ PCIR_AER_UC_SEVERITY
, 4);
630 printf(" %d fatal", bitcount32(sta
& mask
));
631 printf(" %d non-fatal", bitcount32(sta
& ~mask
));
632 sta
= read_config(fd
, &p
->pc_sel
, ptr
+ PCIR_AER_COR_STATUS
, 4);
633 printf(" %d corrected", bitcount32(sta
));
637 ecap_vc(int fd
, struct pci_conf
*p
, uint16_t ptr
, uint8_t ver
)
641 printf("VC %d", ver
);
644 cap1
= read_config(fd
, &p
->pc_sel
, ptr
+ PCIR_VC_CAP1
, 4);
645 printf(" max VC%d", cap1
& PCIM_VC_CAP1_EXT_COUNT
);
646 if ((cap1
& PCIM_VC_CAP1_LOWPRI_EXT_COUNT
) != 0)
647 printf(" lowpri VC0-VC%d",
648 (cap1
& PCIM_VC_CAP1_LOWPRI_EXT_COUNT
) >> 4);
652 ecap_sernum(int fd
, struct pci_conf
*p
, uint16_t ptr
, uint8_t ver
)
656 printf("Serial %d", ver
);
659 low
= read_config(fd
, &p
->pc_sel
, ptr
+ PCIR_SERIAL_LOW
, 4);
660 high
= read_config(fd
, &p
->pc_sel
, ptr
+ PCIR_SERIAL_HIGH
, 4);
661 printf(" %08x%08x", high
, low
);
665 list_ecaps(int fd
, struct pci_conf
*p
)
671 ecap
= read_config(fd
, &p
->pc_sel
, ptr
, 4);
672 if (ecap
== 0xffffffff || ecap
== 0)
675 printf("ecap %04x[%03x] = ", PCI_EXTCAP_ID(ecap
), ptr
);
676 switch (PCI_EXTCAP_ID(ecap
)) {
678 ecap_aer(fd
, p
, ptr
, PCI_EXTCAP_VER(ecap
));
681 ecap_vc(fd
, p
, ptr
, PCI_EXTCAP_VER(ecap
));
684 ecap_sernum(fd
, p
, ptr
, PCI_EXTCAP_VER(ecap
));
687 printf("unknown %d", PCI_EXTCAP_VER(ecap
));
691 ptr
= PCI_EXTCAP_NEXTPTR(ecap
);
694 ecap
= read_config(fd
, &p
->pc_sel
, ptr
, 4);
699 aspm_string(uint8_t aspm
)
714 slot_power(uint32_t cap
)
718 mwatts
= (cap
& PCIEM_SLOTCAP_SPLV
) >> 7;
720 switch (cap
& PCIEM_SLOTCAP_SPLS
) {
737 pci_find_cap(int fd
, struct pci_conf
*p
, uint8_t id
)
742 /* Are capabilities present for this device? */
743 sta
= read_config(fd
, &p
->pc_sel
, PCIR_STATUS
, 2);
744 if (!(sta
& PCIM_STATUS_CAPPRESENT
))
747 switch (p
->pc_hdr
& PCIM_HDRTYPE
) {
748 case PCIM_HDRTYPE_NORMAL
:
749 case PCIM_HDRTYPE_BRIDGE
:
752 case PCIM_HDRTYPE_CARDBUS
:
753 ptr
= PCIR_CAP_PTR_2
;
759 ptr
= read_config(fd
, &p
->pc_sel
, ptr
, 1);
760 while (ptr
!= 0 && ptr
!= 0xff) {
761 cap
= read_config(fd
, &p
->pc_sel
, ptr
+ PCICAP_ID
, 1);
764 ptr
= read_config(fd
, &p
->pc_sel
, ptr
+ PCICAP_NEXTPTR
, 1);
769 /* Find offset of a specific extended capability. Returns 0 on failure. */
771 pcie_find_cap(int fd
, struct pci_conf
*p
, uint16_t id
)
777 ecap
= read_config(fd
, &p
->pc_sel
, ptr
, 4);
778 if (ecap
== 0xffffffff || ecap
== 0)
781 if (PCI_EXTCAP_ID(ecap
) == id
)
783 ptr
= PCI_EXTCAP_NEXTPTR(ecap
);
786 ecap
= read_config(fd
, &p
->pc_sel
, ptr
, 4);