kernel - disklabel64 - Increase partition start alignment to 1 megabyte.
[dragonfly.git] / sys / dev / raid / twa / twa.h
blob4669048abca6d9e082b9d33aee50e02ec0dba8f8
1 /*-
2 * Copyright (c) 2003-04 3ware, Inc.
3 * Copyright (c) 2000 Michael Smith
4 * Copyright (c) 2000 BSDi
5 * All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
28 * $FreeBSD$
29 * $DragonFly: src/sys/dev/raid/twa/twa.h,v 1.4 2006/12/22 23:26:24 swildner Exp $
33 * 3ware driver for 9000 series storage controllers.
35 * Author: Vinod Kashyap
38 #include <sys/thread2.h>
41 * The scheme for the driver version is:
42 * <major change>.<external release>.<3ware internal release>.<development release>
44 #define TWA_DRIVER_VERSION_STRING "2.40.00.000"
46 #define TWA_CDEV_MAJOR 187
48 #define TWA_REQUEST_TIMEOUT_PERIOD 60 /* seconds */
49 #define TWA_MESSAGE_SOURCE_CONTROLLER_ERROR 3
50 #define TWA_MESSAGE_SOURCE_CONTROLLER_EVENT 4
51 #define TWA_MESSAGE_SOURCE_FREEBSD_DRIVER 6
52 #define TWA_MESSAGE_SOURCE_FREEBSD_OS 9
54 #define TWA_MALLOC_CLASS M_TWA
56 /* Macros for bus-space calls. */
57 #define TWA_READ_REGISTER(sc, offset) \
58 (u_int32_t)bus_space_read_4(sc->twa_bus_tag, sc->twa_bus_handle, offset)
59 #define TWA_WRITE_REGISTER(sc, offset, val) \
60 bus_space_write_4(sc->twa_bus_tag, sc->twa_bus_handle, offset, (u_int32_t)val)
62 /* Possible values of tr->tr_status. */
63 #define TWA_CMD_SETUP 0x0 /* being assembled */
64 #define TWA_CMD_BUSY 0x1 /* submitted to controller */
65 #define TWA_CMD_PENDING 0x2 /* in pending queue */
66 #define TWA_CMD_COMPLETE 0x3 /* completed by controller (maybe with error) */
68 /* Possible values of tr->tr_flags. */
69 #define TWA_CMD_DATA_IN (1<<0) /* read request */
70 #define TWA_CMD_DATA_OUT (1<<1) /* write request */
71 #define TWA_CMD_DATA_COPY_NEEDED (1<<2) /* data in ccb is misaligned, have to copy to/from private buffer */
72 #define TWA_CMD_SLEEP_ON_REQUEST (1<<3) /* owner is sleeping on this command */
73 #define TWA_CMD_IN_PROGRESS (1<<4) /* bus_dmamap_load returned EINPROGRESS */
75 /* Possible values of tr->tr_cmd_pkt_type. */
76 #define TWA_CMD_PKT_TYPE_7K (1<<0)
77 #define TWA_CMD_PKT_TYPE_9K (1<<1)
78 #define TWA_CMD_PKT_TYPE_INTERNAL (1<<2)
79 #define TWA_CMD_PKT_TYPE_IOCTL (1<<3)
80 #define TWA_CMD_PKT_TYPE_EXTERNAL (1<<4)
82 /* Possible values of sc->twa_state. */
83 #define TWA_STATE_INTR_ENABLED (1<<0) /* interrupts have been enabled */
84 #define TWA_STATE_SHUTDOWN (1<<1) /* controller is shut down */
85 #define TWA_STATE_OPEN (1<<2) /* control device is open */
86 #define TWA_STATE_SUSPEND (1<<3) /* controller is suspended */
87 #define TWA_STATE_SIMQ_FROZEN (1<<4) /* simq frozen */
89 /* Possible values of sc->twa_ioctl_lock.lock. */
90 #define TWA_LOCK_FREE 0x0 /* lock is free */
91 #define TWA_LOCK_HELD 0x1 /* lock is held */
94 /* Error/AEN message structure. */
95 struct twa_message {
96 u_int32_t code;
97 char *message;
100 #ifdef TWA_DEBUG
101 struct twa_q_statistics {
102 u_int32_t q_length;
103 u_int32_t q_max;
106 #define TWAQ_FREE 0
107 #define TWAQ_BUSY 1
108 #define TWAQ_PENDING 2
109 #define TWAQ_COMPLETE 3
110 #define TWAQ_COUNT 4 /* total number of queues */
111 #endif /* TWA_DEBUG */
113 /* Driver's request packet. */
114 struct twa_request {
115 struct twa_command_packet *tr_command; /* ptr to cmd pkt submitted to controller */
116 u_int32_t tr_request_id; /* request id for tracking with firmware */
118 void *tr_data; /* ptr to data being passed to firmware */
119 size_t tr_length; /* length of buffer being passed to firmware */
121 void *tr_real_data; /* ptr to, and length of data passed */
122 size_t tr_real_length; /* to us from above, in case a buffer copy
123 was done due to non-compliance to
124 alignment requirements */
126 TAILQ_ENTRY(twa_request) tr_link; /* to link this request in a list */
127 struct twa_softc *tr_sc; /* controller that owns us */
129 u_int32_t tr_status; /* command status */
130 u_int32_t tr_flags; /* request flags */
131 u_int32_t tr_error; /* error encountered before request submission */
132 u_int32_t tr_cmd_pkt_type;/* type of request */
133 void *tr_private; /* request specific data to use during callback */
134 void (*tr_callback)(struct twa_request *tr);/* callback handler */
135 bus_addr_t tr_cmd_phys; /* physical address of command in controller space */
136 bus_dmamap_t tr_dma_map; /* DMA map for data */
137 } __attribute__ ((packed));
140 /* Per-controller structure. */
141 struct twa_softc {
142 /* Request queues and arrays. */
143 TAILQ_HEAD(, twa_request) twa_free; /* free request packets */
144 TAILQ_HEAD(, twa_request) twa_busy; /* requests busy in the controller */
145 TAILQ_HEAD(, twa_request) twa_pending; /* internal requests pending */
146 TAILQ_HEAD(, twa_request) twa_complete; /* requests completed by firmware (not by us) */
148 struct twa_request *twa_lookup[TWA_Q_LENGTH];/* requests indexed by request_id */
150 struct twa_request *twa_req_buf;
151 struct twa_command_packet *twa_cmd_pkt_buf;
153 /* AEN handler fields. */
154 struct twa_event_packet *twa_aen_queue[TWA_Q_LENGTH];/* circular queue of AENs from firmware */
155 uint16_t working_srl; /* driver & firmware negotiated srl */
156 uint16_t working_branch; /* branch # of the firmware that the driver is compatible with */
157 uint16_t working_build; /* build # of the firmware that the driver is compatible with */
158 u_int32_t twa_operating_mode; /* base mode/current mode */
159 u_int32_t twa_aen_head; /* AEN queue head */
160 u_int32_t twa_aen_tail; /* AEN queue tail */
161 u_int32_t twa_current_sequence_id;/* index of the last event + 1 */
162 u_int32_t twa_aen_queue_overflow; /* indicates if unretrieved events were overwritten */
163 u_int32_t twa_aen_queue_wrapped; /* indicates if AEN queue ever wrapped */
164 u_int32_t twa_wait_timeout; /* identifier for calling tsleep */
166 /* Controller state. */
167 u_int32_t twa_state;
168 #ifdef TWA_DEBUG
169 struct twa_q_statistics twa_qstats[TWAQ_COUNT]; /* queue statistics */
170 #endif /* TWA_DEBUG */
171 struct {
172 u_int32_t lock; /* lock state */
173 u_int32_t timeout;/* time at which the lock will become available,
174 even if not released */
175 } twa_ioctl_lock; /* lock for use by user applications, for synchronization
176 between ioctl calls */
178 device_t twa_bus_dev; /* bus device */
179 struct resource *twa_io_res; /* register interface window */
180 bus_space_handle_t twa_bus_handle; /* bus space handle */
181 bus_space_tag_t twa_bus_tag; /* bus space tag */
182 bus_dma_tag_t twa_dma_tag; /* data buffer DMA tag */
183 bus_dmamap_t twa_cmd_map; /* DMA map for the array of cmd pkts */
184 bus_addr_t twa_cmd_pkt_phys;/* phys addr of first of array of cmd pkts */
185 struct resource *twa_irq_res; /* interrupt resource*/
186 void *twa_intr_handle;/* interrupt handle */
187 struct intr_config_hook twa_ich; /* delayed-startup hook */
189 struct sysctl_ctx_list twa_sysctl_ctx;
190 struct sysctl_oid *twa_sysctl_tree;
192 struct cam_sim *twa_sim; /* sim for this controller */
193 struct cam_path *twa_path; /* peripheral, path, tgt, lun
194 associated with this controller */
199 * Queue primitives
202 #ifdef TWA_DEBUG
204 #define TWAQ_INIT(sc, qname) \
205 do { \
206 sc->twa_qstats[qname].q_length = 0; \
207 sc->twa_qstats[qname].q_max = 0; \
208 } while(0)
210 #define TWAQ_ADD(sc, qname) \
211 do { \
212 struct twa_q_statistics *qs = &(sc)->twa_qstats[qname]; \
214 qs->q_length++; \
215 if (qs->q_length > qs->q_max) \
216 qs->q_max = qs->q_length; \
217 } while(0)
219 #define TWAQ_REMOVE(sc, qname) (sc)->twa_qstats[qname].q_length--
221 #else /* TWA_DEBUG */
223 #define TWAQ_INIT(sc, qname)
224 #define TWAQ_ADD(sc, qname)
225 #define TWAQ_REMOVE(sc, qname)
227 #endif /* TWA_DEBUG */
229 #define TWAQ_REQUEST_QUEUE(name, index) \
230 static __inline void twa_initq_ ## name(struct twa_softc *sc) \
232 TAILQ_INIT(&sc->twa_ ## name); \
233 TWAQ_INIT(sc, index); \
235 static __inline void twa_enqueue_ ## name(struct twa_request *tr) \
237 crit_enter(); \
238 TAILQ_INSERT_TAIL(&tr->tr_sc->twa_ ## name, tr, tr_link); \
239 TWAQ_ADD(tr->tr_sc, index); \
240 crit_exit(); \
242 static __inline void twa_requeue_ ## name(struct twa_request *tr) \
244 crit_enter(); \
245 TAILQ_INSERT_HEAD(&tr->tr_sc->twa_ ## name, tr, tr_link); \
246 TWAQ_ADD(tr->tr_sc, index); \
247 crit_exit(); \
249 static __inline struct twa_request *twa_dequeue_ ## name(struct twa_softc *sc)\
251 struct twa_request *tr; \
253 crit_enter(); \
254 if ((tr = TAILQ_FIRST(&sc->twa_ ## name)) != NULL) { \
255 TAILQ_REMOVE(&sc->twa_ ## name, tr, tr_link); \
256 TWAQ_REMOVE(sc, index); \
258 crit_exit(); \
259 return(tr); \
261 static __inline void twa_remove_ ## name(struct twa_request *tr) \
263 crit_enter(); \
264 TAILQ_REMOVE(&tr->tr_sc->twa_ ## name, tr, tr_link); \
265 TWAQ_REMOVE(tr->tr_sc, index); \
266 crit_exit(); \
269 TWAQ_REQUEST_QUEUE(free, TWAQ_FREE)
270 TWAQ_REQUEST_QUEUE(busy, TWAQ_BUSY)
271 TWAQ_REQUEST_QUEUE(pending, TWAQ_PENDING)
272 TWAQ_REQUEST_QUEUE(complete, TWAQ_COMPLETE)
275 #ifdef TWA_DEBUG
277 extern u_int8_t twa_dbg_level;
278 extern u_int8_t twa_call_dbg_level;
280 /* Printf with the bus device in question. */
281 #define twa_dbg_dprint(dbg_level, sc, fmt, args...) \
282 do { \
283 if (dbg_level <= twa_dbg_level) \
284 device_printf(sc->twa_bus_dev, \
285 "%s: " fmt "\n", __func__ , ##args);\
286 } while(0)
288 #define twa_dbg_dprint_enter(dbg_level, sc) \
289 do { \
290 if (dbg_level <= twa_call_dbg_level) \
291 device_printf(sc->twa_bus_dev, \
292 "%s: entered.\n", __func__); \
293 } while(0)
295 #define twa_dbg_dprint_exit(dbg_level, sc) \
296 do { \
297 if (dbg_level <= twa_call_dbg_level) \
298 device_printf(sc->twa_bus_dev, \
299 "%s: exiting.\n", __func__); \
300 } while(0)
302 #define twa_dbg_print(dbg_level, fmt, args...) \
303 do { \
304 if (dbg_level <= twa_dbg_level) \
305 kprintf("%s: " fmt "\n", __func__ , ##args);\
306 } while(0)
308 #else
309 #define twa_dbg_dprint(dbg_level, sc, fmt, args...)
310 #define twa_dbg_dprint_enter(dbg_level, sc)
311 #define twa_dbg_dprint_exit(dbg_level, sc)
312 #define twa_dbg_print(dbg_level, fmt, args...)
313 #endif
315 #define twa_printf(sc, fmt, args...) \
316 device_printf(sc->twa_bus_dev, fmt, ##args)