?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Sync ehci.c with FreeBSD
[dragonfly.git] / sys / bus / u4b / controller / ehci.c
blobdbbd5f842800370f15ece58ce80700007f65e645
1 /*-
2 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved.
3 * Copyright (c) 2004 The NetBSD Foundation, Inc. All rights reserved.
4 * Copyright (c) 2004 Lennart Augustsson. All rights reserved.
5 * Copyright (c) 2004 Charles M. Hannum. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 /*
30 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller.
31 *
32 * The EHCI 0.96 spec can be found at
33 * http://developer.intel.com/technology/usb/download/ehci-r096.pdf
34 * The EHCI 1.0 spec can be found at
35 * http://developer.intel.com/technology/usb/download/ehci-r10.pdf
36 * and the USB 2.0 spec at
37 * http://www.usb.org/developers/docs/usb_20.zip
38 *
39 */
40
41 /*
42 * TODO:
43 * 1) command failures are not recovered correctly
44 */
45
46 #include <sys/stdint.h>
47 #include <sys/param.h>
48 #include <sys/queue.h>
49 #include <sys/types.h>
50 #include <sys/systm.h>
51 #include <sys/kernel.h>
52 #include <sys/bus.h>
53 #include <sys/module.h>
54 #include <sys/lock.h>
55 #include <sys/condvar.h>
56 #include <sys/sysctl.h>
57 #include <sys/unistd.h>
58 #include <sys/callout.h>
59 #include <sys/malloc.h>
60 #include <sys/priv.h>
61
62 #include <bus/u4b/usb.h>
63 #include <bus/u4b/usbdi.h>
64
65 #define USB_DEBUG_VAR ehcidebug
66
67 #include <bus/u4b/usb_core.h>
68 #include <bus/u4b/usb_debug.h>
69 #include <bus/u4b/usb_busdma.h>
70 #include <bus/u4b/usb_process.h>
71 #include <bus/u4b/usb_transfer.h>
72 #include <bus/u4b/usb_device.h>
73 #include <bus/u4b/usb_hub.h>
74 #include <bus/u4b/usb_util.h>
75
76 #include <bus/u4b/usb_controller.h>
77 #include <bus/u4b/usb_bus.h>
78 #include <bus/u4b/controller/ehci.h>
79 #include <bus/u4b/controller/ehcireg.h>
80
81 #define EHCI_BUS2SC(bus) \
82 ((ehci_softc_t *)(((uint8_t *)(bus)) - \
83 ((uint8_t *)&(((ehci_softc_t *)0)->sc_bus))))
84
85 #ifdef USB_DEBUG
86 static int ehcidebug = 0;
87 static int ehcinohighspeed = 0;
88 static int ehciiaadbug = 0;
89 static int ehcilostintrbug = 0;
90
91 static SYSCTL_NODE(_hw_usb, OID_AUTO, ehci, CTLFLAG_RW, 0, "USB ehci");
92 SYSCTL_INT(_hw_usb_ehci, OID_AUTO, debug, CTLFLAG_RW,
93 &ehcidebug, 0, "Debug level");
94 SYSCTL_INT(_hw_usb_ehci, OID_AUTO, no_hs, CTLFLAG_RW,
95 &ehcinohighspeed, 0, "Disable High Speed USB");
96 SYSCTL_INT(_hw_usb_ehci, OID_AUTO, iaadbug, CTLFLAG_RW,
97 &ehciiaadbug, 0, "Enable doorbell bug workaround");
98 SYSCTL_INT(_hw_usb_ehci, OID_AUTO, lostintrbug, CTLFLAG_RW,
99 &ehcilostintrbug, 0, "Enable lost interrupt bug workaround");
100
101 TUNABLE_INT("hw.usb.ehci.debug", &ehcidebug);
102 TUNABLE_INT("hw.usb.ehci.no_hs", &ehcinohighspeed);
103 TUNABLE_INT("hw.usb.ehci.iaadbug", &ehciiaadbug);
104 TUNABLE_INT("hw.usb.ehci.lostintrbug", &ehcilostintrbug);
105
106 static void ehci_dump_regs(ehci_softc_t *sc);
107 static void ehci_dump_sqh(ehci_softc_t *sc, ehci_qh_t *sqh);
108
109 #endif
110
111 #define EHCI_INTR_ENDPT 1
112
113 static const struct usb_bus_methods ehci_bus_methods;
114 static const struct usb_pipe_methods ehci_device_bulk_methods;
115 static const struct usb_pipe_methods ehci_device_ctrl_methods;
116 static const struct usb_pipe_methods ehci_device_intr_methods;
117 static const struct usb_pipe_methods ehci_device_isoc_fs_methods;
118 static const struct usb_pipe_methods ehci_device_isoc_hs_methods;
119
120 static void ehci_do_poll(struct usb_bus *);
121 static void ehci_device_done(struct usb_xfer *, usb_error_t);
122 static uint8_t ehci_check_transfer(struct usb_xfer *);
123 static void ehci_timeout(void *);
124 static void ehci_poll_timeout(void *);
125
126 static void ehci_root_intr(ehci_softc_t *sc);
127
128 struct ehci_std_temp {
129 ehci_softc_t *sc;
130 struct usb_page_cache *pc;
131 ehci_qtd_t *td;
132 ehci_qtd_t *td_next;
133 uint32_t average;
134 uint32_t qtd_status;
135 uint32_t len;
136 uint16_t max_frame_size;
137 uint8_t shortpkt;
138 uint8_t auto_data_toggle;
139 uint8_t setup_alt_next;
140 uint8_t last_frame;
141 };
142
143 void
144 ehci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb)
145 {
146 ehci_softc_t *sc = EHCI_BUS2SC(bus);
147 uint32_t i;
148
149 cb(bus, &sc->sc_hw.pframes_pc, &sc->sc_hw.pframes_pg,
150 sizeof(uint32_t) * EHCI_FRAMELIST_COUNT, EHCI_FRAMELIST_ALIGN);
151
152 cb(bus, &sc->sc_hw.terminate_pc, &sc->sc_hw.terminate_pg,
153 sizeof(struct ehci_qh_sub), EHCI_QH_ALIGN);
154
155 cb(bus, &sc->sc_hw.async_start_pc, &sc->sc_hw.async_start_pg,
156 sizeof(ehci_qh_t), EHCI_QH_ALIGN);
157
158 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) {
159 cb(bus, sc->sc_hw.intr_start_pc + i,
160 sc->sc_hw.intr_start_pg + i,
161 sizeof(ehci_qh_t), EHCI_QH_ALIGN);
162 }
163
164 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) {
165 cb(bus, sc->sc_hw.isoc_hs_start_pc + i,
166 sc->sc_hw.isoc_hs_start_pg + i,
167 sizeof(ehci_itd_t), EHCI_ITD_ALIGN);
168 }
169
170 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) {
171 cb(bus, sc->sc_hw.isoc_fs_start_pc + i,
172 sc->sc_hw.isoc_fs_start_pg + i,
173 sizeof(ehci_sitd_t), EHCI_SITD_ALIGN);
174 }
175 }
176
177 usb_error_t
178 ehci_reset(ehci_softc_t *sc)
179 {
180 uint32_t hcr;
181 int i;
182
183 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET);
184 for (i = 0; i < 100; i++) {
185 usb_pause_mtx(NULL, hz / 128);
186 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET;
187 if (!hcr) {
188 if (sc->sc_flags & (EHCI_SCFLG_SETMODE | EHCI_SCFLG_BIGEMMIO)) {
189 /*
190 * Force USBMODE as requested. Controllers
191 * may have multiple operating modes.
192 */
193 uint32_t usbmode = EOREAD4(sc, EHCI_USBMODE);
194 if (sc->sc_flags & EHCI_SCFLG_SETMODE) {
195 usbmode = (usbmode &~ EHCI_UM_CM) | EHCI_UM_CM_HOST;
196 device_printf(sc->sc_bus.bdev,
197 "set host controller mode\n");
198 }
199 if (sc->sc_flags & EHCI_SCFLG_BIGEMMIO) {
200 usbmode = (usbmode &~ EHCI_UM_ES) | EHCI_UM_ES_BE;
201 device_printf(sc->sc_bus.bdev,
202 "set big-endian mode\n");
203 }
204 EOWRITE4(sc, EHCI_USBMODE, usbmode);
205 }
206 return (0);
207 }
208 }
209 device_printf(sc->sc_bus.bdev, "Reset timeout\n");
210 return (USB_ERR_IOERROR);
211 }
212
213 static usb_error_t
214 ehci_hcreset(ehci_softc_t *sc)
215 {
216 uint32_t hcr;
217 int i;
218
219 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */
220 for (i = 0; i < 100; i++) {
221 usb_pause_mtx(NULL, hz / 128);
222 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
223 if (hcr)
224 break;
225 }
226 if (!hcr)
227 /*
228 * Fall through and try reset anyway even though
229 * Table 2-9 in the EHCI spec says this will result
230 * in undefined behavior.
231 */
232 device_printf(sc->sc_bus.bdev, "stop timeout\n");
233
234 return (ehci_reset(sc));
235 }
236
237 static int
238 ehci_init_sub(struct ehci_softc *sc)
239 {
240 struct usb_page_search buf_res;
241 uint32_t cparams;
242 uint32_t hcr;
243 uint8_t i;
244
245 cparams = EREAD4(sc, EHCI_HCCPARAMS);
246
247 DPRINTF("cparams=0x%x\n", cparams);
248
249 if (EHCI_HCC_64BIT(cparams)) {
250 DPRINTF("HCC uses 64-bit structures\n");
251
252 /* MUST clear segment register if 64 bit capable */
253 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0);
254 }
255
256 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res);
257 EOWRITE4(sc, EHCI_PERIODICLISTBASE, buf_res.physaddr);
258
259 usbd_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res);
260 EOWRITE4(sc, EHCI_ASYNCLISTADDR, buf_res.physaddr | EHCI_LINK_QH);
261
262 /* enable interrupts */
263 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
264
265 /* turn on controller */
266 EOWRITE4(sc, EHCI_USBCMD,
267 EHCI_CMD_ITC_1 | /* 1 microframes interrupt delay */
268 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) |
269 EHCI_CMD_ASE |
270 EHCI_CMD_PSE |
271 EHCI_CMD_RS);
272
273 /* Take over port ownership */
274 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF);
275
276 for (i = 0; i < 100; i++) {
277 usb_pause_mtx(NULL, hz / 128);
278 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
279 if (!hcr) {
280 break;
281 }
282 }
283 if (hcr) {
284 device_printf(sc->sc_bus.bdev, "Run timeout\n");
285 return (USB_ERR_IOERROR);
286 }
287 return (USB_ERR_NORMAL_COMPLETION);
288 }
289
290 usb_error_t
291 ehci_init(ehci_softc_t *sc)
292 {
293 struct usb_page_search buf_res;
294 uint32_t version;
295 uint32_t sparams;
296 uint16_t i;
297 uint16_t x;
298 uint16_t y;
299 uint16_t bit;
300 usb_error_t err = 0;
301
302 DPRINTF("start\n");
303
304 usb_callout_init_mtx(&sc->sc_tmo_pcd, &sc->sc_bus.bus_lock, 0);
305 usb_callout_init_mtx(&sc->sc_tmo_poll, &sc->sc_bus.bus_lock, 0);
306
307 sc->sc_offs = EHCI_CAPLENGTH(EREAD4(sc, EHCI_CAPLEN_HCIVERSION));
308
309 #ifdef USB_DEBUG
310 if (ehciiaadbug)
311 sc->sc_flags |= EHCI_SCFLG_IAADBUG;
312 if (ehcilostintrbug)
313 sc->sc_flags |= EHCI_SCFLG_LOSTINTRBUG;
314 if (ehcidebug > 2) {
315 ehci_dump_regs(sc);
316 }
317 #endif
318
319 version = EHCI_HCIVERSION(EREAD4(sc, EHCI_CAPLEN_HCIVERSION));
320 device_printf(sc->sc_bus.bdev, "EHCI version %x.%x\n",
321 version >> 8, version & 0xff);
322
323 sparams = EREAD4(sc, EHCI_HCSPARAMS);
324 DPRINTF("sparams=0x%x\n", sparams);
325
326 sc->sc_noport = EHCI_HCS_N_PORTS(sparams);
327 sc->sc_bus.usbrev = USB_REV_2_0;
328
329 if (!(sc->sc_flags & EHCI_SCFLG_DONTRESET)) {
330 /* Reset the controller */
331 DPRINTF("%s: resetting\n",
332 device_get_nameunit(sc->sc_bus.bdev));
333
334 err = ehci_hcreset(sc);
335 if (err) {
336 device_printf(sc->sc_bus.bdev, "reset timeout\n");
337 return (err);
338 }
339 }
340
341 /*
342 * use current frame-list-size selection 0: 1024*4 bytes 1: 512*4
343 * bytes 2: 256*4 bytes 3: unknown
344 */
345 if (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD)) == 3) {
346 device_printf(sc->sc_bus.bdev, "invalid frame-list-size\n");
347 return (USB_ERR_IOERROR);
348 }
349 /* set up the bus struct */
350 sc->sc_bus.methods = &ehci_bus_methods;
351
352 sc->sc_eintrs = EHCI_NORMAL_INTRS;
353
354 if (1) {
355 struct ehci_qh_sub *qh;
356
357 usbd_get_page(&sc->sc_hw.terminate_pc, 0, &buf_res);
358
359 qh = buf_res.buffer;
360
361 sc->sc_terminate_self = htohc32(sc, buf_res.physaddr);
362
363 /* init terminate TD */
364 qh->qtd_next =
365 htohc32(sc, EHCI_LINK_TERMINATE);
366 qh->qtd_altnext =
367 htohc32(sc, EHCI_LINK_TERMINATE);
368 qh->qtd_status =
369 htohc32(sc, EHCI_QTD_HALTED);
370 }
371
372 for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) {
373 ehci_qh_t *qh;
374
375 usbd_get_page(sc->sc_hw.intr_start_pc + i, 0, &buf_res);
376
377 qh = buf_res.buffer;
378
379 /* initialize page cache pointer */
380
381 qh->page_cache = sc->sc_hw.intr_start_pc + i;
382
383 /* store a pointer to queue head */
384
385 sc->sc_intr_p_last[i] = qh;
386
387 qh->qh_self =
388 htohc32(sc, buf_res.physaddr) |
389 htohc32(sc, EHCI_LINK_QH);
390
391 qh->qh_endp =
392 htohc32(sc, EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH));
393 qh->qh_endphub =
394 htohc32(sc, EHCI_QH_SET_MULT(1));
395 qh->qh_curqtd = 0;
396
397 qh->qh_qtd.qtd_next =
398 htohc32(sc, EHCI_LINK_TERMINATE);
399 qh->qh_qtd.qtd_altnext =
400 htohc32(sc, EHCI_LINK_TERMINATE);
401 qh->qh_qtd.qtd_status =
402 htohc32(sc, EHCI_QTD_HALTED);
403 }
404
405 /*
406 * the QHs are arranged to give poll intervals that are
407 * powers of 2 times 1ms
408 */
409 bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2;
410 while (bit) {
411 x = bit;
412 while (x & bit) {
413 ehci_qh_t *qh_x;
414 ehci_qh_t *qh_y;
415
416 y = (x ^ bit) | (bit / 2);
417
418 qh_x = sc->sc_intr_p_last[x];
419 qh_y = sc->sc_intr_p_last[y];
420
421 /*
422 * the next QH has half the poll interval
423 */
424 qh_x->qh_link = qh_y->qh_self;
425
426 x++;
427 }
428 bit >>= 1;
429 }
430
431 if (1) {
432 ehci_qh_t *qh;
433
434 qh = sc->sc_intr_p_last[0];
435
436 /* the last (1ms) QH terminates */
437 qh->qh_link = htohc32(sc, EHCI_LINK_TERMINATE);
438 }
439 for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) {
440 ehci_sitd_t *sitd;
441 ehci_itd_t *itd;
442
443 usbd_get_page(sc->sc_hw.isoc_fs_start_pc + i, 0, &buf_res);
444
445 sitd = buf_res.buffer;
446
447 /* initialize page cache pointer */
448
449 sitd->page_cache = sc->sc_hw.isoc_fs_start_pc + i;
450
451 /* store a pointer to the transfer descriptor */
452
453 sc->sc_isoc_fs_p_last[i] = sitd;
454
455 /* initialize full speed isochronous */
456
457 sitd->sitd_self =
458 htohc32(sc, buf_res.physaddr) |
459 htohc32(sc, EHCI_LINK_SITD);
460
461 sitd->sitd_back =
462 htohc32(sc, EHCI_LINK_TERMINATE);
463
464 sitd->sitd_next =
465 sc->sc_intr_p_last[i | (EHCI_VIRTUAL_FRAMELIST_COUNT / 2)]->qh_self;
466
467
468 usbd_get_page(sc->sc_hw.isoc_hs_start_pc + i, 0, &buf_res);
469
470 itd = buf_res.buffer;
471
472 /* initialize page cache pointer */
473
474 itd->page_cache = sc->sc_hw.isoc_hs_start_pc + i;
475
476 /* store a pointer to the transfer descriptor */
477
478 sc->sc_isoc_hs_p_last[i] = itd;
479
480 /* initialize high speed isochronous */
481
482 itd->itd_self =
483 htohc32(sc, buf_res.physaddr) |
484 htohc32(sc, EHCI_LINK_ITD);
485
486 itd->itd_next =
487 sitd->sitd_self;
488 }
489
490 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res);
491
492 if (1) {
493 uint32_t *pframes;
494
495 pframes = buf_res.buffer;
496
497 /*
498 * execution order:
499 * pframes -> high speed isochronous ->
500 * full speed isochronous -> interrupt QH's
501 */
502 for (i = 0; i < EHCI_FRAMELIST_COUNT; i++) {
503 pframes[i] = sc->sc_isoc_hs_p_last
504 [i & (EHCI_VIRTUAL_FRAMELIST_COUNT - 1)]->itd_self;
505 }
506 }
507 usbd_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res);
508
509 if (1) {
510
511 ehci_qh_t *qh;
512
513 qh = buf_res.buffer;
514
515 /* initialize page cache pointer */
516
517 qh->page_cache = &sc->sc_hw.async_start_pc;
518
519 /* store a pointer to the queue head */
520
521 sc->sc_async_p_last = qh;
522
523 /* init dummy QH that starts the async list */
524
525 qh->qh_self =
526 htohc32(sc, buf_res.physaddr) |
527 htohc32(sc, EHCI_LINK_QH);
528
529 /* fill the QH */
530 qh->qh_endp =
531 htohc32(sc, EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL);
532 qh->qh_endphub = htohc32(sc, EHCI_QH_SET_MULT(1));
533 qh->qh_link = qh->qh_self;
534 qh->qh_curqtd = 0;
535
536 /* fill the overlay qTD */
537 qh->qh_qtd.qtd_next = htohc32(sc, EHCI_LINK_TERMINATE);
538 qh->qh_qtd.qtd_altnext = htohc32(sc, EHCI_LINK_TERMINATE);
539 qh->qh_qtd.qtd_status = htohc32(sc, EHCI_QTD_HALTED);
540 }
541 /* flush all cache into memory */
542
543 usb_bus_mem_flush_all(&sc->sc_bus, &ehci_iterate_hw_softc);
544
545 #ifdef USB_DEBUG
546 if (ehcidebug) {
547 ehci_dump_sqh(sc, sc->sc_async_p_last);
548 }
549 #endif
550
551 /* finial setup */
552 err = ehci_init_sub(sc);
553
554 if (!err) {
555 /* catch any lost interrupts */
556 ehci_do_poll(&sc->sc_bus);
557 }
558 return (err);
559 }
560
561 /*
562 * shut down the controller when the system is going down
563 */
564 void
565 ehci_detach(ehci_softc_t *sc)
566 {
567 USB_BUS_LOCK(&sc->sc_bus);
568
569 usb_callout_stop(&sc->sc_tmo_pcd);
570 usb_callout_stop(&sc->sc_tmo_poll);
571
572 EOWRITE4(sc, EHCI_USBINTR, 0);
573 USB_BUS_UNLOCK(&sc->sc_bus);
574
575 if (ehci_hcreset(sc)) {
576 DPRINTF("reset failed!\n");
577 }
578
579 /* XXX let stray task complete */
580 usb_pause_mtx(NULL, hz / 20);
581
582 usb_callout_drain(&sc->sc_tmo_pcd);
583 usb_callout_drain(&sc->sc_tmo_poll);
584 }
585
586 static void
587 ehci_suspend(ehci_softc_t *sc)
588 {
589 DPRINTF("stopping the HC\n");
590
591 /* reset HC */
592 ehci_hcreset(sc);
593 }
594
595 static void
596 ehci_resume(ehci_softc_t *sc)
597 {
598 /* reset HC */
599 ehci_hcreset(sc);
600
601 /* setup HC */
602 ehci_init_sub(sc);
603
604 /* catch any lost interrupts */
605 ehci_do_poll(&sc->sc_bus);
606 }
607
608 #ifdef USB_DEBUG
609 static void
610 ehci_dump_regs(ehci_softc_t *sc)
611 {
612 uint32_t i;
613
614 i = EOREAD4(sc, EHCI_USBCMD);
615 kprintf("cmd=0x%08x\n", i);
616
617 if (i & EHCI_CMD_ITC_1)
618 kprintf(" EHCI_CMD_ITC_1\n");
619 if (i & EHCI_CMD_ITC_2)
620 kprintf(" EHCI_CMD_ITC_2\n");
621 if (i & EHCI_CMD_ITC_4)
622 kprintf(" EHCI_CMD_ITC_4\n");
623 if (i & EHCI_CMD_ITC_8)
624 kprintf(" EHCI_CMD_ITC_8\n");
625 if (i & EHCI_CMD_ITC_16)
626 kprintf(" EHCI_CMD_ITC_16\n");
627 if (i & EHCI_CMD_ITC_32)
628 kprintf(" EHCI_CMD_ITC_32\n");
629 if (i & EHCI_CMD_ITC_64)
630 kprintf(" EHCI_CMD_ITC_64\n");
631 if (i & EHCI_CMD_ASPME)
632 kprintf(" EHCI_CMD_ASPME\n");
633 if (i & EHCI_CMD_ASPMC)
634 kprintf(" EHCI_CMD_ASPMC\n");
635 if (i & EHCI_CMD_LHCR)
636 kprintf(" EHCI_CMD_LHCR\n");
637 if (i & EHCI_CMD_IAAD)
638 kprintf(" EHCI_CMD_IAAD\n");
639 if (i & EHCI_CMD_ASE)
640 kprintf(" EHCI_CMD_ASE\n");
641 if (i & EHCI_CMD_PSE)
642 kprintf(" EHCI_CMD_PSE\n");
643 if (i & EHCI_CMD_FLS_M)
644 kprintf(" EHCI_CMD_FLS_M\n");
645 if (i & EHCI_CMD_HCRESET)
646 kprintf(" EHCI_CMD_HCRESET\n");
647 if (i & EHCI_CMD_RS)
648 kprintf(" EHCI_CMD_RS\n");
649
650 i = EOREAD4(sc, EHCI_USBSTS);
651
652 kprintf("sts=0x%08x\n", i);
653
654 if (i & EHCI_STS_ASS)
655 kprintf(" EHCI_STS_ASS\n");
656 if (i & EHCI_STS_PSS)
657 kprintf(" EHCI_STS_PSS\n");
658 if (i & EHCI_STS_REC)
659 kprintf(" EHCI_STS_REC\n");
660 if (i & EHCI_STS_HCH)
661 kprintf(" EHCI_STS_HCH\n");
662 if (i & EHCI_STS_IAA)
663 kprintf(" EHCI_STS_IAA\n");
664 if (i & EHCI_STS_HSE)
665 kprintf(" EHCI_STS_HSE\n");
666 if (i & EHCI_STS_FLR)
667 kprintf(" EHCI_STS_FLR\n");
668 if (i & EHCI_STS_PCD)
669 kprintf(" EHCI_STS_PCD\n");
670 if (i & EHCI_STS_ERRINT)
671 kprintf(" EHCI_STS_ERRINT\n");
672 if (i & EHCI_STS_INT)
673 kprintf(" EHCI_STS_INT\n");
674
675 kprintf("ien=0x%08x\n",
676 EOREAD4(sc, EHCI_USBINTR));
677 kprintf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n",
678 EOREAD4(sc, EHCI_FRINDEX),
679 EOREAD4(sc, EHCI_CTRLDSSEGMENT),
680 EOREAD4(sc, EHCI_PERIODICLISTBASE),
681 EOREAD4(sc, EHCI_ASYNCLISTADDR));
682 for (i = 1; i <= sc->sc_noport; i++) {
683 kprintf("port %d status=0x%08x\n", i,
684 EOREAD4(sc, EHCI_PORTSC(i)));
685 }
686 }
687
688 static void
689 ehci_dump_link(ehci_softc_t *sc, uint32_t link, int type)
690 {
691 link = hc32toh(sc, link);
692 kprintf("0x%08x", link);
693 if (link & EHCI_LINK_TERMINATE)
694 kprintf("<T>");
695 else {
696 kprintf("<");
697 if (type) {
698 switch (EHCI_LINK_TYPE(link)) {
699 case EHCI_LINK_ITD:
700 kprintf("ITD");
701 break;
702 case EHCI_LINK_QH:
703 kprintf("QH");
704 break;
705 case EHCI_LINK_SITD:
706 kprintf("SITD");
707 break;
708 case EHCI_LINK_FSTN:
709 kprintf("FSTN");
710 break;
711 }
712 }
713 kprintf(">");
714 }
715 }
716
717 static void
718 ehci_dump_qtd(ehci_softc_t *sc, ehci_qtd_t *qtd)
719 {
720 uint32_t s;
721
722 kprintf(" next=");
723 ehci_dump_link(sc, qtd->qtd_next, 0);
724 kprintf(" altnext=");
725 ehci_dump_link(sc, qtd->qtd_altnext, 0);
726 kprintf("\n");
727 s = hc32toh(sc, qtd->qtd_status);
728 kprintf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n",
729 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s),
730 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s));
731 kprintf(" cerr=%d pid=%d stat=%s%s%s%s%s%s%s%s\n",
732 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s),
733 (s & EHCI_QTD_ACTIVE) ? "ACTIVE" : "NOT_ACTIVE",
734 (s & EHCI_QTD_HALTED) ? "-HALTED" : "",
735 (s & EHCI_QTD_BUFERR) ? "-BUFERR" : "",
736 (s & EHCI_QTD_BABBLE) ? "-BABBLE" : "",
737 (s & EHCI_QTD_XACTERR) ? "-XACTERR" : "",
738 (s & EHCI_QTD_MISSEDMICRO) ? "-MISSED" : "",
739 (s & EHCI_QTD_SPLITXSTATE) ? "-SPLIT" : "",
740 (s & EHCI_QTD_PINGSTATE) ? "-PING" : "");
741
742 for (s = 0; s < 5; s++) {
743 kprintf(" buffer[%d]=0x%08x\n", s,
744 hc32toh(sc, qtd->qtd_buffer[s]));
745 }
746 for (s = 0; s < 5; s++) {
747 kprintf(" buffer_hi[%d]=0x%08x\n", s,
748 hc32toh(sc, qtd->qtd_buffer_hi[s]));
749 }
750 }
751
752 static uint8_t
753 ehci_dump_sqtd(ehci_softc_t *sc, ehci_qtd_t *sqtd)
754 {
755 uint8_t temp;
756
757 usb_pc_cpu_invalidate(sqtd->page_cache);
758 kprintf("QTD(%p) at 0x%08x:\n", sqtd, hc32toh(sc, sqtd->qtd_self));
759 ehci_dump_qtd(sc, sqtd);
760 temp = (sqtd->qtd_next & htohc32(sc, EHCI_LINK_TERMINATE)) ? 1 : 0;
761 return (temp);
762 }
763
764 static void
765 ehci_dump_sqtds(ehci_softc_t *sc, ehci_qtd_t *sqtd)
766 {
767 uint16_t i;
768 uint8_t stop;
769
770 stop = 0;
771 for (i = 0; sqtd && (i < 20) && !stop; sqtd = sqtd->obj_next, i++) {
772 stop = ehci_dump_sqtd(sc, sqtd);
773 }
774 if (sqtd) {
775 kprintf("dump aborted, too many TDs\n");
776 }
777 }
778
779 static void
780 ehci_dump_sqh(ehci_softc_t *sc, ehci_qh_t *qh)
781 {
782 uint32_t endp;
783 uint32_t endphub;
784
785 usb_pc_cpu_invalidate(qh->page_cache);
786 kprintf("QH(%p) at 0x%08x:\n", qh, hc32toh(sc, qh->qh_self) & ~0x1F);
787 kprintf(" link=");
788 ehci_dump_link(sc, qh->qh_link, 1);
789 kprintf("\n");
790 endp = hc32toh(sc, qh->qh_endp);
791 kprintf(" endp=0x%08x\n", endp);
792 kprintf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n",
793 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp),
794 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp),
795 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp));
796 kprintf(" mpl=0x%x ctl=%d nrl=%d\n",
797 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp),
798 EHCI_QH_GET_NRL(endp));
799 endphub = hc32toh(sc, qh->qh_endphub);
800 kprintf(" endphub=0x%08x\n", endphub);
801 kprintf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n",
802 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub),
803 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub),
804 EHCI_QH_GET_MULT(endphub));
805 kprintf(" curqtd=");
806 ehci_dump_link(sc, qh->qh_curqtd, 0);
807 kprintf("\n");
808 kprintf("Overlay qTD:\n");
809 ehci_dump_qtd(sc, (void *)&qh->qh_qtd);
810 }
811
812 static void
813 ehci_dump_sitd(ehci_softc_t *sc, ehci_sitd_t *sitd)
814 {
815 usb_pc_cpu_invalidate(sitd->page_cache);
816 kprintf("SITD(%p) at 0x%08x\n", sitd, hc32toh(sc, sitd->sitd_self) & ~0x1F);
817 kprintf(" next=0x%08x\n", hc32toh(sc, sitd->sitd_next));
818 kprintf(" portaddr=0x%08x dir=%s addr=%d endpt=0x%x port=0x%x huba=0x%x\n",
819 hc32toh(sc, sitd->sitd_portaddr),
820 (sitd->sitd_portaddr & htohc32(sc, EHCI_SITD_SET_DIR_IN))
821 ? "in" : "out",
822 EHCI_SITD_GET_ADDR(hc32toh(sc, sitd->sitd_portaddr)),
823 EHCI_SITD_GET_ENDPT(hc32toh(sc, sitd->sitd_portaddr)),
824 EHCI_SITD_GET_PORT(hc32toh(sc, sitd->sitd_portaddr)),
825 EHCI_SITD_GET_HUBA(hc32toh(sc, sitd->sitd_portaddr)));
826 kprintf(" mask=0x%08x\n", hc32toh(sc, sitd->sitd_mask));
827 kprintf(" status=0x%08x <%s> len=0x%x\n", hc32toh(sc, sitd->sitd_status),
828 (sitd->sitd_status & htohc32(sc, EHCI_SITD_ACTIVE)) ? "ACTIVE" : "",
829 EHCI_SITD_GET_LEN(hc32toh(sc, sitd->sitd_status)));
830 kprintf(" back=0x%08x, bp=0x%08x,0x%08x,0x%08x,0x%08x\n",
831 hc32toh(sc, sitd->sitd_back),
832 hc32toh(sc, sitd->sitd_bp[0]),
833 hc32toh(sc, sitd->sitd_bp[1]),
834 hc32toh(sc, sitd->sitd_bp_hi[0]),
835 hc32toh(sc, sitd->sitd_bp_hi[1]));
836 }
837
838 static void
839 ehci_dump_itd(ehci_softc_t *sc, ehci_itd_t *itd)
840 {
841 usb_pc_cpu_invalidate(itd->page_cache);
842 kprintf("ITD(%p) at 0x%08x\n", itd, hc32toh(sc, itd->itd_self) & ~0x1F);
843 kprintf(" next=0x%08x\n", hc32toh(sc, itd->itd_next));
844 kprintf(" status[0]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[0]),
845 (itd->itd_status[0] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
846 kprintf(" status[1]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[1]),
847 (itd->itd_status[1] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
848 kprintf(" status[2]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[2]),
849 (itd->itd_status[2] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
850 kprintf(" status[3]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[3]),
851 (itd->itd_status[3] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
852 kprintf(" status[4]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[4]),
853 (itd->itd_status[4] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
854 kprintf(" status[5]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[5]),
855 (itd->itd_status[5] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
856 kprintf(" status[6]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[6]),
857 (itd->itd_status[6] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
858 kprintf(" status[7]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[7]),
859 (itd->itd_status[7] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
860 kprintf(" bp[0]=0x%08x\n", hc32toh(sc, itd->itd_bp[0]));
861 kprintf(" addr=0x%02x; endpt=0x%01x\n",
862 EHCI_ITD_GET_ADDR(hc32toh(sc, itd->itd_bp[0])),
863 EHCI_ITD_GET_ENDPT(hc32toh(sc, itd->itd_bp[0])));
864 kprintf(" bp[1]=0x%08x\n", hc32toh(sc, itd->itd_bp[1]));
865 kprintf(" dir=%s; mpl=0x%02x\n",
866 (hc32toh(sc, itd->itd_bp[1]) & EHCI_ITD_SET_DIR_IN) ? "in" : "out",
867 EHCI_ITD_GET_MPL(hc32toh(sc, itd->itd_bp[1])));
868 kprintf(" bp[2..6]=0x%08x,0x%08x,0x%08x,0x%08x,0x%08x\n",
869 hc32toh(sc, itd->itd_bp[2]),
870 hc32toh(sc, itd->itd_bp[3]),
871 hc32toh(sc, itd->itd_bp[4]),
872 hc32toh(sc, itd->itd_bp[5]),
873 hc32toh(sc, itd->itd_bp[6]));
874 kprintf(" bp_hi=0x%08x,0x%08x,0x%08x,0x%08x,\n"
875 " 0x%08x,0x%08x,0x%08x\n",
876 hc32toh(sc, itd->itd_bp_hi[0]),
877 hc32toh(sc, itd->itd_bp_hi[1]),
878 hc32toh(sc, itd->itd_bp_hi[2]),
879 hc32toh(sc, itd->itd_bp_hi[3]),
880 hc32toh(sc, itd->itd_bp_hi[4]),
881 hc32toh(sc, itd->itd_bp_hi[5]),
882 hc32toh(sc, itd->itd_bp_hi[6]));
883 }
884
885 static void
886 ehci_dump_isoc(ehci_softc_t *sc)
887 {
888 ehci_itd_t *itd;
889 ehci_sitd_t *sitd;
890 uint16_t max = 1000;
891 uint16_t pos;
892
893 pos = (EOREAD4(sc, EHCI_FRINDEX) / 8) &
894 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
895
896 kprintf("%s: isochronous dump from frame 0x%03x:\n",
897 __func__, pos);
898
899 itd = sc->sc_isoc_hs_p_last[pos];
900 sitd = sc->sc_isoc_fs_p_last[pos];
901
902 while (itd && max && max--) {
903 ehci_dump_itd(sc, itd);
904 itd = itd->prev;
905 }
906
907 while (sitd && max && max--) {
908 ehci_dump_sitd(sc, sitd);
909 sitd = sitd->prev;
910 }
911 }
912
913 #endif
914
915 static void
916 ehci_transfer_intr_enqueue(struct usb_xfer *xfer)
917 {
918 /* check for early completion */
919 if (ehci_check_transfer(xfer)) {
920 return;
921 }
922 /* put transfer on interrupt queue */
923 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
924
925 /* start timeout, if any */
926 if (xfer->timeout != 0) {
927 usbd_transfer_timeout_ms(xfer, &ehci_timeout, xfer->timeout);
928 }
929 }
930
931 #define EHCI_APPEND_FS_TD(std,last) (last) = _ehci_append_fs_td(std,last)
932 static ehci_sitd_t *
933 _ehci_append_fs_td(ehci_sitd_t *std, ehci_sitd_t *last)
934 {
935 DPRINTFN(11, "%p to %p\n", std, last);
936
937 /* (sc->sc_bus.mtx) must be locked */
938
939 std->next = last->next;
940 std->sitd_next = last->sitd_next;
941
942 std->prev = last;
943
944 usb_pc_cpu_flush(std->page_cache);
945
946 /*
947 * the last->next->prev is never followed: std->next->prev = std;
948 */
949 last->next = std;
950 last->sitd_next = std->sitd_self;
951
952 usb_pc_cpu_flush(last->page_cache);
953
954 return (std);
955 }
956
957 #define EHCI_APPEND_HS_TD(std,last) (last) = _ehci_append_hs_td(std,last)
958 static ehci_itd_t *
959 _ehci_append_hs_td(ehci_itd_t *std, ehci_itd_t *last)
960 {
961 DPRINTFN(11, "%p to %p\n", std, last);
962
963 /* (sc->sc_bus.mtx) must be locked */
964
965 std->next = last->next;
966 std->itd_next = last->itd_next;
967
968 std->prev = last;
969
970 usb_pc_cpu_flush(std->page_cache);
971
972 /*
973 * the last->next->prev is never followed: std->next->prev = std;
974 */
975 last->next = std;
976 last->itd_next = std->itd_self;
977
978 usb_pc_cpu_flush(last->page_cache);
979
980 return (std);
981 }
982
983 #define EHCI_APPEND_QH(sqh,last) (last) = _ehci_append_qh(sqh,last)
984 static ehci_qh_t *
985 _ehci_append_qh(ehci_qh_t *sqh, ehci_qh_t *last)
986 {
987 DPRINTFN(11, "%p to %p\n", sqh, last);
988
989 if (sqh->prev != NULL) {
990 /* should not happen */
991 DPRINTFN(0, "QH already linked!\n");
992 return (last);
993 }
994 /* (sc->sc_bus.mtx) must be locked */
995
996 sqh->next = last->next;
997 sqh->qh_link = last->qh_link;
998
999 sqh->prev = last;
1000
1001 usb_pc_cpu_flush(sqh->page_cache);
1002
1003 /*
1004 * the last->next->prev is never followed: sqh->next->prev = sqh;
1005 */
1006
1007 last->next = sqh;
1008 last->qh_link = sqh->qh_self;
1009
1010 usb_pc_cpu_flush(last->page_cache);
1011
1012 return (sqh);
1013 }
1014
1015 #define EHCI_REMOVE_FS_TD(std,last) (last) = _ehci_remove_fs_td(std,last)
1016 static ehci_sitd_t *
1017 _ehci_remove_fs_td(ehci_sitd_t *std, ehci_sitd_t *last)
1018 {
1019 DPRINTFN(11, "%p from %p\n", std, last);
1020
1021 /* (sc->sc_bus.mtx) must be locked */
1022
1023 std->prev->next = std->next;
1024 std->prev->sitd_next = std->sitd_next;
1025
1026 usb_pc_cpu_flush(std->prev->page_cache);
1027
1028 if (std->next) {
1029 std->next->prev = std->prev;
1030 usb_pc_cpu_flush(std->next->page_cache);
1031 }
1032 return ((last == std) ? std->prev : last);
1033 }
1034
1035 #define EHCI_REMOVE_HS_TD(std,last) (last) = _ehci_remove_hs_td(std,last)
1036 static ehci_itd_t *
1037 _ehci_remove_hs_td(ehci_itd_t *std, ehci_itd_t *last)
1038 {
1039 DPRINTFN(11, "%p from %p\n", std, last);
1040
1041 /* (sc->sc_bus.mtx) must be locked */
1042
1043 std->prev->next = std->next;
1044 std->prev->itd_next = std->itd_next;
1045
1046 usb_pc_cpu_flush(std->prev->page_cache);
1047
1048 if (std->next) {
1049 std->next->prev = std->prev;
1050 usb_pc_cpu_flush(std->next->page_cache);
1051 }
1052 return ((last == std) ? std->prev : last);
1053 }
1054
1055 #define EHCI_REMOVE_QH(sqh,last) (last) = _ehci_remove_qh(sqh,last)
1056 static ehci_qh_t *
1057 _ehci_remove_qh(ehci_qh_t *sqh, ehci_qh_t *last)
1058 {
1059 DPRINTFN(11, "%p from %p\n", sqh, last);
1060
1061 /* (sc->sc_bus.mtx) must be locked */
1062
1063 /* only remove if not removed from a queue */
1064 if (sqh->prev) {
1065
1066 sqh->prev->next = sqh->next;
1067 sqh->prev->qh_link = sqh->qh_link;
1068
1069 usb_pc_cpu_flush(sqh->prev->page_cache);
1070
1071 if (sqh->next) {
1072 sqh->next->prev = sqh->prev;
1073 usb_pc_cpu_flush(sqh->next->page_cache);
1074 }
1075 last = ((last == sqh) ? sqh->prev : last);
1076
1077 sqh->prev = 0;
1078
1079 usb_pc_cpu_flush(sqh->page_cache);
1080 }
1081 return (last);
1082 }
1083
1084 static void
1085 ehci_data_toggle_update(struct usb_xfer *xfer, uint16_t actlen, uint16_t xlen)
1086 {
1087 uint16_t rem;
1088 uint8_t dt;
1089
1090 /* count number of full packets */
1091 dt = (actlen / xfer->max_packet_size) & 1;
1092
1093 /* compute remainder */
1094 rem = actlen % xfer->max_packet_size;
1095
1096 if (rem > 0)
1097 dt ^= 1; /* short packet at the end */
1098 else if (actlen != xlen)
1099 dt ^= 1; /* zero length packet at the end */
1100 else if (xlen == 0)
1101 dt ^= 1; /* zero length transfer */
1102
1103 xfer->endpoint->toggle_next ^= dt;
1104 }
1105
1106 static usb_error_t
1107 ehci_non_isoc_done_sub(struct usb_xfer *xfer)
1108 {
1109 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
1110 ehci_qtd_t *td;
1111 ehci_qtd_t *td_alt_next;
1112 uint32_t status;
1113 uint16_t len;
1114
1115 td = xfer->td_transfer_cache;
1116 td_alt_next = td->alt_next;
1117
1118 if (xfer->aframes != xfer->nframes) {
1119 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0);
1120 }
1121 while (1) {
1122
1123 usb_pc_cpu_invalidate(td->page_cache);
1124 status = hc32toh(sc, td->qtd_status);
1125
1126 len = EHCI_QTD_GET_BYTES(status);
1127
1128 /*
1129 * Verify the status length and
1130 * add the length to "frlengths[]":
1131 */
1132 if (len > td->len) {
1133 /* should not happen */
1134 DPRINTF("Invalid status length, "
1135 "0x%04x/0x%04x bytes\n", len, td->len);
1136 status |= EHCI_QTD_HALTED;
1137 } else if (xfer->aframes != xfer->nframes) {
1138 xfer->frlengths[xfer->aframes] += td->len - len;
1139 /* manually update data toggle */
1140 ehci_data_toggle_update(xfer, td->len - len, td->len);
1141 }
1142
1143 /* Check for last transfer */
1144 if (((void *)td) == xfer->td_transfer_last) {
1145 td = NULL;
1146 break;
1147 }
1148 /* Check for transfer error */
1149 if (status & EHCI_QTD_HALTED) {
1150 /* the transfer is finished */
1151 td = NULL;
1152 break;
1153 }
1154 /* Check for short transfer */
1155 if (len > 0) {
1156 if (xfer->flags_int.short_frames_ok) {
1157 /* follow alt next */
1158 td = td->alt_next;
1159 } else {
1160 /* the transfer is finished */
1161 td = NULL;
1162 }
1163 break;
1164 }
1165 td = td->obj_next;
1166
1167 if (td->alt_next != td_alt_next) {
1168 /* this USB frame is complete */
1169 break;
1170 }
1171 }
1172
1173 /* update transfer cache */
1174
1175 xfer->td_transfer_cache = td;
1176
1177 #ifdef USB_DEBUG
1178 if (status & EHCI_QTD_STATERRS) {
1179 DPRINTFN(11, "error, addr=%d, endpt=0x%02x, frame=0x%02x"
1180 "status=%s%s%s%s%s%s%s%s\n",
1181 xfer->address, xfer->endpointno, xfer->aframes,
1182 (status & EHCI_QTD_ACTIVE) ? "[ACTIVE]" : "[NOT_ACTIVE]",
1183 (status & EHCI_QTD_HALTED) ? "[HALTED]" : "",
1184 (status & EHCI_QTD_BUFERR) ? "[BUFERR]" : "",
1185 (status & EHCI_QTD_BABBLE) ? "[BABBLE]" : "",
1186 (status & EHCI_QTD_XACTERR) ? "[XACTERR]" : "",
1187 (status & EHCI_QTD_MISSEDMICRO) ? "[MISSED]" : "",
1188 (status & EHCI_QTD_SPLITXSTATE) ? "[SPLIT]" : "",
1189 (status & EHCI_QTD_PINGSTATE) ? "[PING]" : "");
1190 }
1191 #endif
1192
1193 return ((status & EHCI_QTD_HALTED) ?
1194 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION);
1195 }
1196
1197 static void
1198 ehci_non_isoc_done(struct usb_xfer *xfer)
1199 {
1200 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
1201 ehci_qh_t *qh;
1202 uint32_t status;
1203 usb_error_t err = 0;
1204
1205 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
1206 xfer, xfer->endpoint);
1207
1208 #ifdef USB_DEBUG
1209 if (ehcidebug > 10) {
1210 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
1211
1212 ehci_dump_sqtds(sc, xfer->td_transfer_first);
1213 }
1214 #endif
1215
1216 /* extract data toggle directly from the QH's overlay area */
1217
1218 qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
1219
1220 usb_pc_cpu_invalidate(qh->page_cache);
1221
1222 status = hc32toh(sc, qh->qh_qtd.qtd_status);
1223
1224 /* reset scanner */
1225
1226 xfer->td_transfer_cache = xfer->td_transfer_first;
1227
1228 if (xfer->flags_int.control_xfr) {
1229
1230 if (xfer->flags_int.control_hdr) {
1231
1232 err = ehci_non_isoc_done_sub(xfer);
1233 }
1234 xfer->aframes = 1;
1235
1236 if (xfer->td_transfer_cache == NULL) {
1237 goto done;
1238 }
1239 }
1240 while (xfer->aframes != xfer->nframes) {
1241
1242 err = ehci_non_isoc_done_sub(xfer);
1243 xfer->aframes++;
1244
1245 if (xfer->td_transfer_cache == NULL) {
1246 goto done;
1247 }
1248 }
1249
1250 if (xfer->flags_int.control_xfr &&
1251 !xfer->flags_int.control_act) {
1252
1253 err = ehci_non_isoc_done_sub(xfer);
1254 }
1255 done:
1256 ehci_device_done(xfer, err);
1257 }
1258
1259 /*------------------------------------------------------------------------*
1260 * ehci_check_transfer
1261 *
1262 * Return values:
1263 * 0: USB transfer is not finished
1264 * Else: USB transfer is finished
1265 *------------------------------------------------------------------------*/
1266 static uint8_t
1267 ehci_check_transfer(struct usb_xfer *xfer)
1268 {
1269 const struct usb_pipe_methods *methods = xfer->endpoint->methods;
1270 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
1271
1272 uint32_t status;
1273
1274 DPRINTFN(13, "xfer=%p checking transfer\n", xfer);
1275
1276 if (methods == &ehci_device_isoc_fs_methods) {
1277 ehci_sitd_t *td;
1278
1279 /* isochronous full speed transfer */
1280
1281 td = xfer->td_transfer_last;
1282 usb_pc_cpu_invalidate(td->page_cache);
1283 status = hc32toh(sc, td->sitd_status);
1284
1285 /* also check if first is complete */
1286
1287 td = xfer->td_transfer_first;
1288 usb_pc_cpu_invalidate(td->page_cache);
1289 status |= hc32toh(sc, td->sitd_status);
1290
1291 if (!(status & EHCI_SITD_ACTIVE)) {
1292 ehci_device_done(xfer, USB_ERR_NORMAL_COMPLETION);
1293 goto transferred;
1294 }
1295 } else if (methods == &ehci_device_isoc_hs_methods) {
1296 ehci_itd_t *td;
1297
1298 /* isochronous high speed transfer */
1299
1300 /* check last transfer */
1301 td = xfer->td_transfer_last;
1302 usb_pc_cpu_invalidate(td->page_cache);
1303 status = td->itd_status[0];
1304 status |= td->itd_status[1];
1305 status |= td->itd_status[2];
1306 status |= td->itd_status[3];
1307 status |= td->itd_status[4];
1308 status |= td->itd_status[5];
1309 status |= td->itd_status[6];
1310 status |= td->itd_status[7];
1311
1312 /* also check first transfer */
1313 td = xfer->td_transfer_first;
1314 usb_pc_cpu_invalidate(td->page_cache);
1315 status |= td->itd_status[0];
1316 status |= td->itd_status[1];
1317 status |= td->itd_status[2];
1318 status |= td->itd_status[3];
1319 status |= td->itd_status[4];
1320 status |= td->itd_status[5];
1321 status |= td->itd_status[6];
1322 status |= td->itd_status[7];
1323
1324 /* if no transactions are active we continue */
1325 if (!(status & htohc32(sc, EHCI_ITD_ACTIVE))) {
1326 ehci_device_done(xfer, USB_ERR_NORMAL_COMPLETION);
1327 goto transferred;
1328 }
1329 } else {
1330 ehci_qtd_t *td;
1331 ehci_qh_t *qh;
1332
1333 /* non-isochronous transfer */
1334
1335 /*
1336 * check whether there is an error somewhere in the middle,
1337 * or whether there was a short packet (SPD and not ACTIVE)
1338 */
1339 td = xfer->td_transfer_cache;
1340
1341 qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
1342
1343 usb_pc_cpu_invalidate(qh->page_cache);
1344
1345 status = hc32toh(sc, qh->qh_qtd.qtd_status);
1346 if (status & EHCI_QTD_ACTIVE) {
1347 /* transfer is pending */
1348 goto done;
1349 }
1350
1351 while (1) {
1352 usb_pc_cpu_invalidate(td->page_cache);
1353 status = hc32toh(sc, td->qtd_status);
1354
1355 /*
1356 * Check if there is an active TD which
1357 * indicates that the transfer isn't done.
1358 */
1359 if (status & EHCI_QTD_ACTIVE) {
1360 /* update cache */
1361 xfer->td_transfer_cache = td;
1362 goto done;
1363 }
1364 /*
1365 * last transfer descriptor makes the transfer done
1366 */
1367 if (((void *)td) == xfer->td_transfer_last) {
1368 break;
1369 }
1370 /*
1371 * any kind of error makes the transfer done
1372 */
1373 if (status & EHCI_QTD_HALTED) {
1374 break;
1375 }
1376 /*
1377 * if there is no alternate next transfer, a short
1378 * packet also makes the transfer done
1379 */
1380 if (EHCI_QTD_GET_BYTES(status)) {
1381 if (xfer->flags_int.short_frames_ok) {
1382 /* follow alt next */
1383 if (td->alt_next) {
1384 td = td->alt_next;
1385 continue;
1386 }
1387 }
1388 /* transfer is done */
1389 break;
1390 }
1391 td = td->obj_next;
1392 }
1393 ehci_non_isoc_done(xfer);
1394 goto transferred;
1395 }
1396
1397 done:
1398 DPRINTFN(13, "xfer=%p is still active\n", xfer);
1399 return (0);
1400
1401 transferred:
1402 return (1);
1403 }
1404
1405 static void
1406 ehci_pcd_enable(ehci_softc_t *sc)
1407 {
1408 USB_BUS_LOCK_ASSERT(&sc->sc_bus);
1409
1410 sc->sc_eintrs |= EHCI_STS_PCD;
1411 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
1412
1413 /* acknowledge any PCD interrupt */
1414 EOWRITE4(sc, EHCI_USBSTS, EHCI_STS_PCD);
1415
1416 ehci_root_intr(sc);
1417 }
1418
1419 static void
1420 ehci_interrupt_poll(ehci_softc_t *sc)
1421 {
1422 struct usb_xfer *xfer;
1423
1424 repeat:
1425 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
1426 /*
1427 * check if transfer is transferred
1428 */
1429 if (ehci_check_transfer(xfer)) {
1430 /* queue has been modified */
1431 goto repeat;
1432 }
1433 }
1434 }
1435
1436 /*
1437 * Some EHCI chips from VIA / ATI seem to trigger interrupts before
1438 * writing back the qTD status, or miss signalling occasionally under
1439 * heavy load. If the host machine is too fast, we can miss
1440 * transaction completion - when we scan the active list the
1441 * transaction still seems to be active. This generally exhibits
1442 * itself as a umass stall that never recovers.
1443 *
1444 * We work around this behaviour by setting up this callback after any
1445 * softintr that completes with transactions still pending, giving us
1446 * another chance to check for completion after the writeback has
1447 * taken place.
1448 */
1449 static void
1450 ehci_poll_timeout(void *arg)
1451 {
1452 ehci_softc_t *sc = arg;
1453
1454 DPRINTFN(3, "\n");
1455 ehci_interrupt_poll(sc);
1456 }
1457
1458 /*------------------------------------------------------------------------*
1459 * ehci_interrupt - EHCI interrupt handler
1460 *
1461 * NOTE: Do not access "sc->sc_bus.bdev" inside the interrupt handler,
1462 * hence the interrupt handler will be setup before "sc->sc_bus.bdev"
1463 * is present !
1464 *------------------------------------------------------------------------*/
1465 void
1466 ehci_interrupt(ehci_softc_t *sc)
1467 {
1468 uint32_t status;
1469
1470 USB_BUS_LOCK(&sc->sc_bus);
1471
1472 DPRINTFN(16, "real interrupt\n");
1473
1474 #ifdef USB_DEBUG
1475 if (ehcidebug > 15) {
1476 ehci_dump_regs(sc);
1477 }
1478 #endif
1479
1480 status = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS));
1481 if (status == 0) {
1482 /* the interrupt was not for us */
1483 goto done;
1484 }
1485 if (!(status & sc->sc_eintrs)) {
1486 goto done;
1487 }
1488 EOWRITE4(sc, EHCI_USBSTS, status); /* acknowledge */
1489
1490 status &= sc->sc_eintrs;
1491
1492 if (status & EHCI_STS_HSE) {
1493 kprintf("%s: unrecoverable error, "
1494 "controller halted\n", __func__);
1495 #ifdef USB_DEBUG
1496 ehci_dump_regs(sc);
1497 ehci_dump_isoc(sc);
1498 #endif
1499 }
1500 if (status & EHCI_STS_PCD) {
1501 /*
1502 * Disable PCD interrupt for now, because it will be
1503 * on until the port has been reset.
1504 */
1505 sc->sc_eintrs &= ~EHCI_STS_PCD;
1506 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
1507
1508 ehci_root_intr(sc);
1509
1510 /* do not allow RHSC interrupts > 1 per second */
1511 usb_callout_reset(&sc->sc_tmo_pcd, hz,
1512 (void *)&ehci_pcd_enable, sc);
1513 }
1514 status &= ~(EHCI_STS_INT | EHCI_STS_ERRINT | EHCI_STS_PCD | EHCI_STS_IAA);
1515
1516 if (status != 0) {
1517 /* block unprocessed interrupts */
1518 sc->sc_eintrs &= ~status;
1519 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
1520 kprintf("%s: blocking interrupts 0x%x\n", __func__, status);
1521 }
1522 /* poll all the USB transfers */
1523 ehci_interrupt_poll(sc);
1524
1525 if (sc->sc_flags & EHCI_SCFLG_LOSTINTRBUG) {
1526 usb_callout_reset(&sc->sc_tmo_poll, hz / 128,
1527 (void *)&ehci_poll_timeout, sc);
1528 }
1529
1530 done:
1531 USB_BUS_UNLOCK(&sc->sc_bus);
1532 }
1533
1534 /*
1535 * called when a request does not complete
1536 */
1537 static void
1538 ehci_timeout(void *arg)
1539 {
1540 struct usb_xfer *xfer = arg;
1541
1542 DPRINTF("xfer=%p\n", xfer);
1543
1544 USB_BUS_LOCK_ASSERT(xfer->xroot->bus);
1545
1546 /* transfer is transferred */
1547 ehci_device_done(xfer, USB_ERR_TIMEOUT);
1548 }
1549
1550 static void
1551 ehci_do_poll(struct usb_bus *bus)
1552 {
1553 ehci_softc_t *sc = EHCI_BUS2SC(bus);
1554
1555 USB_BUS_LOCK(&sc->sc_bus);
1556 ehci_interrupt_poll(sc);
1557 USB_BUS_UNLOCK(&sc->sc_bus);
1558 }
1559
1560 static void
1561 ehci_setup_standard_chain_sub(struct ehci_std_temp *temp)
1562 {
1563 struct usb_page_search buf_res;
1564 ehci_qtd_t *td;
1565 ehci_qtd_t *td_next;
1566 ehci_qtd_t *td_alt_next;
1567 uint32_t buf_offset;
1568 uint32_t average;
1569 uint32_t len_old;
1570 uint32_t terminate;
1571 uint32_t qtd_altnext;
1572 uint8_t shortpkt_old;
1573 uint8_t precompute;
1574
1575 terminate = temp->sc->sc_terminate_self;
1576 qtd_altnext = temp->sc->sc_terminate_self;
1577 td_alt_next = NULL;
1578 buf_offset = 0;
1579 shortpkt_old = temp->shortpkt;
1580 len_old = temp->len;
1581 precompute = 1;
1582
1583 restart:
1584
1585 td = temp->td;
1586 td_next = temp->td_next;
1587
1588 while (1) {
1589
1590 if (temp->len == 0) {
1591
1592 if (temp->shortpkt) {
1593 break;
1594 }
1595 /* send a Zero Length Packet, ZLP, last */
1596
1597 temp->shortpkt = 1;
1598 average = 0;
1599
1600 } else {
1601
1602 average = temp->average;
1603
1604 if (temp->len < average) {
1605 if (temp->len % temp->max_frame_size) {
1606 temp->shortpkt = 1;
1607 }
1608 average = temp->len;
1609 }
1610 }
1611
1612 if (td_next == NULL) {
1613 panic("%s: out of EHCI transfer descriptors!", __func__);
1614 }
1615 /* get next TD */
1616
1617 td = td_next;
1618 td_next = td->obj_next;
1619
1620 /* check if we are pre-computing */
1621
1622 if (precompute) {
1623
1624 /* update remaining length */
1625
1626 temp->len -= average;
1627
1628 continue;
1629 }
1630 /* fill out current TD */
1631
1632 td->qtd_status =
1633 temp->qtd_status |
1634 htohc32(temp->sc, EHCI_QTD_IOC |
1635 EHCI_QTD_SET_BYTES(average));
1636
1637 if (average == 0) {
1638
1639 if (temp->auto_data_toggle == 0) {
1640
1641 /* update data toggle, ZLP case */
1642
1643 temp->qtd_status ^=
1644 htohc32(temp->sc, EHCI_QTD_TOGGLE_MASK);
1645 }
1646 td->len = 0;
1647
1648 td->qtd_buffer[0] = 0;
1649 td->qtd_buffer_hi[0] = 0;
1650
1651 td->qtd_buffer[1] = 0;
1652 td->qtd_buffer_hi[1] = 0;
1653
1654 } else {
1655
1656 uint8_t x;
1657
1658 if (temp->auto_data_toggle == 0) {
1659
1660 /* update data toggle */
1661
1662 if (((average + temp->max_frame_size - 1) /
1663 temp->max_frame_size) & 1) {
1664 temp->qtd_status ^=
1665 htohc32(temp->sc, EHCI_QTD_TOGGLE_MASK);
1666 }
1667 }
1668 td->len = average;
1669
1670 /* update remaining length */
1671
1672 temp->len -= average;
1673
1674 /* fill out buffer pointers */
1675
1676 usbd_get_page(temp->pc, buf_offset, &buf_res);
1677 td->qtd_buffer[0] =
1678 htohc32(temp->sc, buf_res.physaddr);
1679 td->qtd_buffer_hi[0] = 0;
1680
1681 x = 1;
1682
1683 while (average > EHCI_PAGE_SIZE) {
1684 average -= EHCI_PAGE_SIZE;
1685 buf_offset += EHCI_PAGE_SIZE;
1686 usbd_get_page(temp->pc, buf_offset, &buf_res);
1687 td->qtd_buffer[x] =
1688 htohc32(temp->sc,
1689 buf_res.physaddr & (~0xFFF));
1690 td->qtd_buffer_hi[x] = 0;
1691 x++;
1692 }
1693
1694 /*
1695 * NOTE: The "average" variable is never zero after
1696 * exiting the loop above !
1697 *
1698 * NOTE: We have to subtract one from the offset to
1699 * ensure that we are computing the physical address
1700 * of a valid page !
1701 */
1702 buf_offset += average;
1703 usbd_get_page(temp->pc, buf_offset - 1, &buf_res);
1704 td->qtd_buffer[x] =
1705 htohc32(temp->sc,
1706 buf_res.physaddr & (~0xFFF));
1707 td->qtd_buffer_hi[x] = 0;
1708 }
1709
1710 if (td_next) {
1711 /* link the current TD with the next one */
1712 td->qtd_next = td_next->qtd_self;
1713 }
1714 td->qtd_altnext = qtd_altnext;
1715 td->alt_next = td_alt_next;
1716
1717 usb_pc_cpu_flush(td->page_cache);
1718 }
1719
1720 if (precompute) {
1721 precompute = 0;
1722
1723 /* setup alt next pointer, if any */
1724 if (temp->last_frame) {
1725 td_alt_next = NULL;
1726 qtd_altnext = terminate;
1727 } else {
1728 /* we use this field internally */
1729 td_alt_next = td_next;
1730 if (temp->setup_alt_next) {
1731 qtd_altnext = td_next->qtd_self;
1732 } else {
1733 qtd_altnext = terminate;
1734 }
1735 }
1736
1737 /* restore */
1738 temp->shortpkt = shortpkt_old;
1739 temp->len = len_old;
1740 goto restart;
1741 }
1742 temp->td = td;
1743 temp->td_next = td_next;
1744 }
1745
1746 static void
1747 ehci_setup_standard_chain(struct usb_xfer *xfer, ehci_qh_t **qh_last)
1748 {
1749 struct ehci_std_temp temp;
1750 const struct usb_pipe_methods *methods;
1751 ehci_qh_t *qh;
1752 ehci_qtd_t *td;
1753 uint32_t qh_endp;
1754 uint32_t qh_endphub;
1755 uint32_t x;
1756
1757 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n",
1758 xfer->address, UE_GET_ADDR(xfer->endpointno),
1759 xfer->sumlen, usbd_get_speed(xfer->xroot->udev));
1760
1761 temp.average = xfer->max_hc_frame_size;
1762 temp.max_frame_size = xfer->max_frame_size;
1763 temp.sc = EHCI_BUS2SC(xfer->xroot->bus);
1764
1765 /* toggle the DMA set we are using */
1766 xfer->flags_int.curr_dma_set ^= 1;
1767
1768 /* get next DMA set */
1769 td = xfer->td_start[xfer->flags_int.curr_dma_set];
1770
1771 xfer->td_transfer_first = td;
1772 xfer->td_transfer_cache = td;
1773
1774 temp.td = NULL;
1775 temp.td_next = td;
1776 temp.qtd_status = 0;
1777 temp.last_frame = 0;
1778 temp.setup_alt_next = xfer->flags_int.short_frames_ok;
1779
1780 if (xfer->flags_int.control_xfr) {
1781 if (xfer->endpoint->toggle_next) {
1782 /* DATA1 is next */
1783 temp.qtd_status |=
1784 htohc32(temp.sc, EHCI_QTD_SET_TOGGLE(1));
1785 }
1786 temp.auto_data_toggle = 0;
1787 } else {
1788 temp.auto_data_toggle = 1;
1789 }
1790
1791 if ((xfer->xroot->udev->parent_hs_hub != NULL) ||
1792 (xfer->xroot->udev->address != 0)) {
1793 /* max 3 retries */
1794 temp.qtd_status |=
1795 htohc32(temp.sc, EHCI_QTD_SET_CERR(3));
1796 }
1797 /* check if we should prepend a setup message */
1798
1799 if (xfer->flags_int.control_xfr) {
1800 if (xfer->flags_int.control_hdr) {
1801
1802 xfer->endpoint->toggle_next = 0;
1803
1804 temp.qtd_status &=
1805 htohc32(temp.sc, EHCI_QTD_SET_CERR(3));
1806 temp.qtd_status |= htohc32(temp.sc,
1807 EHCI_QTD_ACTIVE |
1808 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) |
1809 EHCI_QTD_SET_TOGGLE(0));
1810
1811 temp.len = xfer->frlengths[0];
1812 temp.pc = xfer->frbuffers + 0;
1813 temp.shortpkt = temp.len ? 1 : 0;
1814 /* check for last frame */
1815 if (xfer->nframes == 1) {
1816 /* no STATUS stage yet, SETUP is last */
1817 if (xfer->flags_int.control_act) {
1818 temp.last_frame = 1;
1819 temp.setup_alt_next = 0;
1820 }
1821 }
1822 ehci_setup_standard_chain_sub(&temp);
1823 }
1824 x = 1;
1825 } else {
1826 x = 0;
1827 }
1828
1829 while (x != xfer->nframes) {
1830
1831 /* DATA0 / DATA1 message */
1832
1833 temp.len = xfer->frlengths[x];
1834 temp.pc = xfer->frbuffers + x;
1835
1836 x++;
1837
1838 if (x == xfer->nframes) {
1839 if (xfer->flags_int.control_xfr) {
1840 /* no STATUS stage yet, DATA is last */
1841 if (xfer->flags_int.control_act) {
1842 temp.last_frame = 1;
1843 temp.setup_alt_next = 0;
1844 }
1845 } else {
1846 temp.last_frame = 1;
1847 temp.setup_alt_next = 0;
1848 }
1849 }
1850 /* keep previous data toggle and error count */
1851
1852 temp.qtd_status &=
1853 htohc32(temp.sc, EHCI_QTD_SET_CERR(3) |
1854 EHCI_QTD_SET_TOGGLE(1));
1855
1856 if (temp.len == 0) {
1857
1858 /* make sure that we send an USB packet */
1859
1860 temp.shortpkt = 0;
1861
1862 } else {
1863
1864 /* regular data transfer */
1865
1866 temp.shortpkt = (xfer->flags.force_short_xfer) ? 0 : 1;
1867 }
1868
1869 /* set endpoint direction */
1870
1871 temp.qtd_status |=
1872 (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) ?
1873 htohc32(temp.sc, EHCI_QTD_ACTIVE |
1874 EHCI_QTD_SET_PID(EHCI_QTD_PID_IN)) :
1875 htohc32(temp.sc, EHCI_QTD_ACTIVE |
1876 EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT));
1877
1878 ehci_setup_standard_chain_sub(&temp);
1879 }
1880
1881 /* check if we should append a status stage */
1882
1883 if (xfer->flags_int.control_xfr &&
1884 !xfer->flags_int.control_act) {
1885
1886 /*
1887 * Send a DATA1 message and invert the current endpoint
1888 * direction.
1889 */
1890
1891 temp.qtd_status &= htohc32(temp.sc, EHCI_QTD_SET_CERR(3) |
1892 EHCI_QTD_SET_TOGGLE(1));
1893 temp.qtd_status |=
1894 (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) ?
1895 htohc32(temp.sc, EHCI_QTD_ACTIVE |
1896 EHCI_QTD_SET_PID(EHCI_QTD_PID_IN) |
1897 EHCI_QTD_SET_TOGGLE(1)) :
1898 htohc32(temp.sc, EHCI_QTD_ACTIVE |
1899 EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT) |
1900 EHCI_QTD_SET_TOGGLE(1));
1901
1902 temp.len = 0;
1903 temp.pc = NULL;
1904 temp.shortpkt = 0;
1905 temp.last_frame = 1;
1906 temp.setup_alt_next = 0;
1907
1908 ehci_setup_standard_chain_sub(&temp);
1909 }
1910 td = temp.td;
1911
1912 /* the last TD terminates the transfer: */
1913 td->qtd_next = htohc32(temp.sc, EHCI_LINK_TERMINATE);
1914 td->qtd_altnext = htohc32(temp.sc, EHCI_LINK_TERMINATE);
1915
1916 usb_pc_cpu_flush(td->page_cache);
1917
1918 /* must have at least one frame! */
1919
1920 xfer->td_transfer_last = td;
1921
1922 #ifdef USB_DEBUG
1923 if (ehcidebug > 8) {
1924 DPRINTF("nexttog=%d; data before transfer:\n",
1925 xfer->endpoint->toggle_next);
1926 ehci_dump_sqtds(temp.sc,
1927 xfer->td_transfer_first);
1928 }
1929 #endif
1930
1931 methods = xfer->endpoint->methods;
1932
1933 qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
1934
1935 /* the "qh_link" field is filled when the QH is added */
1936
1937 qh_endp =
1938 (EHCI_QH_SET_ADDR(xfer->address) |
1939 EHCI_QH_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)) |
1940 EHCI_QH_SET_MPL(xfer->max_packet_size));
1941
1942 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_HIGH) {
1943 qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH);
1944 if (methods != &ehci_device_intr_methods)
1945 qh_endp |= EHCI_QH_SET_NRL(8);
1946 } else {
1947
1948 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_FULL) {
1949 qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_FULL);
1950 } else {
1951 qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_LOW);
1952 }
1953
1954 if (methods == &ehci_device_ctrl_methods) {
1955 qh_endp |= EHCI_QH_CTL;
1956 }
1957 if (methods != &ehci_device_intr_methods) {
1958 /* Only try one time per microframe! */
1959 qh_endp |= EHCI_QH_SET_NRL(1);
1960 }
1961 }
1962
1963 if (temp.auto_data_toggle == 0) {
1964 /* software computes the data toggle */
1965 qh_endp |= EHCI_QH_DTC;
1966 }
1967
1968 qh->qh_endp = htohc32(temp.sc, qh_endp);
1969
1970 qh_endphub =
1971 (EHCI_QH_SET_MULT(xfer->max_packet_count & 3) |
1972 EHCI_QH_SET_CMASK(xfer->endpoint->usb_cmask) |
1973 EHCI_QH_SET_SMASK(xfer->endpoint->usb_smask) |
1974 EHCI_QH_SET_HUBA(xfer->xroot->udev->hs_hub_addr) |
1975 EHCI_QH_SET_PORT(xfer->xroot->udev->hs_port_no));
1976
1977 qh->qh_endphub = htohc32(temp.sc, qh_endphub);
1978 qh->qh_curqtd = 0;
1979
1980 /* fill the overlay qTD */
1981
1982 if (temp.auto_data_toggle && xfer->endpoint->toggle_next) {
1983 /* DATA1 is next */
1984 qh->qh_qtd.qtd_status = htohc32(temp.sc, EHCI_QTD_SET_TOGGLE(1));
1985 } else {
1986 qh->qh_qtd.qtd_status = 0;
1987 }
1988
1989 td = xfer->td_transfer_first;
1990
1991 qh->qh_qtd.qtd_next = td->qtd_self;
1992 qh->qh_qtd.qtd_altnext =
1993 htohc32(temp.sc, EHCI_LINK_TERMINATE);
1994
1995 usb_pc_cpu_flush(qh->page_cache);
1996
1997 if (xfer->xroot->udev->flags.self_suspended == 0) {
1998 EHCI_APPEND_QH(qh, *qh_last);
1999 }
2000 }
2001
2002 static void
2003 ehci_root_intr(ehci_softc_t *sc)
2004 {
2005 uint16_t i;
2006 uint16_t m;
2007
2008 USB_BUS_LOCK_ASSERT(&sc->sc_bus);
2009
2010 /* clear any old interrupt data */
2011 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata));
2012
2013 /* set bits */
2014 m = (sc->sc_noport + 1);
2015 if (m > (8 * sizeof(sc->sc_hub_idata))) {
2016 m = (8 * sizeof(sc->sc_hub_idata));
2017 }
2018 for (i = 1; i < m; i++) {
2019 /* pick out CHANGE bits from the status register */
2020 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) {
2021 sc->sc_hub_idata[i / 8] |= 1 << (i % 8);
2022 DPRINTF("port %d changed\n", i);
2023 }
2024 }
2025 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
2026 sizeof(sc->sc_hub_idata));
2027 }
2028
2029 static void
2030 ehci_isoc_fs_done(ehci_softc_t *sc, struct usb_xfer *xfer)
2031 {
2032 uint32_t nframes = xfer->nframes;
2033 uint32_t status;
2034 uint32_t *plen = xfer->frlengths;
2035 uint16_t len = 0;
2036 ehci_sitd_t *td = xfer->td_transfer_first;
2037 ehci_sitd_t **pp_last = &sc->sc_isoc_fs_p_last[xfer->qh_pos];
2038
2039 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
2040 xfer, xfer->endpoint);
2041
2042 while (nframes--) {
2043 if (td == NULL) {
2044 panic("%s:%d: out of TD's\n",
2045 __func__, __LINE__);
2046 }
2047 if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) {
2048 pp_last = &sc->sc_isoc_fs_p_last[0];
2049 }
2050 #ifdef USB_DEBUG
2051 if (ehcidebug > 15) {
2052 DPRINTF("isoc FS-TD\n");
2053 ehci_dump_sitd(sc, td);
2054 }
2055 #endif
2056 usb_pc_cpu_invalidate(td->page_cache);
2057 status = hc32toh(sc, td->sitd_status);
2058
2059 len = EHCI_SITD_GET_LEN(status);
2060
2061 DPRINTFN(2, "status=0x%08x, rem=%u\n", status, len);
2062
2063 if (*plen >= len) {
2064 len = *plen - len;
2065 } else {
2066 len = 0;
2067 }
2068
2069 *plen = len;
2070
2071 /* remove FS-TD from schedule */
2072 EHCI_REMOVE_FS_TD(td, *pp_last);
2073
2074 pp_last++;
2075 plen++;
2076 td = td->obj_next;
2077 }
2078
2079 xfer->aframes = xfer->nframes;
2080 }
2081
2082 static void
2083 ehci_isoc_hs_done(ehci_softc_t *sc, struct usb_xfer *xfer)
2084 {
2085 uint32_t nframes = xfer->nframes;
2086 uint32_t status;
2087 uint32_t *plen = xfer->frlengths;
2088 uint16_t len = 0;
2089 uint8_t td_no = 0;
2090 ehci_itd_t *td = xfer->td_transfer_first;
2091 ehci_itd_t **pp_last = &sc->sc_isoc_hs_p_last[xfer->qh_pos];
2092
2093 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
2094 xfer, xfer->endpoint);
2095
2096 while (nframes) {
2097 if (td == NULL) {
2098 panic("%s:%d: out of TD's\n",
2099 __func__, __LINE__);
2100 }
2101 if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) {
2102 pp_last = &sc->sc_isoc_hs_p_last[0];
2103 }
2104 #ifdef USB_DEBUG
2105 if (ehcidebug > 15) {
2106 DPRINTF("isoc HS-TD\n");
2107 ehci_dump_itd(sc, td);
2108 }
2109 #endif
2110
2111 usb_pc_cpu_invalidate(td->page_cache);
2112 status = hc32toh(sc, td->itd_status[td_no]);
2113
2114 len = EHCI_ITD_GET_LEN(status);
2115
2116 DPRINTFN(2, "status=0x%08x, len=%u\n", status, len);
2117
2118 if (xfer->endpoint->usb_smask & (1 << td_no)) {
2119
2120 if (*plen >= len) {
2121 /*
2122 * The length is valid. NOTE: The
2123 * complete length is written back
2124 * into the status field, and not the
2125 * remainder like with other transfer
2126 * descriptor types.
2127 */
2128 } else {
2129 /* Invalid length - truncate */
2130 len = 0;
2131 }
2132
2133 *plen = len;
2134 plen++;
2135 nframes--;
2136 }
2137
2138 td_no++;
2139
2140 if ((td_no == 8) || (nframes == 0)) {
2141 /* remove HS-TD from schedule */
2142 EHCI_REMOVE_HS_TD(td, *pp_last);
2143 pp_last++;
2144
2145 td_no = 0;
2146 td = td->obj_next;
2147 }
2148 }
2149 xfer->aframes = xfer->nframes;
2150 }
2151
2152 /* NOTE: "done" can be run two times in a row,
2153 * from close and from interrupt
2154 */
2155 static void
2156 ehci_device_done(struct usb_xfer *xfer, usb_error_t error)
2157 {
2158 const struct usb_pipe_methods *methods = xfer->endpoint->methods;
2159 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2160
2161 USB_BUS_LOCK_ASSERT(&sc->sc_bus);
2162
2163 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
2164 xfer, xfer->endpoint, error);
2165
2166 if ((methods == &ehci_device_bulk_methods) ||
2167 (methods == &ehci_device_ctrl_methods)) {
2168 #ifdef USB_DEBUG
2169 if (ehcidebug > 8) {
2170 DPRINTF("nexttog=%d; data after transfer:\n",
2171 xfer->endpoint->toggle_next);
2172 ehci_dump_sqtds(sc,
2173 xfer->td_transfer_first);
2174 }
2175 #endif
2176
2177 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
2178 sc->sc_async_p_last);
2179 }
2180 if (methods == &ehci_device_intr_methods) {
2181 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
2182 sc->sc_intr_p_last[xfer->qh_pos]);
2183 }
2184 /*
2185 * Only finish isochronous transfers once which will update
2186 * "xfer->frlengths".
2187 */
2188 if (xfer->td_transfer_first &&
2189 xfer->td_transfer_last) {
2190 if (methods == &ehci_device_isoc_fs_methods) {
2191 ehci_isoc_fs_done(sc, xfer);
2192 }
2193 if (methods == &ehci_device_isoc_hs_methods) {
2194 ehci_isoc_hs_done(sc, xfer);
2195 }
2196 xfer->td_transfer_first = NULL;
2197 xfer->td_transfer_last = NULL;
2198 }
2199 /* dequeue transfer and start next transfer */
2200 usbd_transfer_done(xfer, error);
2201 }
2202
2203 /*------------------------------------------------------------------------*
2204 * ehci bulk support
2205 *------------------------------------------------------------------------*/
2206 static void
2207 ehci_device_bulk_open(struct usb_xfer *xfer)
2208 {
2209 return;
2210 }
2211
2212 static void
2213 ehci_device_bulk_close(struct usb_xfer *xfer)
2214 {
2215 ehci_device_done(xfer, USB_ERR_CANCELLED);
2216 }
2217
2218 static void
2219 ehci_device_bulk_enter(struct usb_xfer *xfer)
2220 {
2221 return;
2222 }
2223
2224 static void
2225 ehci_device_bulk_start(struct usb_xfer *xfer)
2226 {
2227 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2228 uint32_t temp;
2229
2230 /* setup TD's and QH */
2231 ehci_setup_standard_chain(xfer, &sc->sc_async_p_last);
2232
2233 /* put transfer on interrupt queue */
2234 ehci_transfer_intr_enqueue(xfer);
2235
2236 /*
2237 * XXX Certain nVidia chipsets choke when using the IAAD
2238 * feature too frequently.
2239 */
2240 if (sc->sc_flags & EHCI_SCFLG_IAADBUG)
2241 return;
2242
2243 /* XXX Performance quirk: Some Host Controllers have a too low
2244 * interrupt rate. Issue an IAAD to stimulate the Host
2245 * Controller after queueing the BULK transfer.
2246 */
2247 temp = EOREAD4(sc, EHCI_USBCMD);
2248 if (!(temp & EHCI_CMD_IAAD))
2249 EOWRITE4(sc, EHCI_USBCMD, temp | EHCI_CMD_IAAD);
2250 }
2251
2252 static const struct usb_pipe_methods ehci_device_bulk_methods =
2253 {
2254 .open = ehci_device_bulk_open,
2255 .close = ehci_device_bulk_close,
2256 .enter = ehci_device_bulk_enter,
2257 .start = ehci_device_bulk_start,
2258 };
2259
2260 /*------------------------------------------------------------------------*
2261 * ehci control support
2262 *------------------------------------------------------------------------*/
2263 static void
2264 ehci_device_ctrl_open(struct usb_xfer *xfer)
2265 {
2266 return;
2267 }
2268
2269 static void
2270 ehci_device_ctrl_close(struct usb_xfer *xfer)
2271 {
2272 ehci_device_done(xfer, USB_ERR_CANCELLED);
2273 }
2274
2275 static void
2276 ehci_device_ctrl_enter(struct usb_xfer *xfer)
2277 {
2278 return;
2279 }
2280
2281 static void
2282 ehci_device_ctrl_start(struct usb_xfer *xfer)
2283 {
2284 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2285
2286 /* setup TD's and QH */
2287 ehci_setup_standard_chain(xfer, &sc->sc_async_p_last);
2288
2289 /* put transfer on interrupt queue */
2290 ehci_transfer_intr_enqueue(xfer);
2291 }
2292
2293 static const struct usb_pipe_methods ehci_device_ctrl_methods =
2294 {
2295 .open = ehci_device_ctrl_open,
2296 .close = ehci_device_ctrl_close,
2297 .enter = ehci_device_ctrl_enter,
2298 .start = ehci_device_ctrl_start,
2299 };
2300
2301 /*------------------------------------------------------------------------*
2302 * ehci interrupt support
2303 *------------------------------------------------------------------------*/
2304 static void
2305 ehci_device_intr_open(struct usb_xfer *xfer)
2306 {
2307 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2308 uint16_t best;
2309 uint16_t bit;
2310 uint16_t x;
2311
2312 usb_hs_bandwidth_alloc(xfer);
2313
2314 /*
2315 * Find the best QH position corresponding to the given interval:
2316 */
2317
2318 best = 0;
2319 bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2;
2320 while (bit) {
2321 if (xfer->interval >= bit) {
2322 x = bit;
2323 best = bit;
2324 while (x & bit) {
2325 if (sc->sc_intr_stat[x] <
2326 sc->sc_intr_stat[best]) {
2327 best = x;
2328 }
2329 x++;
2330 }
2331 break;
2332 }
2333 bit >>= 1;
2334 }
2335
2336 sc->sc_intr_stat[best]++;
2337 xfer->qh_pos = best;
2338
2339 DPRINTFN(3, "best=%d interval=%d\n",
2340 best, xfer->interval);
2341 }
2342
2343 static void
2344 ehci_device_intr_close(struct usb_xfer *xfer)
2345 {
2346 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2347
2348 sc->sc_intr_stat[xfer->qh_pos]--;
2349
2350 ehci_device_done(xfer, USB_ERR_CANCELLED);
2351
2352 /* bandwidth must be freed after device done */
2353 usb_hs_bandwidth_free(xfer);
2354 }
2355
2356 static void
2357 ehci_device_intr_enter(struct usb_xfer *xfer)
2358 {
2359 return;
2360 }
2361
2362 static void
2363 ehci_device_intr_start(struct usb_xfer *xfer)
2364 {
2365 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2366
2367 /* setup TD's and QH */
2368 ehci_setup_standard_chain(xfer, &sc->sc_intr_p_last[xfer->qh_pos]);
2369
2370 /* put transfer on interrupt queue */
2371 ehci_transfer_intr_enqueue(xfer);
2372 }
2373
2374 static const struct usb_pipe_methods ehci_device_intr_methods =
2375 {
2376 .open = ehci_device_intr_open,
2377 .close = ehci_device_intr_close,
2378 .enter = ehci_device_intr_enter,
2379 .start = ehci_device_intr_start,
2380 };
2381
2382 /*------------------------------------------------------------------------*
2383 * ehci full speed isochronous support
2384 *------------------------------------------------------------------------*/
2385 static void
2386 ehci_device_isoc_fs_open(struct usb_xfer *xfer)
2387 {
2388 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2389 ehci_sitd_t *td;
2390 uint32_t sitd_portaddr;
2391 uint8_t ds;
2392
2393 sitd_portaddr =
2394 EHCI_SITD_SET_ADDR(xfer->address) |
2395 EHCI_SITD_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)) |
2396 EHCI_SITD_SET_HUBA(xfer->xroot->udev->hs_hub_addr) |
2397 EHCI_SITD_SET_PORT(xfer->xroot->udev->hs_port_no);
2398
2399 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) {
2400 sitd_portaddr |= EHCI_SITD_SET_DIR_IN;
2401 }
2402 sitd_portaddr = htohc32(sc, sitd_portaddr);
2403
2404 /* initialize all TD's */
2405
2406 for (ds = 0; ds != 2; ds++) {
2407
2408 for (td = xfer->td_start[ds]; td; td = td->obj_next) {
2409
2410 td->sitd_portaddr = sitd_portaddr;
2411
2412 /*
2413 * TODO: make some kind of automatic
2414 * SMASK/CMASK selection based on micro-frame
2415 * usage
2416 *
2417 * micro-frame usage (8 microframes per 1ms)
2418 */
2419 td->sitd_back = htohc32(sc, EHCI_LINK_TERMINATE);
2420
2421 usb_pc_cpu_flush(td->page_cache);
2422 }
2423 }
2424 }
2425
2426 static void
2427 ehci_device_isoc_fs_close(struct usb_xfer *xfer)
2428 {
2429 ehci_device_done(xfer, USB_ERR_CANCELLED);
2430 }
2431
2432 static void
2433 ehci_device_isoc_fs_enter(struct usb_xfer *xfer)
2434 {
2435 struct usb_page_search buf_res;
2436 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2437 ehci_sitd_t *td;
2438 ehci_sitd_t *td_last = NULL;
2439 ehci_sitd_t **pp_last;
2440 uint32_t *plen;
2441 uint32_t buf_offset;
2442 uint32_t nframes;
2443 uint32_t temp;
2444 uint32_t sitd_mask;
2445 uint16_t tlen;
2446 uint8_t sa;
2447 uint8_t sb;
2448
2449 #ifdef USB_DEBUG
2450 uint8_t once = 1;
2451
2452 #endif
2453
2454 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n",
2455 xfer, xfer->endpoint->isoc_next, xfer->nframes);
2456
2457 /* get the current frame index */
2458
2459 nframes = EOREAD4(sc, EHCI_FRINDEX) / 8;
2460
2461 /*
2462 * check if the frame index is within the window where the frames
2463 * will be inserted
2464 */
2465 buf_offset = (nframes - xfer->endpoint->isoc_next) &
2466 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2467
2468 if ((xfer->endpoint->is_synced == 0) ||
2469 (buf_offset < xfer->nframes)) {
2470 /*
2471 * If there is data underflow or the pipe queue is empty we
2472 * schedule the transfer a few frames ahead of the current
2473 * frame position. Else two isochronous transfers might
2474 * overlap.
2475 */
2476 xfer->endpoint->isoc_next = (nframes + 3) &
2477 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2478 xfer->endpoint->is_synced = 1;
2479 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2480 }
2481 /*
2482 * compute how many milliseconds the insertion is ahead of the
2483 * current frame position:
2484 */
2485 buf_offset = (xfer->endpoint->isoc_next - nframes) &
2486 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2487
2488 /*
2489 * pre-compute when the isochronous transfer will be finished:
2490 */
2491 xfer->isoc_time_complete =
2492 usb_isoc_time_expand(&sc->sc_bus, nframes) +
2493 buf_offset + xfer->nframes;
2494
2495 /* get the real number of frames */
2496
2497 nframes = xfer->nframes;
2498
2499 buf_offset = 0;
2500
2501 plen = xfer->frlengths;
2502
2503 /* toggle the DMA set we are using */
2504 xfer->flags_int.curr_dma_set ^= 1;
2505
2506 /* get next DMA set */
2507 td = xfer->td_start[xfer->flags_int.curr_dma_set];
2508 xfer->td_transfer_first = td;
2509
2510 pp_last = &sc->sc_isoc_fs_p_last[xfer->endpoint->isoc_next];
2511
2512 /* store starting position */
2513
2514 xfer->qh_pos = xfer->endpoint->isoc_next;
2515
2516 while (nframes--) {
2517 if (td == NULL) {
2518 panic("%s:%d: out of TD's\n",
2519 __func__, __LINE__);
2520 }
2521 if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) {
2522 pp_last = &sc->sc_isoc_fs_p_last[0];
2523 }
2524 /* reuse sitd_portaddr and sitd_back from last transfer */
2525
2526 if (*plen > xfer->max_frame_size) {
2527 #ifdef USB_DEBUG
2528 if (once) {
2529 once = 0;
2530 kprintf("%s: frame length(%d) exceeds %d "
2531 "bytes (frame truncated)\n",
2532 __func__, *plen,
2533 xfer->max_frame_size);
2534 }
2535 #endif
2536 *plen = xfer->max_frame_size;
2537 }
2538
2539 /* allocate a slot */
2540
2541 sa = usbd_fs_isoc_schedule_alloc_slot(xfer,
2542 xfer->isoc_time_complete - nframes - 1);
2543
2544 if(sa == 255) {
2545 /*
2546 * Schedule is FULL, set length to zero:
2547 */
2548
2549 *plen = 0;
2550 sa = USB_FS_ISOC_UFRAME_MAX - 1;
2551 }
2552 if (*plen) {
2553 /*
2554 * only call "usbd_get_page()" when we have a
2555 * non-zero length
2556 */
2557 usbd_get_page(xfer->frbuffers, buf_offset, &buf_res);
2558 td->sitd_bp[0] = htohc32(sc, buf_res.physaddr);
2559 buf_offset += *plen;
2560 /*
2561 * NOTE: We need to subtract one from the offset so
2562 * that we are on a valid page!
2563 */
2564 usbd_get_page(xfer->frbuffers, buf_offset - 1,
2565 &buf_res);
2566 temp = buf_res.physaddr & ~0xFFF;
2567 } else {
2568 td->sitd_bp[0] = 0;
2569 temp = 0;
2570 }
2571
2572 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) {
2573 tlen = *plen;
2574 if (tlen <= 188) {
2575 temp |= 1; /* T-count = 1, TP = ALL */
2576 tlen = 1;
2577 } else {
2578 tlen += 187;
2579 tlen /= 188;
2580 temp |= tlen; /* T-count = [1..6] */
2581 temp |= 8; /* TP = Begin */
2582 }
2583
2584 tlen += sa;
2585
2586 if (tlen >= 8) {
2587 sb = 0;
2588 } else {
2589 sb = (1 << tlen);
2590 }
2591
2592 sa = (1 << sa);
2593 sa = (sb - sa) & 0x3F;
2594 sb = 0;
2595 } else {
2596 sb = (-(4 << sa)) & 0xFE;
2597 sa = (1 << sa) & 0x3F;
2598 }
2599
2600 sitd_mask = (EHCI_SITD_SET_SMASK(sa) |
2601 EHCI_SITD_SET_CMASK(sb));
2602
2603 td->sitd_bp[1] = htohc32(sc, temp);
2604
2605 td->sitd_mask = htohc32(sc, sitd_mask);
2606
2607 if (nframes == 0) {
2608 td->sitd_status = htohc32(sc,
2609 EHCI_SITD_IOC |
2610 EHCI_SITD_ACTIVE |
2611 EHCI_SITD_SET_LEN(*plen));
2612 } else {
2613 td->sitd_status = htohc32(sc,
2614 EHCI_SITD_ACTIVE |
2615 EHCI_SITD_SET_LEN(*plen));
2616 }
2617 usb_pc_cpu_flush(td->page_cache);
2618
2619 #ifdef USB_DEBUG
2620 if (ehcidebug > 15) {
2621 DPRINTF("FS-TD %d\n", nframes);
2622 ehci_dump_sitd(sc, td);
2623 }
2624 #endif
2625 /* insert TD into schedule */
2626 EHCI_APPEND_FS_TD(td, *pp_last);
2627 pp_last++;
2628
2629 plen++;
2630 td_last = td;
2631 td = td->obj_next;
2632 }
2633
2634 xfer->td_transfer_last = td_last;
2635
2636 /* update isoc_next */
2637 xfer->endpoint->isoc_next = (pp_last - &sc->sc_isoc_fs_p_last[0]) &
2638 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2639
2640 /*
2641 * We don't allow cancelling of the SPLIT transaction USB FULL
2642 * speed transfer, because it disturbs the bandwidth
2643 * computation algorithm.
2644 */
2645 xfer->flags_int.can_cancel_immed = 0;
2646 }
2647
2648 static void
2649 ehci_device_isoc_fs_start(struct usb_xfer *xfer)
2650 {
2651 /*
2652 * We don't allow cancelling of the SPLIT transaction USB FULL
2653 * speed transfer, because it disturbs the bandwidth
2654 * computation algorithm.
2655 */
2656 xfer->flags_int.can_cancel_immed = 0;
2657
2658 /* set a default timeout */
2659 if (xfer->timeout == 0)
2660 xfer->timeout = 500; /* ms */
2661
2662 /* put transfer on interrupt queue */
2663 ehci_transfer_intr_enqueue(xfer);
2664 }
2665
2666 static const struct usb_pipe_methods ehci_device_isoc_fs_methods =
2667 {
2668 .open = ehci_device_isoc_fs_open,
2669 .close = ehci_device_isoc_fs_close,
2670 .enter = ehci_device_isoc_fs_enter,
2671 .start = ehci_device_isoc_fs_start,
2672 };
2673
2674 /*------------------------------------------------------------------------*
2675 * ehci high speed isochronous support
2676 *------------------------------------------------------------------------*/
2677 static void
2678 ehci_device_isoc_hs_open(struct usb_xfer *xfer)
2679 {
2680 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2681 ehci_itd_t *td;
2682 uint32_t temp;
2683 uint8_t ds;
2684
2685 usb_hs_bandwidth_alloc(xfer);
2686
2687 /* initialize all TD's */
2688
2689 for (ds = 0; ds != 2; ds++) {
2690
2691 for (td = xfer->td_start[ds]; td; td = td->obj_next) {
2692
2693 /* set TD inactive */
2694 td->itd_status[0] = 0;
2695 td->itd_status[1] = 0;
2696 td->itd_status[2] = 0;
2697 td->itd_status[3] = 0;
2698 td->itd_status[4] = 0;
2699 td->itd_status[5] = 0;
2700 td->itd_status[6] = 0;
2701 td->itd_status[7] = 0;
2702
2703 /* set endpoint and address */
2704 td->itd_bp[0] = htohc32(sc,
2705 EHCI_ITD_SET_ADDR(xfer->address) |
2706 EHCI_ITD_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)));
2707
2708 temp =
2709 EHCI_ITD_SET_MPL(xfer->max_packet_size & 0x7FF);
2710
2711 /* set direction */
2712 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) {
2713 temp |= EHCI_ITD_SET_DIR_IN;
2714 }
2715 /* set maximum packet size */
2716 td->itd_bp[1] = htohc32(sc, temp);
2717
2718 /* set transfer multiplier */
2719 td->itd_bp[2] = htohc32(sc, xfer->max_packet_count & 3);
2720
2721 usb_pc_cpu_flush(td->page_cache);
2722 }
2723 }
2724 }
2725
2726 static void
2727 ehci_device_isoc_hs_close(struct usb_xfer *xfer)
2728 {
2729 ehci_device_done(xfer, USB_ERR_CANCELLED);
2730
2731 /* bandwidth must be freed after device done */
2732 usb_hs_bandwidth_free(xfer);
2733 }
2734
2735 static void
2736 ehci_device_isoc_hs_enter(struct usb_xfer *xfer)
2737 {
2738 struct usb_page_search buf_res;
2739 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2740 ehci_itd_t *td;
2741 ehci_itd_t *td_last = NULL;
2742 ehci_itd_t **pp_last;
2743 bus_size_t page_addr;
2744 uint32_t *plen;
2745 uint32_t status;
2746 uint32_t buf_offset;
2747 uint32_t nframes;
2748 uint32_t itd_offset[8 + 1];
2749 uint8_t x;
2750 uint8_t td_no;
2751 uint8_t page_no;
2752 uint8_t shift = usbd_xfer_get_fps_shift(xfer);
2753
2754 #ifdef USB_DEBUG
2755 uint8_t once = 1;
2756
2757 #endif
2758
2759 DPRINTFN(6, "xfer=%p next=%d nframes=%d shift=%d\n",
2760 xfer, xfer->endpoint->isoc_next, xfer->nframes, (int)shift);
2761
2762 /* get the current frame index */
2763
2764 nframes = EOREAD4(sc, EHCI_FRINDEX) / 8;
2765
2766 /*
2767 * check if the frame index is within the window where the frames
2768 * will be inserted
2769 */
2770 buf_offset = (nframes - xfer->endpoint->isoc_next) &
2771 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2772
2773 if ((xfer->endpoint->is_synced == 0) ||
2774 (buf_offset < (((xfer->nframes << shift) + 7) / 8))) {
2775 /*
2776 * If there is data underflow or the pipe queue is empty we
2777 * schedule the transfer a few frames ahead of the current
2778 * frame position. Else two isochronous transfers might
2779 * overlap.
2780 */
2781 xfer->endpoint->isoc_next = (nframes + 3) &
2782 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2783 xfer->endpoint->is_synced = 1;
2784 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2785 }
2786 /*
2787 * compute how many milliseconds the insertion is ahead of the
2788 * current frame position:
2789 */
2790 buf_offset = (xfer->endpoint->isoc_next - nframes) &
2791 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2792
2793 /*
2794 * pre-compute when the isochronous transfer will be finished:
2795 */
2796 xfer->isoc_time_complete =
2797 usb_isoc_time_expand(&sc->sc_bus, nframes) + buf_offset +
2798 (((xfer->nframes << shift) + 7) / 8);
2799
2800 /* get the real number of frames */
2801
2802 nframes = xfer->nframes;
2803
2804 buf_offset = 0;
2805 td_no = 0;
2806
2807 plen = xfer->frlengths;
2808
2809 /* toggle the DMA set we are using */
2810 xfer->flags_int.curr_dma_set ^= 1;
2811
2812 /* get next DMA set */
2813 td = xfer->td_start[xfer->flags_int.curr_dma_set];
2814 xfer->td_transfer_first = td;
2815
2816 pp_last = &sc->sc_isoc_hs_p_last[xfer->endpoint->isoc_next];
2817
2818 /* store starting position */
2819
2820 xfer->qh_pos = xfer->endpoint->isoc_next;
2821
2822 while (nframes) {
2823 if (td == NULL) {
2824 panic("%s:%d: out of TD's\n",
2825 __func__, __LINE__);
2826 }
2827 if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) {
2828 pp_last = &sc->sc_isoc_hs_p_last[0];
2829 }
2830 /* range check */
2831 if (*plen > xfer->max_frame_size) {
2832 #ifdef USB_DEBUG
2833 if (once) {
2834 once = 0;
2835 kprintf("%s: frame length(%d) exceeds %d bytes "
2836 "(frame truncated)\n",
2837 __func__, *plen, xfer->max_frame_size);
2838 }
2839 #endif
2840 *plen = xfer->max_frame_size;
2841 }
2842
2843 if (xfer->endpoint->usb_smask & (1 << td_no)) {
2844 status = (EHCI_ITD_SET_LEN(*plen) |
2845 EHCI_ITD_ACTIVE |
2846 EHCI_ITD_SET_PG(0));
2847 td->itd_status[td_no] = htohc32(sc, status);
2848 itd_offset[td_no] = buf_offset;
2849 buf_offset += *plen;
2850 plen++;
2851 nframes --;
2852 } else {
2853 td->itd_status[td_no] = 0; /* not active */
2854 itd_offset[td_no] = buf_offset;
2855 }
2856
2857 td_no++;
2858
2859 if ((td_no == 8) || (nframes == 0)) {
2860
2861 /* the rest of the transfers are not active, if any */
2862 for (x = td_no; x != 8; x++) {
2863 td->itd_status[x] = 0; /* not active */
2864 }
2865
2866 /* check if there is any data to be transferred */
2867 if (itd_offset[0] != buf_offset) {
2868 page_no = 0;
2869 itd_offset[td_no] = buf_offset;
2870
2871 /* get first page offset */
2872 usbd_get_page(xfer->frbuffers, itd_offset[0], &buf_res);
2873 /* get page address */
2874 page_addr = buf_res.physaddr & ~0xFFF;
2875 /* update page address */
2876 td->itd_bp[0] &= htohc32(sc, 0xFFF);
2877 td->itd_bp[0] |= htohc32(sc, page_addr);
2878
2879 for (x = 0; x != td_no; x++) {
2880 /* set page number and page offset */
2881 status = (EHCI_ITD_SET_PG(page_no) |
2882 (buf_res.physaddr & 0xFFF));
2883 td->itd_status[x] |= htohc32(sc, status);
2884
2885 /* get next page offset */
2886 if (itd_offset[x + 1] == buf_offset) {
2887 /*
2888 * We subtract one so that
2889 * we don't go off the last
2890 * page!
2891 */
2892 usbd_get_page(xfer->frbuffers, buf_offset - 1, &buf_res);
2893 } else {
2894 usbd_get_page(xfer->frbuffers, itd_offset[x + 1], &buf_res);
2895 }
2896
2897 /* check if we need a new page */
2898 if ((buf_res.physaddr ^ page_addr) & ~0xFFF) {
2899 /* new page needed */
2900 page_addr = buf_res.physaddr & ~0xFFF;
2901 if (page_no == 6) {
2902 panic("%s: too many pages\n", __func__);
2903 }
2904 page_no++;
2905 /* update page address */
2906 td->itd_bp[page_no] &= htohc32(sc, 0xFFF);
2907 td->itd_bp[page_no] |= htohc32(sc, page_addr);
2908 }
2909 }
2910 }
2911 /* set IOC bit if we are complete */
2912 if (nframes == 0) {
2913 td->itd_status[td_no - 1] |= htohc32(sc, EHCI_ITD_IOC);
2914 }
2915 usb_pc_cpu_flush(td->page_cache);
2916 #ifdef USB_DEBUG
2917 if (ehcidebug > 15) {
2918 DPRINTF("HS-TD %d\n", nframes);
2919 ehci_dump_itd(sc, td);
2920 }
2921 #endif
2922 /* insert TD into schedule */
2923 EHCI_APPEND_HS_TD(td, *pp_last);
2924 pp_last++;
2925
2926 td_no = 0;
2927 td_last = td;
2928 td = td->obj_next;
2929 }
2930 }
2931
2932 xfer->td_transfer_last = td_last;
2933
2934 /* update isoc_next */
2935 xfer->endpoint->isoc_next = (pp_last - &sc->sc_isoc_hs_p_last[0]) &
2936 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2937 }
2938
2939 static void
2940 ehci_device_isoc_hs_start(struct usb_xfer *xfer)
2941 {
2942 /* put transfer on interrupt queue */
2943 ehci_transfer_intr_enqueue(xfer);
2944 }
2945
2946 static const struct usb_pipe_methods ehci_device_isoc_hs_methods =
2947 {
2948 .open = ehci_device_isoc_hs_open,
2949 .close = ehci_device_isoc_hs_close,
2950 .enter = ehci_device_isoc_hs_enter,
2951 .start = ehci_device_isoc_hs_start,
2952 };
2953
2954 /*------------------------------------------------------------------------*
2955 * ehci root control support
2956 *------------------------------------------------------------------------*
2957 * Simulate a hardware hub by handling all the necessary requests.
2958 *------------------------------------------------------------------------*/
2959
2960 static const
2961 struct usb_device_descriptor ehci_devd =
2962 {
2963 sizeof(struct usb_device_descriptor),
2964 UDESC_DEVICE, /* type */
2965 {0x00, 0x02}, /* USB version */
2966 UDCLASS_HUB, /* class */
2967 UDSUBCLASS_HUB, /* subclass */
2968 UDPROTO_HSHUBSTT, /* protocol */
2969 64, /* max packet */
2970 {0}, {0}, {0x00, 0x01}, /* device id */
2971 1, 2, 0, /* string indicies */
2972 1 /* # of configurations */
2973 };
2974
2975 static const
2976 struct usb_device_qualifier ehci_odevd =
2977 {
2978 sizeof(struct usb_device_qualifier),
2979 UDESC_DEVICE_QUALIFIER, /* type */
2980 {0x00, 0x02}, /* USB version */
2981 UDCLASS_HUB, /* class */
2982 UDSUBCLASS_HUB, /* subclass */
2983 UDPROTO_FSHUB, /* protocol */
2984 0, /* max packet */
2985 0, /* # of configurations */
2986 0
2987 };
2988
2989 static const struct ehci_config_desc ehci_confd = {
2990 .confd = {
2991 .bLength = sizeof(struct usb_config_descriptor),
2992 .bDescriptorType = UDESC_CONFIG,
2993 .wTotalLength[0] = sizeof(ehci_confd),
2994 .bNumInterface = 1,
2995 .bConfigurationValue = 1,
2996 .iConfiguration = 0,
2997 .bmAttributes = UC_SELF_POWERED,
2998 .bMaxPower = 0 /* max power */
2999 },
3000 .ifcd = {
3001 .bLength = sizeof(struct usb_interface_descriptor),
3002 .bDescriptorType = UDESC_INTERFACE,
3003 .bNumEndpoints = 1,
3004 .bInterfaceClass = UICLASS_HUB,
3005 .bInterfaceSubClass = UISUBCLASS_HUB,
3006 .bInterfaceProtocol = 0,
3007 },
3008 .endpd = {
3009 .bLength = sizeof(struct usb_endpoint_descriptor),
3010 .bDescriptorType = UDESC_ENDPOINT,
3011 .bEndpointAddress = UE_DIR_IN | EHCI_INTR_ENDPT,
3012 .bmAttributes = UE_INTERRUPT,
3013 .wMaxPacketSize[0] = 8, /* max packet (63 ports) */
3014 .bInterval = 255,
3015 },
3016 };
3017
3018 static const
3019 struct usb_hub_descriptor ehci_hubd =
3020 {
3021 .bDescLength = 0, /* dynamic length */
3022 .bDescriptorType = UDESC_HUB,
3023 };
3024
3025 static void
3026 ehci_disown(ehci_softc_t *sc, uint16_t index, uint8_t lowspeed)
3027 {
3028 uint32_t port;
3029 uint32_t v;
3030
3031 DPRINTF("index=%d lowspeed=%d\n", index, lowspeed);
3032
3033 port = EHCI_PORTSC(index);
3034 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR;
3035 EOWRITE4(sc, port, v | EHCI_PS_PO);
3036 }
3037
3038 static usb_error_t
3039 ehci_roothub_exec(struct usb_device *udev,
3040 struct usb_device_request *req, const void **pptr, uint16_t *plength)
3041 {
3042 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus);
3043 const char *str_ptr;
3044 const void *ptr;
3045 uint32_t port;
3046 uint32_t v;
3047 uint16_t len;
3048 uint16_t i;
3049 uint16_t value;
3050 uint16_t index;
3051 usb_error_t err;
3052
3053 USB_BUS_LOCK_ASSERT(&sc->sc_bus);
3054
3055 /* buffer reset */
3056 ptr = (const void *)&sc->sc_hub_desc;
3057 len = 0;
3058 err = 0;
3059
3060 value = UGETW(req->wValue);
3061 index = UGETW(req->wIndex);
3062
3063 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x "
3064 "wValue=0x%04x wIndex=0x%04x\n",
3065 req->bmRequestType, req->bRequest,
3066 UGETW(req->wLength), value, index);
3067
3068 #define C(x,y) ((x) | ((y) << 8))
3069 switch (C(req->bRequest, req->bmRequestType)) {
3070 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
3071 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
3072 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
3073 /*
3074 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
3075 * for the integrated root hub.
3076 */
3077 break;
3078 case C(UR_GET_CONFIG, UT_READ_DEVICE):
3079 len = 1;
3080 sc->sc_hub_desc.temp[0] = sc->sc_conf;
3081 break;
3082 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
3083 switch (value >> 8) {
3084 case UDESC_DEVICE:
3085 if ((value & 0xff) != 0) {
3086 err = USB_ERR_IOERROR;
3087 goto done;
3088 }
3089 len = sizeof(ehci_devd);
3090 ptr = (const void *)&ehci_devd;
3091 break;
3092 /*
3093 * We can't really operate at another speed,
3094 * but the specification says we need this
3095 * descriptor:
3096 */
3097 case UDESC_DEVICE_QUALIFIER:
3098 if ((value & 0xff) != 0) {
3099 err = USB_ERR_IOERROR;
3100 goto done;
3101 }
3102 len = sizeof(ehci_odevd);
3103 ptr = (const void *)&ehci_odevd;
3104 break;
3105
3106 case UDESC_CONFIG:
3107 if ((value & 0xff) != 0) {
3108 err = USB_ERR_IOERROR;
3109 goto done;
3110 }
3111 len = sizeof(ehci_confd);
3112 ptr = (const void *)&ehci_confd;
3113 break;
3114
3115 case UDESC_STRING:
3116 switch (value & 0xff) {
3117 case 0: /* Language table */
3118 str_ptr = "\001";
3119 break;
3120
3121 case 1: /* Vendor */
3122 str_ptr = sc->sc_vendor;
3123 break;
3124
3125 case 2: /* Product */
3126 str_ptr = "EHCI root HUB";
3127 break;
3128
3129 default:
3130 str_ptr = "";
3131 break;
3132 }
3133
3134 len = usb_make_str_desc(
3135 sc->sc_hub_desc.temp,
3136 sizeof(sc->sc_hub_desc.temp),
3137 str_ptr);
3138 break;
3139 default:
3140 err = USB_ERR_IOERROR;
3141 goto done;
3142 }
3143 break;
3144 case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
3145 len = 1;
3146 sc->sc_hub_desc.temp[0] = 0;
3147 break;
3148 case C(UR_GET_STATUS, UT_READ_DEVICE):
3149 len = 2;
3150 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED);
3151 break;
3152 case C(UR_GET_STATUS, UT_READ_INTERFACE):
3153 case C(UR_GET_STATUS, UT_READ_ENDPOINT):
3154 len = 2;
3155 USETW(sc->sc_hub_desc.stat.wStatus, 0);
3156 break;
3157 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
3158 if (value >= EHCI_MAX_DEVICES) {
3159 err = USB_ERR_IOERROR;
3160 goto done;
3161 }
3162 sc->sc_addr = value;
3163 break;
3164 case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
3165 if ((value != 0) && (value != 1)) {
3166 err = USB_ERR_IOERROR;
3167 goto done;
3168 }
3169 sc->sc_conf = value;
3170 break;
3171 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
3172 break;
3173 case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
3174 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
3175 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
3176 err = USB_ERR_IOERROR;
3177 goto done;
3178 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
3179 break;
3180 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
3181 break;
3182 /* Hub requests */
3183 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
3184 break;
3185 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
3186 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n");
3187
3188 if ((index < 1) ||
3189 (index > sc->sc_noport)) {
3190 err = USB_ERR_IOERROR;
3191 goto done;
3192 }
3193 port = EHCI_PORTSC(index);
3194 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR;
3195 switch (value) {
3196 case UHF_PORT_ENABLE:
3197 EOWRITE4(sc, port, v & ~EHCI_PS_PE);
3198 break;
3199 case UHF_PORT_SUSPEND:
3200 if ((v & EHCI_PS_SUSP) && (!(v & EHCI_PS_FPR))) {
3201
3202 /*
3203 * waking up a High Speed device is rather
3204 * complicated if
3205 */
3206 EOWRITE4(sc, port, v | EHCI_PS_FPR);
3207 }
3208 /* wait 20ms for resume sequence to complete */
3209 usb_pause_mtx(&sc->sc_bus.bus_lock, hz / 50);
3210
3211 EOWRITE4(sc, port, v & ~(EHCI_PS_SUSP |
3212 EHCI_PS_FPR | (3 << 10) /* High Speed */ ));
3213
3214 /* 4ms settle time */
3215 usb_pause_mtx(&sc->sc_bus.bus_lock, hz / 250);
3216 break;
3217 case UHF_PORT_POWER:
3218 EOWRITE4(sc, port, v & ~EHCI_PS_PP);
3219 break;
3220 case UHF_PORT_TEST:
3221 DPRINTFN(3, "clear port test "
3222 "%d\n", index);
3223 break;
3224 case UHF_PORT_INDICATOR:
3225 DPRINTFN(3, "clear port ind "
3226 "%d\n", index);
3227 EOWRITE4(sc, port, v & ~EHCI_PS_PIC);
3228 break;
3229 case UHF_C_PORT_CONNECTION:
3230 EOWRITE4(sc, port, v | EHCI_PS_CSC);
3231 break;
3232 case UHF_C_PORT_ENABLE:
3233 EOWRITE4(sc, port, v | EHCI_PS_PEC);
3234 break;
3235 case UHF_C_PORT_SUSPEND:
3236 EOWRITE4(sc, port, v | EHCI_PS_SUSP);
3237 break;
3238 case UHF_C_PORT_OVER_CURRENT:
3239 EOWRITE4(sc, port, v | EHCI_PS_OCC);
3240 break;
3241 case UHF_C_PORT_RESET:
3242 sc->sc_isreset = 0;
3243 break;
3244 default:
3245 err = USB_ERR_IOERROR;
3246 goto done;
3247 }
3248 break;
3249 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
3250 if ((value & 0xff) != 0) {
3251 err = USB_ERR_IOERROR;
3252 goto done;
3253 }
3254 v = EREAD4(sc, EHCI_HCSPARAMS);
3255
3256 sc->sc_hub_desc.hubd = ehci_hubd;
3257 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport;
3258
3259 if (EHCI_HCS_PPC(v))
3260 i = UHD_PWR_INDIVIDUAL;
3261 else
3262 i = UHD_PWR_NO_SWITCH;
3263
3264 if (EHCI_HCS_P_INDICATOR(v))
3265 i |= UHD_PORT_IND;
3266
3267 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i);
3268 /* XXX can't find out? */
3269 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 200;
3270 /* XXX don't know if ports are removable or not */
3271 sc->sc_hub_desc.hubd.bDescLength =
3272 8 + ((sc->sc_noport + 7) / 8);
3273 len = sc->sc_hub_desc.hubd.bDescLength;
3274 break;
3275 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
3276 len = 16;
3277 memset(sc->sc_hub_desc.temp, 0, 16);
3278 break;
3279 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
3280 DPRINTFN(9, "get port status i=%d\n",
3281 index);
3282 if ((index < 1) ||
3283 (index > sc->sc_noport)) {
3284 err = USB_ERR_IOERROR;
3285 goto done;
3286 }
3287 v = EOREAD4(sc, EHCI_PORTSC(index));
3288 DPRINTFN(9, "port status=0x%04x\n", v);
3289 if (sc->sc_flags & (EHCI_SCFLG_FORCESPEED | EHCI_SCFLG_TT)) {
3290 if ((v & 0xc000000) == 0x8000000)
3291 i = UPS_HIGH_SPEED;
3292 else if ((v & 0xc000000) == 0x4000000)
3293 i = UPS_LOW_SPEED;
3294 else
3295 i = 0;
3296 } else {
3297 i = UPS_HIGH_SPEED;
3298 }
3299 if (v & EHCI_PS_CS)
3300 i |= UPS_CURRENT_CONNECT_STATUS;
3301 if (v & EHCI_PS_PE)
3302 i |= UPS_PORT_ENABLED;
3303 if ((v & EHCI_PS_SUSP) && !(v & EHCI_PS_FPR))
3304 i |= UPS_SUSPEND;
3305 if (v & EHCI_PS_OCA)
3306 i |= UPS_OVERCURRENT_INDICATOR;
3307 if (v & EHCI_PS_PR)
3308 i |= UPS_RESET;
3309 if (v & EHCI_PS_PP)
3310 i |= UPS_PORT_POWER;
3311 USETW(sc->sc_hub_desc.ps.wPortStatus, i);
3312 i = 0;
3313 if (v & EHCI_PS_CSC)
3314 i |= UPS_C_CONNECT_STATUS;
3315 if (v & EHCI_PS_PEC)
3316 i |= UPS_C_PORT_ENABLED;
3317 if (v & EHCI_PS_OCC)
3318 i |= UPS_C_OVERCURRENT_INDICATOR;
3319 if (v & EHCI_PS_FPR)
3320 i |= UPS_C_SUSPEND;
3321 if (sc->sc_isreset)
3322 i |= UPS_C_PORT_RESET;
3323 USETW(sc->sc_hub_desc.ps.wPortChange, i);
3324 len = sizeof(sc->sc_hub_desc.ps);
3325 break;
3326 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
3327 err = USB_ERR_IOERROR;
3328 goto done;
3329 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
3330 break;
3331 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
3332 if ((index < 1) ||
3333 (index > sc->sc_noport)) {
3334 err = USB_ERR_IOERROR;
3335 goto done;
3336 }
3337 port = EHCI_PORTSC(index);
3338 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR;
3339 switch (value) {
3340 case UHF_PORT_ENABLE:
3341 EOWRITE4(sc, port, v | EHCI_PS_PE);
3342 break;
3343 case UHF_PORT_SUSPEND:
3344 EOWRITE4(sc, port, v | EHCI_PS_SUSP);
3345 break;
3346 case UHF_PORT_RESET:
3347 DPRINTFN(6, "reset port %d\n", index);
3348 #ifdef USB_DEBUG
3349 if (ehcinohighspeed) {
3350 /*
3351 * Connect USB device to companion
3352 * controller.
3353 */
3354 ehci_disown(sc, index, 1);
3355 break;
3356 }
3357 #endif
3358 if (EHCI_PS_IS_LOWSPEED(v) &&
3359 (sc->sc_flags & EHCI_SCFLG_TT) == 0) {
3360 /* Low speed device, give up ownership. */
3361 ehci_disown(sc, index, 1);
3362 break;
3363 }
3364 /* Start reset sequence. */
3365 v &= ~(EHCI_PS_PE | EHCI_PS_PR);
3366 EOWRITE4(sc, port, v | EHCI_PS_PR);
3367
3368 /* Wait for reset to complete. */
3369 usb_pause_mtx(&sc->sc_bus.bus_lock,
3370 USB_MS_TO_TICKS(usb_port_root_reset_delay));
3371
3372 /* Terminate reset sequence. */
3373 if (!(sc->sc_flags & EHCI_SCFLG_NORESTERM))
3374 EOWRITE4(sc, port, v);
3375
3376 /* Wait for HC to complete reset. */
3377 usb_pause_mtx(&sc->sc_bus.bus_lock,
3378 USB_MS_TO_TICKS(EHCI_PORT_RESET_COMPLETE));
3379
3380 v = EOREAD4(sc, port);
3381 DPRINTF("ehci after reset, status=0x%08x\n", v);
3382 if (v & EHCI_PS_PR) {
3383 device_printf(sc->sc_bus.bdev,
3384 "port reset timeout\n");
3385 err = USB_ERR_TIMEOUT;
3386 goto done;
3387 }
3388 if (!(v & EHCI_PS_PE) &&
3389 (sc->sc_flags & EHCI_SCFLG_TT) == 0) {
3390 /* Not a high speed device, give up ownership.*/
3391 ehci_disown(sc, index, 0);
3392 break;
3393 }
3394 sc->sc_isreset = 1;
3395 DPRINTF("ehci port %d reset, status = 0x%08x\n",
3396 index, v);
3397 break;
3398
3399 case UHF_PORT_POWER:
3400 DPRINTFN(3, "set port power %d\n", index);
3401 EOWRITE4(sc, port, v | EHCI_PS_PP);
3402 break;
3403
3404 case UHF_PORT_TEST:
3405 DPRINTFN(3, "set port test %d\n", index);
3406 break;
3407
3408 case UHF_PORT_INDICATOR:
3409 DPRINTFN(3, "set port ind %d\n", index);
3410 EOWRITE4(sc, port, v | EHCI_PS_PIC);
3411 break;
3412
3413 default:
3414 err = USB_ERR_IOERROR;
3415 goto done;
3416 }
3417 break;
3418 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER):
3419 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER):
3420 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER):
3421 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER):
3422 break;
3423 default:
3424 err = USB_ERR_IOERROR;
3425 goto done;
3426 }
3427 done:
3428 *plength = len;
3429 *pptr = ptr;
3430 return (err);
3431 }
3432
3433 static void
3434 ehci_xfer_setup(struct usb_setup_params *parm)
3435 {
3436 struct usb_page_search page_info;
3437 struct usb_page_cache *pc;
3438 ehci_softc_t *sc;
3439 struct usb_xfer *xfer;
3440 void *last_obj;
3441 uint32_t nqtd;
3442 uint32_t nqh;
3443 uint32_t nsitd;
3444 uint32_t nitd;
3445 uint32_t n;
3446
3447 sc = EHCI_BUS2SC(parm->udev->bus);
3448 xfer = parm->curr_xfer;
3449
3450 nqtd = 0;
3451 nqh = 0;
3452 nsitd = 0;
3453 nitd = 0;
3454
3455 /*
3456 * compute maximum number of some structures
3457 */
3458 if (parm->methods == &ehci_device_ctrl_methods) {
3459
3460 /*
3461 * The proof for the "nqtd" formula is illustrated like
3462 * this:
3463 *
3464 * +------------------------------------+
3465 * | |
3466 * | |remainder -> |
3467 * | +-----+---+ |
3468 * | | xxx | x | frm 0 |
3469 * | +-----+---++ |
3470 * | | xxx | xx | frm 1 |
3471 * | +-----+----+ |
3472 * | ... |
3473 * +------------------------------------+
3474 *
3475 * "xxx" means a completely full USB transfer descriptor
3476 *
3477 * "x" and "xx" means a short USB packet
3478 *
3479 * For the remainder of an USB transfer modulo
3480 * "max_data_length" we need two USB transfer descriptors.
3481 * One to transfer the remaining data and one to finalise
3482 * with a zero length packet in case the "force_short_xfer"
3483 * flag is set. We only need two USB transfer descriptors in
3484 * the case where the transfer length of the first one is a
3485 * factor of "max_frame_size". The rest of the needed USB
3486 * transfer descriptors is given by the buffer size divided
3487 * by the maximum data payload.
3488 */
3489 parm->hc_max_packet_size = 0x400;
3490 parm->hc_max_packet_count = 1;
3491 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX;
3492 xfer->flags_int.bdma_enable = 1;
3493
3494 usbd_transfer_setup_sub(parm);
3495
3496 nqh = 1;
3497 nqtd = ((2 * xfer->nframes) + 1 /* STATUS */
3498 + (xfer->max_data_length / xfer->max_hc_frame_size));
3499
3500 } else if (parm->methods == &ehci_device_bulk_methods) {
3501
3502 parm->hc_max_packet_size = 0x400;
3503 parm->hc_max_packet_count = 1;
3504 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX;
3505 xfer->flags_int.bdma_enable = 1;
3506
3507 usbd_transfer_setup_sub(parm);
3508
3509 nqh = 1;
3510 nqtd = ((2 * xfer->nframes)
3511 + (xfer->max_data_length / xfer->max_hc_frame_size));
3512
3513 } else if (parm->methods == &ehci_device_intr_methods) {
3514
3515 if (parm->speed == USB_SPEED_HIGH) {
3516 parm->hc_max_packet_size = 0x400;
3517 parm->hc_max_packet_count = 3;
3518 } else if (parm->speed == USB_SPEED_FULL) {
3519 parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME;
3520 parm->hc_max_packet_count = 1;
3521 } else {
3522 parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME / 8;
3523 parm->hc_max_packet_count = 1;
3524 }
3525
3526 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX;
3527 xfer->flags_int.bdma_enable = 1;
3528
3529 usbd_transfer_setup_sub(parm);
3530
3531 nqh = 1;
3532 nqtd = ((2 * xfer->nframes)
3533 + (xfer->max_data_length / xfer->max_hc_frame_size));
3534
3535 } else if (parm->methods == &ehci_device_isoc_fs_methods) {
3536
3537 parm->hc_max_packet_size = 0x3FF;
3538 parm->hc_max_packet_count = 1;
3539 parm->hc_max_frame_size = 0x3FF;
3540 xfer->flags_int.bdma_enable = 1;
3541
3542 usbd_transfer_setup_sub(parm);
3543
3544 nsitd = xfer->nframes;
3545
3546 } else if (parm->methods == &ehci_device_isoc_hs_methods) {
3547
3548 parm->hc_max_packet_size = 0x400;
3549 parm->hc_max_packet_count = 3;
3550 parm->hc_max_frame_size = 0xC00;
3551 xfer->flags_int.bdma_enable = 1;
3552
3553 usbd_transfer_setup_sub(parm);
3554
3555 nitd = ((xfer->nframes + 7) / 8) <<
3556 usbd_xfer_get_fps_shift(xfer);
3557
3558 } else {
3559
3560 parm->hc_max_packet_size = 0x400;
3561 parm->hc_max_packet_count = 1;
3562 parm->hc_max_frame_size = 0x400;
3563
3564 usbd_transfer_setup_sub(parm);
3565 }
3566
3567 alloc_dma_set:
3568
3569 if (parm->err) {
3570 return;
3571 }
3572 /*
3573 * Allocate queue heads and transfer descriptors
3574 */
3575 last_obj = NULL;
3576
3577 if (usbd_transfer_setup_sub_malloc(
3578 parm, &pc, sizeof(ehci_itd_t),
3579 EHCI_ITD_ALIGN, nitd)) {
3580 parm->err = USB_ERR_NOMEM;
3581 return;
3582 }
3583 if (parm->buf) {
3584 for (n = 0; n != nitd; n++) {
3585 ehci_itd_t *td;
3586
3587 usbd_get_page(pc + n, 0, &page_info);
3588
3589 td = page_info.buffer;
3590
3591 /* init TD */
3592 td->itd_self = htohc32(sc, page_info.physaddr | EHCI_LINK_ITD);
3593 td->obj_next = last_obj;
3594 td->page_cache = pc + n;
3595
3596 last_obj = td;
3597
3598 usb_pc_cpu_flush(pc + n);
3599 }
3600 }
3601 if (usbd_transfer_setup_sub_malloc(
3602 parm, &pc, sizeof(ehci_sitd_t),
3603 EHCI_SITD_ALIGN, nsitd)) {
3604 parm->err = USB_ERR_NOMEM;
3605 return;
3606 }
3607 if (parm->buf) {
3608 for (n = 0; n != nsitd; n++) {
3609 ehci_sitd_t *td;
3610
3611 usbd_get_page(pc + n, 0, &page_info);
3612
3613 td = page_info.buffer;
3614
3615 /* init TD */
3616 td->sitd_self = htohc32(sc, page_info.physaddr | EHCI_LINK_SITD);
3617 td->obj_next = last_obj;
3618 td->page_cache = pc + n;
3619
3620 last_obj = td;
3621
3622 usb_pc_cpu_flush(pc + n);
3623 }
3624 }
3625 if (usbd_transfer_setup_sub_malloc(
3626 parm, &pc, sizeof(ehci_qtd_t),
3627 EHCI_QTD_ALIGN, nqtd)) {
3628 parm->err = USB_ERR_NOMEM;
3629 return;
3630 }
3631 if (parm->buf) {
3632 for (n = 0; n != nqtd; n++) {
3633 ehci_qtd_t *qtd;
3634
3635 usbd_get_page(pc + n, 0, &page_info);
3636
3637 qtd = page_info.buffer;
3638
3639 /* init TD */
3640 qtd->qtd_self = htohc32(sc, page_info.physaddr);
3641 qtd->obj_next = last_obj;
3642 qtd->page_cache = pc + n;
3643
3644 last_obj = qtd;
3645
3646 usb_pc_cpu_flush(pc + n);
3647 }
3648 }
3649 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj;
3650
3651 last_obj = NULL;
3652
3653 if (usbd_transfer_setup_sub_malloc(
3654 parm, &pc, sizeof(ehci_qh_t),
3655 EHCI_QH_ALIGN, nqh)) {
3656 parm->err = USB_ERR_NOMEM;
3657 return;
3658 }
3659 if (parm->buf) {
3660 for (n = 0; n != nqh; n++) {
3661 ehci_qh_t *qh;
3662
3663 usbd_get_page(pc + n, 0, &page_info);
3664
3665 qh = page_info.buffer;
3666
3667 /* init QH */
3668 qh->qh_self = htohc32(sc, page_info.physaddr | EHCI_LINK_QH);
3669 qh->obj_next = last_obj;
3670 qh->page_cache = pc + n;
3671
3672 last_obj = qh;
3673
3674 usb_pc_cpu_flush(pc + n);
3675 }
3676 }
3677 xfer->qh_start[xfer->flags_int.curr_dma_set] = last_obj;
3678
3679 if (!xfer->flags_int.curr_dma_set) {
3680 xfer->flags_int.curr_dma_set = 1;
3681 goto alloc_dma_set;
3682 }
3683 }
3684
3685 static void
3686 ehci_xfer_unsetup(struct usb_xfer *xfer)
3687 {
3688 return;
3689 }
3690
3691 static void
3692 ehci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
3693 struct usb_endpoint *ep)
3694 {
3695 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus);
3696
3697 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n",
3698 ep, udev->address,
3699 edesc->bEndpointAddress, udev->flags.usb_mode,
3700 sc->sc_addr);
3701
3702 if (udev->device_index != sc->sc_addr) {
3703
3704 if ((udev->speed != USB_SPEED_HIGH) &&
3705 ((udev->hs_hub_addr == 0) ||
3706 (udev->hs_port_no == 0) ||
3707 (udev->parent_hs_hub == NULL) ||
3708 (udev->parent_hs_hub->hub == NULL))) {
3709 /* We need a transaction translator */
3710 goto done;
3711 }
3712 switch (edesc->bmAttributes & UE_XFERTYPE) {
3713 case UE_CONTROL:
3714 ep->methods = &ehci_device_ctrl_methods;
3715 break;
3716 case UE_INTERRUPT:
3717 ep->methods = &ehci_device_intr_methods;
3718 break;
3719 case UE_ISOCHRONOUS:
3720 if (udev->speed == USB_SPEED_HIGH) {
3721 ep->methods = &ehci_device_isoc_hs_methods;
3722 } else if (udev->speed == USB_SPEED_FULL) {
3723 ep->methods = &ehci_device_isoc_fs_methods;
3724 }
3725 break;
3726 case UE_BULK:
3727 ep->methods = &ehci_device_bulk_methods;
3728 break;
3729 default:
3730 /* do nothing */
3731 break;
3732 }
3733 }
3734 done:
3735 return;
3736 }
3737
3738 static void
3739 ehci_get_dma_delay(struct usb_device *udev, uint32_t *pus)
3740 {
3741 /*
3742 * Wait until the hardware has finished any possible use of
3743 * the transfer descriptor(s) and QH
3744 */
3745 *pus = (188); /* microseconds */
3746 }
3747
3748 static void
3749 ehci_device_resume(struct usb_device *udev)
3750 {
3751 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus);
3752 struct usb_xfer *xfer;
3753 const struct usb_pipe_methods *methods;
3754
3755 DPRINTF("\n");
3756
3757 USB_BUS_LOCK(udev->bus);
3758
3759 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3760
3761 if (xfer->xroot->udev == udev) {
3762
3763 methods = xfer->endpoint->methods;
3764
3765 if ((methods == &ehci_device_bulk_methods) ||
3766 (methods == &ehci_device_ctrl_methods)) {
3767 EHCI_APPEND_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
3768 sc->sc_async_p_last);
3769 }
3770 if (methods == &ehci_device_intr_methods) {
3771 EHCI_APPEND_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
3772 sc->sc_intr_p_last[xfer->qh_pos]);
3773 }
3774 }
3775 }
3776
3777 USB_BUS_UNLOCK(udev->bus);
3778
3779 return;
3780 }
3781
3782 static void
3783 ehci_device_suspend(struct usb_device *udev)
3784 {
3785 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus);
3786 struct usb_xfer *xfer;
3787 const struct usb_pipe_methods *methods;
3788
3789 DPRINTF("\n");
3790
3791 USB_BUS_LOCK(udev->bus);
3792
3793 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3794
3795 if (xfer->xroot->udev == udev) {
3796
3797 methods = xfer->endpoint->methods;
3798
3799 if ((methods == &ehci_device_bulk_methods) ||
3800 (methods == &ehci_device_ctrl_methods)) {
3801 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
3802 sc->sc_async_p_last);
3803 }
3804 if (methods == &ehci_device_intr_methods) {
3805 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
3806 sc->sc_intr_p_last[xfer->qh_pos]);
3807 }
3808 }
3809 }
3810
3811 USB_BUS_UNLOCK(udev->bus);
3812 }
3813
3814 static void
3815 ehci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
3816 {
3817 struct ehci_softc *sc = EHCI_BUS2SC(bus);
3818
3819 switch (state) {
3820 case USB_HW_POWER_SUSPEND:
3821 case USB_HW_POWER_SHUTDOWN:
3822 ehci_suspend(sc);
3823 break;
3824 case USB_HW_POWER_RESUME:
3825 ehci_resume(sc);
3826 break;
3827 default:
3828 break;
3829 }
3830 }
3831
3832 static void
3833 ehci_set_hw_power(struct usb_bus *bus)
3834 {
3835 ehci_softc_t *sc = EHCI_BUS2SC(bus);
3836 uint32_t temp;
3837 uint32_t flags;
3838
3839 DPRINTF("\n");
3840
3841 USB_BUS_LOCK(bus);
3842
3843 flags = bus->hw_power_state;
3844
3845 temp = EOREAD4(sc, EHCI_USBCMD);
3846
3847 temp &= ~(EHCI_CMD_ASE | EHCI_CMD_PSE);
3848
3849 if (flags & (USB_HW_POWER_CONTROL |
3850 USB_HW_POWER_BULK)) {
3851 DPRINTF("Async is active\n");
3852 temp |= EHCI_CMD_ASE;
3853 }
3854 if (flags & (USB_HW_POWER_INTERRUPT |
3855 USB_HW_POWER_ISOC)) {
3856 DPRINTF("Periodic is active\n");
3857 temp |= EHCI_CMD_PSE;
3858 }
3859 EOWRITE4(sc, EHCI_USBCMD, temp);
3860
3861 USB_BUS_UNLOCK(bus);
3862
3863 return;
3864 }
3865
3866 static const struct usb_bus_methods ehci_bus_methods =
3867 {
3868 .endpoint_init = ehci_ep_init,
3869 .xfer_setup = ehci_xfer_setup,
3870 .xfer_unsetup = ehci_xfer_unsetup,
3871 .get_dma_delay = ehci_get_dma_delay,
3872 .device_resume = ehci_device_resume,
3873 .device_suspend = ehci_device_suspend,
3874 .set_hw_power = ehci_set_hw_power,
3875 .set_hw_power_sleep = ehci_set_hw_power_sleep,
3876 .roothub_exec = ehci_roothub_exec,
3877 .xfer_poll = ehci_do_poll,
3878 };
DragonFly BSD