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kernel/nata: Pass interrupt function to ata_setup_interrupt().
[dragonfly.git] / sys / dev / disk / nata / ata-all.h
blob4235742a3b4c15aeb9e7e57e139600167ecad36d
1 /*-
2 * Copyright (c) 1998 - 2006 Søren Schmidt <sos@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * $FreeBSD: src/sys/dev/ata/ata-all.h,v 1.123 2007/04/08 19:18:51 sos Exp $
27 */
28
29 #include <sys/param.h>
30 #include <sys/bio.h>
31 #include <sys/bus.h>
32 #include <sys/callout.h>
33 #include <sys/kernel.h>
34 #include <sys/malloc.h>
35 #include <sys/nata.h>
36 #include <sys/objcache.h>
37 #include <sys/queue.h>
38 #include <sys/rman.h>
39 #include <sys/systm.h>
40 #include <sys/taskqueue.h>
41
42 #include <machine/bus_dma.h>
43
44 /* ATA register defines */
45 #define ATA_DATA 0 /* (RW) data */
46
47 #define ATA_FEATURE 1 /* (W) feature */
48 #define ATA_F_DMA 0x01 /* enable DMA */
49 #define ATA_F_OVL 0x02 /* enable overlap */
50
51 #define ATA_COUNT 2 /* (W) sector count */
52
53 #define ATA_SECTOR 3 /* (RW) sector # */
54 #define ATA_CYL_LSB 4 /* (RW) cylinder# LSB */
55 #define ATA_CYL_MSB 5 /* (RW) cylinder# MSB */
56 #define ATA_DRIVE 6 /* (W) Sector/Drive/Head */
57 #define ATA_D_LBA 0x40 /* use LBA addressing */
58 #define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */
59
60 #define ATA_COMMAND 7 /* (W) command */
61
62 #define ATA_ERROR 8 /* (R) error */
63 #define ATA_E_ILI 0x01 /* illegal length */
64 #define ATA_E_NM 0x02 /* no media */
65 #define ATA_E_ABORT 0x04 /* command aborted */
66 #define ATA_E_MCR 0x08 /* media change request */
67 #define ATA_E_IDNF 0x10 /* ID not found */
68 #define ATA_E_MC 0x20 /* media changed */
69 #define ATA_E_UNC 0x40 /* uncorrectable data */
70 #define ATA_E_ICRC 0x80 /* UDMA crc error */
71 #define ATA_E_ATAPI_SENSE_MASK 0xf0 /* ATAPI sense key mask */
72
73 #define ATA_IREASON 9 /* (R) interrupt reason */
74 #define ATA_I_CMD 0x01 /* cmd (1) | data (0) */
75 #define ATA_I_IN 0x02 /* read (1) | write (0) */
76 #define ATA_I_RELEASE 0x04 /* released bus (1) */
77 #define ATA_I_TAGMASK 0xf8 /* tag mask */
78
79 #define ATA_STATUS 10 /* (R) status */
80 #define ATA_ALTSTAT 11 /* (R) alternate status */
81 #define ATA_S_ERROR 0x01 /* error */
82 #define ATA_S_INDEX 0x02 /* index */
83 #define ATA_S_CORR 0x04 /* data corrected */
84 #define ATA_S_DRQ 0x08 /* data request */
85 #define ATA_S_DSC 0x10 /* drive seek completed */
86 #define ATA_S_SERVICE 0x10 /* drive needs service */
87 #define ATA_S_DWF 0x20 /* drive write fault */
88 #define ATA_S_DMA 0x20 /* DMA ready */
89 #define ATA_S_READY 0x40 /* drive ready */
90 #define ATA_S_BUSY 0x80 /* busy */
91
92 #define ATA_CONTROL 12 /* (W) control */
93
94 #define ATA_CTLOFFSET 0x206 /* control register offset */
95 #define ATA_PCCARD_CTLOFFSET 0x0e /* do for PCCARD devices */
96 #define ATA_A_IDS 0x02 /* disable interrupts */
97 #define ATA_A_RESET 0x04 /* RESET controller */
98 #define ATA_A_4BIT 0x08 /* 4 head bits */
99 #define ATA_A_HOB 0x80 /* High Order Byte enable */
100
101 /* SATA register defines */
102 #define ATA_SSTATUS 13
103 #define ATA_SS_DET_MASK 0x0000000f
104 #define ATA_SS_DET_NO_DEVICE 0x00000000
105 #define ATA_SS_DET_DEV_PRESENT 0x00000001
106 #define ATA_SS_DET_PHY_ONLINE 0x00000003
107 #define ATA_SS_DET_PHY_OFFLINE 0x00000004
108
109 #define ATA_SS_SPD_MASK 0x000000f0
110 #define ATA_SS_SPD_NO_SPEED 0x00000000
111 #define ATA_SS_SPD_GEN1 0x00000010
112 #define ATA_SS_SPD_GEN2 0x00000020
113
114 #define ATA_SS_IPM_MASK 0x00000f00
115 #define ATA_SS_IPM_NO_DEVICE 0x00000000
116 #define ATA_SS_IPM_ACTIVE 0x00000100
117 #define ATA_SS_IPM_PARTIAL 0x00000200
118 #define ATA_SS_IPM_SLUMBER 0x00000600
119
120 #define ATA_SS_CONWELL_MASK \
121 (ATA_SS_DET_MASK|ATA_SS_SPD_MASK|ATA_SS_IPM_MASK)
122 #define ATA_SS_CONWELL_GEN1 \
123 (ATA_SS_DET_PHY_ONLINE|ATA_SS_SPD_GEN1|ATA_SS_IPM_ACTIVE)
124 #define ATA_SS_CONWELL_GEN2 \
125 (ATA_SS_DET_PHY_ONLINE|ATA_SS_SPD_GEN2|ATA_SS_IPM_ACTIVE)
126
127 #define ATA_SERROR 14
128 #define ATA_SE_DATA_CORRECTED 0x00000001
129 #define ATA_SE_COMM_CORRECTED 0x00000002
130 #define ATA_SE_DATA_ERR 0x00000100
131 #define ATA_SE_COMM_ERR 0x00000200
132 #define ATA_SE_PROT_ERR 0x00000400
133 #define ATA_SE_HOST_ERR 0x00000800
134 #define ATA_SE_PHY_CHANGED 0x00010000
135 #define ATA_SE_PHY_IERROR 0x00020000
136 #define ATA_SE_COMM_WAKE 0x00040000
137 #define ATA_SE_DECODE_ERR 0x00080000
138 #define ATA_SE_PARITY_ERR 0x00100000
139 #define ATA_SE_CRC_ERR 0x00200000
140 #define ATA_SE_HANDSHAKE_ERR 0x00400000
141 #define ATA_SE_LINKSEQ_ERR 0x00800000
142 #define ATA_SE_TRANSPORT_ERR 0x01000000
143 #define ATA_SE_UNKNOWN_FIS 0x02000000
144
145 #define ATA_SCONTROL 15
146 #define ATA_SC_DET_MASK 0x0000000f
147 #define ATA_SC_DET_IDLE 0x00000000
148 #define ATA_SC_DET_RESET 0x00000001
149 #define ATA_SC_DET_DISABLE 0x00000004
150
151 #define ATA_SC_SPD_MASK 0x000000f0
152 #define ATA_SC_SPD_NO_SPEED 0x00000000
153 #define ATA_SC_SPD_SPEED_GEN1 0x00000010
154 #define ATA_SC_SPD_SPEED_GEN2 0x00000020
155
156 #define ATA_SC_IPM_MASK 0x00000f00
157 #define ATA_SC_IPM_NONE 0x00000000
158 #define ATA_SC_IPM_DIS_PARTIAL 0x00000100
159 #define ATA_SC_IPM_DIS_SLUMBER 0x00000200
160
161 #define ATA_SACTIVE 16
162
163 /* SATA AHCI v1.0 register defines */
164 #define ATA_AHCI_CAP 0x00
165 #define ATA_AHCI_NPMASK 0x1f
166 #define ATA_AHCI_CAP_CLO 0x01000000
167 #define ATA_AHCI_CAP_64BIT 0x80000000
168
169 #define ATA_AHCI_GHC 0x04
170 #define ATA_AHCI_GHC_AE 0x80000000
171 #define ATA_AHCI_GHC_IE 0x00000002
172 #define ATA_AHCI_GHC_HR 0x00000001
173
174 #define ATA_AHCI_IS 0x08
175 #define ATA_AHCI_PI 0x0c
176 #define ATA_AHCI_VS 0x10
177
178 #define ATA_AHCI_OFFSET 0x80
179
180 #define ATA_AHCI_P_CLB 0x100
181 #define ATA_AHCI_P_CLBU 0x104
182 #define ATA_AHCI_P_FB 0x108
183 #define ATA_AHCI_P_FBU 0x10c
184 #define ATA_AHCI_P_IS 0x110
185 #define ATA_AHCI_P_IE 0x114
186 #define ATA_AHCI_P_IX_DHR 0x00000001
187 #define ATA_AHCI_P_IX_PS 0x00000002
188 #define ATA_AHCI_P_IX_DS 0x00000004
189 #define ATA_AHCI_P_IX_SDB 0x00000008
190 #define ATA_AHCI_P_IX_UF 0x00000010
191 #define ATA_AHCI_P_IX_DP 0x00000020
192 #define ATA_AHCI_P_IX_PC 0x00000040
193 #define ATA_AHCI_P_IX_DI 0x00000080
194
195 #define ATA_AHCI_P_IX_PRC 0x00400000
196 #define ATA_AHCI_P_IX_IPM 0x00800000
197 #define ATA_AHCI_P_IX_OF 0x01000000
198 #define ATA_AHCI_P_IX_INF 0x04000000
199 #define ATA_AHCI_P_IX_IF 0x08000000
200 #define ATA_AHCI_P_IX_HBD 0x10000000
201 #define ATA_AHCI_P_IX_HBF 0x20000000
202 #define ATA_AHCI_P_IX_TFE 0x40000000
203 #define ATA_AHCI_P_IX_CPD 0x80000000
204
205 #define ATA_AHCI_P_CMD 0x118
206 #define ATA_AHCI_P_CMD_ST 0x00000001
207 #define ATA_AHCI_P_CMD_SUD 0x00000002
208 #define ATA_AHCI_P_CMD_POD 0x00000004
209 #define ATA_AHCI_P_CMD_CLO 0x00000008
210 #define ATA_AHCI_P_CMD_FRE 0x00000010
211 #define ATA_AHCI_P_CMD_CCS_MASK 0x00001f00
212 #define ATA_AHCI_P_CMD_ISS 0x00002000
213 #define ATA_AHCI_P_CMD_FR 0x00004000
214 #define ATA_AHCI_P_CMD_CR 0x00008000
215 #define ATA_AHCI_P_CMD_CPS 0x00010000
216 #define ATA_AHCI_P_CMD_PMA 0x00020000
217 #define ATA_AHCI_P_CMD_HPCP 0x00040000
218 #define ATA_AHCI_P_CMD_ISP 0x00080000
219 #define ATA_AHCI_P_CMD_CPD 0x00100000
220 #define ATA_AHCI_P_CMD_ATAPI 0x01000000
221 #define ATA_AHCI_P_CMD_DLAE 0x02000000
222 #define ATA_AHCI_P_CMD_ALPE 0x04000000
223 #define ATA_AHCI_P_CMD_ASP 0x08000000
224 #define ATA_AHCI_P_CMD_ICC_MASK 0xf0000000
225 #define ATA_AHCI_P_CMD_NOOP 0x00000000
226 #define ATA_AHCI_P_CMD_ACTIVE 0x10000000
227 #define ATA_AHCI_P_CMD_PARTIAL 0x20000000
228 #define ATA_AHCI_P_CMD_SLUMPER 0x60000000
229
230 #define ATA_AHCI_P_TFD 0x120
231 #define ATA_AHCI_P_SIG 0x124
232 #define ATA_AHCI_P_SSTS 0x128
233 #define ATA_AHCI_P_SCTL 0x12c
234 #define ATA_AHCI_P_SERR 0x130
235 #define ATA_AHCI_P_SACT 0x134
236 #define ATA_AHCI_P_CI 0x138
237
238 #define ATA_AHCI_CL_SIZE 32
239 #define ATA_AHCI_CL_OFFSET 0
240 #define ATA_AHCI_FB_OFFSET 1024
241 #define ATA_AHCI_CT_OFFSET 1024+256
242 #define ATA_AHCI_CT_SG_OFFSET 128
243 #define ATA_AHCI_CT_SIZE 256
244
245 struct ata_ahci_dma_prd {
246 u_int64_t dba;
247 u_int32_t reserved;
248 u_int32_t dbc; /* 0 based */
249 #define ATA_AHCI_PRD_MASK 0x003fffff /* max 4MB */
250 #define ATA_AHCI_PRD_IPC (1<<31)
251 } __packed;
252
253 struct ata_ahci_cmd_tab {
254 u_int8_t cfis[64];
255 u_int8_t acmd[32];
256 u_int8_t reserved[32];
257 struct ata_ahci_dma_prd prd_tab[16];
258 } __packed;
259
260 struct ata_ahci_cmd_list {
261 u_int16_t cmd_flags;
262 u_int16_t prd_length; /* PRD entries */
263 u_int32_t bytecount;
264 u_int64_t cmd_table_phys; /* 128byte aligned */
265 } __packed;
266
267 /* DMA register defines */
268 #define ATA_DMA_ENTRIES 256
269 #define ATA_DMA_EOT 0x80000000
270
271 #define ATA_BMCMD_PORT 17
272 #define ATA_BMCMD_START_STOP 0x01
273 #define ATA_BMCMD_WRITE_READ 0x08
274
275 #define ATA_BMDEVSPEC_0 18
276 #define ATA_BMSTAT_PORT 19
277 #define ATA_BMSTAT_ACTIVE 0x01
278 #define ATA_BMSTAT_ERROR 0x02
279 #define ATA_BMSTAT_INTERRUPT 0x04
280 #define ATA_BMSTAT_MASK 0x07
281 #define ATA_BMSTAT_DMA_MASTER 0x20
282 #define ATA_BMSTAT_DMA_SLAVE 0x40
283 #define ATA_BMSTAT_DMA_SIMPLEX 0x80
284
285 #define ATA_BMDEVSPEC_1 20
286 #define ATA_BMDTP_PORT 21
287
288 #define ATA_IDX_ADDR 22
289 #define ATA_IDX_DATA 23
290 #define ATA_MAX_RES 24
291
292 /* misc defines */
293 #define ATA_PRIMARY 0x1f0
294 #define ATA_SECONDARY 0x170
295 #define ATA_IOSIZE 0x08
296 #define ATA_CTLIOSIZE 0x01
297 #define ATA_BMIOSIZE 0x08
298 #define ATA_IOADDR_RID 0
299 #define ATA_CTLADDR_RID 1
300 #define ATA_BMADDR_RID 0x20
301 #define ATA_IRQ_RID 0
302 #define ATA_DEV(device) ((device == ATA_MASTER) ? 0 : 1)
303 #define ATA_CFA_MAGIC1 0x844A
304 #define ATA_CFA_MAGIC2 0x848A
305 #define ATA_CFA_MAGIC3 0x8400
306 #define ATAPI_MAGIC_LSB 0x14
307 #define ATAPI_MAGIC_MSB 0xeb
308 #define ATAPI_P_READ (ATA_S_DRQ | ATA_I_IN)
309 #define ATAPI_P_WRITE (ATA_S_DRQ)
310 #define ATAPI_P_CMDOUT (ATA_S_DRQ | ATA_I_CMD)
311 #define ATAPI_P_DONEDRQ (ATA_S_DRQ | ATA_I_CMD | ATA_I_IN)
312 #define ATAPI_P_DONE (ATA_I_CMD | ATA_I_IN)
313 #define ATAPI_P_ABORT 0
314 #define ATA_INTR_FLAGS (INTR_NOPOLL)
315 #define ATA_OP_CONTINUES 0
316 #define ATA_OP_FINISHED 1
317 #define ATA_MAX_28BIT_LBA 268435455UL
318
319 /* structure used for composite atomic operations */
320 #define MAX_COMPOSITES 32 /* u_int32_t bits */
321 struct ata_composite {
322 struct lock lock; /* control lock */
323 u_int32_t rd_needed; /* needed read subdisks */
324 u_int32_t rd_done; /* done read subdisks */
325 u_int32_t wr_needed; /* needed write subdisks */
326 u_int32_t wr_depend; /* write depends on subdisks */
327 u_int32_t wr_done; /* done write subdisks */
328 struct ata_request *request[MAX_COMPOSITES];
329 u_int32_t residual; /* bytes still to transfer */
330 caddr_t data_1;
331 caddr_t data_2;
332 };
333
334 /* structure used to queue an ATA/ATAPI request */
335 struct ata_request {
336 device_t dev; /* device handle */
337 device_t parent; /* channel handle */
338 union {
339 struct {
340 u_int8_t command; /* command reg */
341 u_int16_t feature; /* feature reg */
342 u_int16_t count; /* count reg */
343 u_int64_t lba; /* lba reg */
344 } ata;
345 struct {
346 u_int8_t ccb[16]; /* ATAPI command block */
347 struct atapi_sense sense; /* ATAPI request sense data */
348 u_int8_t saved_cmd; /* ATAPI saved command */
349 } atapi;
350 } u;
351 u_int32_t bytecount; /* bytes to transfer */
352 u_int32_t transfersize; /* bytes pr transfer */
353 caddr_t data; /* pointer to data buf */
354 int flags;
355 #define ATA_R_CONTROL 0x00000001
356 #define ATA_R_READ 0x00000002
357 #define ATA_R_WRITE 0x00000004
358 #define ATA_R_ATAPI 0x00000008
359 #define ATA_R_DMA 0x00000010
360 #define ATA_R_QUIET 0x00000020
361 #define ATA_R_TIMEOUT 0x00000040
362 #define ATA_R_COMPLETED 0x00000080
363
364 #define ATA_R_ORDERED 0x00000100
365 #define ATA_R_AT_HEAD 0x00000200
366 #define ATA_R_REQUEUE 0x00000400
367 #define ATA_R_THREAD 0x00000800
368 #define ATA_R_DIRECT 0x00001000
369
370 #define ATA_R_HWCMDQUEUED 0x00010000
371
372 #define ATA_R_DEBUG 0x10000000
373 #define ATA_R_DANGER1 0x20000000
374 #define ATA_R_DANGER2 0x40000000
375
376 u_int8_t status; /* ATA status */
377 u_int8_t error; /* ATA error */
378 u_int8_t dmastat; /* DMA status */
379 u_int32_t donecount; /* bytes transferred */
380 int result; /* result error code */
381 void (*callback)(struct ata_request *request);
382 struct lock done; /* request done sema */
383 int retries; /* retry count */
384 int timeout; /* timeout for this cmd */
385 int unused01;
386 struct callout callout; /* callout management */
387 struct task task; /* task management */
388 struct bio *bio; /* bio for this request */
389 int this; /* this request ID */
390 struct ata_composite *composite; /* for composite atomic ops */
391 void *driver; /* driver specific */
392 TAILQ_ENTRY(ata_request) chain; /* list management */
393 };
394
395 /* define this for debugging request processing */
396 #if 0
397 #define ATA_DEBUG_RQ(request, string) \
398 { \
399 if (request->flags & ATA_R_DEBUG) \
400 device_printf(request->dev, "req=%p %s " string "\n", \
401 request, ata_cmd2str(request)); \
402 }
403 #else
404 #define ATA_DEBUG_RQ(request, string)
405 #endif
406
407
408 /* structure describing an ATA/ATAPI device */
409 struct ata_device {
410 device_t dev; /* device handle */
411 int unit; /* physical unit */
412 #define ATA_MASTER 0x00
413 #define ATA_SLAVE 0x10
414
415 struct ata_params param; /* ata param structure */
416 int mode; /* current transfermode */
417 u_int32_t max_iosize; /* max IO size */
418 int flags;
419 #define ATA_D_USE_CHS 0x0001
420 #define ATA_D_MEDIA_CHANGED 0x0002
421 #define ATA_D_ENC_PRESENT 0x0004
422 #define ATA_D_48BIT_ACTIVE 0x0008
423 int opencount; /* when tracking needed */
424 };
425
426 /* structure for holding DMA Physical Region Descriptors (PRD) entries */
427 struct ata_dma_prdentry {
428 u_int32_t addr;
429 u_int32_t count;
430 };
431
432 /* structure used by the setprd function */
433 struct ata_dmasetprd_args {
434 void *dmatab;
435 int nsegs;
436 int error;
437 };
438
439 /* structure holding DMA related information */
440 struct ata_dma {
441 bus_dma_tag_t dmatag; /* parent DMA tag */
442 bus_dma_tag_t sg_tag; /* SG list DMA tag */
443 bus_dmamap_t sg_map; /* SG list DMA map */
444 void *sg; /* DMA transfer table */
445 bus_addr_t sg_bus; /* bus address of dmatab */
446 bus_dma_tag_t data_tag; /* data DMA tag */
447 bus_dmamap_t data_map; /* data DMA map */
448 bus_dma_tag_t work_tag; /* workspace DMA tag */
449 bus_dmamap_t work_map; /* workspace DMA map */
450 u_int8_t *work; /* workspace */
451 bus_addr_t work_bus; /* bus address of dmatab */
452
453 u_int32_t alignment; /* DMA SG list alignment */
454 u_int32_t boundary; /* DMA SG list boundary */
455 u_int32_t segsize; /* DMA SG list segment size */
456 u_int32_t max_iosize; /* DMA data max IO size */
457 u_int32_t cur_iosize; /* DMA data current IO size */
458 u_int64_t max_address; /* highest DMA'able address */
459 int flags;
460 #define ATA_DMA_READ 0x01 /* transaction is a read */
461 #define ATA_DMA_LOADED 0x02 /* DMA tables etc loaded */
462 #define ATA_DMA_ACTIVE 0x04 /* DMA transfer in progress */
463
464 void (*alloc)(device_t dev);
465 void (*free)(device_t dev);
466 void (*setprd)(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
467 int (*load)(device_t dev, caddr_t data, int32_t count, int dir, void *addr, int *nsegs);
468 int (*unload)(device_t dev);
469 int (*start)(device_t dev);
470 int (*stop)(device_t dev);
471 void (*reset)(device_t dev);
472 };
473
474 /* structure holding lowlevel functions */
475 struct ata_lowlevel {
476 int (*status)(device_t dev);
477 int (*begin_transaction)(struct ata_request *request);
478 int (*end_transaction)(struct ata_request *request);
479 int (*command)(struct ata_request *request);
480 };
481
482 /* structure holding resources for an ATA channel */
483 struct ata_resource {
484 struct resource *res;
485 int offset;
486 };
487
488 /* structure describing an ATA channel */
489 struct ata_channel {
490 device_t dev; /* device handle */
491 int unit; /* physical channel */
492 struct ata_resource r_io[ATA_MAX_RES];/* I/O resources */
493 struct resource *r_irq; /* interrupt of this channel */
494 void *ih; /* interrupt handle */
495 struct ata_lowlevel hw; /* lowlevel HW functions */
496 struct ata_dma *dma; /* DMA data / functions */
497 int flags; /* channel flags */
498 #define ATA_NO_SLAVE 0x01
499 #define ATA_USE_16BIT 0x02
500 #define ATA_ATAPI_DMA_RO 0x04
501 #define ATA_NO_48BIT_DMA 0x08
502 #define ATA_ALWAYS_DMASTAT 0x10
503
504 int devices; /* what is present */
505 #define ATA_ATA_MASTER 0x01
506 #define ATA_ATA_SLAVE 0x02
507 #define ATA_ATAPI_MASTER 0x04
508 #define ATA_ATAPI_SLAVE 0x08
509 #define ATA_PORTMULTIPLIER 0x10
510
511 struct lock state_mtx; /* state lock */
512 int state; /* ATA channel state */
513 #define ATA_IDLE 0x0000
514 #define ATA_ACTIVE 0x0001
515 #define ATA_STALL_QUEUE 0x0002
516
517 struct lock queue_mtx; /* queue lock */
518 TAILQ_HEAD(, ata_request) ata_queue; /* head of ATA queue */
519 int reorder; /* limit sort reordering */
520 struct ata_request *transition;
521 struct ata_request *running; /* currently running request */
522 };
523
524 /* disk bay/enclosure related */
525 #define ATA_LED_OFF 0x00
526 #define ATA_LED_RED 0x01
527 #define ATA_LED_GREEN 0x02
528 #define ATA_LED_ORANGE 0x03
529 #define ATA_LED_MASK 0x03
530
531 /* externs */
532 extern int (*ata_raid_ioctl_func)(u_long cmd, caddr_t data);
533 extern devclass_t ata_devclass;
534 extern int ata_wc;
535
536 /* public prototypes */
537 /* ata-all.c: */
538 int ata_probe(device_t dev);
539 int ata_attach(device_t dev);
540 int ata_detach(device_t dev);
541 int ata_reinit(device_t dev);
542 int ata_suspend(device_t dev);
543 int ata_resume(device_t dev);
544 int ata_interrupt(void *data);
545 int ata_device_ioctl(device_t dev, u_long cmd, caddr_t data);
546 int ata_identify(device_t dev);
547 void ata_default_registers(device_t dev);
548 void ata_modify_if_48bit(struct ata_request *request);
549 void ata_udelay(int interval);
550 const char *ata_mode2str(int mode);
551 void ata_print_cable(device_t dev, u_int8_t *who);
552 int ata_atapi(device_t dev);
553 int ata_pmode(struct ata_params *ap);
554 int ata_wmode(struct ata_params *ap);
555 int ata_umode(struct ata_params *ap);
556 int ata_limit_mode(device_t dev, int mode, int maxmode);
557
558 /* ata-queue.c: */
559 int ata_controlcmd(device_t dev, u_int8_t command, u_int16_t feature, u_int64_t lba, u_int16_t count);
560 int ata_atapicmd(device_t dev, u_int8_t *ccb, caddr_t data, int count, int flags, int timeout);
561 void ata_drop_requests(device_t dev);
562 void ata_queue_init(struct ata_channel *ch);
563 void ata_queue_request(struct ata_request *request);
564 void ata_start(device_t dev);
565 void ata_finish(struct ata_request *request);
566 void ata_timeout(struct ata_request *);
567 void ata_catch_inflight(device_t dev);
568 void ata_fail_requests(device_t dev);
569 const char *ata_cmd2str(struct ata_request *request);
570
571 /* ata-lowlevel.c: */
572 void ata_generic_hw(device_t dev);
573 int ata_begin_transaction(struct ata_request *);
574 int ata_end_transaction(struct ata_request *);
575 void ata_generic_reset(device_t dev);
576 int ata_generic_command(struct ata_request *request);
577
578 /* ata-dma.c: */
579 void ata_dmainit(device_t);
580
581 /* ata-sata.c: */
582 void ata_sata_phy_check_events(device_t dev);
583 void ata_sata_phy_event(void *context, int dummy);
584 int ata_sata_phy_reset(device_t dev);
585 void ata_sata_setmode(device_t dev, int mode);
586 int ata_request2fis_h2d(struct ata_request *request, u_int8_t *fis);
587
588 /* macros for alloc/free of struct ata_request */
589 extern struct objcache *ata_request_cache;
590 #define ata_alloc_request() objcache_get(ata_request_cache, M_WAITOK)
591 /* zero the object so objects in the cache are guaranteed to be zero'ed */
592 #define ata_free_request(request) { \
593 if (!(request->flags & ATA_R_DANGER2)) { \
594 bzero(request, sizeof(struct ata_request)); \
595 objcache_put(ata_request_cache, request); \
596 } \
597 }
598 /* macros for alloc/free of struct ata_composite */
599 extern struct objcache *ata_composite_cache;
600 #define ata_alloc_composite() objcache_get(ata_composite_cache, M_WAITOK)
601 /* zero the object so objects in the cache are guaranteed to be zero'ed */
602 #define ata_free_composite(composite) { \
603 bzero(composite, sizeof(struct ata_composite)); \
604 objcache_put(ata_composite_cache, composite); \
605 }
606
607 MALLOC_DECLARE(M_ATA);
608
609 /* misc newbus defines */
610 #define GRANDPARENT(dev) device_get_parent(device_get_parent(dev))
611
612 /* macros to hide busspace uglyness */
613 #define ATA_INB(res, offset) \
614 bus_space_read_1(rman_get_bustag((res)), \
615 rman_get_bushandle((res)), (offset))
616
617 #define ATA_INW(res, offset) \
618 bus_space_read_2(rman_get_bustag((res)), \
619 rman_get_bushandle((res)), (offset))
620 #define ATA_INL(res, offset) \
621 bus_space_read_4(rman_get_bustag((res)), \
622 rman_get_bushandle((res)), (offset))
623 #define ATA_INSW(res, offset, addr, count) \
624 bus_space_read_multi_2(rman_get_bustag((res)), \
625 rman_get_bushandle((res)), \
626 (offset), (addr), (count))
627 #define ATA_INSW_STRM(res, offset, addr, count) \
628 bus_space_read_multi_stream_2(rman_get_bustag((res)), \
629 rman_get_bushandle((res)), \
630 (offset), (addr), (count))
631 #define ATA_INSL(res, offset, addr, count) \
632 bus_space_read_multi_4(rman_get_bustag((res)), \
633 rman_get_bushandle((res)), \
634 (offset), (addr), (count))
635 #define ATA_INSL_STRM(res, offset, addr, count) \
636 bus_space_read_multi_stream_4(rman_get_bustag((res)), \
637 rman_get_bushandle((res)), \
638 (offset), (addr), (count))
639 #define ATA_OUTB(res, offset, value) \
640 bus_space_write_1(rman_get_bustag((res)), \
641 rman_get_bushandle((res)), (offset), (value))
642 #define ATA_OUTW(res, offset, value) \
643 bus_space_write_2(rman_get_bustag((res)), \
644 rman_get_bushandle((res)), (offset), (value))
645 #define ATA_OUTL(res, offset, value) \
646 bus_space_write_4(rman_get_bustag((res)), \
647 rman_get_bushandle((res)), (offset), (value))
648 #define ATA_OUTSW(res, offset, addr, count) \
649 bus_space_write_multi_2(rman_get_bustag((res)), \
650 rman_get_bushandle((res)), \
651 (offset), (addr), (count))
652 #define ATA_OUTSW_STRM(res, offset, addr, count) \
653 bus_space_write_multi_stream_2(rman_get_bustag((res)), \
654 rman_get_bushandle((res)), \
655 (offset), (addr), (count))
656 #define ATA_OUTSL(res, offset, addr, count) \
657 bus_space_write_multi_4(rman_get_bustag((res)), \
658 rman_get_bushandle((res)), \
659 (offset), (addr), (count))
660 #define ATA_OUTSL_STRM(res, offset, addr, count) \
661 bus_space_write_multi_stream_4(rman_get_bustag((res)), \
662 rman_get_bushandle((res)), \
663 (offset), (addr), (count))
664
665 #define ATA_IDX_INB(ch, idx) \
666 ATA_INB(ch->r_io[idx].res, ch->r_io[idx].offset)
667
668 #define ATA_IDX_INW(ch, idx) \
669 ATA_INW(ch->r_io[idx].res, ch->r_io[idx].offset)
670
671 #define ATA_IDX_INL(ch, idx) \
672 ATA_INL(ch->r_io[idx].res, ch->r_io[idx].offset)
673
674 #define ATA_IDX_INSW(ch, idx, addr, count) \
675 ATA_INSW(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
676
677 #define ATA_IDX_INSW_STRM(ch, idx, addr, count) \
678 ATA_INSW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
679
680 #define ATA_IDX_INSL(ch, idx, addr, count) \
681 ATA_INSL(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
682
683 #define ATA_IDX_INSL_STRM(ch, idx, addr, count) \
684 ATA_INSL_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
685
686 #define ATA_IDX_OUTB(ch, idx, value) \
687 ATA_OUTB(ch->r_io[idx].res, ch->r_io[idx].offset, value)
688
689 #define ATA_IDX_OUTW(ch, idx, value) \
690 ATA_OUTW(ch->r_io[idx].res, ch->r_io[idx].offset, value)
691
692 #define ATA_IDX_OUTL(ch, idx, value) \
693 ATA_OUTL(ch->r_io[idx].res, ch->r_io[idx].offset, value)
694
695 #define ATA_IDX_OUTSW(ch, idx, addr, count) \
696 ATA_OUTSW(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
697
698 #define ATA_IDX_OUTSW_STRM(ch, idx, addr, count) \
699 ATA_OUTSW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
700
701 #define ATA_IDX_OUTSL(ch, idx, addr, count) \
702 ATA_OUTSL(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
703
704 #define ATA_IDX_OUTSL_STRM(ch, idx, addr, count) \
705 ATA_OUTSL_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
706
707 /* Dragonfly: Default request timeout increased from 5 to 10 */
708 #define ATA_DEFAULT_TIMEOUT 10
DragonFly BSD