contrib/binutils-2.27/opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright (C) 2007-2016 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with GAS; see the file COPYING.  If not, write to the Free
  18    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  19    02110-1301, USA.  */
  20
  21 #include "opcode/i386.h"
  22 #ifdef HAVE_LIMITS_H
  23 #include <limits.h>
  24 #endif
  25
  26 #ifndef CHAR_BIT
  27 #define CHAR_BIT 8
  28 #endif
  29
  30 /* Position of cpu flags bitfiled.  */
  31
  32 enum
  33 {
  34   /* i186 or better required */
  35   Cpu186 = 0,
  36   /* i286 or better required */
  37   Cpu286,
  38   /* i386 or better required */
  39   Cpu386,
  40   /* i486 or better required */
  41   Cpu486,
  42   /* i585 or better required */
  43   Cpu586,
  44   /* i686 or better required */
  45   Cpu686,
  46   /* CLFLUSH Instruction support required */
  47   CpuClflush,
  48   /* NOP Instruction support required */
  49   CpuNop,
  50   /* SYSCALL Instructions support required */
  51   CpuSYSCALL,
  52   /* Floating point support required */
  53   Cpu8087,
  54   /* i287 support required */
  55   Cpu287,
  56   /* i387 support required */
  57   Cpu387,
  58   /* i686 and floating point support required */
  59   Cpu687,
  60   /* SSE3 and floating point support required */
  61   CpuFISTTP,
  62   /* MMX support required */
  63   CpuMMX,
  64   /* SSE support required */
  65   CpuSSE,
  66   /* SSE2 support required */
  67   CpuSSE2,
  68   /* 3dnow! support required */
  69   Cpu3dnow,
  70   /* 3dnow! Extensions support required */
  71   Cpu3dnowA,
  72   /* SSE3 support required */
  73   CpuSSE3,
  74   /* VIA PadLock required */
  75   CpuPadLock,
  76   /* AMD Secure Virtual Machine Ext-s required */
  77   CpuSVME,
  78   /* VMX Instructions required */
  79   CpuVMX,
  80   /* SMX Instructions required */
  81   CpuSMX,
  82   /* SSSE3 support required */
  83   CpuSSSE3,
  84   /* SSE4a support required */
  85   CpuSSE4a,
  86   /* ABM New Instructions required */
  87   CpuABM,
  88   /* SSE4.1 support required */
  89   CpuSSE4_1,
  90   /* SSE4.2 support required */
  91   CpuSSE4_2,
  92   /* AVX support required */
  93   CpuAVX,
  94   /* AVX2 support required */
  95   CpuAVX2,
  96   /* Intel AVX-512 Foundation Instructions support required */
  97   CpuAVX512F,
  98   /* Intel AVX-512 Conflict Detection Instructions support required */
  99   CpuAVX512CD,
 100   /* Intel AVX-512 Exponential and Reciprocal Instructions support
 101      required */
 102   CpuAVX512ER,
 103   /* Intel AVX-512 Prefetch Instructions support required */
 104   CpuAVX512PF,
 105   /* Intel AVX-512 VL Instructions support required.  */
 106   CpuAVX512VL,
 107   /* Intel AVX-512 DQ Instructions support required.  */
 108   CpuAVX512DQ,
 109   /* Intel AVX-512 BW Instructions support required.  */
 110   CpuAVX512BW,
 111   /* Intel L1OM support required */
 112   CpuL1OM,
 113   /* Intel K1OM support required */
 114   CpuK1OM,
 115   /* Intel IAMCU support required */
 116   CpuIAMCU,
 117   /* Xsave/xrstor New Instructions support required */
 118   CpuXsave,
 119   /* Xsaveopt New Instructions support required */
 120   CpuXsaveopt,
 121   /* AES support required */
 122   CpuAES,
 123   /* PCLMUL support required */
 124   CpuPCLMUL,
 125   /* FMA support required */
 126   CpuFMA,
 127   /* FMA4 support required */
 128   CpuFMA4,
 129   /* XOP support required */
 130   CpuXOP,
 131   /* LWP support required */
 132   CpuLWP,
 133   /* BMI support required */
 134   CpuBMI,
 135   /* TBM support required */
 136   CpuTBM,
 137   /* MOVBE Instruction support required */
 138   CpuMovbe,
 139   /* CMPXCHG16B instruction support required.  */
 140   CpuCX16,
 141   /* EPT Instructions required */
 142   CpuEPT,
 143   /* RDTSCP Instruction support required */
 144   CpuRdtscp,
 145   /* FSGSBASE Instructions required */
 146   CpuFSGSBase,
 147   /* RDRND Instructions required */
 148   CpuRdRnd,
 149   /* F16C Instructions required */
 150   CpuF16C,
 151   /* Intel BMI2 support required */
 152   CpuBMI2,
 153   /* LZCNT support required */
 154   CpuLZCNT,
 155   /* HLE support required */
 156   CpuHLE,
 157   /* RTM support required */
 158   CpuRTM,
 159   /* INVPCID Instructions required */
 160   CpuINVPCID,
 161   /* VMFUNC Instruction required */
 162   CpuVMFUNC,
 163   /* Intel MPX Instructions required  */
 164   CpuMPX,
 165   /* 64bit support available, used by -march= in assembler.  */
 166   CpuLM,
 167   /* RDRSEED instruction required.  */
 168   CpuRDSEED,
 169   /* Multi-presisionn add-carry instructions are required.  */
 170   CpuADX,
 171   /* Supports prefetchw and prefetch instructions.  */
 172   CpuPRFCHW,
 173   /* SMAP instructions required.  */
 174   CpuSMAP,
 175   /* SHA instructions required.  */
 176   CpuSHA,
 177   /* VREX support required  */
 178   CpuVREX,
 179   /* CLFLUSHOPT instruction required */
 180   CpuClflushOpt,
 181   /* XSAVES/XRSTORS instruction required */
 182   CpuXSAVES,
 183   /* XSAVEC instruction required */
 184   CpuXSAVEC,
 185   /* PREFETCHWT1 instruction required */
 186   CpuPREFETCHWT1,
 187   /* SE1 instruction required */
 188   CpuSE1,
 189   /* CLWB instruction required */
 190   CpuCLWB,
 191   /* PCOMMIT instruction required */
 192   CpuPCOMMIT,
 193   /* Intel AVX-512 IFMA Instructions support required.  */
 194   CpuAVX512IFMA,
 195   /* Intel AVX-512 VBMI Instructions support required.  */
 196   CpuAVX512VBMI,
 197   /* mwaitx instruction required */
 198   CpuMWAITX,
 199   /* Clzero instruction required */
 200   CpuCLZERO,
 201   /* OSPKE instruction required */
 202   CpuOSPKE,
 203   /* RDPID instruction required */
 204   CpuRDPID,
 205   /* MMX register support required */
 206   CpuRegMMX,
 207   /* XMM register support required */
 208   CpuRegXMM,
 209   /* YMM register support required */
 210   CpuRegYMM,
 211   /* ZMM register support required */
 212   CpuRegZMM,
 213   /* Mask register support required */
 214   CpuRegMask,
 215   /* 64bit support required  */
 216   Cpu64,
 217   /* Not supported in the 64bit mode  */
 218   CpuNo64,
 219   /* The last bitfield in i386_cpu_flags.  */
 220   CpuMax = CpuNo64
 221 };
 222
 223 #define CpuNumOfUints \
 224   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
 225 #define CpuNumOfBits \
 226   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 227
 228 /* If you get a compiler error for zero width of the unused field,
 229    comment it out.  */
 230 #define CpuUnused       (CpuMax + 1)
 231
 232 /* We can check if an instruction is available with array instead
 233    of bitfield. */
 234 typedef union i386_cpu_flags
 235 {
 236   struct
 237     {
 238       unsigned int cpui186:1;
 239       unsigned int cpui286:1;
 240       unsigned int cpui386:1;
 241       unsigned int cpui486:1;
 242       unsigned int cpui586:1;
 243       unsigned int cpui686:1;
 244       unsigned int cpuclflush:1;
 245       unsigned int cpunop:1;
 246       unsigned int cpusyscall:1;
 247       unsigned int cpu8087:1;
 248       unsigned int cpu287:1;
 249       unsigned int cpu387:1;
 250       unsigned int cpu687:1;
 251       unsigned int cpufisttp:1;
 252       unsigned int cpummx:1;
 253       unsigned int cpusse:1;
 254       unsigned int cpusse2:1;
 255       unsigned int cpua3dnow:1;
 256       unsigned int cpua3dnowa:1;
 257       unsigned int cpusse3:1;
 258       unsigned int cpupadlock:1;
 259       unsigned int cpusvme:1;
 260       unsigned int cpuvmx:1;
 261       unsigned int cpusmx:1;
 262       unsigned int cpussse3:1;
 263       unsigned int cpusse4a:1;
 264       unsigned int cpuabm:1;
 265       unsigned int cpusse4_1:1;
 266       unsigned int cpusse4_2:1;
 267       unsigned int cpuavx:1;
 268       unsigned int cpuavx2:1;
 269       unsigned int cpuavx512f:1;
 270       unsigned int cpuavx512cd:1;
 271       unsigned int cpuavx512er:1;
 272       unsigned int cpuavx512pf:1;
 273       unsigned int cpuavx512vl:1;
 274       unsigned int cpuavx512dq:1;
 275       unsigned int cpuavx512bw:1;
 276       unsigned int cpul1om:1;
 277       unsigned int cpuk1om:1;
 278       unsigned int cpuiamcu:1;
 279       unsigned int cpuxsave:1;
 280       unsigned int cpuxsaveopt:1;
 281       unsigned int cpuaes:1;
 282       unsigned int cpupclmul:1;
 283       unsigned int cpufma:1;
 284       unsigned int cpufma4:1;
 285       unsigned int cpuxop:1;
 286       unsigned int cpulwp:1;
 287       unsigned int cpubmi:1;
 288       unsigned int cputbm:1;
 289       unsigned int cpumovbe:1;
 290       unsigned int cpucx16:1;
 291       unsigned int cpuept:1;
 292       unsigned int cpurdtscp:1;
 293       unsigned int cpufsgsbase:1;
 294       unsigned int cpurdrnd:1;
 295       unsigned int cpuf16c:1;
 296       unsigned int cpubmi2:1;
 297       unsigned int cpulzcnt:1;
 298       unsigned int cpuhle:1;
 299       unsigned int cpurtm:1;
 300       unsigned int cpuinvpcid:1;
 301       unsigned int cpuvmfunc:1;
 302       unsigned int cpumpx:1;
 303       unsigned int cpulm:1;
 304       unsigned int cpurdseed:1;
 305       unsigned int cpuadx:1;
 306       unsigned int cpuprfchw:1;
 307       unsigned int cpusmap:1;
 308       unsigned int cpusha:1;
 309       unsigned int cpuvrex:1;
 310       unsigned int cpuclflushopt:1;
 311       unsigned int cpuxsaves:1;
 312       unsigned int cpuxsavec:1;
 313       unsigned int cpuprefetchwt1:1;
 314       unsigned int cpuse1:1;
 315       unsigned int cpuclwb:1;
 316       unsigned int cpupcommit:1;
 317       unsigned int cpuavx512ifma:1;
 318       unsigned int cpuavx512vbmi:1;
 319       unsigned int cpumwaitx:1;
 320       unsigned int cpuclzero:1;
 321       unsigned int cpuospke:1;
 322       unsigned int cpurdpid:1;
 323       unsigned int cpuregmmx:1;
 324       unsigned int cpuregxmm:1;
 325       unsigned int cpuregymm:1;
 326       unsigned int cpuregzmm:1;
 327       unsigned int cpuregmask:1;
 328       unsigned int cpu64:1;
 329       unsigned int cpuno64:1;
 330 #ifdef CpuUnused
 331       unsigned int unused:(CpuNumOfBits - CpuUnused);
 332 #endif
 333     } bitfield;
 334   unsigned int array[CpuNumOfUints];
 335 } i386_cpu_flags;
 336
 337 /* Position of opcode_modifier bits.  */
 338
 339 enum
 340 {
 341   /* has direction bit. */
 342   D = 0,
 343   /* set if operands can be words or dwords encoded the canonical way */
 344   W,
 345   /* Skip the current insn and use the next insn in i386-opc.tbl to swap
 346      operand in encoding.  */
 347   S,
 348   /* insn has a modrm byte. */
 349   Modrm,
 350   /* register is in low 3 bits of opcode */
 351   ShortForm,
 352   /* special case for jump insns.  */
 353   Jump,
 354   /* call and jump */
 355   JumpDword,
 356   /* loop and jecxz */
 357   JumpByte,
 358   /* special case for intersegment leaps/calls */
 359   JumpInterSegment,
 360   /* FP insn memory format bit, sized by 0x4 */
 361   FloatMF,
 362   /* src/dest swap for floats. */
 363   FloatR,
 364   /* has float insn direction bit. */
 365   FloatD,
 366   /* needs size prefix if in 32-bit mode */
 367   Size16,
 368   /* needs size prefix if in 16-bit mode */
 369   Size32,
 370   /* needs size prefix if in 64-bit mode */
 371   Size64,
 372   /* check register size.  */
 373   CheckRegSize,
 374   /* instruction ignores operand size prefix and in Intel mode ignores
 375      mnemonic size suffix check.  */
 376   IgnoreSize,
 377   /* default insn size depends on mode */
 378   DefaultSize,
 379   /* b suffix on instruction illegal */
 380   No_bSuf,
 381   /* w suffix on instruction illegal */
 382   No_wSuf,
 383   /* l suffix on instruction illegal */
 384   No_lSuf,
 385   /* s suffix on instruction illegal */
 386   No_sSuf,
 387   /* q suffix on instruction illegal */
 388   No_qSuf,
 389   /* long double suffix on instruction illegal */
 390   No_ldSuf,
 391   /* instruction needs FWAIT */
 392   FWait,
 393   /* quick test for string instructions */
 394   IsString,
 395   /* quick test if branch instruction is MPX supported */
 396   BNDPrefixOk,
 397   /* quick test for lockable instructions */
 398   IsLockable,
 399   /* fake an extra reg operand for clr, imul and special register
 400      processing for some instructions.  */
 401   RegKludge,
 402   /* The first operand must be xmm0 */
 403   FirstXmm0,
 404   /* An implicit xmm0 as the first operand */
 405   Implicit1stXmm0,
 406   /* The HLE prefix is OK:
 407      1. With a LOCK prefix.
 408      2. With or without a LOCK prefix.
 409      3. With a RELEASE (0xf3) prefix.
 410    */
 411 #define HLEPrefixNone           0
 412 #define HLEPrefixLock           1
 413 #define HLEPrefixAny            2
 414 #define HLEPrefixRelease        3
 415   HLEPrefixOk,
 416   /* An instruction on which a "rep" prefix is acceptable.  */
 417   RepPrefixOk,
 418   /* Convert to DWORD */
 419   ToDword,
 420   /* Convert to QWORD */
 421   ToQword,
 422   /* Address prefix changes operand 0 */
 423   AddrPrefixOp0,
 424   /* opcode is a prefix */
 425   IsPrefix,
 426   /* instruction has extension in 8 bit imm */
 427   ImmExt,
 428   /* instruction don't need Rex64 prefix.  */
 429   NoRex64,
 430   /* instruction require Rex64 prefix.  */
 431   Rex64,
 432   /* deprecated fp insn, gets a warning */
 433   Ugh,
 434   /* insn has VEX prefix:
 435         1: 128bit VEX prefix.
 436         2: 256bit VEX prefix.
 437         3: Scalar VEX prefix.
 438    */
 439 #define VEX128          1
 440 #define VEX256          2
 441 #define VEXScalar       3
 442   Vex,
 443   /* How to encode VEX.vvvv:
 444      0: VEX.vvvv must be 1111b.
 445      1: VEX.NDS.  Register-only source is encoded in VEX.vvvv where
 446         the content of source registers will be preserved.
 447         VEX.DDS.  The second register operand is encoded in VEX.vvvv
 448         where the content of first source register will be overwritten
 449         by the result.
 450         VEX.NDD2.  The second destination register operand is encoded in
 451         VEX.vvvv for instructions with 2 destination register operands.
 452         For assembler, there are no difference between VEX.NDS, VEX.DDS
 453         and VEX.NDD2.
 454      2. VEX.NDD.  Register destination is encoded in VEX.vvvv for
 455      instructions with 1 destination register operand.
 456      3. VEX.LWP.  Register destination is encoded in VEX.vvvv and one
 457         of the operands can access a memory location.
 458    */
 459 #define VEXXDS  1
 460 #define VEXNDD  2
 461 #define VEXLWP  3
 462   VexVVVV,
 463   /* How the VEX.W bit is used:
 464      0: Set by the REX.W bit.
 465      1: VEX.W0.  Should always be 0.
 466      2: VEX.W1.  Should always be 1.
 467    */
 468 #define VEXW0   1
 469 #define VEXW1   2
 470   VexW,
 471   /* VEX opcode prefix:
 472      0: VEX 0x0F opcode prefix.
 473      1: VEX 0x0F38 opcode prefix.
 474      2: VEX 0x0F3A opcode prefix
 475      3: XOP 0x08 opcode prefix.
 476      4: XOP 0x09 opcode prefix
 477      5: XOP 0x0A opcode prefix.
 478    */
 479 #define VEX0F           0
 480 #define VEX0F38         1
 481 #define VEX0F3A         2
 482 #define XOP08           3
 483 #define XOP09           4
 484 #define XOP0A           5
 485   VexOpcode,
 486   /* number of VEX source operands:
 487      0: <= 2 source operands.
 488      1: 2 XOP source operands.
 489      2: 3 source operands.
 490    */
 491 #define XOP2SOURCES     1
 492 #define VEX3SOURCES     2
 493   VexSources,
 494   /* instruction has VEX 8 bit imm */
 495   VexImmExt,
 496   /* Instruction with vector SIB byte:
 497         1: 128bit vector register.
 498         2: 256bit vector register.
 499         3: 512bit vector register.
 500    */
 501 #define VecSIB128       1
 502 #define VecSIB256       2
 503 #define VecSIB512       3
 504   VecSIB,
 505   /* SSE to AVX support required */
 506   SSE2AVX,
 507   /* No AVX equivalent */
 508   NoAVX,
 509
 510   /* insn has EVEX prefix:
 511         1: 512bit EVEX prefix.
 512         2: 128bit EVEX prefix.
 513         3: 256bit EVEX prefix.
 514         4: Length-ignored (LIG) EVEX prefix.
 515    */
 516 #define EVEX512                1
 517 #define EVEX128                2
 518 #define EVEX256                3
 519 #define EVEXLIG                4
 520   EVex,
 521
 522   /* AVX512 masking support:
 523         1: Zeroing-masking.
 524         2: Merging-masking.
 525         3: Both zeroing and merging masking.
 526    */
 527 #define ZEROING_MASKING 1
 528 #define MERGING_MASKING 2
 529 #define BOTH_MASKING    3
 530   Masking,
 531
 532   /* Input element size of vector insn:
 533         0: 32bit.
 534         1: 64bit.
 535    */
 536   VecESize,
 537
 538   /* Broadcast factor.
 539         0: No broadcast.
 540         1: 1to16 broadcast.
 541         2: 1to8 broadcast.
 542    */
 543 #define NO_BROADCAST    0
 544 #define BROADCAST_1TO16 1
 545 #define BROADCAST_1TO8  2
 546 #define BROADCAST_1TO4  3
 547 #define BROADCAST_1TO2  4
 548   Broadcast,
 549
 550   /* Static rounding control is supported.  */
 551   StaticRounding,
 552
 553   /* Supress All Exceptions is supported.  */
 554   SAE,
 555
 556   /* Copressed Disp8*N attribute.  */
 557   Disp8MemShift,
 558
 559   /* Default mask isn't allowed.  */
 560   NoDefMask,
 561
 562   /* Compatible with old (<= 2.8.1) versions of gcc  */
 563   OldGcc,
 564   /* AT&T mnemonic.  */
 565   ATTMnemonic,
 566   /* AT&T syntax.  */
 567   ATTSyntax,
 568   /* Intel syntax.  */
 569   IntelSyntax,
 570   /* AMD64.  */
 571   AMD64,
 572   /* Intel64.  */
 573   Intel64,
 574   /* The last bitfield in i386_opcode_modifier.  */
 575   Opcode_Modifier_Max
 576 };
 577
 578 typedef struct i386_opcode_modifier
 579 {
 580   unsigned int d:1;
 581   unsigned int w:1;
 582   unsigned int s:1;
 583   unsigned int modrm:1;
 584   unsigned int shortform:1;
 585   unsigned int jump:1;
 586   unsigned int jumpdword:1;
 587   unsigned int jumpbyte:1;
 588   unsigned int jumpintersegment:1;
 589   unsigned int floatmf:1;
 590   unsigned int floatr:1;
 591   unsigned int floatd:1;
 592   unsigned int size16:1;
 593   unsigned int size32:1;
 594   unsigned int size64:1;
 595   unsigned int checkregsize:1;
 596   unsigned int ignoresize:1;
 597   unsigned int defaultsize:1;
 598   unsigned int no_bsuf:1;
 599   unsigned int no_wsuf:1;
 600   unsigned int no_lsuf:1;
 601   unsigned int no_ssuf:1;
 602   unsigned int no_qsuf:1;
 603   unsigned int no_ldsuf:1;
 604   unsigned int fwait:1;
 605   unsigned int isstring:1;
 606   unsigned int bndprefixok:1;
 607   unsigned int islockable:1;
 608   unsigned int regkludge:1;
 609   unsigned int firstxmm0:1;
 610   unsigned int implicit1stxmm0:1;
 611   unsigned int hleprefixok:2;
 612   unsigned int repprefixok:1;
 613   unsigned int todword:1;
 614   unsigned int toqword:1;
 615   unsigned int addrprefixop0:1;
 616   unsigned int isprefix:1;
 617   unsigned int immext:1;
 618   unsigned int norex64:1;
 619   unsigned int rex64:1;
 620   unsigned int ugh:1;
 621   unsigned int vex:2;
 622   unsigned int vexvvvv:2;
 623   unsigned int vexw:2;
 624   unsigned int vexopcode:3;
 625   unsigned int vexsources:2;
 626   unsigned int veximmext:1;
 627   unsigned int vecsib:2;
 628   unsigned int sse2avx:1;
 629   unsigned int noavx:1;
 630   unsigned int evex:3;
 631   unsigned int masking:2;
 632   unsigned int vecesize:1;
 633   unsigned int broadcast:3;
 634   unsigned int staticrounding:1;
 635   unsigned int sae:1;
 636   unsigned int disp8memshift:3;
 637   unsigned int nodefmask:1;
 638   unsigned int oldgcc:1;
 639   unsigned int attmnemonic:1;
 640   unsigned int attsyntax:1;
 641   unsigned int intelsyntax:1;
 642   unsigned int amd64:1;
 643   unsigned int intel64:1;
 644 } i386_opcode_modifier;
 645
 646 /* Position of operand_type bits.  */
 647
 648 enum
 649 {
 650   /* 8bit register */
 651   Reg8 = 0,
 652   /* 16bit register */
 653   Reg16,
 654   /* 32bit register */
 655   Reg32,
 656   /* 64bit register */
 657   Reg64,
 658   /* Floating pointer stack register */
 659   FloatReg,
 660   /* MMX register */
 661   RegMMX,
 662   /* SSE register */
 663   RegXMM,
 664   /* AVX registers */
 665   RegYMM,
 666   /* AVX512 registers */
 667   RegZMM,
 668   /* Vector Mask registers */
 669   RegMask,
 670   /* Control register */
 671   Control,
 672   /* Debug register */
 673   Debug,
 674   /* Test register */
 675   Test,
 676   /* 2 bit segment register */
 677   SReg2,
 678   /* 3 bit segment register */
 679   SReg3,
 680   /* 1 bit immediate */
 681   Imm1,
 682   /* 8 bit immediate */
 683   Imm8,
 684   /* 8 bit immediate sign extended */
 685   Imm8S,
 686   /* 16 bit immediate */
 687   Imm16,
 688   /* 32 bit immediate */
 689   Imm32,
 690   /* 32 bit immediate sign extended */
 691   Imm32S,
 692   /* 64 bit immediate */
 693   Imm64,
 694   /* 8bit/16bit/32bit displacements are used in different ways,
 695      depending on the instruction.  For jumps, they specify the
 696      size of the PC relative displacement, for instructions with
 697      memory operand, they specify the size of the offset relative
 698      to the base register, and for instructions with memory offset
 699      such as `mov 1234,%al' they specify the size of the offset
 700      relative to the segment base.  */
 701   /* 8 bit displacement */
 702   Disp8,
 703   /* 16 bit displacement */
 704   Disp16,
 705   /* 32 bit displacement */
 706   Disp32,
 707   /* 32 bit signed displacement */
 708   Disp32S,
 709   /* 64 bit displacement */
 710   Disp64,
 711   /* Accumulator %al/%ax/%eax/%rax */
 712   Acc,
 713   /* Floating pointer top stack register %st(0) */
 714   FloatAcc,
 715   /* Register which can be used for base or index in memory operand.  */
 716   BaseIndex,
 717   /* Register to hold in/out port addr = dx */
 718   InOutPortReg,
 719   /* Register to hold shift count = cl */
 720   ShiftCount,
 721   /* Absolute address for jump.  */
 722   JumpAbsolute,
 723   /* String insn operand with fixed es segment */
 724   EsSeg,
 725   /* RegMem is for instructions with a modrm byte where the register
 726      destination operand should be encoded in the mod and regmem fields.
 727      Normally, it will be encoded in the reg field. We add a RegMem
 728      flag to the destination register operand to indicate that it should
 729      be encoded in the regmem field.  */
 730   RegMem,
 731   /* Memory.  */
 732   Mem,
 733   /* BYTE memory. */
 734   Byte,
 735   /* WORD memory. 2 byte */
 736   Word,
 737   /* DWORD memory. 4 byte */
 738   Dword,
 739   /* FWORD memory. 6 byte */
 740   Fword,
 741   /* QWORD memory. 8 byte */
 742   Qword,
 743   /* TBYTE memory. 10 byte */
 744   Tbyte,
 745   /* XMMWORD memory. */
 746   Xmmword,
 747   /* YMMWORD memory. */
 748   Ymmword,
 749   /* ZMMWORD memory.  */
 750   Zmmword,
 751   /* Unspecified memory size.  */
 752   Unspecified,
 753   /* Any memory size.  */
 754   Anysize,
 755
 756   /* Vector 4 bit immediate.  */
 757   Vec_Imm4,
 758
 759   /* Bound register.  */
 760   RegBND,
 761
 762   /* Vector 8bit displacement */
 763   Vec_Disp8,
 764
 765   /* The last bitfield in i386_operand_type.  */
 766   OTMax
 767 };
 768
 769 #define OTNumOfUints \
 770   (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
 771 #define OTNumOfBits \
 772   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 773
 774 /* If you get a compiler error for zero width of the unused field,
 775    comment it out.  */
 776 #define OTUnused                (OTMax + 1)
 777
 778 typedef union i386_operand_type
 779 {
 780   struct
 781     {
 782       unsigned int reg8:1;
 783       unsigned int reg16:1;
 784       unsigned int reg32:1;
 785       unsigned int reg64:1;
 786       unsigned int floatreg:1;
 787       unsigned int regmmx:1;
 788       unsigned int regxmm:1;
 789       unsigned int regymm:1;
 790       unsigned int regzmm:1;
 791       unsigned int regmask:1;
 792       unsigned int control:1;
 793       unsigned int debug:1;
 794       unsigned int test:1;
 795       unsigned int sreg2:1;
 796       unsigned int sreg3:1;
 797       unsigned int imm1:1;
 798       unsigned int imm8:1;
 799       unsigned int imm8s:1;
 800       unsigned int imm16:1;
 801       unsigned int imm32:1;
 802       unsigned int imm32s:1;
 803       unsigned int imm64:1;
 804       unsigned int disp8:1;
 805       unsigned int disp16:1;
 806       unsigned int disp32:1;
 807       unsigned int disp32s:1;
 808       unsigned int disp64:1;
 809       unsigned int acc:1;
 810       unsigned int floatacc:1;
 811       unsigned int baseindex:1;
 812       unsigned int inoutportreg:1;
 813       unsigned int shiftcount:1;
 814       unsigned int jumpabsolute:1;
 815       unsigned int esseg:1;
 816       unsigned int regmem:1;
 817       unsigned int mem:1;
 818       unsigned int byte:1;
 819       unsigned int word:1;
 820       unsigned int dword:1;
 821       unsigned int fword:1;
 822       unsigned int qword:1;
 823       unsigned int tbyte:1;
 824       unsigned int xmmword:1;
 825       unsigned int ymmword:1;
 826       unsigned int zmmword:1;
 827       unsigned int unspecified:1;
 828       unsigned int anysize:1;
 829       unsigned int vec_imm4:1;
 830       unsigned int regbnd:1;
 831       unsigned int vec_disp8:1;
 832 #ifdef OTUnused
 833       unsigned int unused:(OTNumOfBits - OTUnused);
 834 #endif
 835     } bitfield;
 836   unsigned int array[OTNumOfUints];
 837 } i386_operand_type;
 838
 839 typedef struct insn_template
 840 {
 841   /* instruction name sans width suffix ("mov" for movl insns) */
 842   char *name;
 843
 844   /* how many operands */
 845   unsigned int operands;
 846
 847   /* base_opcode is the fundamental opcode byte without optional
 848      prefix(es).  */
 849   unsigned int base_opcode;
 850 #define Opcode_D        0x2 /* Direction bit:
 851                                set if Reg --> Regmem;
 852                                unset if Regmem --> Reg. */
 853 #define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
 854 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
 855
 856   /* extension_opcode is the 3 bit extension for group <n> insns.
 857      This field is also used to store the 8-bit opcode suffix for the
 858      AMD 3DNow! instructions.
 859      If this template has no extension opcode (the usual case) use None
 860      Instructions */
 861   unsigned int extension_opcode;
 862 #define None 0xffff             /* If no extension_opcode is possible.  */
 863
 864   /* Opcode length.  */
 865   unsigned char opcode_length;
 866
 867   /* cpu feature flags */
 868   i386_cpu_flags cpu_flags;
 869
 870   /* the bits in opcode_modifier are used to generate the final opcode from
 871      the base_opcode.  These bits also are used to detect alternate forms of
 872      the same instruction */
 873   i386_opcode_modifier opcode_modifier;
 874
 875   /* operand_types[i] describes the type of operand i.  This is made
 876      by OR'ing together all of the possible type masks.  (e.g.
 877      'operand_types[i] = Reg|Imm' specifies that operand i can be
 878      either a register or an immediate operand.  */
 879   i386_operand_type operand_types[MAX_OPERANDS];
 880 }
 881 insn_template;
 882
 883 extern const insn_template i386_optab[];
 884
 885 /* these are for register name --> number & type hash lookup */
 886 typedef struct
 887 {
 888   char *reg_name;
 889   i386_operand_type reg_type;
 890   unsigned char reg_flags;
 891 #define RegRex      0x1  /* Extended register.  */
 892 #define RegRex64    0x2  /* Extended 8 bit register.  */
 893 #define RegVRex     0x4  /* Extended vector register.  */
 894   unsigned char reg_num;
 895 #define RegRip  ((unsigned char ) ~0)
 896 #define RegEip  (RegRip - 1)
 897 /* EIZ and RIZ are fake index registers.  */
 898 #define RegEiz  (RegEip - 1)
 899 #define RegRiz  (RegEiz - 1)
 900 /* FLAT is a fake segment register (Intel mode).  */
 901 #define RegFlat     ((unsigned char) ~0)
 902   signed char dw2_regnum[2];
 903 #define Dw2Inval (-1)
 904 }
 905 reg_entry;
 906
 907 /* Entries in i386_regtab.  */
 908 #define REGNAM_AL 1
 909 #define REGNAM_AX 25
 910 #define REGNAM_EAX 41
 911
 912 extern const reg_entry i386_regtab[];
 913 extern const unsigned int i386_regtab_size;
 914
 915 typedef struct
 916 {
 917   char *seg_name;
 918   unsigned int seg_prefix;
 919 }
 920 seg_entry;
 921
 922 extern const seg_entry cs;
 923 extern const seg_entry ds;
 924 extern const seg_entry ss;
 925 extern const seg_entry es;
 926 extern const seg_entry fs;
 927 extern const seg_entry gs;