sys/dev/drm/radeon_irq.c

   1 /* radeon_irq.c -- IRQ handling for radeon -*- linux-c -*- */
   2 /*-
   3  * Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   4  *
   5  * The Weather Channel (TM) funded Tungsten Graphics to develop the
   6  * initial release of the Radeon 8500 driver under the XFree86 license.
   7  * This notice must be preserved.
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining a
  10  * copy of this software and associated documentation files (the "Software"),
  11  * to deal in the Software without restriction, including without limitation
  12  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  13  * and/or sell copies of the Software, and to permit persons to whom the
  14  * Software is furnished to do so, subject to the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the next
  17  * paragraph) shall be included in all copies or substantial portions of the
  18  * Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  21  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  23  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  24  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  25  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  26  * DEALINGS IN THE SOFTWARE.
  27  *
  28  * Authors:
  29  *    Keith Whitwell <keith@tungstengraphics.com>
  30  *    Michel D�zer <michel@daenzer.net>
  31  * __FBSDID("$FreeBSD: src/sys/dev/drm/radeon_irq.c,v 1.16 2009/09/28 22:37:07 rnoland Exp $");
  32  */
  33
  34 #include "dev/drm/drmP.h"
  35 #include "dev/drm/drm.h"
  36 #include "dev/drm/radeon_drm.h"
  37 #include "dev/drm/radeon_drv.h"
  38
  39 void radeon_irq_set_state(struct drm_device *dev, u32 mask, int state)
  40 {
  41         drm_radeon_private_t *dev_priv = dev->dev_private;
  42
  43         if (state)
  44                 dev_priv->irq_enable_reg |= mask;
  45         else
  46                 dev_priv->irq_enable_reg &= ~mask;
  47
  48         if (dev->irq_enabled)
  49                 RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg);
  50 }
  51
  52 static void r500_vbl_irq_set_state(struct drm_device *dev, u32 mask, int state)
  53 {
  54         drm_radeon_private_t *dev_priv = dev->dev_private;
  55
  56         if (state)
  57                 dev_priv->r500_disp_irq_reg |= mask;
  58         else
  59                 dev_priv->r500_disp_irq_reg &= ~mask;
  60
  61         if (dev->irq_enabled)
  62                 RADEON_WRITE(R500_DxMODE_INT_MASK, dev_priv->r500_disp_irq_reg);
  63 }
  64
  65 int radeon_enable_vblank(struct drm_device *dev, int crtc)
  66 {
  67         drm_radeon_private_t *dev_priv = dev->dev_private;
  68
  69         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
  70                 switch (crtc) {
  71                 case 0:
  72                         r500_vbl_irq_set_state(dev, R500_D1MODE_INT_MASK, 1);
  73                         break;
  74                 case 1:
  75                         r500_vbl_irq_set_state(dev, R500_D2MODE_INT_MASK, 1);
  76                         break;
  77                 default:
  78                         DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
  79                                   crtc);
  80                         return EINVAL;
  81                 }
  82         } else {
  83                 switch (crtc) {
  84                 case 0:
  85                         radeon_irq_set_state(dev, RADEON_CRTC_VBLANK_MASK, 1);
  86                         break;
  87                 case 1:
  88                         radeon_irq_set_state(dev, RADEON_CRTC2_VBLANK_MASK, 1);
  89                         break;
  90                 default:
  91                         DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
  92                                   crtc);
  93                         return EINVAL;
  94                 }
  95         }
  96
  97         return 0;
  98 }
  99
 100 void radeon_disable_vblank(struct drm_device *dev, int crtc)
 101 {
 102         drm_radeon_private_t *dev_priv = dev->dev_private;
 103
 104         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
 105                 switch (crtc) {
 106                 case 0:
 107                         r500_vbl_irq_set_state(dev, R500_D1MODE_INT_MASK, 0);
 108                         break;
 109                 case 1:
 110                         r500_vbl_irq_set_state(dev, R500_D2MODE_INT_MASK, 0);
 111                         break;
 112                 default:
 113                         DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
 114                                   crtc);
 115                         break;
 116                 }
 117         } else {
 118                 switch (crtc) {
 119                 case 0:
 120                         radeon_irq_set_state(dev, RADEON_CRTC_VBLANK_MASK, 0);
 121                         break;
 122                 case 1:
 123                         radeon_irq_set_state(dev, RADEON_CRTC2_VBLANK_MASK, 0);
 124                         break;
 125                 default:
 126                         DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
 127                                   crtc);
 128                         break;
 129                 }
 130         }
 131 }
 132
 133 static __inline__ u32 radeon_acknowledge_irqs(drm_radeon_private_t * dev_priv, u32 *r500_disp_int)
 134 {
 135         u32 irqs = RADEON_READ(RADEON_GEN_INT_STATUS);
 136         u32 irq_mask = RADEON_SW_INT_TEST;
 137
 138         *r500_disp_int = 0;
 139         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
 140                 /* vbl interrupts in a different place */
 141
 142                 if (irqs & R500_DISPLAY_INT_STATUS) {
 143                         /* if a display interrupt */
 144                         u32 disp_irq;
 145
 146                         disp_irq = RADEON_READ(R500_DISP_INTERRUPT_STATUS);
 147
 148                         *r500_disp_int = disp_irq;
 149                         if (disp_irq & R500_D1_VBLANK_INTERRUPT) {
 150                                 RADEON_WRITE(R500_D1MODE_VBLANK_STATUS, R500_VBLANK_ACK);
 151                         }
 152                         if (disp_irq & R500_D2_VBLANK_INTERRUPT) {
 153                                 RADEON_WRITE(R500_D2MODE_VBLANK_STATUS, R500_VBLANK_ACK);
 154                         }
 155                 }
 156                 irq_mask |= R500_DISPLAY_INT_STATUS;
 157         } else
 158                 irq_mask |= RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT;
 159
 160         irqs &= irq_mask;
 161
 162         if (irqs)
 163                 RADEON_WRITE(RADEON_GEN_INT_STATUS, irqs);
 164
 165         return irqs;
 166 }
 167
 168 /* Interrupts - Used for device synchronization and flushing in the
 169  * following circumstances:
 170  *
 171  * - Exclusive FB access with hw idle:
 172  *    - Wait for GUI Idle (?) interrupt, then do normal flush.
 173  *
 174  * - Frame throttling, NV_fence:
 175  *    - Drop marker irq's into command stream ahead of time.
 176  *    - Wait on irq's with lock *not held*
 177  *    - Check each for termination condition
 178  *
 179  * - Internally in cp_getbuffer, etc:
 180  *    - as above, but wait with lock held???
 181  *
 182  * NOTE: These functions are misleadingly named -- the irq's aren't
 183  * tied to dma at all, this is just a hangover from dri prehistory.
 184  */
 185
 186 irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS)
 187 {
 188         struct drm_device *dev = (struct drm_device *) arg;
 189         drm_radeon_private_t *dev_priv =
 190             (drm_radeon_private_t *) dev->dev_private;
 191         u32 stat;
 192         u32 r500_disp_int;
 193         u32 tmp;
 194
 195         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
 196                 return IRQ_NONE;
 197
 198         /* Only consider the bits we're interested in - others could be used
 199          * outside the DRM
 200          */
 201         stat = radeon_acknowledge_irqs(dev_priv, &r500_disp_int);
 202         if (!stat)
 203                 return IRQ_NONE;
 204
 205         stat &= dev_priv->irq_enable_reg;
 206
 207         /* SW interrupt */
 208         if (stat & RADEON_SW_INT_TEST)
 209                 DRM_WAKEUP(&dev_priv->swi_queue);
 210
 211         /* VBLANK interrupt */
 212         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
 213                 if (r500_disp_int & R500_D1_VBLANK_INTERRUPT)
 214                         drm_handle_vblank(dev, 0);
 215                 if (r500_disp_int & R500_D2_VBLANK_INTERRUPT)
 216                         drm_handle_vblank(dev, 1);
 217         } else {
 218                 if (stat & RADEON_CRTC_VBLANK_STAT)
 219                         drm_handle_vblank(dev, 0);
 220                 if (stat & RADEON_CRTC2_VBLANK_STAT)
 221                         drm_handle_vblank(dev, 1);
 222         }
 223         if (dev->msi_enabled) {
 224                 switch(dev_priv->flags & RADEON_FAMILY_MASK) {
 225                         case CHIP_RS400:
 226                         case CHIP_RS480:
 227                                 tmp = RADEON_READ(RADEON_AIC_CNTL) &
 228                                     ~RS400_MSI_REARM;
 229                                 RADEON_WRITE(RADEON_AIC_CNTL, tmp);
 230                                 RADEON_WRITE(RADEON_AIC_CNTL,
 231                                     tmp | RS400_MSI_REARM);
 232                                 break;
 233                         case CHIP_RS600:
 234                         case CHIP_RS690:
 235                         case CHIP_RS740:
 236                                 tmp = RADEON_READ(RADEON_BUS_CNTL) &
 237                                     ~RS600_MSI_REARM;
 238                                 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
 239                                 RADEON_WRITE(RADEON_BUS_CNTL, tmp |
 240                                     RS600_MSI_REARM);
 241                                 break;
 242                          default:
 243                                 tmp = RADEON_READ(RADEON_MSI_REARM_EN) &
 244                                     ~RV370_MSI_REARM_EN;
 245                                 RADEON_WRITE(RADEON_MSI_REARM_EN, tmp);
 246                                 RADEON_WRITE(RADEON_MSI_REARM_EN,
 247                                     tmp | RV370_MSI_REARM_EN);
 248                                 break;
 249                 }
 250         }
 251         return IRQ_HANDLED;
 252 }
 253
 254 static int radeon_emit_irq(struct drm_device * dev)
 255 {
 256         drm_radeon_private_t *dev_priv = dev->dev_private;
 257         unsigned int ret;
 258         RING_LOCALS;
 259
 260         atomic_inc(&dev_priv->swi_emitted);
 261         ret = atomic_read(&dev_priv->swi_emitted);
 262
 263         BEGIN_RING(4);
 264         OUT_RING_REG(RADEON_LAST_SWI_REG, ret);
 265         OUT_RING_REG(RADEON_GEN_INT_STATUS, RADEON_SW_INT_FIRE);
 266         ADVANCE_RING();
 267         COMMIT_RING();
 268
 269         return ret;
 270 }
 271
 272 static int radeon_wait_irq(struct drm_device * dev, int swi_nr)
 273 {
 274         drm_radeon_private_t *dev_priv =
 275             (drm_radeon_private_t *) dev->dev_private;
 276         int ret = 0;
 277
 278         if (RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr)
 279                 return 0;
 280
 281         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 282
 283         DRM_WAIT_ON(ret, dev_priv->swi_queue, 3 * DRM_HZ,
 284                     RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr);
 285
 286         if (ret == -ERESTART)
 287                 DRM_DEBUG("restarting syscall");
 288
 289         return ret;
 290 }
 291
 292 u32 radeon_get_vblank_counter(struct drm_device *dev, int crtc)
 293 {
 294         drm_radeon_private_t *dev_priv = dev->dev_private;
 295
 296         if (!dev_priv) {
 297                 DRM_ERROR("called with no initialization\n");
 298                 return -EINVAL;
 299         }
 300
 301         if (crtc < 0 || crtc > 1) {
 302                 DRM_ERROR("Invalid crtc %d\n", crtc);
 303                 return -EINVAL;
 304         }
 305
 306         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
 307                 if (crtc == 0)
 308                         return RADEON_READ(R500_D1CRTC_FRAME_COUNT);
 309                 else
 310                         return RADEON_READ(R500_D2CRTC_FRAME_COUNT);
 311         } else {
 312                 if (crtc == 0)
 313                         return RADEON_READ(RADEON_CRTC_CRNT_FRAME);
 314                 else
 315                         return RADEON_READ(RADEON_CRTC2_CRNT_FRAME);
 316         }
 317 }
 318
 319 /* Needs the lock as it touches the ring.
 320  */
 321 int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_priv)
 322 {
 323         drm_radeon_private_t *dev_priv = dev->dev_private;
 324         drm_radeon_irq_emit_t *emit = data;
 325         int result;
 326
 327         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
 328                 return -EINVAL;
 329
 330         LOCK_TEST_WITH_RETURN(dev, file_priv);
 331
 332         if (!dev_priv) {
 333                 DRM_ERROR("called with no initialization\n");
 334                 return -EINVAL;
 335         }
 336
 337         result = radeon_emit_irq(dev);
 338
 339         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
 340                 DRM_ERROR("copy_to_user\n");
 341                 return -EFAULT;
 342         }
 343
 344         return 0;
 345 }
 346
 347 /* Doesn't need the hardware lock.
 348  */
 349 int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_priv)
 350 {
 351         drm_radeon_private_t *dev_priv = dev->dev_private;
 352         drm_radeon_irq_wait_t *irqwait = data;
 353
 354         if (!dev_priv) {
 355                 DRM_ERROR("called with no initialization\n");
 356                 return -EINVAL;
 357         }
 358
 359         return radeon_wait_irq(dev, irqwait->irq_seq);
 360 }
 361
 362 /* drm_dma.h hooks
 363 */
 364 void radeon_driver_irq_preinstall(struct drm_device * dev)
 365 {
 366         drm_radeon_private_t *dev_priv =
 367             (drm_radeon_private_t *) dev->dev_private;
 368         u32 dummy;
 369
 370         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
 371                 return;
 372
 373         /* Disable *all* interrupts */
 374         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600)
 375                 RADEON_WRITE(R500_DxMODE_INT_MASK, 0);
 376         RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
 377
 378         /* Clear bits if they're already high */
 379         radeon_acknowledge_irqs(dev_priv, &dummy);
 380 }
 381
 382 int radeon_driver_irq_postinstall(struct drm_device * dev)
 383 {
 384         drm_radeon_private_t *dev_priv =
 385             (drm_radeon_private_t *) dev->dev_private;
 386
 387         atomic_set(&dev_priv->swi_emitted, 0);
 388         DRM_INIT_WAITQUEUE(&dev_priv->swi_queue);
 389
 390         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
 391                 return 0;
 392
 393         radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);
 394
 395         return 0;
 396 }
 397
 398 void radeon_driver_irq_uninstall(struct drm_device * dev)
 399 {
 400         drm_radeon_private_t *dev_priv =
 401             (drm_radeon_private_t *) dev->dev_private;
 402         if (!dev_priv)
 403                 return;
 404
 405         dev_priv->irq_enabled = 0;
 406
 407         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
 408                 return;
 409
 410         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600)
 411                 RADEON_WRITE(R500_DxMODE_INT_MASK, 0);
 412         /* Disable *all* interrupts */
 413         RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
 414 }
 415
 416
 417 int radeon_vblank_crtc_get(struct drm_device *dev)
 418 {
 419         drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private;
 420
 421         return dev_priv->vblank_crtc;
 422 }
 423
 424 int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value)
 425 {
 426         drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private;
 427         if (value & ~(DRM_RADEON_VBLANK_CRTC1 | DRM_RADEON_VBLANK_CRTC2)) {
 428                 DRM_ERROR("called with invalid crtc 0x%x\n", (unsigned int)value);
 429                 return -EINVAL;
 430         }
 431         dev_priv->vblank_crtc = (unsigned int)value;
 432         return 0;
 433 }