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DRM from FreeBSD current, tested for r600
[dragonfly.git] / sys / dev / drm / radeon_drv.h
blob33001a20e73edea2278140f3a47f53a2ce153473
1 /* radeon_drv.h -- Private header for radeon driver -*- linux-c -*-
2 *
3 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * All rights reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
25 *
26 * Authors:
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
29 * __FBSDID("$FreeBSD: src/sys/dev/drm/radeon_drv.h,v 1.27 2009/09/28 22:40:29 rnoland Exp $");
30 */
31
32 #ifndef __RADEON_DRV_H__
33 #define __RADEON_DRV_H__
34
35 /* General customization:
36 */
37
38 #define DRIVER_AUTHOR "Gareth Hughes, Keith Whitwell, others."
39
40 #define DRIVER_NAME "radeon"
41 #define DRIVER_DESC "ATI Radeon"
42 #define DRIVER_DATE "20080613"
43
44 /* Interface history:
45 *
46 * 1.1 - ??
47 * 1.2 - Add vertex2 ioctl (keith)
48 * - Add stencil capability to clear ioctl (gareth, keith)
49 * - Increase MAX_TEXTURE_LEVELS (brian)
50 * 1.3 - Add cmdbuf ioctl (keith)
51 * - Add support for new radeon packets (keith)
52 * - Add getparam ioctl (keith)
53 * - Add flip-buffers ioctl, deprecate fullscreen foo (keith).
54 * 1.4 - Add scratch registers to get_param ioctl.
55 * 1.5 - Add r200 packets to cmdbuf ioctl
56 * - Add r200 function to init ioctl
57 * - Add 'scalar2' instruction to cmdbuf
58 * 1.6 - Add static GART memory manager
59 * Add irq handler (won't be turned on unless X server knows to)
60 * Add irq ioctls and irq_active getparam.
61 * Add wait command for cmdbuf ioctl
62 * Add GART offset query for getparam
63 * 1.7 - Add support for cube map registers: R200_PP_CUBIC_FACES_[0..5]
64 * and R200_PP_CUBIC_OFFSET_F1_[0..5].
65 * Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and
66 * R200_EMIT_PP_CUBIC_OFFSETS_[0..5]. (brian)
67 * 1.8 - Remove need to call cleanup ioctls on last client exit (keith)
68 * Add 'GET' queries for starting additional clients on different VT's.
69 * 1.9 - Add DRM_IOCTL_RADEON_CP_RESUME ioctl.
70 * Add texture rectangle support for r100.
71 * 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which
72 * clients use to tell the DRM where they think the framebuffer is
73 * located in the card's address space
74 * 1.11- Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color
75 * and GL_EXT_blend_[func|equation]_separate on r200
76 * 1.12- Add R300 CP microcode support - this just loads the CP on r300
77 * (No 3D support yet - just microcode loading).
78 * 1.13- Add packet R200_EMIT_TCL_POINT_SPRITE_CNTL for ARB_point_parameters
79 * - Add hyperz support, add hyperz flags to clear ioctl.
80 * 1.14- Add support for color tiling
81 * - Add R100/R200 surface allocation/free support
82 * 1.15- Add support for texture micro tiling
83 * - Add support for r100 cube maps
84 * 1.16- Add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear
85 * texture filtering on r200
86 * 1.17- Add initial support for R300 (3D).
87 * 1.18- Add support for GL_ATI_fragment_shader, new packets
88 * R200_EMIT_PP_AFS_0/1, R200_EMIT_PP_TXCTLALL_0-5 (replaces
89 * R200_EMIT_PP_TXFILTER_0-5, 2 more regs) and R200_EMIT_ATF_TFACTOR
90 * (replaces R200_EMIT_TFACTOR_0 (8 consts instead of 6)
91 * 1.19- Add support for gart table in FB memory and PCIE r300
92 * 1.20- Add support for r300 texrect
93 * 1.21- Add support for card type getparam
94 * 1.22- Add support for texture cache flushes (R300_TX_CNTL)
95 * 1.23- Add new radeon memory map work from benh
96 * 1.24- Add general-purpose packet for manipulating scratch registers (r300)
97 * 1.25- Add support for r200 vertex programs (R200_EMIT_VAP_PVS_CNTL,
98 * new packet type)
99 * 1.26- Add support for variable size PCI(E) gart aperture
100 * 1.27- Add support for IGP GART
101 * 1.28- Add support for VBL on CRTC2
102 * 1.29- R500 3D cmd buffer support
103 * 1.30- Add support for occlusion queries
104 * 1.31- Add support for num Z pipes from GET_PARAM
105 */
106 #define DRIVER_MAJOR 1
107 #define DRIVER_MINOR 31
108 #define DRIVER_PATCHLEVEL 0
109
110 /*
111 * Radeon chip families
112 */
113 enum radeon_family {
114 CHIP_R100,
115 CHIP_RV100,
116 CHIP_RS100,
117 CHIP_RV200,
118 CHIP_RS200,
119 CHIP_R200,
120 CHIP_RV250,
121 CHIP_RS300,
122 CHIP_RV280,
123 CHIP_R300,
124 CHIP_R350,
125 CHIP_RV350,
126 CHIP_RV380,
127 CHIP_R420,
128 CHIP_R423,
129 CHIP_RV410,
130 CHIP_RS400,
131 CHIP_RS480,
132 CHIP_RS600,
133 CHIP_RS690,
134 CHIP_RS740,
135 CHIP_RV515,
136 CHIP_R520,
137 CHIP_RV530,
138 CHIP_RV560,
139 CHIP_RV570,
140 CHIP_R580,
141 CHIP_R600,
142 CHIP_RV610,
143 CHIP_RV630,
144 CHIP_RV670,
145 CHIP_RV620,
146 CHIP_RV635,
147 CHIP_RS780,
148 CHIP_RS880,
149 CHIP_RV770,
150 CHIP_RV730,
151 CHIP_RV710,
152 CHIP_RV740,
153 CHIP_LAST,
154 };
155
156 enum radeon_cp_microcode_version {
157 UCODE_R100,
158 UCODE_R200,
159 UCODE_R300,
160 };
161
162 /*
163 * Chip flags
164 */
165 enum radeon_chip_flags {
166 RADEON_FAMILY_MASK = 0x0000ffffUL,
167 RADEON_FLAGS_MASK = 0xffff0000UL,
168 RADEON_IS_MOBILITY = 0x00010000UL,
169 RADEON_IS_IGP = 0x00020000UL,
170 RADEON_SINGLE_CRTC = 0x00040000UL,
171 RADEON_IS_AGP = 0x00080000UL,
172 RADEON_HAS_HIERZ = 0x00100000UL,
173 RADEON_IS_PCIE = 0x00200000UL,
174 RADEON_NEW_MEMMAP = 0x00400000UL,
175 RADEON_IS_PCI = 0x00800000UL,
176 RADEON_IS_IGPGART = 0x01000000UL,
177 };
178
179 typedef struct drm_radeon_freelist {
180 unsigned int age;
181 struct drm_buf *buf;
182 struct drm_radeon_freelist *next;
183 struct drm_radeon_freelist *prev;
184 } drm_radeon_freelist_t;
185
186 typedef struct drm_radeon_ring_buffer {
187 u32 *start;
188 u32 *end;
189 int size;
190 int size_l2qw;
191
192 int rptr_update; /* Double Words */
193 int rptr_update_l2qw; /* log2 Quad Words */
194
195 int fetch_size; /* Double Words */
196 int fetch_size_l2ow; /* log2 Oct Words */
197
198 u32 tail;
199 u32 tail_mask;
200 int space;
201
202 int high_mark;
203 } drm_radeon_ring_buffer_t;
204
205 typedef struct drm_radeon_depth_clear_t {
206 u32 rb3d_cntl;
207 u32 rb3d_zstencilcntl;
208 u32 se_cntl;
209 } drm_radeon_depth_clear_t;
210
211 struct drm_radeon_driver_file_fields {
212 int64_t radeon_fb_delta;
213 };
214
215 struct mem_block {
216 struct mem_block *next;
217 struct mem_block *prev;
218 int start;
219 int size;
220 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
221 };
222
223 struct radeon_surface {
224 int refcount;
225 u32 lower;
226 u32 upper;
227 u32 flags;
228 };
229
230 struct radeon_virt_surface {
231 int surface_index;
232 u32 lower;
233 u32 upper;
234 u32 flags;
235 struct drm_file *file_priv;
236 #define PCIGART_FILE_PRIV ((void *) -1L)
237 };
238
239 struct drm_radeon_kernel_chunk {
240 uint32_t chunk_id;
241 uint32_t length_dw;
242 uint32_t __user *chunk_data;
243 uint32_t *kdata;
244 };
245
246 struct drm_radeon_cs_parser {
247 struct drm_device *dev;
248 struct drm_file *file_priv;
249 uint32_t num_chunks;
250 struct drm_radeon_kernel_chunk *chunks;
251 int ib_index;
252 int reloc_index;
253 uint32_t card_offset;
254 void *ib;
255 };
256
257 /* command submission struct */
258 struct drm_radeon_cs_priv {
259 DRM_SPINTYPE cs_mutex;
260 uint32_t id_wcnt;
261 uint32_t id_scnt;
262 uint32_t id_last_wcnt;
263 uint32_t id_last_scnt;
264
265 int (*parse)(struct drm_radeon_cs_parser *parser);
266 void (*id_emit)(struct drm_radeon_cs_parser *parser, uint32_t *id);
267 uint32_t (*id_last_get)(struct drm_device *dev);
268 /* this ib handling callback are for hidding memory manager drm
269 * from memory manager less drm, free have to emit ib discard
270 * sequence into the ring */
271 int (*ib_get)(struct drm_radeon_cs_parser *parser);
272 uint32_t (*ib_get_ptr)(struct drm_device *dev, void *ib);
273 void (*ib_free)(struct drm_radeon_cs_parser *parser, int error);
274 /* do a relocation either MM or non-MM */
275 int (*relocate)(struct drm_radeon_cs_parser *parser,
276 uint32_t *reloc, uint64_t *offset);
277 };
278
279 #define RADEON_FLUSH_EMITED (1 << 0)
280 #define RADEON_PURGE_EMITED (1 << 1)
281
282 typedef struct drm_radeon_private {
283 drm_radeon_ring_buffer_t ring;
284 drm_radeon_sarea_t *sarea_priv;
285
286 u32 fb_location;
287 u32 fb_size;
288 int new_memmap;
289
290 int gart_size;
291 u32 gart_vm_start;
292 unsigned long gart_buffers_offset;
293
294 int cp_mode;
295 int cp_running;
296
297 drm_radeon_freelist_t *head;
298 drm_radeon_freelist_t *tail;
299 int last_buf;
300 int writeback_works;
301
302 int usec_timeout;
303
304 int microcode_version;
305
306 struct {
307 u32 boxes;
308 int freelist_timeouts;
309 int freelist_loops;
310 int requested_bufs;
311 int last_frame_reads;
312 int last_clear_reads;
313 int clears;
314 int texture_uploads;
315 } stats;
316
317 int do_boxes;
318 int page_flipping;
319
320 u32 color_fmt;
321 unsigned int front_offset;
322 unsigned int front_pitch;
323 unsigned int back_offset;
324 unsigned int back_pitch;
325
326 u32 depth_fmt;
327 unsigned int depth_offset;
328 unsigned int depth_pitch;
329
330 u32 front_pitch_offset;
331 u32 back_pitch_offset;
332 u32 depth_pitch_offset;
333
334 drm_radeon_depth_clear_t depth_clear;
335
336 unsigned long ring_offset;
337 unsigned long ring_rptr_offset;
338 unsigned long buffers_offset;
339 unsigned long gart_textures_offset;
340
341 drm_local_map_t *sarea;
342 drm_local_map_t *cp_ring;
343 drm_local_map_t *ring_rptr;
344 drm_local_map_t *gart_textures;
345
346 struct mem_block *gart_heap;
347 struct mem_block *fb_heap;
348
349 /* SW interrupt */
350 wait_queue_head_t swi_queue;
351 atomic_t swi_emitted;
352 int vblank_crtc;
353 uint32_t irq_enable_reg;
354 int irq_enabled;
355 uint32_t r500_disp_irq_reg;
356
357 struct radeon_surface surfaces[RADEON_MAX_SURFACES];
358 struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES];
359
360 unsigned long pcigart_offset;
361 unsigned int pcigart_offset_set;
362 struct drm_ati_pcigart_info gart_info;
363
364 u32 scratch_ages[5];
365
366 /* starting from here on, data is preserved accross an open */
367 uint32_t flags; /* see radeon_chip_flags */
368 unsigned long fb_aper_offset;
369
370 int num_gb_pipes;
371 int num_z_pipes;
372 int track_flush;
373 drm_local_map_t *mmio;
374
375 /* r6xx/r7xx pipe/shader config */
376 int r600_max_pipes;
377 int r600_max_tile_pipes;
378 int r600_max_simds;
379 int r600_max_backends;
380 int r600_max_gprs;
381 int r600_max_threads;
382 int r600_max_stack_entries;
383 int r600_max_hw_contexts;
384 int r600_max_gs_threads;
385 int r600_sx_max_export_size;
386 int r600_sx_max_export_pos_size;
387 int r600_sx_max_export_smx_size;
388 int r600_sq_num_cf_insts;
389 int r700_sx_num_of_sets;
390 int r700_sc_prim_fifo_size;
391 int r700_sc_hiz_tile_fifo_size;
392 int r700_sc_earlyz_tile_fifo_fize;
393 /* r6xx/r7xx drm blit vertex buffer */
394 struct drm_buf *blit_vb;
395
396 /* CS */
397 struct drm_radeon_cs_priv cs;
398 struct drm_buf *cs_buf;
399
400 } drm_radeon_private_t;
401
402 typedef struct drm_radeon_buf_priv {
403 u32 age;
404 } drm_radeon_buf_priv_t;
405
406 typedef struct drm_radeon_kcmd_buffer {
407 int bufsz;
408 char *buf;
409 int nbox;
410 struct drm_clip_rect __user *boxes;
411 } drm_radeon_kcmd_buffer_t;
412
413 extern int radeon_no_wb;
414 extern struct drm_ioctl_desc radeon_ioctls[];
415 extern int radeon_max_ioctl;
416
417 extern u32 radeon_get_ring_head(drm_radeon_private_t *dev_priv);
418 extern void radeon_set_ring_head(drm_radeon_private_t *dev_priv, u32 val);
419
420 #define GET_RING_HEAD(dev_priv) radeon_get_ring_head(dev_priv)
421 #define SET_RING_HEAD(dev_priv, val) radeon_set_ring_head(dev_priv, val)
422
423 /* Check whether the given hardware address is inside the framebuffer or the
424 * GART area.
425 */
426 static __inline__ int radeon_check_offset(drm_radeon_private_t *dev_priv,
427 u64 off)
428 {
429 u64 fb_start = dev_priv->fb_location;
430 u64 fb_end = fb_start + dev_priv->fb_size - 1;
431 u64 gart_start = dev_priv->gart_vm_start;
432 u64 gart_end = gart_start + dev_priv->gart_size - 1;
433
434 return ((off >= fb_start && off <= fb_end) ||
435 (off >= gart_start && off <= gart_end));
436 }
437
438 /* radeon_cp.c */
439 extern int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv);
440 extern int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv);
441 extern int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv);
442 extern int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv);
443 extern int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv);
444 extern int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv);
445 extern int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv);
446 extern int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv);
447 extern int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv);
448 extern u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv);
449 extern void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc);
450 extern void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base);
451 extern u32 RADEON_READ_MM(drm_radeon_private_t *dev_priv, int addr);
452
453 extern void radeon_freelist_reset(struct drm_device * dev);
454 extern struct drm_buf *radeon_freelist_get(struct drm_device * dev);
455
456 extern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n);
457
458 extern int radeon_do_cp_idle(drm_radeon_private_t * dev_priv);
459
460 extern int radeon_driver_preinit(struct drm_device *dev, unsigned long flags);
461 extern int radeon_presetup(struct drm_device *dev);
462 extern int radeon_driver_postcleanup(struct drm_device *dev);
463
464 extern int radeon_mem_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv);
465 extern int radeon_mem_free(struct drm_device *dev, void *data, struct drm_file *file_priv);
466 extern int radeon_mem_init_heap(struct drm_device *dev, void *data, struct drm_file *file_priv);
467 extern void radeon_mem_takedown(struct mem_block **heap);
468 extern void radeon_mem_release(struct drm_file *file_priv,
469 struct mem_block *heap);
470
471 extern void radeon_enable_bm(struct drm_radeon_private *dev_priv);
472 extern u32 radeon_read_ring_rptr(drm_radeon_private_t *dev_priv, u32 off);
473 extern void radeon_write_ring_rptr(drm_radeon_private_t *dev_priv, u32 off, u32 val);
474
475 /* radeon_irq.c */
476 extern void radeon_irq_set_state(struct drm_device *dev, u32 mask, int state);
477 extern int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_priv);
478 extern int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_priv);
479
480 extern void radeon_do_release(struct drm_device * dev);
481 extern u32 radeon_get_vblank_counter(struct drm_device *dev, int crtc);
482 extern int radeon_enable_vblank(struct drm_device *dev, int crtc);
483 extern void radeon_disable_vblank(struct drm_device *dev, int crtc);
484 extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS);
485 extern void radeon_driver_irq_preinstall(struct drm_device * dev);
486 extern int radeon_driver_irq_postinstall(struct drm_device *dev);
487 extern void radeon_driver_irq_uninstall(struct drm_device * dev);
488 extern void radeon_enable_interrupt(struct drm_device *dev);
489 extern int radeon_vblank_crtc_get(struct drm_device *dev);
490 extern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value);
491
492 extern int radeon_driver_load(struct drm_device *dev, unsigned long flags);
493 extern int radeon_driver_unload(struct drm_device *dev);
494 extern int radeon_driver_firstopen(struct drm_device *dev);
495 extern void radeon_driver_preclose(struct drm_device *dev,
496 struct drm_file *file_priv);
497 extern void radeon_driver_postclose(struct drm_device *dev,
498 struct drm_file *file_priv);
499 extern void radeon_driver_lastclose(struct drm_device * dev);
500 extern int radeon_driver_open(struct drm_device *dev,
501 struct drm_file *file_priv);
502 extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd,
503 unsigned long arg);
504
505 /* r300_cmdbuf.c */
506 extern void r300_init_reg_flags(struct drm_device *dev);
507
508 extern int r300_do_cp_cmdbuf(struct drm_device *dev,
509 struct drm_file *file_priv,
510 drm_radeon_kcmd_buffer_t *cmdbuf);
511
512 /* r600_cp.c */
513 extern int r600_do_engine_reset(struct drm_device *dev);
514 extern int r600_do_cleanup_cp(struct drm_device *dev);
515 extern int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
516 struct drm_file *file_priv);
517 extern int r600_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv);
518 extern int r600_do_cp_idle(drm_radeon_private_t *dev_priv);
519 extern void r600_do_cp_start(drm_radeon_private_t *dev_priv);
520 extern void r600_do_cp_reset(drm_radeon_private_t *dev_priv);
521 extern void r600_do_cp_stop(drm_radeon_private_t *dev_priv);
522 extern int r600_cp_dispatch_indirect(struct drm_device *dev,
523 struct drm_buf *buf, int start, int end);
524 extern int r600_page_table_init(struct drm_device *dev);
525 extern void r600_page_table_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info);
526 extern void r600_cp_dispatch_swap(struct drm_device * dev);
527 extern int r600_cp_dispatch_texture(struct drm_device * dev,
528 struct drm_file *file_priv,
529 drm_radeon_texture_t * tex,
530 drm_radeon_tex_image_t * image);
531
532 /* r600_blit.c */
533 extern int
534 r600_prepare_blit_copy(struct drm_device *dev);
535 extern void
536 r600_done_blit_copy(struct drm_device *dev);
537 extern void
538 r600_blit_copy(struct drm_device *dev,
539 uint64_t src_gpu_addr, uint64_t dst_gpu_addr,
540 int size_bytes);
541 extern void
542 r600_blit_swap(struct drm_device *dev,
543 uint64_t src_gpu_addr, uint64_t dst_gpu_addr,
544 int sx, int sy, int dx, int dy,
545 int w, int h, int src_pitch, int dst_pitch, int cpp);
546
547 /* radeon_state.c */
548 extern void radeon_cp_discard_buffer(struct drm_device * dev, struct drm_buf * buf);
549
550 /* radeon_cs.c */
551 extern int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *fpriv);
552 extern int r600_cs_init(struct drm_device *dev);
553
554 /* Flags for stats.boxes
555 */
556 #define RADEON_BOX_DMA_IDLE 0x1
557 #define RADEON_BOX_RING_FULL 0x2
558 #define RADEON_BOX_FLIP 0x4
559 #define RADEON_BOX_WAIT_IDLE 0x8
560 #define RADEON_BOX_TEXTURE_LOAD 0x10
561
562 /* Register definitions, register access macros and drmAddMap constants
563 * for Radeon kernel driver.
564 */
565 #define RADEON_MM_INDEX 0x0000
566 #define RADEON_MM_DATA 0x0004
567
568 #define RADEON_AGP_COMMAND 0x0f60
569 #define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */
570 # define RADEON_AGP_ENABLE (1<<8)
571 #define RADEON_AUX_SCISSOR_CNTL 0x26f0
572 # define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24)
573 # define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25)
574 # define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26)
575 # define RADEON_SCISSOR_0_ENABLE (1 << 28)
576 # define RADEON_SCISSOR_1_ENABLE (1 << 29)
577 # define RADEON_SCISSOR_2_ENABLE (1 << 30)
578
579 /*
580 * PCIE radeons (rv370/rv380, rv410, r423/r430/r480, r5xx)
581 * don't have an explicit bus mastering disable bit. It's handled
582 * by the PCI D-states. PMI_BM_DIS disables D-state bus master
583 * handling, not bus mastering itself.
584 */
585 #define RADEON_BUS_CNTL 0x0030
586 /* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
587 # define RADEON_BUS_MASTER_DIS (1 << 6)
588 /* rs600/rs690/rs740 */
589 # define RS600_BUS_MASTER_DIS (1 << 14)
590 # define RS600_MSI_REARM (1 << 20)
591 /* see RS400_MSI_REARM in AIC_CNTL for rs480 */
592
593 #define RADEON_BUS_CNTL1 0x0034
594 # define RADEON_PMI_BM_DIS (1 << 2)
595 # define RADEON_PMI_INT_DIS (1 << 3)
596
597 #define RV370_BUS_CNTL 0x004c
598 # define RV370_PMI_BM_DIS (1 << 5)
599 # define RV370_PMI_INT_DIS (1 << 6)
600
601 #define RADEON_MSI_REARM_EN 0x0160
602 /* rv370/rv380, rv410, r423/r430/r480, r5xx */
603 # define RV370_MSI_REARM_EN (1 << 0)
604
605 #define RADEON_CLOCK_CNTL_DATA 0x000c
606 # define RADEON_PLL_WR_EN (1 << 7)
607 #define RADEON_CLOCK_CNTL_INDEX 0x0008
608 #define RADEON_CONFIG_APER_SIZE 0x0108
609 #define RADEON_CONFIG_MEMSIZE 0x00f8
610 #define RADEON_CRTC_OFFSET 0x0224
611 #define RADEON_CRTC_OFFSET_CNTL 0x0228
612 # define RADEON_CRTC_TILE_EN (1 << 15)
613 # define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16)
614 #define RADEON_CRTC2_OFFSET 0x0324
615 #define RADEON_CRTC2_OFFSET_CNTL 0x0328
616
617 #define RADEON_PCIE_INDEX 0x0030
618 #define RADEON_PCIE_DATA 0x0034
619 #define RADEON_PCIE_TX_GART_CNTL 0x10
620 # define RADEON_PCIE_TX_GART_EN (1 << 0)
621 # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0 << 1)
622 # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1 << 1)
623 # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3 << 1)
624 # define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0 << 3)
625 # define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1 << 3)
626 # define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1 << 5)
627 # define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1 << 8)
628 #define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11
629 #define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12
630 #define RADEON_PCIE_TX_GART_BASE 0x13
631 #define RADEON_PCIE_TX_GART_START_LO 0x14
632 #define RADEON_PCIE_TX_GART_START_HI 0x15
633 #define RADEON_PCIE_TX_GART_END_LO 0x16
634 #define RADEON_PCIE_TX_GART_END_HI 0x17
635
636 #define RS480_NB_MC_INDEX 0x168
637 # define RS480_NB_MC_IND_WR_EN (1 << 8)
638 #define RS480_NB_MC_DATA 0x16c
639
640 #define RS690_MC_INDEX 0x78
641 # define RS690_MC_INDEX_MASK 0x1ff
642 # define RS690_MC_INDEX_WR_EN (1 << 9)
643 # define RS690_MC_INDEX_WR_ACK 0x7f
644 #define RS690_MC_DATA 0x7c
645
646 /* MC indirect registers */
647 #define RS480_MC_MISC_CNTL 0x18
648 # define RS480_DISABLE_GTW (1 << 1)
649 /* switch between MCIND GART and MM GART registers. 0 = mmgart, 1 = mcind gart */
650 # define RS480_GART_INDEX_REG_EN (1 << 12)
651 # define RS690_BLOCK_GFX_D3_EN (1 << 14)
652 #define RS480_K8_FB_LOCATION 0x1e
653 #define RS480_GART_FEATURE_ID 0x2b
654 # define RS480_HANG_EN (1 << 11)
655 # define RS480_TLB_ENABLE (1 << 18)
656 # define RS480_P2P_ENABLE (1 << 19)
657 # define RS480_GTW_LAC_EN (1 << 25)
658 # define RS480_2LEVEL_GART (0 << 30)
659 # define RS480_1LEVEL_GART (1 << 30)
660 # define RS480_PDC_EN (1 << 31)
661 #define RS480_GART_BASE 0x2c
662 #define RS480_GART_CACHE_CNTRL 0x2e
663 # define RS480_GART_CACHE_INVALIDATE (1 << 0) /* wait for it to clear */
664 #define RS480_AGP_ADDRESS_SPACE_SIZE 0x38
665 # define RS480_GART_EN (1 << 0)
666 # define RS480_VA_SIZE_32MB (0 << 1)
667 # define RS480_VA_SIZE_64MB (1 << 1)
668 # define RS480_VA_SIZE_128MB (2 << 1)
669 # define RS480_VA_SIZE_256MB (3 << 1)
670 # define RS480_VA_SIZE_512MB (4 << 1)
671 # define RS480_VA_SIZE_1GB (5 << 1)
672 # define RS480_VA_SIZE_2GB (6 << 1)
673 #define RS480_AGP_MODE_CNTL 0x39
674 # define RS480_POST_GART_Q_SIZE (1 << 18)
675 # define RS480_NONGART_SNOOP (1 << 19)
676 # define RS480_AGP_RD_BUF_SIZE (1 << 20)
677 # define RS480_REQ_TYPE_SNOOP_SHIFT 22
678 # define RS480_REQ_TYPE_SNOOP_MASK 0x3
679 # define RS480_REQ_TYPE_SNOOP_DIS (1 << 24)
680 #define RS480_MC_MISC_UMA_CNTL 0x5f
681 #define RS480_MC_MCLK_CNTL 0x7a
682 #define RS480_MC_UMA_DUALCH_CNTL 0x86
683
684 #define RS690_MC_FB_LOCATION 0x100
685 #define RS690_MC_AGP_LOCATION 0x101
686 #define RS690_MC_AGP_BASE 0x102
687 #define RS690_MC_AGP_BASE_2 0x103
688
689 #define RS600_MC_INDEX 0x70
690 # define RS600_MC_ADDR_MASK 0xffff
691 # define RS600_MC_IND_SEQ_RBS_0 (1 << 16)
692 # define RS600_MC_IND_SEQ_RBS_1 (1 << 17)
693 # define RS600_MC_IND_SEQ_RBS_2 (1 << 18)
694 # define RS600_MC_IND_SEQ_RBS_3 (1 << 19)
695 # define RS600_MC_IND_AIC_RBS (1 << 20)
696 # define RS600_MC_IND_CITF_ARB0 (1 << 21)
697 # define RS600_MC_IND_CITF_ARB1 (1 << 22)
698 # define RS600_MC_IND_WR_EN (1 << 23)
699 #define RS600_MC_DATA 0x74
700
701 #define RS600_MC_STATUS 0x0
702 # define RS600_MC_IDLE (1 << 1)
703 #define RS600_MC_FB_LOCATION 0x4
704 #define RS600_MC_AGP_LOCATION 0x5
705 #define RS600_AGP_BASE 0x6
706 #define RS600_AGP_BASE_2 0x7
707 #define RS600_MC_CNTL1 0x9
708 # define RS600_ENABLE_PAGE_TABLES (1 << 26)
709 #define RS600_MC_PT0_CNTL 0x100
710 # define RS600_ENABLE_PT (1 << 0)
711 # define RS600_EFFECTIVE_L2_CACHE_SIZE(x) ((x) << 15)
712 # define RS600_EFFECTIVE_L2_QUEUE_SIZE(x) ((x) << 21)
713 # define RS600_INVALIDATE_ALL_L1_TLBS (1 << 28)
714 # define RS600_INVALIDATE_L2_CACHE (1 << 29)
715 #define RS600_MC_PT0_CONTEXT0_CNTL 0x102
716 # define RS600_ENABLE_PAGE_TABLE (1 << 0)
717 # define RS600_PAGE_TABLE_TYPE_FLAT (0 << 1)
718 #define RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR 0x112
719 #define RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR 0x114
720 #define RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR 0x11c
721 #define RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR 0x12c
722 #define RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR 0x13c
723 #define RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR 0x14c
724 #define RS600_MC_PT0_CLIENT0_CNTL 0x16c
725 # define RS600_ENABLE_TRANSLATION_MODE_OVERRIDE (1 << 0)
726 # define RS600_TRANSLATION_MODE_OVERRIDE (1 << 1)
727 # define RS600_SYSTEM_ACCESS_MODE_MASK (3 << 8)
728 # define RS600_SYSTEM_ACCESS_MODE_PA_ONLY (0 << 8)
729 # define RS600_SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 8)
730 # define RS600_SYSTEM_ACCESS_MODE_IN_SYS (2 << 8)
731 # define RS600_SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 8)
732 # define RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASSTHROUGH (0 << 10)
733 # define RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 10)
734 # define RS600_EFFECTIVE_L1_CACHE_SIZE(x) ((x) << 11)
735 # define RS600_ENABLE_FRAGMENT_PROCESSING (1 << 14)
736 # define RS600_EFFECTIVE_L1_QUEUE_SIZE(x) ((x) << 15)
737 # define RS600_INVALIDATE_L1_TLB (1 << 20)
738
739 #define R520_MC_IND_INDEX 0x70
740 #define R520_MC_IND_WR_EN (1 << 24)
741 #define R520_MC_IND_DATA 0x74
742
743 #define RV515_MC_FB_LOCATION 0x01
744 #define RV515_MC_AGP_LOCATION 0x02
745 #define RV515_MC_AGP_BASE 0x03
746 #define RV515_MC_AGP_BASE_2 0x04
747
748 #define R520_MC_FB_LOCATION 0x04
749 #define R520_MC_AGP_LOCATION 0x05
750 #define R520_MC_AGP_BASE 0x06
751 #define R520_MC_AGP_BASE_2 0x07
752
753 #define RADEON_MPP_TB_CONFIG 0x01c0
754 #define RADEON_MEM_CNTL 0x0140
755 #define RADEON_MEM_SDRAM_MODE_REG 0x0158
756 #define RADEON_AGP_BASE_2 0x015c /* r200+ only */
757 #define RS480_AGP_BASE_2 0x0164
758 #define RADEON_AGP_BASE 0x0170
759
760 /* pipe config regs */
761 #define R400_GB_PIPE_SELECT 0x402c
762 #define RV530_GB_PIPE_SELECT2 0x4124
763 #define R500_DYN_SCLK_PWMEM_PIPE 0x000d /* PLL */
764 #define R300_GB_TILE_CONFIG 0x4018
765 # define R300_ENABLE_TILING (1 << 0)
766 # define R300_PIPE_COUNT_RV350 (0 << 1)
767 # define R300_PIPE_COUNT_R300 (3 << 1)
768 # define R300_PIPE_COUNT_R420_3P (6 << 1)
769 # define R300_PIPE_COUNT_R420 (7 << 1)
770 # define R300_TILE_SIZE_8 (0 << 4)
771 # define R300_TILE_SIZE_16 (1 << 4)
772 # define R300_TILE_SIZE_32 (2 << 4)
773 # define R300_SUBPIXEL_1_12 (0 << 16)
774 # define R300_SUBPIXEL_1_16 (1 << 16)
775 #define R300_DST_PIPE_CONFIG 0x170c
776 # define R300_PIPE_AUTO_CONFIG (1 << 31)
777 #define R300_RB2D_DSTCACHE_MODE 0x3428
778 # define R300_DC_AUTOFLUSH_ENABLE (1 << 8)
779 # define R300_DC_DC_DISABLE_IGNORE_PE (1 << 17)
780
781 #define RADEON_RB3D_COLOROFFSET 0x1c40
782 #define RADEON_RB3D_COLORPITCH 0x1c48
783
784 #define RADEON_SRC_X_Y 0x1590
785
786 #define RADEON_DP_GUI_MASTER_CNTL 0x146c
787 # define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
788 # define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
789 # define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4)
790 # define RADEON_GMC_BRUSH_NONE (15 << 4)
791 # define RADEON_GMC_DST_16BPP (4 << 8)
792 # define RADEON_GMC_DST_24BPP (5 << 8)
793 # define RADEON_GMC_DST_32BPP (6 << 8)
794 # define RADEON_GMC_DST_DATATYPE_SHIFT 8
795 # define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12)
796 # define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24)
797 # define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24)
798 # define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28)
799 # define RADEON_GMC_WR_MSK_DIS (1 << 30)
800 # define RADEON_ROP3_S 0x00cc0000
801 # define RADEON_ROP3_P 0x00f00000
802 #define RADEON_DP_WRITE_MASK 0x16cc
803 #define RADEON_SRC_PITCH_OFFSET 0x1428
804 #define RADEON_DST_PITCH_OFFSET 0x142c
805 #define RADEON_DST_PITCH_OFFSET_C 0x1c80
806 # define RADEON_DST_TILE_LINEAR (0 << 30)
807 # define RADEON_DST_TILE_MACRO (1 << 30)
808 # define RADEON_DST_TILE_MICRO (2 << 30)
809 # define RADEON_DST_TILE_BOTH (3 << 30)
810
811 #define RADEON_SCRATCH_REG0 0x15e0
812 #define RADEON_SCRATCH_REG1 0x15e4
813 #define RADEON_SCRATCH_REG2 0x15e8
814 #define RADEON_SCRATCH_REG3 0x15ec
815 #define RADEON_SCRATCH_REG4 0x15f0
816 #define RADEON_SCRATCH_REG5 0x15f4
817 #define RADEON_SCRATCH_UMSK 0x0770
818 #define RADEON_SCRATCH_ADDR 0x0774
819
820 #define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x))
821
822 extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
823
824 #define GET_SCRATCH(dev_priv, x) radeon_get_scratch(dev_priv, x)
825
826 #define R600_SCRATCH_REG0 0x8500
827 #define R600_SCRATCH_REG1 0x8504
828 #define R600_SCRATCH_REG2 0x8508
829 #define R600_SCRATCH_REG3 0x850c
830 #define R600_SCRATCH_REG4 0x8510
831 #define R600_SCRATCH_REG5 0x8514
832 #define R600_SCRATCH_REG6 0x8518
833 #define R600_SCRATCH_REG7 0x851c
834 #define R600_SCRATCH_UMSK 0x8540
835 #define R600_SCRATCH_ADDR 0x8544
836
837 #define R600_SCRATCHOFF(x) (R600_SCRATCH_REG_OFFSET + 4*(x))
838
839 #define RADEON_GEN_INT_CNTL 0x0040
840 # define RADEON_CRTC_VBLANK_MASK (1 << 0)
841 # define RADEON_CRTC2_VBLANK_MASK (1 << 9)
842 # define RADEON_GUI_IDLE_INT_ENABLE (1 << 19)
843 # define RADEON_SW_INT_ENABLE (1 << 25)
844
845 #define RADEON_GEN_INT_STATUS 0x0044
846 # define RADEON_CRTC_VBLANK_STAT (1 << 0)
847 # define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0)
848 # define RADEON_CRTC2_VBLANK_STAT (1 << 9)
849 # define RADEON_CRTC2_VBLANK_STAT_ACK (1 << 9)
850 # define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19)
851 # define RADEON_SW_INT_TEST (1 << 25)
852 # define RADEON_SW_INT_TEST_ACK (1 << 25)
853 # define RADEON_SW_INT_FIRE (1 << 26)
854 # define R500_DISPLAY_INT_STATUS (1 << 0)
855
856 #define RADEON_HOST_PATH_CNTL 0x0130
857 # define RADEON_HDP_SOFT_RESET (1 << 26)
858 # define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28)
859 # define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28)
860
861 #define RADEON_ISYNC_CNTL 0x1724
862 # define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0)
863 # define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1)
864 # define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2)
865 # define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3)
866 # define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4)
867 # define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5)
868
869 #define RADEON_RBBM_GUICNTL 0x172c
870 # define RADEON_HOST_DATA_SWAP_NONE (0 << 0)
871 # define RADEON_HOST_DATA_SWAP_16BIT (1 << 0)
872 # define RADEON_HOST_DATA_SWAP_32BIT (2 << 0)
873 # define RADEON_HOST_DATA_SWAP_HDW (3 << 0)
874
875 #define RADEON_MC_AGP_LOCATION 0x014c
876 #define RADEON_MC_FB_LOCATION 0x0148
877 #define RADEON_MCLK_CNTL 0x0012
878 # define RADEON_FORCEON_MCLKA (1 << 16)
879 # define RADEON_FORCEON_MCLKB (1 << 17)
880 # define RADEON_FORCEON_YCLKA (1 << 18)
881 # define RADEON_FORCEON_YCLKB (1 << 19)
882 # define RADEON_FORCEON_MC (1 << 20)
883 # define RADEON_FORCEON_AIC (1 << 21)
884
885 #define RADEON_PP_BORDER_COLOR_0 0x1d40
886 #define RADEON_PP_BORDER_COLOR_1 0x1d44
887 #define RADEON_PP_BORDER_COLOR_2 0x1d48
888 #define RADEON_PP_CNTL 0x1c38
889 # define RADEON_SCISSOR_ENABLE (1 << 1)
890 #define RADEON_PP_LUM_MATRIX 0x1d00
891 #define RADEON_PP_MISC 0x1c14
892 #define RADEON_PP_ROT_MATRIX_0 0x1d58
893 #define RADEON_PP_TXFILTER_0 0x1c54
894 #define RADEON_PP_TXOFFSET_0 0x1c5c
895 #define RADEON_PP_TXFILTER_1 0x1c6c
896 #define RADEON_PP_TXFILTER_2 0x1c84
897
898 #define R300_RB2D_DSTCACHE_CTLSTAT 0x342c /* use R300_DSTCACHE_CTLSTAT */
899 #define R300_DSTCACHE_CTLSTAT 0x1714
900 # define R300_RB2D_DC_FLUSH (3 << 0)
901 # define R300_RB2D_DC_FREE (3 << 2)
902 # define R300_RB2D_DC_FLUSH_ALL 0xf
903 # define R300_RB2D_DC_BUSY (1 << 31)
904 #define RADEON_RB3D_CNTL 0x1c3c
905 # define RADEON_ALPHA_BLEND_ENABLE (1 << 0)
906 # define RADEON_PLANE_MASK_ENABLE (1 << 1)
907 # define RADEON_DITHER_ENABLE (1 << 2)
908 # define RADEON_ROUND_ENABLE (1 << 3)
909 # define RADEON_SCALE_DITHER_ENABLE (1 << 4)
910 # define RADEON_DITHER_INIT (1 << 5)
911 # define RADEON_ROP_ENABLE (1 << 6)
912 # define RADEON_STENCIL_ENABLE (1 << 7)
913 # define RADEON_Z_ENABLE (1 << 8)
914 # define RADEON_ZBLOCK16 (1 << 15)
915 #define RADEON_RB3D_DEPTHOFFSET 0x1c24
916 #define RADEON_RB3D_DEPTHCLEARVALUE 0x3230
917 #define RADEON_RB3D_DEPTHPITCH 0x1c28
918 #define RADEON_RB3D_PLANEMASK 0x1d84
919 #define RADEON_RB3D_STENCILREFMASK 0x1d7c
920 #define RADEON_RB3D_ZCACHE_MODE 0x3250
921 #define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254
922 # define RADEON_RB3D_ZC_FLUSH (1 << 0)
923 # define RADEON_RB3D_ZC_FREE (1 << 2)
924 # define RADEON_RB3D_ZC_FLUSH_ALL 0x5
925 # define RADEON_RB3D_ZC_BUSY (1 << 31)
926 #define R300_ZB_ZCACHE_CTLSTAT 0x4f18
927 # define R300_ZC_FLUSH (1 << 0)
928 # define R300_ZC_FREE (1 << 1)
929 # define R300_ZC_BUSY (1 << 31)
930 #define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c
931 # define RADEON_RB3D_DC_FLUSH (3 << 0)
932 # define RADEON_RB3D_DC_FREE (3 << 2)
933 # define RADEON_RB3D_DC_FLUSH_ALL 0xf
934 # define RADEON_RB3D_DC_BUSY (1 << 31)
935 #define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c
936 # define R300_RB3D_DC_FLUSH (2 << 0)
937 # define R300_RB3D_DC_FREE (2 << 2)
938 # define R300_RB3D_DC_FINISH (1 << 4)
939 #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
940 # define RADEON_Z_TEST_MASK (7 << 4)
941 # define RADEON_Z_TEST_ALWAYS (7 << 4)
942 # define RADEON_Z_HIERARCHY_ENABLE (1 << 8)
943 # define RADEON_STENCIL_TEST_ALWAYS (7 << 12)
944 # define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16)
945 # define RADEON_STENCIL_ZPASS_REPLACE (2 << 20)
946 # define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24)
947 # define RADEON_Z_COMPRESSION_ENABLE (1 << 28)
948 # define RADEON_FORCE_Z_DIRTY (1 << 29)
949 # define RADEON_Z_WRITE_ENABLE (1 << 30)
950 # define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31)
951 #define RADEON_RBBM_SOFT_RESET 0x00f0
952 # define RADEON_SOFT_RESET_CP (1 << 0)
953 # define RADEON_SOFT_RESET_HI (1 << 1)
954 # define RADEON_SOFT_RESET_SE (1 << 2)
955 # define RADEON_SOFT_RESET_RE (1 << 3)
956 # define RADEON_SOFT_RESET_PP (1 << 4)
957 # define RADEON_SOFT_RESET_E2 (1 << 5)
958 # define RADEON_SOFT_RESET_RB (1 << 6)
959 # define RADEON_SOFT_RESET_HDP (1 << 7)
960 /*
961 * 6:0 Available slots in the FIFO
962 * 8 Host Interface active
963 * 9 CP request active
964 * 10 FIFO request active
965 * 11 Host Interface retry active
966 * 12 CP retry active
967 * 13 FIFO retry active
968 * 14 FIFO pipeline busy
969 * 15 Event engine busy
970 * 16 CP command stream busy
971 * 17 2D engine busy
972 * 18 2D portion of render backend busy
973 * 20 3D setup engine busy
974 * 26 GA engine busy
975 * 27 CBA 2D engine busy
976 * 31 2D engine busy or 3D engine busy or FIFO not empty or CP busy or
977 * command stream queue not empty or Ring Buffer not empty
978 */
979 #define RADEON_RBBM_STATUS 0x0e40
980 /* Same as the previous RADEON_RBBM_STATUS; this is a mirror of that register. */
981 /* #define RADEON_RBBM_STATUS 0x1740 */
982 /* bits 6:0 are dword slots available in the cmd fifo */
983 # define RADEON_RBBM_FIFOCNT_MASK 0x007f
984 # define RADEON_HIRQ_ON_RBB (1 << 8)
985 # define RADEON_CPRQ_ON_RBB (1 << 9)
986 # define RADEON_CFRQ_ON_RBB (1 << 10)
987 # define RADEON_HIRQ_IN_RTBUF (1 << 11)
988 # define RADEON_CPRQ_IN_RTBUF (1 << 12)
989 # define RADEON_CFRQ_IN_RTBUF (1 << 13)
990 # define RADEON_PIPE_BUSY (1 << 14)
991 # define RADEON_ENG_EV_BUSY (1 << 15)
992 # define RADEON_CP_CMDSTRM_BUSY (1 << 16)
993 # define RADEON_E2_BUSY (1 << 17)
994 # define RADEON_RB2D_BUSY (1 << 18)
995 # define RADEON_RB3D_BUSY (1 << 19) /* not used on r300 */
996 # define RADEON_VAP_BUSY (1 << 20)
997 # define RADEON_RE_BUSY (1 << 21) /* not used on r300 */
998 # define RADEON_TAM_BUSY (1 << 22) /* not used on r300 */
999 # define RADEON_TDM_BUSY (1 << 23) /* not used on r300 */
1000 # define RADEON_PB_BUSY (1 << 24) /* not used on r300 */
1001 # define RADEON_TIM_BUSY (1 << 25) /* not used on r300 */
1002 # define RADEON_GA_BUSY (1 << 26)
1003 # define RADEON_CBA2D_BUSY (1 << 27)
1004 # define RADEON_RBBM_ACTIVE (1 << 31)
1005 #define RADEON_RE_LINE_PATTERN 0x1cd0
1006 #define RADEON_RE_MISC 0x26c4
1007 #define RADEON_RE_TOP_LEFT 0x26c0
1008 #define RADEON_RE_WIDTH_HEIGHT 0x1c44
1009 #define RADEON_RE_STIPPLE_ADDR 0x1cc8
1010 #define RADEON_RE_STIPPLE_DATA 0x1ccc
1011
1012 #define RADEON_SCISSOR_TL_0 0x1cd8
1013 #define RADEON_SCISSOR_BR_0 0x1cdc
1014 #define RADEON_SCISSOR_TL_1 0x1ce0
1015 #define RADEON_SCISSOR_BR_1 0x1ce4
1016 #define RADEON_SCISSOR_TL_2 0x1ce8
1017 #define RADEON_SCISSOR_BR_2 0x1cec
1018 #define RADEON_SE_COORD_FMT 0x1c50
1019 #define RADEON_SE_CNTL 0x1c4c
1020 # define RADEON_FFACE_CULL_CW (0 << 0)
1021 # define RADEON_BFACE_SOLID (3 << 1)
1022 # define RADEON_FFACE_SOLID (3 << 3)
1023 # define RADEON_FLAT_SHADE_VTX_LAST (3 << 6)
1024 # define RADEON_DIFFUSE_SHADE_FLAT (1 << 8)
1025 # define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8)
1026 # define RADEON_ALPHA_SHADE_FLAT (1 << 10)
1027 # define RADEON_ALPHA_SHADE_GOURAUD (2 << 10)
1028 # define RADEON_SPECULAR_SHADE_FLAT (1 << 12)
1029 # define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12)
1030 # define RADEON_FOG_SHADE_FLAT (1 << 14)
1031 # define RADEON_FOG_SHADE_GOURAUD (2 << 14)
1032 # define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24)
1033 # define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25)
1034 # define RADEON_VTX_PIX_CENTER_OGL (1 << 27)
1035 # define RADEON_ROUND_MODE_TRUNC (0 << 28)
1036 # define RADEON_ROUND_PREC_8TH_PIX (1 << 30)
1037 #define RADEON_SE_CNTL_STATUS 0x2140
1038 #define RADEON_SE_LINE_WIDTH 0x1db8
1039 #define RADEON_SE_VPORT_XSCALE 0x1d98
1040 #define RADEON_SE_ZBIAS_FACTOR 0x1db0
1041 #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210
1042 #define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254
1043 #define RADEON_SE_TCL_VECTOR_INDX_REG 0x2200
1044 # define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16
1045 # define RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28
1046 #define RADEON_SE_TCL_VECTOR_DATA_REG 0x2204
1047 #define RADEON_SE_TCL_SCALAR_INDX_REG 0x2208
1048 # define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16
1049 #define RADEON_SE_TCL_SCALAR_DATA_REG 0x220C
1050 #define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8
1051 #define RADEON_SURFACE_ACCESS_CLR 0x0bfc
1052 #define RADEON_SURFACE_CNTL 0x0b00
1053 # define RADEON_SURF_TRANSLATION_DIS (1 << 8)
1054 # define RADEON_NONSURF_AP0_SWP_MASK (3 << 20)
1055 # define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20)
1056 # define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20)
1057 # define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20)
1058 # define RADEON_NONSURF_AP1_SWP_MASK (3 << 22)
1059 # define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22)
1060 # define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22)
1061 # define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22)
1062 #define RADEON_SURFACE0_INFO 0x0b0c
1063 # define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0)
1064 # define RADEON_SURF_TILE_MODE_MASK (3 << 16)
1065 # define RADEON_SURF_TILE_MODE_MACRO (0 << 16)
1066 # define RADEON_SURF_TILE_MODE_MICRO (1 << 16)
1067 # define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16)
1068 # define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16)
1069 #define RADEON_SURFACE0_LOWER_BOUND 0x0b04
1070 #define RADEON_SURFACE0_UPPER_BOUND 0x0b08
1071 # define RADEON_SURF_ADDRESS_FIXED_MASK (0x3ff << 0)
1072 #define RADEON_SURFACE1_INFO 0x0b1c
1073 #define RADEON_SURFACE1_LOWER_BOUND 0x0b14
1074 #define RADEON_SURFACE1_UPPER_BOUND 0x0b18
1075 #define RADEON_SURFACE2_INFO 0x0b2c
1076 #define RADEON_SURFACE2_LOWER_BOUND 0x0b24
1077 #define RADEON_SURFACE2_UPPER_BOUND 0x0b28
1078 #define RADEON_SURFACE3_INFO 0x0b3c
1079 #define RADEON_SURFACE3_LOWER_BOUND 0x0b34
1080 #define RADEON_SURFACE3_UPPER_BOUND 0x0b38
1081 #define RADEON_SURFACE4_INFO 0x0b4c
1082 #define RADEON_SURFACE4_LOWER_BOUND 0x0b44
1083 #define RADEON_SURFACE4_UPPER_BOUND 0x0b48
1084 #define RADEON_SURFACE5_INFO 0x0b5c
1085 #define RADEON_SURFACE5_LOWER_BOUND 0x0b54
1086 #define RADEON_SURFACE5_UPPER_BOUND 0x0b58
1087 #define RADEON_SURFACE6_INFO 0x0b6c
1088 #define RADEON_SURFACE6_LOWER_BOUND 0x0b64
1089 #define RADEON_SURFACE6_UPPER_BOUND 0x0b68
1090 #define RADEON_SURFACE7_INFO 0x0b7c
1091 #define RADEON_SURFACE7_LOWER_BOUND 0x0b74
1092 #define RADEON_SURFACE7_UPPER_BOUND 0x0b78
1093 #define RADEON_SW_SEMAPHORE 0x013c
1094
1095 #define RADEON_WAIT_UNTIL 0x1720
1096 # define RADEON_WAIT_CRTC_PFLIP (1 << 0)
1097 # define RADEON_WAIT_2D_IDLE (1 << 14)
1098 # define RADEON_WAIT_3D_IDLE (1 << 15)
1099 # define RADEON_WAIT_2D_IDLECLEAN (1 << 16)
1100 # define RADEON_WAIT_3D_IDLECLEAN (1 << 17)
1101 # define RADEON_WAIT_HOST_IDLECLEAN (1 << 18)
1102
1103 #define RADEON_RB3D_ZMASKOFFSET 0x3234
1104 #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
1105 # define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)
1106 # define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)
1107
1108 /* CP registers */
1109 #define RADEON_CP_ME_RAM_ADDR 0x07d4
1110 #define RADEON_CP_ME_RAM_RADDR 0x07d8
1111 #define RADEON_CP_ME_RAM_DATAH 0x07dc
1112 #define RADEON_CP_ME_RAM_DATAL 0x07e0
1113
1114 #define RADEON_CP_RB_BASE 0x0700
1115 #define RADEON_CP_RB_CNTL 0x0704
1116 # define RADEON_BUF_SWAP_32BIT (2 << 16)
1117 # define RADEON_RB_NO_UPDATE (1 << 27)
1118 # define RADEON_RB_RPTR_WR_ENA (1 << 31)
1119 #define RADEON_CP_RB_RPTR_ADDR 0x070c
1120 #define RADEON_CP_RB_RPTR 0x0710
1121 #define RADEON_CP_RB_WPTR 0x0714
1122
1123 #define RADEON_CP_RB_WPTR_DELAY 0x0718
1124 # define RADEON_PRE_WRITE_TIMER_SHIFT 0
1125 # define RADEON_PRE_WRITE_LIMIT_SHIFT 23
1126
1127 #define RADEON_CP_IB_BASE 0x0738
1128
1129 #define RADEON_CP_CSQ_CNTL 0x0740
1130 # define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0)
1131 # define RADEON_CSQ_PRIDIS_INDDIS (0 << 28)
1132 # define RADEON_CSQ_PRIPIO_INDDIS (1 << 28)
1133 # define RADEON_CSQ_PRIBM_INDDIS (2 << 28)
1134 # define RADEON_CSQ_PRIPIO_INDBM (3 << 28)
1135 # define RADEON_CSQ_PRIBM_INDBM (4 << 28)
1136 # define RADEON_CSQ_PRIPIO_INDPIO (15 << 28)
1137
1138 #define RADEON_AIC_CNTL 0x01d0
1139 # define RADEON_PCIGART_TRANSLATE_EN (1 << 0)
1140 # define RS400_MSI_REARM (1 << 3)
1141 #define RADEON_AIC_STAT 0x01d4
1142 #define RADEON_AIC_PT_BASE 0x01d8
1143 #define RADEON_AIC_LO_ADDR 0x01dc
1144 #define RADEON_AIC_HI_ADDR 0x01e0
1145 #define RADEON_AIC_TLB_ADDR 0x01e4
1146 #define RADEON_AIC_TLB_DATA 0x01e8
1147
1148 /* CP command packets */
1149 #define RADEON_CP_PACKET0 0x00000000
1150 # define RADEON_ONE_REG_WR (1 << 15)
1151 #define RADEON_CP_PACKET1 0x40000000
1152 #define RADEON_CP_PACKET2 0x80000000
1153 #define RADEON_CP_PACKET3 0xC0000000
1154 # define RADEON_CP_NOP 0x00001000
1155 # define RADEON_CP_NEXT_CHAR 0x00001900
1156 # define RADEON_CP_PLY_NEXTSCAN 0x00001D00
1157 # define RADEON_CP_SET_SCISSORS 0x00001E00
1158 /* GEN_INDX_PRIM is unsupported starting with R300 */
1159 # define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300
1160 # define RADEON_WAIT_FOR_IDLE 0x00002600
1161 # define RADEON_3D_DRAW_VBUF 0x00002800
1162 # define RADEON_3D_DRAW_IMMD 0x00002900
1163 # define RADEON_3D_DRAW_INDX 0x00002A00
1164 # define RADEON_CP_LOAD_PALETTE 0x00002C00
1165 # define RADEON_3D_LOAD_VBPNTR 0x00002F00
1166 # define RADEON_MPEG_IDCT_MACROBLOCK 0x00003000
1167 # define RADEON_MPEG_IDCT_MACROBLOCK_REV 0x00003100
1168 # define RADEON_3D_CLEAR_ZMASK 0x00003200
1169 # define RADEON_CP_INDX_BUFFER 0x00003300
1170 # define RADEON_CP_3D_DRAW_VBUF_2 0x00003400
1171 # define RADEON_CP_3D_DRAW_IMMD_2 0x00003500
1172 # define RADEON_CP_3D_DRAW_INDX_2 0x00003600
1173 # define RADEON_3D_CLEAR_HIZ 0x00003700
1174 # define RADEON_CP_3D_CLEAR_CMASK 0x00003802
1175 # define RADEON_CNTL_HOSTDATA_BLT 0x00009400
1176 # define RADEON_CNTL_PAINT_MULTI 0x00009A00
1177 # define RADEON_CNTL_BITBLT_MULTI 0x00009B00
1178 # define RADEON_CNTL_SET_SCISSORS 0xC0001E00
1179
1180 # define R600_IT_INDIRECT_BUFFER 0x00003200
1181 # define R600_IT_ME_INITIALIZE 0x00004400
1182 # define R600_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
1183 # define R600_IT_EVENT_WRITE 0x00004600
1184 # define R600_IT_SET_CONFIG_REG 0x00006800
1185 # define R600_SET_CONFIG_REG_OFFSET 0x00008000
1186 # define R600_SET_CONFIG_REG_END 0x0000ac00
1187
1188 #define RADEON_CP_PACKET_MASK 0xC0000000
1189 #define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000
1190 #define RADEON_CP_PACKET0_REG_MASK 0x000007ff
1191 #define RADEON_CP_PACKET1_REG0_MASK 0x000007ff
1192 #define RADEON_CP_PACKET1_REG1_MASK 0x003ff800
1193
1194 #define RADEON_VTX_Z_PRESENT (1 << 31)
1195 #define RADEON_VTX_PKCOLOR_PRESENT (1 << 3)
1196
1197 #define RADEON_PRIM_TYPE_NONE (0 << 0)
1198 #define RADEON_PRIM_TYPE_POINT (1 << 0)
1199 #define RADEON_PRIM_TYPE_LINE (2 << 0)
1200 #define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0)
1201 #define RADEON_PRIM_TYPE_TRI_LIST (4 << 0)
1202 #define RADEON_PRIM_TYPE_TRI_FAN (5 << 0)
1203 #define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0)
1204 #define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0)
1205 #define RADEON_PRIM_TYPE_RECT_LIST (8 << 0)
1206 #define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0)
1207 #define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0)
1208 #define RADEON_PRIM_TYPE_MASK 0xf
1209 #define RADEON_PRIM_WALK_IND (1 << 4)
1210 #define RADEON_PRIM_WALK_LIST (2 << 4)
1211 #define RADEON_PRIM_WALK_RING (3 << 4)
1212 #define RADEON_COLOR_ORDER_BGRA (0 << 6)
1213 #define RADEON_COLOR_ORDER_RGBA (1 << 6)
1214 #define RADEON_MAOS_ENABLE (1 << 7)
1215 #define RADEON_VTX_FMT_R128_MODE (0 << 8)
1216 #define RADEON_VTX_FMT_RADEON_MODE (1 << 8)
1217 #define RADEON_NUM_VERTICES_SHIFT 16
1218
1219 #define RADEON_COLOR_FORMAT_CI8 2
1220 #define RADEON_COLOR_FORMAT_ARGB1555 3
1221 #define RADEON_COLOR_FORMAT_RGB565 4
1222 #define RADEON_COLOR_FORMAT_ARGB8888 6
1223 #define RADEON_COLOR_FORMAT_RGB332 7
1224 #define RADEON_COLOR_FORMAT_RGB8 9
1225 #define RADEON_COLOR_FORMAT_ARGB4444 15
1226
1227 #define RADEON_TXFORMAT_I8 0
1228 #define RADEON_TXFORMAT_AI88 1
1229 #define RADEON_TXFORMAT_RGB332 2
1230 #define RADEON_TXFORMAT_ARGB1555 3
1231 #define RADEON_TXFORMAT_RGB565 4
1232 #define RADEON_TXFORMAT_ARGB4444 5
1233 #define RADEON_TXFORMAT_ARGB8888 6
1234 #define RADEON_TXFORMAT_RGBA8888 7
1235 #define RADEON_TXFORMAT_Y8 8
1236 #define RADEON_TXFORMAT_VYUY422 10
1237 #define RADEON_TXFORMAT_YVYU422 11
1238 #define RADEON_TXFORMAT_DXT1 12
1239 #define RADEON_TXFORMAT_DXT23 14
1240 #define RADEON_TXFORMAT_DXT45 15
1241
1242 #define R200_PP_TXCBLEND_0 0x2f00
1243 #define R200_PP_TXCBLEND_1 0x2f10
1244 #define R200_PP_TXCBLEND_2 0x2f20
1245 #define R200_PP_TXCBLEND_3 0x2f30
1246 #define R200_PP_TXCBLEND_4 0x2f40
1247 #define R200_PP_TXCBLEND_5 0x2f50
1248 #define R200_PP_TXCBLEND_6 0x2f60
1249 #define R200_PP_TXCBLEND_7 0x2f70
1250 #define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268
1251 #define R200_PP_TFACTOR_0 0x2ee0
1252 #define R200_SE_VTX_FMT_0 0x2088
1253 #define R200_SE_VAP_CNTL 0x2080
1254 #define R200_SE_TCL_MATRIX_SEL_0 0x2230
1255 #define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8
1256 #define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0
1257 #define R200_PP_TXFILTER_5 0x2ca0
1258 #define R200_PP_TXFILTER_4 0x2c80
1259 #define R200_PP_TXFILTER_3 0x2c60
1260 #define R200_PP_TXFILTER_2 0x2c40
1261 #define R200_PP_TXFILTER_1 0x2c20
1262 #define R200_PP_TXFILTER_0 0x2c00
1263 #define R200_PP_TXOFFSET_5 0x2d78
1264 #define R200_PP_TXOFFSET_4 0x2d60
1265 #define R200_PP_TXOFFSET_3 0x2d48
1266 #define R200_PP_TXOFFSET_2 0x2d30
1267 #define R200_PP_TXOFFSET_1 0x2d18
1268 #define R200_PP_TXOFFSET_0 0x2d00
1269
1270 #define R200_PP_CUBIC_FACES_0 0x2c18
1271 #define R200_PP_CUBIC_FACES_1 0x2c38
1272 #define R200_PP_CUBIC_FACES_2 0x2c58
1273 #define R200_PP_CUBIC_FACES_3 0x2c78
1274 #define R200_PP_CUBIC_FACES_4 0x2c98
1275 #define R200_PP_CUBIC_FACES_5 0x2cb8
1276 #define R200_PP_CUBIC_OFFSET_F1_0 0x2d04
1277 #define R200_PP_CUBIC_OFFSET_F2_0 0x2d08
1278 #define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c
1279 #define R200_PP_CUBIC_OFFSET_F4_0 0x2d10
1280 #define R200_PP_CUBIC_OFFSET_F5_0 0x2d14
1281 #define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c
1282 #define R200_PP_CUBIC_OFFSET_F2_1 0x2d20
1283 #define R200_PP_CUBIC_OFFSET_F3_1 0x2d24
1284 #define R200_PP_CUBIC_OFFSET_F4_1 0x2d28
1285 #define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c
1286 #define R200_PP_CUBIC_OFFSET_F1_2 0x2d34
1287 #define R200_PP_CUBIC_OFFSET_F2_2 0x2d38
1288 #define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c
1289 #define R200_PP_CUBIC_OFFSET_F4_2 0x2d40
1290 #define R200_PP_CUBIC_OFFSET_F5_2 0x2d44
1291 #define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c
1292 #define R200_PP_CUBIC_OFFSET_F2_3 0x2d50
1293 #define R200_PP_CUBIC_OFFSET_F3_3 0x2d54
1294 #define R200_PP_CUBIC_OFFSET_F4_3 0x2d58
1295 #define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c
1296 #define R200_PP_CUBIC_OFFSET_F1_4 0x2d64
1297 #define R200_PP_CUBIC_OFFSET_F2_4 0x2d68
1298 #define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c
1299 #define R200_PP_CUBIC_OFFSET_F4_4 0x2d70
1300 #define R200_PP_CUBIC_OFFSET_F5_4 0x2d74
1301 #define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c
1302 #define R200_PP_CUBIC_OFFSET_F2_5 0x2d80
1303 #define R200_PP_CUBIC_OFFSET_F3_5 0x2d84
1304 #define R200_PP_CUBIC_OFFSET_F4_5 0x2d88
1305 #define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c
1306
1307 #define R200_RE_AUX_SCISSOR_CNTL 0x26f0
1308 #define R200_SE_VTE_CNTL 0x20b0
1309 #define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250
1310 #define R200_PP_TAM_DEBUG3 0x2d9c
1311 #define R200_PP_CNTL_X 0x2cc4
1312 #define R200_SE_VAP_CNTL_STATUS 0x2140
1313 #define R200_RE_SCISSOR_TL_0 0x1cd8
1314 #define R200_RE_SCISSOR_TL_1 0x1ce0
1315 #define R200_RE_SCISSOR_TL_2 0x1ce8
1316 #define R200_RB3D_DEPTHXY_OFFSET 0x1d60
1317 #define R200_RE_AUX_SCISSOR_CNTL 0x26f0
1318 #define R200_SE_VTX_STATE_CNTL 0x2180
1319 #define R200_RE_POINTSIZE 0x2648
1320 #define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254
1321
1322 #define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */
1323 #define RADEON_PP_TEX_SIZE_1 0x1d0c
1324 #define RADEON_PP_TEX_SIZE_2 0x1d14
1325
1326 #define RADEON_PP_CUBIC_FACES_0 0x1d24
1327 #define RADEON_PP_CUBIC_FACES_1 0x1d28
1328 #define RADEON_PP_CUBIC_FACES_2 0x1d2c
1329 #define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */
1330 #define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00
1331 #define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14
1332
1333 #define RADEON_SE_TCL_STATE_FLUSH 0x2284
1334
1335 #define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001
1336 #define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000
1337 #define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012
1338 #define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100
1339 #define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200
1340 #define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001
1341 #define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002
1342 #define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b
1343 #define R200_3D_DRAW_IMMD_2 0xC0003500
1344 #define R200_SE_VTX_FMT_1 0x208c
1345 #define R200_RE_CNTL 0x1c50
1346
1347 #define R200_RB3D_BLENDCOLOR 0x3218
1348
1349 #define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4
1350
1351 #define R200_PP_TRI_PERF 0x2cf8
1352
1353 #define R200_PP_AFS_0 0x2f80
1354 #define R200_PP_AFS_1 0x2f00 /* same as txcblend_0 */
1355
1356 #define R200_VAP_PVS_CNTL_1 0x22D0
1357
1358 #define RADEON_CRTC_CRNT_FRAME 0x0214
1359 #define RADEON_CRTC2_CRNT_FRAME 0x0314
1360
1361 #define R500_D1CRTC_STATUS 0x609c
1362 #define R500_D2CRTC_STATUS 0x689c
1363 #define R500_CRTC_V_BLANK (1<<0)
1364
1365 #define R500_D1CRTC_FRAME_COUNT 0x60a4
1366 #define R500_D2CRTC_FRAME_COUNT 0x68a4
1367
1368 #define R500_D1MODE_V_COUNTER 0x6530
1369 #define R500_D2MODE_V_COUNTER 0x6d30
1370
1371 #define R500_D1MODE_VBLANK_STATUS 0x6534
1372 #define R500_D2MODE_VBLANK_STATUS 0x6d34
1373 #define R500_VBLANK_OCCURED (1<<0)
1374 #define R500_VBLANK_ACK (1<<4)
1375 #define R500_VBLANK_STAT (1<<12)
1376 #define R500_VBLANK_INT (1<<16)
1377
1378 #define R500_DxMODE_INT_MASK 0x6540
1379 #define R500_D1MODE_INT_MASK (1<<0)
1380 #define R500_D2MODE_INT_MASK (1<<8)
1381
1382 #define R500_DISP_INTERRUPT_STATUS 0x7edc
1383 #define R500_D1_VBLANK_INTERRUPT (1 << 4)
1384 #define R500_D2_VBLANK_INTERRUPT (1 << 5)
1385
1386 /* R6xx/R7xx registers */
1387 #define R600_MC_VM_FB_LOCATION 0x2180
1388 #define R600_MC_VM_AGP_TOP 0x2184
1389 #define R600_MC_VM_AGP_BOT 0x2188
1390 #define R600_MC_VM_AGP_BASE 0x218c
1391 #define R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190
1392 #define R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194
1393 #define R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198
1394
1395 #define R700_MC_VM_FB_LOCATION 0x2024
1396 #define R700_MC_VM_AGP_TOP 0x2028
1397 #define R700_MC_VM_AGP_BOT 0x202c
1398 #define R700_MC_VM_AGP_BASE 0x2030
1399 #define R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034
1400 #define R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038
1401 #define R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203c
1402
1403 #define R600_MCD_RD_A_CNTL 0x219c
1404 #define R600_MCD_RD_B_CNTL 0x21a0
1405
1406 #define R600_MCD_WR_A_CNTL 0x21a4
1407 #define R600_MCD_WR_B_CNTL 0x21a8
1408
1409 #define R600_MCD_RD_SYS_CNTL 0x2200
1410 #define R600_MCD_WR_SYS_CNTL 0x2214
1411
1412 #define R600_MCD_RD_GFX_CNTL 0x21fc
1413 #define R600_MCD_RD_HDP_CNTL 0x2204
1414 #define R600_MCD_RD_PDMA_CNTL 0x2208
1415 #define R600_MCD_RD_SEM_CNTL 0x220c
1416 #define R600_MCD_WR_GFX_CNTL 0x2210
1417 #define R600_MCD_WR_HDP_CNTL 0x2218
1418 #define R600_MCD_WR_PDMA_CNTL 0x221c
1419 #define R600_MCD_WR_SEM_CNTL 0x2220
1420
1421 # define R600_MCD_L1_TLB (1 << 0)
1422 # define R600_MCD_L1_FRAG_PROC (1 << 1)
1423 # define R600_MCD_L1_STRICT_ORDERING (1 << 2)
1424
1425 # define R600_MCD_SYSTEM_ACCESS_MODE_MASK (3 << 6)
1426 # define R600_MCD_SYSTEM_ACCESS_MODE_PA_ONLY (0 << 6)
1427 # define R600_MCD_SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 6)
1428 # define R600_MCD_SYSTEM_ACCESS_MODE_IN_SYS (2 << 6)
1429 # define R600_MCD_SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 6)
1430
1431 # define R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 8)
1432 # define R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 8)
1433
1434 # define R600_MCD_SEMAPHORE_MODE (1 << 10)
1435 # define R600_MCD_WAIT_L2_QUERY (1 << 11)
1436 # define R600_MCD_EFFECTIVE_L1_TLB_SIZE(x) ((x) << 12)
1437 # define R600_MCD_EFFECTIVE_L1_QUEUE_SIZE(x) ((x) << 15)
1438
1439 #define R700_MC_VM_MD_L1_TLB0_CNTL 0x2654
1440 #define R700_MC_VM_MD_L1_TLB1_CNTL 0x2658
1441 #define R700_MC_VM_MD_L1_TLB2_CNTL 0x265c
1442
1443 #define R700_MC_VM_MB_L1_TLB0_CNTL 0x2234
1444 #define R700_MC_VM_MB_L1_TLB1_CNTL 0x2238
1445 #define R700_MC_VM_MB_L1_TLB2_CNTL 0x223c
1446 #define R700_MC_VM_MB_L1_TLB3_CNTL 0x2240
1447
1448 # define R700_ENABLE_L1_TLB (1 << 0)
1449 # define R700_ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
1450 # define R700_SYSTEM_ACCESS_MODE_IN_SYS (2 << 3)
1451 # define R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)
1452 # define R700_EFFECTIVE_L1_TLB_SIZE(x) ((x) << 15)
1453 # define R700_EFFECTIVE_L1_QUEUE_SIZE(x) ((x) << 18)
1454
1455 #define R700_MC_ARB_RAMCFG 0x2760
1456 # define R700_NOOFBANK_SHIFT 0
1457 # define R700_NOOFBANK_MASK 0x3
1458 # define R700_NOOFRANK_SHIFT 2
1459 # define R700_NOOFRANK_MASK 0x1
1460 # define R700_NOOFROWS_SHIFT 3
1461 # define R700_NOOFROWS_MASK 0x7
1462 # define R700_NOOFCOLS_SHIFT 6
1463 # define R700_NOOFCOLS_MASK 0x3
1464 # define R700_CHANSIZE_SHIFT 8
1465 # define R700_CHANSIZE_MASK 0x1
1466 # define R700_BURSTLENGTH_SHIFT 9
1467 # define R700_BURSTLENGTH_MASK 0x1
1468 #define R600_RAMCFG 0x2408
1469 # define R600_NOOFBANK_SHIFT 0
1470 # define R600_NOOFBANK_MASK 0x1
1471 # define R600_NOOFRANK_SHIFT 1
1472 # define R600_NOOFRANK_MASK 0x1
1473 # define R600_NOOFROWS_SHIFT 2
1474 # define R600_NOOFROWS_MASK 0x7
1475 # define R600_NOOFCOLS_SHIFT 5
1476 # define R600_NOOFCOLS_MASK 0x3
1477 # define R600_CHANSIZE_SHIFT 7
1478 # define R600_CHANSIZE_MASK 0x1
1479 # define R600_BURSTLENGTH_SHIFT 8
1480 # define R600_BURSTLENGTH_MASK 0x1
1481
1482 #define R600_VM_L2_CNTL 0x1400
1483 # define R600_VM_L2_CACHE_EN (1 << 0)
1484 # define R600_VM_L2_FRAG_PROC (1 << 1)
1485 # define R600_VM_ENABLE_PTE_CACHE_LRU_W (1 << 9)
1486 # define R600_VM_L2_CNTL_QUEUE_SIZE(x) ((x) << 13)
1487 # define R700_VM_L2_CNTL_QUEUE_SIZE(x) ((x) << 14)
1488
1489 #define R600_VM_L2_CNTL2 0x1404
1490 # define R600_VM_L2_CNTL2_INVALIDATE_ALL_L1_TLBS (1 << 0)
1491 # define R600_VM_L2_CNTL2_INVALIDATE_L2_CACHE (1 << 1)
1492 #define R600_VM_L2_CNTL3 0x1408
1493 # define R600_VM_L2_CNTL3_BANK_SELECT_0(x) ((x) << 0)
1494 # define R600_VM_L2_CNTL3_BANK_SELECT_1(x) ((x) << 5)
1495 # define R600_VM_L2_CNTL3_CACHE_UPDATE_MODE(x) ((x) << 10)
1496 # define R700_VM_L2_CNTL3_BANK_SELECT(x) ((x) << 0)
1497 # define R700_VM_L2_CNTL3_CACHE_UPDATE_MODE(x) ((x) << 6)
1498
1499 #define R600_VM_L2_STATUS 0x140c
1500
1501 #define R600_VM_CONTEXT0_CNTL 0x1410
1502 # define R600_VM_ENABLE_CONTEXT (1 << 0)
1503 # define R600_VM_PAGE_TABLE_DEPTH_FLAT (0 << 1)
1504
1505 #define R600_VM_CONTEXT0_CNTL2 0x1430
1506 #define R600_VM_CONTEXT0_REQUEST_RESPONSE 0x1470
1507 #define R600_VM_CONTEXT0_INVALIDATION_LOW_ADDR 0x1490
1508 #define R600_VM_CONTEXT0_INVALIDATION_HIGH_ADDR 0x14b0
1509 #define R600_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x1574
1510 #define R600_VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x1594
1511 #define R600_VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x15b4
1512
1513 #define R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c
1514 #define R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155c
1515 #define R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157c
1516
1517 #define R600_HDP_HOST_PATH_CNTL 0x2c00
1518
1519 #define R600_GRBM_CNTL 0x8000
1520 # define R600_GRBM_READ_TIMEOUT(x) ((x) << 0)
1521
1522 #define R600_GRBM_STATUS 0x8010
1523 # define R600_CMDFIFO_AVAIL_MASK 0x1f
1524 # define R700_CMDFIFO_AVAIL_MASK 0xf
1525 # define R600_GUI_ACTIVE (1 << 31)
1526 #define R600_GRBM_STATUS2 0x8014
1527 #define R600_GRBM_SOFT_RESET 0x8020
1528 # define R600_SOFT_RESET_CP (1 << 0)
1529 #define R600_WAIT_UNTIL 0x8040
1530
1531 #define R600_CP_SEM_WAIT_TIMER 0x85bc
1532 #define R600_CP_ME_CNTL 0x86d8
1533 # define R600_CP_ME_HALT (1 << 28)
1534 #define R600_CP_QUEUE_THRESHOLDS 0x8760
1535 # define R600_ROQ_IB1_START(x) ((x) << 0)
1536 # define R600_ROQ_IB2_START(x) ((x) << 8)
1537 #define R600_CP_MEQ_THRESHOLDS 0x8764
1538 # define R700_STQ_SPLIT(x) ((x) << 0)
1539 # define R600_MEQ_END(x) ((x) << 16)
1540 # define R600_ROQ_END(x) ((x) << 24)
1541 #define R600_CP_PERFMON_CNTL 0x87fc
1542 #define R600_CP_RB_BASE 0xc100
1543 #define R600_CP_RB_CNTL 0xc104
1544 # define R600_RB_BUFSZ(x) ((x) << 0)
1545 # define R600_RB_BLKSZ(x) ((x) << 8)
1546 # define R600_RB_NO_UPDATE (1 << 27)
1547 # define R600_RB_RPTR_WR_ENA (1 << 31)
1548 #define R600_CP_RB_RPTR_WR 0xc108
1549 #define R600_CP_RB_RPTR_ADDR 0xc10c
1550 #define R600_CP_RB_RPTR_ADDR_HI 0xc110
1551 #define R600_CP_RB_WPTR 0xc114
1552 #define R600_CP_RB_WPTR_ADDR 0xc118
1553 #define R600_CP_RB_WPTR_ADDR_HI 0xc11c
1554 #define R600_CP_RB_RPTR 0x8700
1555 #define R600_CP_RB_WPTR_DELAY 0x8704
1556 #define R600_CP_PFP_UCODE_ADDR 0xc150
1557 #define R600_CP_PFP_UCODE_DATA 0xc154
1558 #define R600_CP_ME_RAM_RADDR 0xc158
1559 #define R600_CP_ME_RAM_WADDR 0xc15c
1560 #define R600_CP_ME_RAM_DATA 0xc160
1561 #define R600_CP_DEBUG 0xc1fc
1562
1563 #define R600_PA_CL_ENHANCE 0x8a14
1564 # define R600_CLIP_VTX_REORDER_ENA (1 << 0)
1565 # define R600_NUM_CLIP_SEQ(x) ((x) << 1)
1566 #define R600_PA_SC_LINE_STIPPLE_STATE 0x8b10
1567 #define R600_PA_SC_MULTI_CHIP_CNTL 0x8b20
1568 #define R700_PA_SC_FORCE_EOV_MAX_CNTS 0x8b24
1569 # define R700_FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
1570 # define R700_FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16)
1571 #define R600_PA_SC_AA_SAMPLE_LOCS_2S 0x8b40
1572 #define R600_PA_SC_AA_SAMPLE_LOCS_4S 0x8b44
1573 #define R600_PA_SC_AA_SAMPLE_LOCS_8S_WD0 0x8b48
1574 #define R600_PA_SC_AA_SAMPLE_LOCS_8S_WD1 0x8b4c
1575 # define R600_S0_X(x) ((x) << 0)
1576 # define R600_S0_Y(x) ((x) << 4)
1577 # define R600_S1_X(x) ((x) << 8)
1578 # define R600_S1_Y(x) ((x) << 12)
1579 # define R600_S2_X(x) ((x) << 16)
1580 # define R600_S2_Y(x) ((x) << 20)
1581 # define R600_S3_X(x) ((x) << 24)
1582 # define R600_S3_Y(x) ((x) << 28)
1583 # define R600_S4_X(x) ((x) << 0)
1584 # define R600_S4_Y(x) ((x) << 4)
1585 # define R600_S5_X(x) ((x) << 8)
1586 # define R600_S5_Y(x) ((x) << 12)
1587 # define R600_S6_X(x) ((x) << 16)
1588 # define R600_S6_Y(x) ((x) << 20)
1589 # define R600_S7_X(x) ((x) << 24)
1590 # define R600_S7_Y(x) ((x) << 28)
1591 #define R600_PA_SC_FIFO_SIZE 0x8bd0
1592 # define R600_SC_PRIM_FIFO_SIZE(x) ((x) << 0)
1593 # define R600_SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 8)
1594 # define R600_SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 16)
1595 #define R700_PA_SC_FIFO_SIZE_R7XX 0x8bcc
1596 # define R700_SC_PRIM_FIFO_SIZE(x) ((x) << 0)
1597 # define R700_SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12)
1598 # define R700_SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20)
1599 #define R600_PA_SC_ENHANCE 0x8bf0
1600 # define R600_FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
1601 # define R600_FORCE_EOV_MAX_TILE_CNT(x) ((x) << 12)
1602 #define R600_PA_SC_CLIPRECT_RULE 0x2820c
1603 #define R700_PA_SC_EDGERULE 0x28230
1604 #define R600_PA_SC_LINE_STIPPLE 0x28a0c
1605 #define R600_PA_SC_MODE_CNTL 0x28a4c
1606 #define R600_PA_SC_AA_CONFIG 0x28c04
1607
1608 #define R600_SX_EXPORT_BUFFER_SIZES 0x900c
1609 # define R600_COLOR_BUFFER_SIZE(x) ((x) << 0)
1610 # define R600_POSITION_BUFFER_SIZE(x) ((x) << 8)
1611 # define R600_SMX_BUFFER_SIZE(x) ((x) << 16)
1612 #define R600_SX_DEBUG_1 0x9054
1613 # define R600_SMX_EVENT_RELEASE (1 << 0)
1614 # define R600_ENABLE_NEW_SMX_ADDRESS (1 << 16)
1615 #define R700_SX_DEBUG_1 0x9058
1616 # define R700_ENABLE_NEW_SMX_ADDRESS (1 << 16)
1617 #define R600_SX_MISC 0x28350
1618
1619 #define R600_DB_DEBUG 0x9830
1620 # define R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE (1 << 31)
1621 #define R600_DB_WATERMARKS 0x9838
1622 # define R600_DEPTH_FREE(x) ((x) << 0)
1623 # define R600_DEPTH_FLUSH(x) ((x) << 5)
1624 # define R600_DEPTH_PENDING_FREE(x) ((x) << 15)
1625 # define R600_DEPTH_CACHELINE_FREE(x) ((x) << 20)
1626 #define R700_DB_DEBUG3 0x98b0
1627 # define R700_DB_CLK_OFF_DELAY(x) ((x) << 11)
1628 #define RV700_DB_DEBUG4 0x9b8c
1629 # define RV700_DISABLE_TILE_COVERED_FOR_PS_ITER (1 << 6)
1630
1631 #define R600_VGT_CACHE_INVALIDATION 0x88c4
1632 # define R600_CACHE_INVALIDATION(x) ((x) << 0)
1633 # define R600_VC_ONLY 0
1634 # define R600_TC_ONLY 1
1635 # define R600_VC_AND_TC 2
1636 # define R700_AUTO_INVLD_EN(x) ((x) << 6)
1637 # define R700_NO_AUTO 0
1638 # define R700_ES_AUTO 1
1639 # define R700_GS_AUTO 2
1640 # define R700_ES_AND_GS_AUTO 3
1641 #define R600_VGT_GS_PER_ES 0x88c8
1642 #define R600_VGT_ES_PER_GS 0x88cc
1643 #define R600_VGT_GS_PER_VS 0x88e8
1644 #define R600_VGT_GS_VERTEX_REUSE 0x88d4
1645 #define R600_VGT_NUM_INSTANCES 0x8974
1646 #define R600_VGT_STRMOUT_EN 0x28ab0
1647 #define R600_VGT_EVENT_INITIATOR 0x28a90
1648 # define R600_CACHE_FLUSH_AND_INV_EVENT (0x16 << 0)
1649 #define R600_VGT_VERTEX_REUSE_BLOCK_CNTL 0x28c58
1650 # define R600_VTX_REUSE_DEPTH_MASK 0xff
1651 #define R600_VGT_OUT_DEALLOC_CNTL 0x28c5c
1652 # define R600_DEALLOC_DIST_MASK 0x7f
1653
1654 #define R600_CB_COLOR0_BASE 0x28040
1655 #define R600_CB_COLOR1_BASE 0x28044
1656 #define R600_CB_COLOR2_BASE 0x28048
1657 #define R600_CB_COLOR3_BASE 0x2804c
1658 #define R600_CB_COLOR4_BASE 0x28050
1659 #define R600_CB_COLOR5_BASE 0x28054
1660 #define R600_CB_COLOR6_BASE 0x28058
1661 #define R600_CB_COLOR7_BASE 0x2805c
1662 #define R600_CB_COLOR7_FRAG 0x280fc
1663
1664 #define R600_TC_CNTL 0x9608
1665 # define R600_TC_L2_SIZE(x) ((x) << 5)
1666 # define R600_L2_DISABLE_LATE_HIT (1 << 9)
1667
1668 #define R600_ARB_POP 0x2418
1669 # define R600_ENABLE_TC128 (1 << 30)
1670 #define R600_ARB_GDEC_RD_CNTL 0x246c
1671
1672 #define R600_TA_CNTL_AUX 0x9508
1673 # define R600_DISABLE_CUBE_WRAP (1 << 0)
1674 # define R600_DISABLE_CUBE_ANISO (1 << 1)
1675 # define R700_GETLOD_SELECT(x) ((x) << 2)
1676 # define R600_SYNC_GRADIENT (1 << 24)
1677 # define R600_SYNC_WALKER (1 << 25)
1678 # define R600_SYNC_ALIGNER (1 << 26)
1679 # define R600_BILINEAR_PRECISION_6_BIT (0 << 31)
1680 # define R600_BILINEAR_PRECISION_8_BIT (1 << 31)
1681
1682 #define R700_TCP_CNTL 0x9610
1683
1684 #define R600_SMX_DC_CTL0 0xa020
1685 # define R700_USE_HASH_FUNCTION (1 << 0)
1686 # define R700_CACHE_DEPTH(x) ((x) << 1)
1687 # define R700_FLUSH_ALL_ON_EVENT (1 << 10)
1688 # define R700_STALL_ON_EVENT (1 << 11)
1689 #define R700_SMX_EVENT_CTL 0xa02c
1690 # define R700_ES_FLUSH_CTL(x) ((x) << 0)
1691 # define R700_GS_FLUSH_CTL(x) ((x) << 3)
1692 # define R700_ACK_FLUSH_CTL(x) ((x) << 6)
1693 # define R700_SYNC_FLUSH_CTL (1 << 8)
1694
1695 #define R600_SQ_CONFIG 0x8c00
1696 # define R600_VC_ENABLE (1 << 0)
1697 # define R600_EXPORT_SRC_C (1 << 1)
1698 # define R600_DX9_CONSTS (1 << 2)
1699 # define R600_ALU_INST_PREFER_VECTOR (1 << 3)
1700 # define R600_DX10_CLAMP (1 << 4)
1701 # define R600_CLAUSE_SEQ_PRIO(x) ((x) << 8)
1702 # define R600_PS_PRIO(x) ((x) << 24)
1703 # define R600_VS_PRIO(x) ((x) << 26)
1704 # define R600_GS_PRIO(x) ((x) << 28)
1705 # define R600_ES_PRIO(x) ((x) << 30)
1706 #define R600_SQ_GPR_RESOURCE_MGMT_1 0x8c04
1707 # define R600_NUM_PS_GPRS(x) ((x) << 0)
1708 # define R600_NUM_VS_GPRS(x) ((x) << 16)
1709 # define R700_DYN_GPR_ENABLE (1 << 27)
1710 # define R600_NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28)
1711 #define R600_SQ_GPR_RESOURCE_MGMT_2 0x8c08
1712 # define R600_NUM_GS_GPRS(x) ((x) << 0)
1713 # define R600_NUM_ES_GPRS(x) ((x) << 16)
1714 #define R600_SQ_THREAD_RESOURCE_MGMT 0x8c0c
1715 # define R600_NUM_PS_THREADS(x) ((x) << 0)
1716 # define R600_NUM_VS_THREADS(x) ((x) << 8)
1717 # define R600_NUM_GS_THREADS(x) ((x) << 16)
1718 # define R600_NUM_ES_THREADS(x) ((x) << 24)
1719 #define R600_SQ_STACK_RESOURCE_MGMT_1 0x8c10
1720 # define R600_NUM_PS_STACK_ENTRIES(x) ((x) << 0)
1721 # define R600_NUM_VS_STACK_ENTRIES(x) ((x) << 16)
1722 #define R600_SQ_STACK_RESOURCE_MGMT_2 0x8c14
1723 # define R600_NUM_GS_STACK_ENTRIES(x) ((x) << 0)
1724 # define R600_NUM_ES_STACK_ENTRIES(x) ((x) << 16)
1725 #define R600_SQ_MS_FIFO_SIZES 0x8cf0
1726 # define R600_CACHE_FIFO_SIZE(x) ((x) << 0)
1727 # define R600_FETCH_FIFO_HIWATER(x) ((x) << 8)
1728 # define R600_DONE_FIFO_HIWATER(x) ((x) << 16)
1729 # define R600_ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24)
1730 #define R700_SQ_DYN_GPR_SIZE_SIMD_AB_0 0x8db0
1731 # define R700_SIMDA_RING0(x) ((x) << 0)
1732 # define R700_SIMDA_RING1(x) ((x) << 8)
1733 # define R700_SIMDB_RING0(x) ((x) << 16)
1734 # define R700_SIMDB_RING1(x) ((x) << 24)
1735 #define R700_SQ_DYN_GPR_SIZE_SIMD_AB_1 0x8db4
1736 #define R700_SQ_DYN_GPR_SIZE_SIMD_AB_2 0x8db8
1737 #define R700_SQ_DYN_GPR_SIZE_SIMD_AB_3 0x8dbc
1738 #define R700_SQ_DYN_GPR_SIZE_SIMD_AB_4 0x8dc0
1739 #define R700_SQ_DYN_GPR_SIZE_SIMD_AB_5 0x8dc4
1740 #define R700_SQ_DYN_GPR_SIZE_SIMD_AB_6 0x8dc8
1741 #define R700_SQ_DYN_GPR_SIZE_SIMD_AB_7 0x8dcc
1742
1743 #define R600_SPI_PS_IN_CONTROL_0 0x286cc
1744 # define R600_NUM_INTERP(x) ((x) << 0)
1745 # define R600_POSITION_ENA (1 << 8)
1746 # define R600_POSITION_CENTROID (1 << 9)
1747 # define R600_POSITION_ADDR(x) ((x) << 10)
1748 # define R600_PARAM_GEN(x) ((x) << 15)
1749 # define R600_PARAM_GEN_ADDR(x) ((x) << 19)
1750 # define R600_BARYC_SAMPLE_CNTL(x) ((x) << 26)
1751 # define R600_PERSP_GRADIENT_ENA (1 << 28)
1752 # define R600_LINEAR_GRADIENT_ENA (1 << 29)
1753 # define R600_POSITION_SAMPLE (1 << 30)
1754 # define R600_BARYC_AT_SAMPLE_ENA (1 << 31)
1755 #define R600_SPI_PS_IN_CONTROL_1 0x286d0
1756 # define R600_GEN_INDEX_PIX (1 << 0)
1757 # define R600_GEN_INDEX_PIX_ADDR(x) ((x) << 1)
1758 # define R600_FRONT_FACE_ENA (1 << 8)
1759 # define R600_FRONT_FACE_CHAN(x) ((x) << 9)
1760 # define R600_FRONT_FACE_ALL_BITS (1 << 11)
1761 # define R600_FRONT_FACE_ADDR(x) ((x) << 12)
1762 # define R600_FOG_ADDR(x) ((x) << 17)
1763 # define R600_FIXED_PT_POSITION_ENA (1 << 24)
1764 # define R600_FIXED_PT_POSITION_ADDR(x) ((x) << 25)
1765 # define R700_POSITION_ULC (1 << 30)
1766 #define R600_SPI_INPUT_Z 0x286d8
1767
1768 #define R600_SPI_CONFIG_CNTL 0x9100
1769 # define R600_GPR_WRITE_PRIORITY(x) ((x) << 0)
1770 # define R600_DISABLE_INTERP_1 (1 << 5)
1771 #define R600_SPI_CONFIG_CNTL_1 0x913c
1772 # define R600_VTX_DONE_DELAY(x) ((x) << 0)
1773 # define R600_INTERP_ONE_PRIM_PER_ROW (1 << 4)
1774
1775 #define R600_GB_TILING_CONFIG 0x98f0
1776 # define R600_PIPE_TILING(x) ((x) << 1)
1777 # define R600_BANK_TILING(x) ((x) << 4)
1778 # define R600_GROUP_SIZE(x) ((x) << 6)
1779 # define R600_ROW_TILING(x) ((x) << 8)
1780 # define R600_BANK_SWAPS(x) ((x) << 11)
1781 # define R600_SAMPLE_SPLIT(x) ((x) << 14)
1782 # define R600_BACKEND_MAP(x) ((x) << 16)
1783 #define R600_DCP_TILING_CONFIG 0x6ca0
1784 #define R600_HDP_TILING_CONFIG 0x2f3c
1785
1786 #define R600_CC_RB_BACKEND_DISABLE 0x98f4
1787 #define R700_CC_SYS_RB_BACKEND_DISABLE 0x3f88
1788 # define R600_BACKEND_DISABLE(x) ((x) << 16)
1789
1790 #define R600_CC_GC_SHADER_PIPE_CONFIG 0x8950
1791 #define R600_GC_USER_SHADER_PIPE_CONFIG 0x8954
1792 # define R600_INACTIVE_QD_PIPES(x) ((x) << 8)
1793 # define R600_INACTIVE_QD_PIPES_MASK (0xff << 8)
1794 # define R600_INACTIVE_SIMDS(x) ((x) << 16)
1795 # define R600_INACTIVE_SIMDS_MASK (0xff << 16)
1796
1797 #define R700_CGTS_SYS_TCC_DISABLE 0x3f90
1798 #define R700_CGTS_USER_SYS_TCC_DISABLE 0x3f94
1799 #define R700_CGTS_TCC_DISABLE 0x9148
1800 #define R700_CGTS_USER_TCC_DISABLE 0x914c
1801
1802 /* Constants */
1803 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
1804
1805 #define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0
1806 #define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1
1807 #define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2
1808 #define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3
1809 #define RADEON_LAST_DISPATCH 1
1810
1811 #define R600_LAST_FRAME_REG R600_SCRATCH_REG0
1812 #define R600_LAST_DISPATCH_REG R600_SCRATCH_REG1
1813 #define R600_LAST_CLEAR_REG R600_SCRATCH_REG2
1814 #define R600_LAST_SWI_REG R600_SCRATCH_REG3
1815
1816 #define RADEON_MAX_VB_AGE 0x7fffffff
1817 #define RADEON_MAX_VB_VERTS (0xffff)
1818
1819 #define RADEON_RING_HIGH_MARK 128
1820
1821 #define RADEON_PCIGART_TABLE_SIZE (32*1024)
1822
1823 #define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
1824 #define RADEON_WRITE(reg, val) \
1825 do { \
1826 if (reg < 0x10000) { \
1827 DRM_WRITE32(dev_priv->mmio, (reg), (val)); \
1828 } else { \
1829 DRM_WRITE32(dev_priv->mmio, RADEON_MM_INDEX, (reg)); \
1830 DRM_WRITE32(dev_priv->mmio, RADEON_MM_DATA, (val)); \
1831 } \
1832 } while (0)
1833 #define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) )
1834 #define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )
1835
1836 #define RADEON_WRITE_PLL(addr, val) \
1837 do { \
1838 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, \
1839 ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \
1840 RADEON_WRITE(RADEON_CLOCK_CNTL_DATA, (val)); \
1841 } while (0)
1842
1843 #define RADEON_WRITE_PCIE(addr, val) \
1844 do { \
1845 RADEON_WRITE8(RADEON_PCIE_INDEX, \
1846 ((addr) & 0xff)); \
1847 RADEON_WRITE(RADEON_PCIE_DATA, (val)); \
1848 } while (0)
1849
1850 #define R500_WRITE_MCIND(addr, val) \
1851 do { \
1852 RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff)); \
1853 RADEON_WRITE(R520_MC_IND_DATA, (val)); \
1854 RADEON_WRITE(R520_MC_IND_INDEX, 0); \
1855 } while (0)
1856
1857 #define RS480_WRITE_MCIND(addr, val) \
1858 do { \
1859 RADEON_WRITE(RS480_NB_MC_INDEX, \
1860 ((addr) & 0xff) | RS480_NB_MC_IND_WR_EN); \
1861 RADEON_WRITE(RS480_NB_MC_DATA, (val)); \
1862 RADEON_WRITE(RS480_NB_MC_INDEX, 0xff); \
1863 } while (0)
1864
1865 #define RS690_WRITE_MCIND(addr, val) \
1866 do { \
1867 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_EN | ((addr) & RS690_MC_INDEX_MASK)); \
1868 RADEON_WRITE(RS690_MC_DATA, val); \
1869 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); \
1870 } while (0)
1871
1872 #define RS600_WRITE_MCIND(addr, val) \
1873 do { \
1874 RADEON_WRITE(RS600_MC_INDEX, RS600_MC_IND_WR_EN | RS600_MC_IND_CITF_ARB0 | ((addr) & RS600_MC_ADDR_MASK)); \
1875 RADEON_WRITE(RS600_MC_DATA, val); \
1876 } while (0)
1877
1878 #define IGP_WRITE_MCIND(addr, val) \
1879 do { \
1880 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || \
1881 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) \
1882 RS690_WRITE_MCIND(addr, val); \
1883 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) \
1884 RS600_WRITE_MCIND(addr, val); \
1885 else \
1886 RS480_WRITE_MCIND(addr, val); \
1887 } while (0)
1888
1889 #define CP_PACKET0( reg, n ) \
1890 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
1891 #define CP_PACKET0_TABLE( reg, n ) \
1892 (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2))
1893 #define CP_PACKET1( reg0, reg1 ) \
1894 (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2))
1895 #define CP_PACKET2() \
1896 (RADEON_CP_PACKET2)
1897 #define CP_PACKET3( pkt, n ) \
1898 (RADEON_CP_PACKET3 | (pkt) | ((n) << 16))
1899
1900 /* ================================================================
1901 * Engine control helper macros
1902 */
1903
1904 #define RADEON_WAIT_UNTIL_2D_IDLE() do { \
1905 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) \
1906 OUT_RING( CP_PACKET0( R600_WAIT_UNTIL, 0 ) ); \
1907 else \
1908 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1909 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
1910 RADEON_WAIT_HOST_IDLECLEAN) ); \
1911 } while (0)
1912
1913 #define RADEON_WAIT_UNTIL_3D_IDLE() do { \
1914 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) \
1915 OUT_RING( CP_PACKET0( R600_WAIT_UNTIL, 0 ) ); \
1916 else \
1917 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1918 OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \
1919 RADEON_WAIT_HOST_IDLECLEAN) ); \
1920 } while (0)
1921
1922 #define RADEON_WAIT_UNTIL_IDLE() do { \
1923 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) \
1924 OUT_RING( CP_PACKET0( R600_WAIT_UNTIL, 0 ) ); \
1925 else \
1926 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1927 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
1928 RADEON_WAIT_3D_IDLECLEAN | \
1929 RADEON_WAIT_HOST_IDLECLEAN) ); \
1930 } while (0)
1931
1932 #define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \
1933 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) \
1934 OUT_RING( CP_PACKET0( R600_WAIT_UNTIL, 0 ) ); \
1935 else \
1936 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1937 OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \
1938 } while (0)
1939
1940 #define RADEON_FLUSH_CACHE() do { \
1941 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1942 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \
1943 OUT_RING(RADEON_RB3D_DC_FLUSH); \
1944 } else { \
1945 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \
1946 OUT_RING(R300_RB3D_DC_FLUSH); \
1947 } \
1948 } while (0)
1949
1950 #define RADEON_PURGE_CACHE() do { \
1951 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1952 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \
1953 OUT_RING(RADEON_RB3D_DC_FLUSH | RADEON_RB3D_DC_FREE); \
1954 } else { \
1955 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \
1956 OUT_RING(R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); \
1957 } \
1958 } while (0)
1959
1960 #define RADEON_FLUSH_ZCACHE() do { \
1961 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1962 OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \
1963 OUT_RING(RADEON_RB3D_ZC_FLUSH); \
1964 } else { \
1965 OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); \
1966 OUT_RING(R300_ZC_FLUSH); \
1967 } \
1968 } while (0)
1969
1970 #define RADEON_PURGE_ZCACHE() do { \
1971 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1972 OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \
1973 OUT_RING(RADEON_RB3D_ZC_FLUSH | RADEON_RB3D_ZC_FREE); \
1974 } else { \
1975 OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); \
1976 OUT_RING(R300_ZC_FLUSH | R300_ZC_FREE); \
1977 } \
1978 } while (0)
1979
1980 /* ================================================================
1981 * Misc helper macros
1982 */
1983
1984 /* Perfbox functionality only.
1985 */
1986 #define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \
1987 do { \
1988 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \
1989 u32 head = GET_RING_HEAD( dev_priv ); \
1990 if (head == dev_priv->ring.tail) \
1991 dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \
1992 } \
1993 } while (0)
1994
1995 #define VB_AGE_TEST_WITH_RETURN( dev_priv ) \
1996 do { \
1997 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; \
1998 if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \
1999 int __ret; \
2000 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) \
2001 __ret = r600_do_cp_idle(dev_priv); \
2002 else \
2003 __ret = radeon_do_cp_idle(dev_priv); \
2004 if ( __ret ) return __ret; \
2005 sarea_priv->last_dispatch = 0; \
2006 radeon_freelist_reset( dev ); \
2007 } \
2008 } while (0)
2009
2010 #define RADEON_DISPATCH_AGE( age ) do { \
2011 OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \
2012 OUT_RING( age ); \
2013 } while (0)
2014
2015 #define RADEON_FRAME_AGE( age ) do { \
2016 OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \
2017 OUT_RING( age ); \
2018 } while (0)
2019
2020 #define RADEON_CLEAR_AGE( age ) do { \
2021 OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \
2022 OUT_RING( age ); \
2023 } while (0)
2024
2025 #define R600_DISPATCH_AGE(age) do { \
2026 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \
2027 OUT_RING((R600_LAST_DISPATCH_REG - R600_SET_CONFIG_REG_OFFSET) >> 2); \
2028 OUT_RING(age); \
2029 } while (0)
2030
2031 #define R600_FRAME_AGE(age) do { \
2032 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \
2033 OUT_RING((R600_LAST_FRAME_REG - R600_SET_CONFIG_REG_OFFSET) >> 2); \
2034 OUT_RING(age); \
2035 } while (0)
2036
2037 #define R600_CLEAR_AGE(age) do { \
2038 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \
2039 OUT_RING((R600_LAST_CLEAR_REG - R600_SET_CONFIG_REG_OFFSET) >> 2); \
2040 OUT_RING(age); \
2041 } while (0)
2042
2043 /* ================================================================
2044 * Ring control
2045 */
2046
2047 #define RADEON_VERBOSE 0
2048
2049 #define RING_LOCALS int write, _nr, _align_nr; unsigned int mask; u32 *ring;
2050
2051 #define RADEON_RING_ALIGN 16
2052
2053 #define BEGIN_RING( n ) do { \
2054 if ( RADEON_VERBOSE ) { \
2055 DRM_INFO( "BEGIN_RING( %d )\n", (n)); \
2056 } \
2057 _align_nr = RADEON_RING_ALIGN - ((dev_priv->ring.tail + n) & (RADEON_RING_ALIGN - 1)); \
2058 _align_nr += n; \
2059 if ( dev_priv->ring.space <= (_align_nr) * sizeof(u32) ) { \
2060 COMMIT_RING(); \
2061 radeon_wait_ring( dev_priv, (_align_nr) * sizeof(u32) ); \
2062 } \
2063 _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \
2064 ring = dev_priv->ring.start; \
2065 write = dev_priv->ring.tail; \
2066 mask = dev_priv->ring.tail_mask; \
2067 } while (0)
2068
2069 #define ADVANCE_RING() do { \
2070 if ( RADEON_VERBOSE ) { \
2071 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \
2072 write, dev_priv->ring.tail ); \
2073 } \
2074 if (((dev_priv->ring.tail + _nr) & mask) != write) { \
2075 DRM_ERROR( \
2076 "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \
2077 ((dev_priv->ring.tail + _nr) & mask), \
2078 write, __LINE__); \
2079 } else \
2080 dev_priv->ring.tail = write; \
2081 } while (0)
2082
2083 extern void radeon_commit_ring(drm_radeon_private_t *dev_priv);
2084
2085 #define COMMIT_RING() do { \
2086 radeon_commit_ring(dev_priv); \
2087 } while(0)
2088
2089 #define OUT_RING( x ) do { \
2090 if ( RADEON_VERBOSE ) { \
2091 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \
2092 (unsigned int)(x), write ); \
2093 } \
2094 ring[write++] = (x); \
2095 write &= mask; \
2096 } while (0)
2097
2098 #define OUT_RING_REG( reg, val ) do { \
2099 OUT_RING( CP_PACKET0( reg, 0 ) ); \
2100 OUT_RING( val ); \
2101 } while (0)
2102
2103 #define OUT_RING_TABLE( tab, sz ) do { \
2104 int _size = (sz); \
2105 int *_tab = (int *)(tab); \
2106 \
2107 if (write + _size > mask) { \
2108 int _i = (mask+1) - write; \
2109 _size -= _i; \
2110 while (_i > 0 ) { \
2111 *(int *)(ring + write) = *_tab++; \
2112 write++; \
2113 _i--; \
2114 } \
2115 write = 0; \
2116 _tab += _i; \
2117 } \
2118 while (_size > 0) { \
2119 *(ring + write) = *_tab++; \
2120 write++; \
2121 _size--; \
2122 } \
2123 write &= mask; \
2124 } while (0)
2125
2126 #endif /* __RADEON_DRV_H__ */
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