sys/dev/drm/radeon_drm.h

   1 /* radeon_drm.h -- Public header for the radeon driver -*- linux-c -*-
   2  *
   3  * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
   4  * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
   5  * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All rights reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  23  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  24  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  25  * DEALINGS IN THE SOFTWARE.
  26  *
  27  * Authors:
  28  *    Kevin E. Martin <martin@valinux.com>
  29  *    Gareth Hughes <gareth@valinux.com>
  30  *    Keith Whitwell <keith@tungstengraphics.com>
  31  * __FBSDID("$FreeBSD: src/sys/dev/drm/radeon_drm.h,v 1.18 2009/08/23 15:02:58 rnoland Exp $");
  32  */
  33
  34 #ifndef __RADEON_DRM_H__
  35 #define __RADEON_DRM_H__
  36
  37 /* WARNING: If you change any of these defines, make sure to change the
  38  * defines in the X server file (radeon_sarea.h)
  39  */
  40 #ifndef __RADEON_SAREA_DEFINES__
  41 #define __RADEON_SAREA_DEFINES__
  42
  43 /* Old style state flags, required for sarea interface (1.1 and 1.2
  44  * clears) and 1.2 drm_vertex2 ioctl.
  45  */
  46 #define RADEON_UPLOAD_CONTEXT           0x00000001
  47 #define RADEON_UPLOAD_VERTFMT           0x00000002
  48 #define RADEON_UPLOAD_LINE              0x00000004
  49 #define RADEON_UPLOAD_BUMPMAP           0x00000008
  50 #define RADEON_UPLOAD_MASKS             0x00000010
  51 #define RADEON_UPLOAD_VIEWPORT          0x00000020
  52 #define RADEON_UPLOAD_SETUP             0x00000040
  53 #define RADEON_UPLOAD_TCL               0x00000080
  54 #define RADEON_UPLOAD_MISC              0x00000100
  55 #define RADEON_UPLOAD_TEX0              0x00000200
  56 #define RADEON_UPLOAD_TEX1              0x00000400
  57 #define RADEON_UPLOAD_TEX2              0x00000800
  58 #define RADEON_UPLOAD_TEX0IMAGES        0x00001000
  59 #define RADEON_UPLOAD_TEX1IMAGES        0x00002000
  60 #define RADEON_UPLOAD_TEX2IMAGES        0x00004000
  61 #define RADEON_UPLOAD_CLIPRECTS         0x00008000      /* handled client-side */
  62 #define RADEON_REQUIRE_QUIESCENCE       0x00010000
  63 #define RADEON_UPLOAD_ZBIAS             0x00020000      /* version 1.2 and newer */
  64 #define RADEON_UPLOAD_ALL               0x003effff
  65 #define RADEON_UPLOAD_CONTEXT_ALL       0x003e01ff
  66
  67 /* New style per-packet identifiers for use in cmd_buffer ioctl with
  68  * the RADEON_EMIT_PACKET command.  Comments relate new packets to old
  69  * state bits and the packet size:
  70  */
  71 #define RADEON_EMIT_PP_MISC                         0   /* context/7 */
  72 #define RADEON_EMIT_PP_CNTL                         1   /* context/3 */
  73 #define RADEON_EMIT_RB3D_COLORPITCH                 2   /* context/1 */
  74 #define RADEON_EMIT_RE_LINE_PATTERN                 3   /* line/2 */
  75 #define RADEON_EMIT_SE_LINE_WIDTH                   4   /* line/1 */
  76 #define RADEON_EMIT_PP_LUM_MATRIX                   5   /* bumpmap/1 */
  77 #define RADEON_EMIT_PP_ROT_MATRIX_0                 6   /* bumpmap/2 */
  78 #define RADEON_EMIT_RB3D_STENCILREFMASK             7   /* masks/3 */
  79 #define RADEON_EMIT_SE_VPORT_XSCALE                 8   /* viewport/6 */
  80 #define RADEON_EMIT_SE_CNTL                         9   /* setup/2 */
  81 #define RADEON_EMIT_SE_CNTL_STATUS                  10  /* setup/1 */
  82 #define RADEON_EMIT_RE_MISC                         11  /* misc/1 */
  83 #define RADEON_EMIT_PP_TXFILTER_0                   12  /* tex0/6 */
  84 #define RADEON_EMIT_PP_BORDER_COLOR_0               13  /* tex0/1 */
  85 #define RADEON_EMIT_PP_TXFILTER_1                   14  /* tex1/6 */
  86 #define RADEON_EMIT_PP_BORDER_COLOR_1               15  /* tex1/1 */
  87 #define RADEON_EMIT_PP_TXFILTER_2                   16  /* tex2/6 */
  88 #define RADEON_EMIT_PP_BORDER_COLOR_2               17  /* tex2/1 */
  89 #define RADEON_EMIT_SE_ZBIAS_FACTOR                 18  /* zbias/2 */
  90 #define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT           19  /* tcl/11 */
  91 #define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED   20  /* material/17 */
  92 #define R200_EMIT_PP_TXCBLEND_0                     21  /* tex0/4 */
  93 #define R200_EMIT_PP_TXCBLEND_1                     22  /* tex1/4 */
  94 #define R200_EMIT_PP_TXCBLEND_2                     23  /* tex2/4 */
  95 #define R200_EMIT_PP_TXCBLEND_3                     24  /* tex3/4 */
  96 #define R200_EMIT_PP_TXCBLEND_4                     25  /* tex4/4 */
  97 #define R200_EMIT_PP_TXCBLEND_5                     26  /* tex5/4 */
  98 #define R200_EMIT_PP_TXCBLEND_6                     27  /* /4 */
  99 #define R200_EMIT_PP_TXCBLEND_7                     28  /* /4 */
 100 #define R200_EMIT_TCL_LIGHT_MODEL_CTL_0             29  /* tcl/7 */
 101 #define R200_EMIT_TFACTOR_0                         30  /* tf/7 */
 102 #define R200_EMIT_VTX_FMT_0                         31  /* vtx/5 */
 103 #define R200_EMIT_VAP_CTL                           32  /* vap/1 */
 104 #define R200_EMIT_MATRIX_SELECT_0                   33  /* msl/5 */
 105 #define R200_EMIT_TEX_PROC_CTL_2                    34  /* tcg/5 */
 106 #define R200_EMIT_TCL_UCP_VERT_BLEND_CTL            35  /* tcl/1 */
 107 #define R200_EMIT_PP_TXFILTER_0                     36  /* tex0/6 */
 108 #define R200_EMIT_PP_TXFILTER_1                     37  /* tex1/6 */
 109 #define R200_EMIT_PP_TXFILTER_2                     38  /* tex2/6 */
 110 #define R200_EMIT_PP_TXFILTER_3                     39  /* tex3/6 */
 111 #define R200_EMIT_PP_TXFILTER_4                     40  /* tex4/6 */
 112 #define R200_EMIT_PP_TXFILTER_5                     41  /* tex5/6 */
 113 #define R200_EMIT_PP_TXOFFSET_0                     42  /* tex0/1 */
 114 #define R200_EMIT_PP_TXOFFSET_1                     43  /* tex1/1 */
 115 #define R200_EMIT_PP_TXOFFSET_2                     44  /* tex2/1 */
 116 #define R200_EMIT_PP_TXOFFSET_3                     45  /* tex3/1 */
 117 #define R200_EMIT_PP_TXOFFSET_4                     46  /* tex4/1 */
 118 #define R200_EMIT_PP_TXOFFSET_5                     47  /* tex5/1 */
 119 #define R200_EMIT_VTE_CNTL                          48  /* vte/1 */
 120 #define R200_EMIT_OUTPUT_VTX_COMP_SEL               49  /* vtx/1 */
 121 #define R200_EMIT_PP_TAM_DEBUG3                     50  /* tam/1 */
 122 #define R200_EMIT_PP_CNTL_X                         51  /* cst/1 */
 123 #define R200_EMIT_RB3D_DEPTHXY_OFFSET               52  /* cst/1 */
 124 #define R200_EMIT_RE_AUX_SCISSOR_CNTL               53  /* cst/1 */
 125 #define R200_EMIT_RE_SCISSOR_TL_0                   54  /* cst/2 */
 126 #define R200_EMIT_RE_SCISSOR_TL_1                   55  /* cst/2 */
 127 #define R200_EMIT_RE_SCISSOR_TL_2                   56  /* cst/2 */
 128 #define R200_EMIT_SE_VAP_CNTL_STATUS                57  /* cst/1 */
 129 #define R200_EMIT_SE_VTX_STATE_CNTL                 58  /* cst/1 */
 130 #define R200_EMIT_RE_POINTSIZE                      59  /* cst/1 */
 131 #define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0       60  /* cst/4 */
 132 #define R200_EMIT_PP_CUBIC_FACES_0                  61
 133 #define R200_EMIT_PP_CUBIC_OFFSETS_0                62
 134 #define R200_EMIT_PP_CUBIC_FACES_1                  63
 135 #define R200_EMIT_PP_CUBIC_OFFSETS_1                64
 136 #define R200_EMIT_PP_CUBIC_FACES_2                  65
 137 #define R200_EMIT_PP_CUBIC_OFFSETS_2                66
 138 #define R200_EMIT_PP_CUBIC_FACES_3                  67
 139 #define R200_EMIT_PP_CUBIC_OFFSETS_3                68
 140 #define R200_EMIT_PP_CUBIC_FACES_4                  69
 141 #define R200_EMIT_PP_CUBIC_OFFSETS_4                70
 142 #define R200_EMIT_PP_CUBIC_FACES_5                  71
 143 #define R200_EMIT_PP_CUBIC_OFFSETS_5                72
 144 #define RADEON_EMIT_PP_TEX_SIZE_0                   73
 145 #define RADEON_EMIT_PP_TEX_SIZE_1                   74
 146 #define RADEON_EMIT_PP_TEX_SIZE_2                   75
 147 #define R200_EMIT_RB3D_BLENDCOLOR                   76
 148 #define R200_EMIT_TCL_POINT_SPRITE_CNTL             77
 149 #define RADEON_EMIT_PP_CUBIC_FACES_0                78
 150 #define RADEON_EMIT_PP_CUBIC_OFFSETS_T0             79
 151 #define RADEON_EMIT_PP_CUBIC_FACES_1                80
 152 #define RADEON_EMIT_PP_CUBIC_OFFSETS_T1             81
 153 #define RADEON_EMIT_PP_CUBIC_FACES_2                82
 154 #define RADEON_EMIT_PP_CUBIC_OFFSETS_T2             83
 155 #define R200_EMIT_PP_TRI_PERF_CNTL                  84
 156 #define R200_EMIT_PP_AFS_0                          85
 157 #define R200_EMIT_PP_AFS_1                          86
 158 #define R200_EMIT_ATF_TFACTOR                       87
 159 #define R200_EMIT_PP_TXCTLALL_0                     88
 160 #define R200_EMIT_PP_TXCTLALL_1                     89
 161 #define R200_EMIT_PP_TXCTLALL_2                     90
 162 #define R200_EMIT_PP_TXCTLALL_3                     91
 163 #define R200_EMIT_PP_TXCTLALL_4                     92
 164 #define R200_EMIT_PP_TXCTLALL_5                     93
 165 #define R200_EMIT_VAP_PVS_CNTL                      94
 166 #define RADEON_MAX_STATE_PACKETS                    95
 167
 168 /* Commands understood by cmd_buffer ioctl.  More can be added but
 169  * obviously these can't be removed or changed:
 170  */
 171 #define RADEON_CMD_PACKET      1        /* emit one of the register packets above */
 172 #define RADEON_CMD_SCALARS     2        /* emit scalar data */
 173 #define RADEON_CMD_VECTORS     3        /* emit vector data */
 174 #define RADEON_CMD_DMA_DISCARD 4        /* discard current dma buf */
 175 #define RADEON_CMD_PACKET3     5        /* emit hw packet */
 176 #define RADEON_CMD_PACKET3_CLIP 6       /* emit hw packet wrapped in cliprects */
 177 #define RADEON_CMD_SCALARS2     7       /* r200 stopgap */
 178 #define RADEON_CMD_WAIT         8       /* emit hw wait commands -- note:
 179                                          *  doesn't make the cpu wait, just
 180                                          *  the graphics hardware */
 181 #define RADEON_CMD_VECLINEAR    9       /* another r200 stopgap */
 182
 183 typedef union {
 184         int i;
 185         struct {
 186                 unsigned char cmd_type, pad0, pad1, pad2;
 187         } header;
 188         struct {
 189                 unsigned char cmd_type, packet_id, pad0, pad1;
 190         } packet;
 191         struct {
 192                 unsigned char cmd_type, offset, stride, count;
 193         } scalars;
 194         struct {
 195                 unsigned char cmd_type, offset, stride, count;
 196         } vectors;
 197         struct {
 198                 unsigned char cmd_type, addr_lo, addr_hi, count;
 199         } veclinear;
 200         struct {
 201                 unsigned char cmd_type, buf_idx, pad0, pad1;
 202         } dma;
 203         struct {
 204                 unsigned char cmd_type, flags, pad0, pad1;
 205         } wait;
 206 } drm_radeon_cmd_header_t;
 207
 208 #define RADEON_WAIT_2D  0x1
 209 #define RADEON_WAIT_3D  0x2
 210
 211 /* Allowed parameters for R300_CMD_PACKET3
 212  */
 213 #define R300_CMD_PACKET3_CLEAR          0
 214 #define R300_CMD_PACKET3_RAW            1
 215
 216 /* Commands understood by cmd_buffer ioctl for R300.
 217  * The interface has not been stabilized, so some of these may be removed
 218  * and eventually reordered before stabilization.
 219  */
 220 #define R300_CMD_PACKET0                1
 221 #define R300_CMD_VPU                    2       /* emit vertex program upload */
 222 #define R300_CMD_PACKET3                3       /* emit a packet3 */
 223 #define R300_CMD_END3D                  4       /* emit sequence ending 3d rendering */
 224 #define R300_CMD_CP_DELAY               5
 225 #define R300_CMD_DMA_DISCARD            6
 226 #define R300_CMD_WAIT                   7
 227 #       define R300_WAIT_2D             0x1
 228 #       define R300_WAIT_3D             0x2
 229 /* these two defines are DOING IT WRONG - however
 230  * we have userspace which relies on using these.
 231  * The wait interface is backwards compat new
 232  * code should use the NEW_WAIT defines below
 233  * THESE ARE NOT BIT FIELDS
 234  */
 235 #       define R300_WAIT_2D_CLEAN       0x3
 236 #       define R300_WAIT_3D_CLEAN       0x4
 237
 238 #       define R300_NEW_WAIT_2D_3D      0x3
 239 #       define R300_NEW_WAIT_2D_2D_CLEAN        0x4
 240 #       define R300_NEW_WAIT_3D_3D_CLEAN        0x6
 241 #       define R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN    0x8
 242
 243 #define R300_CMD_SCRATCH                8
 244 #define R300_CMD_R500FP                 9
 245
 246 typedef union {
 247         unsigned int u;
 248         struct {
 249                 unsigned char cmd_type, pad0, pad1, pad2;
 250         } header;
 251         struct {
 252                 unsigned char cmd_type, count, reglo, reghi;
 253         } packet0;
 254         struct {
 255                 unsigned char cmd_type, count, adrlo, adrhi;
 256         } vpu;
 257         struct {
 258                 unsigned char cmd_type, packet, pad0, pad1;
 259         } packet3;
 260         struct {
 261                 unsigned char cmd_type, packet;
 262                 unsigned short count;   /* amount of packet2 to emit */
 263         } delay;
 264         struct {
 265                 unsigned char cmd_type, buf_idx, pad0, pad1;
 266         } dma;
 267         struct {
 268                 unsigned char cmd_type, flags, pad0, pad1;
 269         } wait;
 270         struct {
 271                 unsigned char cmd_type, reg, n_bufs, flags;
 272         } scratch;
 273         struct {
 274                 unsigned char cmd_type, count, adrlo, adrhi_flags;
 275         } r500fp;
 276 } drm_r300_cmd_header_t;
 277
 278 #define RADEON_FRONT                    0x1
 279 #define RADEON_BACK                     0x2
 280 #define RADEON_DEPTH                    0x4
 281 #define RADEON_STENCIL                  0x8
 282 #define RADEON_CLEAR_FASTZ              0x80000000
 283 #define RADEON_USE_HIERZ                0x40000000
 284 #define RADEON_USE_COMP_ZBUF            0x20000000
 285
 286 #define R500FP_CONSTANT_TYPE  (1 << 1)
 287 #define R500FP_CONSTANT_CLAMP (1 << 2)
 288
 289 /* Primitive types
 290  */
 291 #define RADEON_POINTS                   0x1
 292 #define RADEON_LINES                    0x2
 293 #define RADEON_LINE_STRIP               0x3
 294 #define RADEON_TRIANGLES                0x4
 295 #define RADEON_TRIANGLE_FAN             0x5
 296 #define RADEON_TRIANGLE_STRIP           0x6
 297
 298 /* Vertex/indirect buffer size
 299  */
 300 #define RADEON_BUFFER_SIZE              65536
 301
 302 /* Byte offsets for indirect buffer data
 303  */
 304 #define RADEON_INDEX_PRIM_OFFSET        20
 305
 306 #define RADEON_SCRATCH_REG_OFFSET       32
 307 #define R600_SCRATCH_REG_OFFSET         256
 308
 309 #define RADEON_NR_SAREA_CLIPRECTS       12
 310
 311 /* There are 2 heaps (local/GART).  Each region within a heap is a
 312  * minimum of 64k, and there are at most 64 of them per heap.
 313  */
 314 #define RADEON_LOCAL_TEX_HEAP           0
 315 #define RADEON_GART_TEX_HEAP            1
 316 #define RADEON_NR_TEX_HEAPS             2
 317 #define RADEON_NR_TEX_REGIONS           64
 318 #define RADEON_LOG_TEX_GRANULARITY      16
 319
 320 #define RADEON_MAX_TEXTURE_LEVELS       12
 321 #define RADEON_MAX_TEXTURE_UNITS        3
 322
 323 #define RADEON_MAX_SURFACES             8
 324
 325 /* Blits have strict offset rules.  All blit offset must be aligned on
 326  * a 1K-byte boundary.
 327  */
 328 #define RADEON_OFFSET_SHIFT             10
 329 #define RADEON_OFFSET_ALIGN             (1 << RADEON_OFFSET_SHIFT)
 330 #define RADEON_OFFSET_MASK              (RADEON_OFFSET_ALIGN - 1)
 331
 332 #endif                          /* __RADEON_SAREA_DEFINES__ */
 333
 334 typedef struct {
 335         unsigned int red;
 336         unsigned int green;
 337         unsigned int blue;
 338         unsigned int alpha;
 339 } radeon_color_regs_t;
 340
 341 typedef struct {
 342         /* Context state */
 343         unsigned int pp_misc;   /* 0x1c14 */
 344         unsigned int pp_fog_color;
 345         unsigned int re_solid_color;
 346         unsigned int rb3d_blendcntl;
 347         unsigned int rb3d_depthoffset;
 348         unsigned int rb3d_depthpitch;
 349         unsigned int rb3d_zstencilcntl;
 350
 351         unsigned int pp_cntl;   /* 0x1c38 */
 352         unsigned int rb3d_cntl;
 353         unsigned int rb3d_coloroffset;
 354         unsigned int re_width_height;
 355         unsigned int rb3d_colorpitch;
 356         unsigned int se_cntl;
 357
 358         /* Vertex format state */
 359         unsigned int se_coord_fmt;      /* 0x1c50 */
 360
 361         /* Line state */
 362         unsigned int re_line_pattern;   /* 0x1cd0 */
 363         unsigned int re_line_state;
 364
 365         unsigned int se_line_width;     /* 0x1db8 */
 366
 367         /* Bumpmap state */
 368         unsigned int pp_lum_matrix;     /* 0x1d00 */
 369
 370         unsigned int pp_rot_matrix_0;   /* 0x1d58 */
 371         unsigned int pp_rot_matrix_1;
 372
 373         /* Mask state */
 374         unsigned int rb3d_stencilrefmask;       /* 0x1d7c */
 375         unsigned int rb3d_ropcntl;
 376         unsigned int rb3d_planemask;
 377
 378         /* Viewport state */
 379         unsigned int se_vport_xscale;   /* 0x1d98 */
 380         unsigned int se_vport_xoffset;
 381         unsigned int se_vport_yscale;
 382         unsigned int se_vport_yoffset;
 383         unsigned int se_vport_zscale;
 384         unsigned int se_vport_zoffset;
 385
 386         /* Setup state */
 387         unsigned int se_cntl_status;    /* 0x2140 */
 388
 389         /* Misc state */
 390         unsigned int re_top_left;       /* 0x26c0 */
 391         unsigned int re_misc;
 392 } drm_radeon_context_regs_t;
 393
 394 typedef struct {
 395         /* Zbias state */
 396         unsigned int se_zbias_factor;   /* 0x1dac */
 397         unsigned int se_zbias_constant;
 398 } drm_radeon_context2_regs_t;
 399
 400 /* Setup registers for each texture unit
 401  */
 402 typedef struct {
 403         unsigned int pp_txfilter;
 404         unsigned int pp_txformat;
 405         unsigned int pp_txoffset;
 406         unsigned int pp_txcblend;
 407         unsigned int pp_txablend;
 408         unsigned int pp_tfactor;
 409         unsigned int pp_border_color;
 410 } drm_radeon_texture_regs_t;
 411
 412 typedef struct {
 413         unsigned int start;
 414         unsigned int finish;
 415         unsigned int prim:8;
 416         unsigned int stateidx:8;
 417         unsigned int numverts:16;       /* overloaded as offset/64 for elt prims */
 418         unsigned int vc_format; /* vertex format */
 419 } drm_radeon_prim_t;
 420
 421 typedef struct {
 422         drm_radeon_context_regs_t context;
 423         drm_radeon_texture_regs_t tex[RADEON_MAX_TEXTURE_UNITS];
 424         drm_radeon_context2_regs_t context2;
 425         unsigned int dirty;
 426 } drm_radeon_state_t;
 427
 428 typedef struct {
 429         /* The channel for communication of state information to the
 430          * kernel on firing a vertex buffer with either of the
 431          * obsoleted vertex/index ioctls.
 432          */
 433         drm_radeon_context_regs_t context_state;
 434         drm_radeon_texture_regs_t tex_state[RADEON_MAX_TEXTURE_UNITS];
 435         unsigned int dirty;
 436         unsigned int vertsize;
 437         unsigned int vc_format;
 438
 439         /* The current cliprects, or a subset thereof.
 440          */
 441         struct drm_clip_rect boxes[RADEON_NR_SAREA_CLIPRECTS];
 442         unsigned int nbox;
 443
 444         /* Counters for client-side throttling of rendering clients.
 445          */
 446         unsigned int last_frame;
 447         unsigned int last_dispatch;
 448         unsigned int last_clear;
 449
 450         struct drm_tex_region tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS +
 451                                                        1];
 452         unsigned int tex_age[RADEON_NR_TEX_HEAPS];
 453         int ctx_owner;
 454         int pfState;            /* number of 3d windows (0,1,2ormore) */
 455         int pfCurrentPage;      /* which buffer is being displayed? */
 456         int crtc2_base;         /* CRTC2 frame offset */
 457         int tiling_enabled;     /* set by drm, read by 2d + 3d clients */
 458 } drm_radeon_sarea_t;
 459
 460 /* WARNING: If you change any of these defines, make sure to change the
 461  * defines in the Xserver file (xf86drmRadeon.h)
 462  *
 463  * KW: actually it's illegal to change any of this (backwards compatibility).
 464  */
 465
 466 /* Radeon specific ioctls
 467  * The device specific ioctl range is 0x40 to 0x79.
 468  */
 469 #define DRM_RADEON_CP_INIT    0x00
 470 #define DRM_RADEON_CP_START   0x01
 471 #define DRM_RADEON_CP_STOP    0x02
 472 #define DRM_RADEON_CP_RESET   0x03
 473 #define DRM_RADEON_CP_IDLE    0x04
 474 #define DRM_RADEON_RESET      0x05
 475 #define DRM_RADEON_FULLSCREEN 0x06
 476 #define DRM_RADEON_SWAP       0x07
 477 #define DRM_RADEON_CLEAR      0x08
 478 #define DRM_RADEON_VERTEX     0x09
 479 #define DRM_RADEON_INDICES    0x0A
 480 #define DRM_RADEON_NOT_USED
 481 #define DRM_RADEON_STIPPLE    0x0C
 482 #define DRM_RADEON_INDIRECT   0x0D
 483 #define DRM_RADEON_TEXTURE    0x0E
 484 #define DRM_RADEON_VERTEX2    0x0F
 485 #define DRM_RADEON_CMDBUF     0x10
 486 #define DRM_RADEON_GETPARAM   0x11
 487 #define DRM_RADEON_FLIP       0x12
 488 #define DRM_RADEON_ALLOC      0x13
 489 #define DRM_RADEON_FREE       0x14
 490 #define DRM_RADEON_INIT_HEAP  0x15
 491 #define DRM_RADEON_IRQ_EMIT   0x16
 492 #define DRM_RADEON_IRQ_WAIT   0x17
 493 #define DRM_RADEON_CP_RESUME  0x18
 494 #define DRM_RADEON_SETPARAM   0x19
 495 #define DRM_RADEON_SURF_ALLOC 0x1a
 496 #define DRM_RADEON_SURF_FREE  0x1b
 497
 498 #define DRM_RADEON_CS         0x26
 499
 500 #define DRM_IOCTL_RADEON_CP_INIT    DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t)
 501 #define DRM_IOCTL_RADEON_CP_START   DRM_IO(  DRM_COMMAND_BASE + DRM_RADEON_CP_START)
 502 #define DRM_IOCTL_RADEON_CP_STOP    DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t)
 503 #define DRM_IOCTL_RADEON_CP_RESET   DRM_IO(  DRM_COMMAND_BASE + DRM_RADEON_CP_RESET)
 504 #define DRM_IOCTL_RADEON_CP_IDLE    DRM_IO(  DRM_COMMAND_BASE + DRM_RADEON_CP_IDLE)
 505 #define DRM_IOCTL_RADEON_RESET      DRM_IO(  DRM_COMMAND_BASE + DRM_RADEON_RESET)
 506 #define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FULLSCREEN, drm_radeon_fullscreen_t)
 507 #define DRM_IOCTL_RADEON_SWAP       DRM_IO(  DRM_COMMAND_BASE + DRM_RADEON_SWAP)
 508 #define DRM_IOCTL_RADEON_CLEAR      DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CLEAR, drm_radeon_clear_t)
 509 #define DRM_IOCTL_RADEON_VERTEX     DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX, drm_radeon_vertex_t)
 510 #define DRM_IOCTL_RADEON_INDICES    DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INDICES, drm_radeon_indices_t)
 511 #define DRM_IOCTL_RADEON_STIPPLE    DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_STIPPLE, drm_radeon_stipple_t)
 512 #define DRM_IOCTL_RADEON_INDIRECT   DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INDIRECT, drm_radeon_indirect_t)
 513 #define DRM_IOCTL_RADEON_TEXTURE    DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_TEXTURE, drm_radeon_texture_t)
 514 #define DRM_IOCTL_RADEON_VERTEX2    DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX2, drm_radeon_vertex2_t)
 515 #define DRM_IOCTL_RADEON_CMDBUF     DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CMDBUF, drm_radeon_cmd_buffer_t)
 516 #define DRM_IOCTL_RADEON_GETPARAM   DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GETPARAM, drm_radeon_getparam_t)
 517 #define DRM_IOCTL_RADEON_FLIP       DRM_IO(  DRM_COMMAND_BASE + DRM_RADEON_FLIP)
 518 #define DRM_IOCTL_RADEON_ALLOC      DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_ALLOC, drm_radeon_mem_alloc_t)
 519 #define DRM_IOCTL_RADEON_FREE       DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FREE, drm_radeon_mem_free_t)
 520 #define DRM_IOCTL_RADEON_INIT_HEAP  DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INIT_HEAP, drm_radeon_mem_init_heap_t)
 521 #define DRM_IOCTL_RADEON_IRQ_EMIT   DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_IRQ_EMIT, drm_radeon_irq_emit_t)
 522 #define DRM_IOCTL_RADEON_IRQ_WAIT   DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_IRQ_WAIT, drm_radeon_irq_wait_t)
 523 #define DRM_IOCTL_RADEON_CP_RESUME  DRM_IO(  DRM_COMMAND_BASE + DRM_RADEON_CP_RESUME)
 524 #define DRM_IOCTL_RADEON_SETPARAM   DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, drm_radeon_setparam_t)
 525 #define DRM_IOCTL_RADEON_SURF_ALLOC DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_ALLOC, drm_radeon_surface_alloc_t)
 526 #define DRM_IOCTL_RADEON_SURF_FREE  DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_FREE, drm_radeon_surface_free_t)
 527 #define DRM_IOCTL_RADEON_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_CS, struct drm_radeon_cs)
 528
 529 typedef struct drm_radeon_init {
 530         enum {
 531                 RADEON_INIT_CP = 0x01,
 532                 RADEON_CLEANUP_CP = 0x02,
 533                 RADEON_INIT_R200_CP = 0x03,
 534                 RADEON_INIT_R300_CP = 0x04,
 535                 RADEON_INIT_R600_CP = 0x05,
 536         } func;
 537         unsigned long sarea_priv_offset;
 538         int is_pci; /* for overriding only */
 539         int cp_mode;
 540         int gart_size;
 541         int ring_size;
 542         int usec_timeout;
 543
 544         unsigned int fb_bpp;
 545         unsigned int front_offset, front_pitch;
 546         unsigned int back_offset, back_pitch;
 547         unsigned int depth_bpp;
 548         unsigned int depth_offset, depth_pitch;
 549
 550         unsigned long fb_offset DEPRECATED;     /* deprecated, driver asks hardware */
 551         unsigned long mmio_offset DEPRECATED;   /* deprecated, driver asks hardware */
 552         unsigned long ring_offset;
 553         unsigned long ring_rptr_offset;
 554         unsigned long buffers_offset;
 555         unsigned long gart_textures_offset;
 556 } drm_radeon_init_t;
 557
 558 typedef struct drm_radeon_cp_stop {
 559         int flush;
 560         int idle;
 561 } drm_radeon_cp_stop_t;
 562
 563 typedef struct drm_radeon_fullscreen {
 564         enum {
 565                 RADEON_INIT_FULLSCREEN = 0x01,
 566                 RADEON_CLEANUP_FULLSCREEN = 0x02
 567         } func;
 568 } drm_radeon_fullscreen_t;
 569
 570 #define CLEAR_X1        0
 571 #define CLEAR_Y1        1
 572 #define CLEAR_X2        2
 573 #define CLEAR_Y2        3
 574 #define CLEAR_DEPTH     4
 575
 576 typedef union drm_radeon_clear_rect {
 577         float f[5];
 578         unsigned int ui[5];
 579 } drm_radeon_clear_rect_t;
 580
 581 typedef struct drm_radeon_clear {
 582         unsigned int flags;
 583         unsigned int clear_color;
 584         unsigned int clear_depth;
 585         unsigned int color_mask;
 586         unsigned int depth_mask;        /* misnamed field:  should be stencil */
 587         drm_radeon_clear_rect_t __user *depth_boxes;
 588 } drm_radeon_clear_t;
 589
 590 typedef struct drm_radeon_vertex {
 591         int prim;
 592         int idx;                /* Index of vertex buffer */
 593         int count;              /* Number of vertices in buffer */
 594         int discard;            /* Client finished with buffer? */
 595 } drm_radeon_vertex_t;
 596
 597 typedef struct drm_radeon_indices {
 598         int prim;
 599         int idx;
 600         int start;
 601         int end;
 602         int discard;            /* Client finished with buffer? */
 603 } drm_radeon_indices_t;
 604
 605 /* v1.2 - obsoletes drm_radeon_vertex and drm_radeon_indices
 606  *      - allows multiple primitives and state changes in a single ioctl
 607  *      - supports driver change to emit native primitives
 608  */
 609 typedef struct drm_radeon_vertex2 {
 610         int idx;                /* Index of vertex buffer */
 611         int discard;            /* Client finished with buffer? */
 612         int nr_states;
 613         drm_radeon_state_t __user *state;
 614         int nr_prims;
 615         drm_radeon_prim_t __user *prim;
 616 } drm_radeon_vertex2_t;
 617
 618 /* v1.3 - obsoletes drm_radeon_vertex2
 619  *      - allows arbitarily large cliprect list
 620  *      - allows updating of tcl packet, vector and scalar state
 621  *      - allows memory-efficient description of state updates
 622  *      - allows state to be emitted without a primitive
 623  *           (for clears, ctx switches)
 624  *      - allows more than one dma buffer to be referenced per ioctl
 625  *      - supports tcl driver
 626  *      - may be extended in future versions with new cmd types, packets
 627  */
 628 typedef struct drm_radeon_cmd_buffer {
 629         int bufsz;
 630         char __user *buf;
 631         int nbox;
 632         struct drm_clip_rect __user *boxes;
 633 } drm_radeon_cmd_buffer_t;
 634
 635 typedef struct drm_radeon_tex_image {
 636         unsigned int x, y;      /* Blit coordinates */
 637         unsigned int width, height;
 638         const void __user *data;
 639 } drm_radeon_tex_image_t;
 640
 641 typedef struct drm_radeon_texture {
 642         unsigned int offset;
 643         int pitch;
 644         int format;
 645         int width;              /* Texture image coordinates */
 646         int height;
 647         drm_radeon_tex_image_t __user *image;
 648 } drm_radeon_texture_t;
 649
 650 typedef struct drm_radeon_stipple {
 651         unsigned int __user *mask;
 652 } drm_radeon_stipple_t;
 653
 654 typedef struct drm_radeon_indirect {
 655         int idx;
 656         int start;
 657         int end;
 658         int discard;
 659 } drm_radeon_indirect_t;
 660
 661 #define RADEON_INDIRECT_DISCARD (1 << 0)
 662 #define RADEON_INDIRECT_NOFLUSH (1 << 1)
 663
 664 /* enum for card type parameters */
 665 #define RADEON_CARD_PCI 0
 666 #define RADEON_CARD_AGP 1
 667 #define RADEON_CARD_PCIE 2
 668
 669 /* 1.3: An ioctl to get parameters that aren't available to the 3d
 670  * client any other way.
 671  */
 672 #define RADEON_PARAM_GART_BUFFER_OFFSET    1    /* card offset of 1st GART buffer */
 673 #define RADEON_PARAM_LAST_FRAME            2
 674 #define RADEON_PARAM_LAST_DISPATCH         3
 675 #define RADEON_PARAM_LAST_CLEAR            4
 676 /* Added with DRM version 1.6. */
 677 #define RADEON_PARAM_IRQ_NR                5
 678 #define RADEON_PARAM_GART_BASE             6    /* card offset of GART base */
 679 /* Added with DRM version 1.8. */
 680 #define RADEON_PARAM_REGISTER_HANDLE       7    /* for drmMap() */
 681 #define RADEON_PARAM_STATUS_HANDLE         8
 682 #define RADEON_PARAM_SAREA_HANDLE          9
 683 #define RADEON_PARAM_GART_TEX_HANDLE       10
 684 #define RADEON_PARAM_SCRATCH_OFFSET        11
 685 #define RADEON_PARAM_CARD_TYPE             12
 686 #define RADEON_PARAM_VBLANK_CRTC           13   /* VBLANK CRTC */
 687 #define RADEON_PARAM_FB_LOCATION           14   /* FB location */
 688 #define RADEON_PARAM_NUM_GB_PIPES          15   /* num GB pipes */
 689 #define RADEON_PARAM_DEVICE_ID             16
 690 #define RADEON_PARAM_NUM_Z_PIPES           17   /* num Z pipes */
 691
 692 typedef struct drm_radeon_getparam {
 693         int param;
 694         void __user *value;
 695 } drm_radeon_getparam_t;
 696
 697 /* 1.6: Set up a memory manager for regions of shared memory:
 698  */
 699 #define RADEON_MEM_REGION_GART 1
 700 #define RADEON_MEM_REGION_FB   2
 701
 702 typedef struct drm_radeon_mem_alloc {
 703         int region;
 704         int alignment;
 705         int size;
 706         int __user *region_offset;      /* offset from start of fb or GART */
 707 } drm_radeon_mem_alloc_t;
 708
 709 typedef struct drm_radeon_mem_free {
 710         int region;
 711         int region_offset;
 712 } drm_radeon_mem_free_t;
 713
 714 typedef struct drm_radeon_mem_init_heap {
 715         int region;
 716         int size;
 717         int start;
 718 } drm_radeon_mem_init_heap_t;
 719
 720 /* 1.6: Userspace can request & wait on irq's:
 721  */
 722 typedef struct drm_radeon_irq_emit {
 723         int __user *irq_seq;
 724 } drm_radeon_irq_emit_t;
 725
 726 typedef struct drm_radeon_irq_wait {
 727         int irq_seq;
 728 } drm_radeon_irq_wait_t;
 729
 730 /* 1.10: Clients tell the DRM where they think the framebuffer is located in
 731  * the card's address space, via a new generic ioctl to set parameters
 732  */
 733
 734 typedef struct drm_radeon_setparam {
 735         unsigned int param;
 736         int64_t value;
 737 } drm_radeon_setparam_t;
 738
 739 #define RADEON_SETPARAM_FB_LOCATION    1        /* determined framebuffer location */
 740 #define RADEON_SETPARAM_SWITCH_TILING  2        /* enable/disable color tiling */
 741 #define RADEON_SETPARAM_PCIGART_LOCATION 3      /* PCI Gart Location */
 742
 743 #define RADEON_SETPARAM_NEW_MEMMAP 4            /* Use new memory map */
 744 #define RADEON_SETPARAM_PCIGART_TABLE_SIZE 5    /* PCI GART Table Size */
 745 #define RADEON_SETPARAM_VBLANK_CRTC 6           /* VBLANK CRTC */
 746 /* 1.14: Clients can allocate/free a surface
 747  */
 748 typedef struct drm_radeon_surface_alloc {
 749         unsigned int address;
 750         unsigned int size;
 751         unsigned int flags;
 752 } drm_radeon_surface_alloc_t;
 753
 754 typedef struct drm_radeon_surface_free {
 755         unsigned int address;
 756 } drm_radeon_surface_free_t;
 757
 758 #define DRM_RADEON_VBLANK_CRTC1         1
 759 #define DRM_RADEON_VBLANK_CRTC2         2
 760
 761 /* New interface which obsolete all previous interface.
 762  */
 763 #define RADEON_CHUNK_ID_RELOCS 0x01
 764 #define RADEON_CHUNK_ID_IB     0x02
 765 #define RADEON_CHUNK_ID_OLD 0xff
 766
 767 struct drm_radeon_cs_chunk {
 768         uint32_t chunk_id;
 769         uint32_t length_dw;
 770         uint64_t chunk_data;
 771 };
 772
 773 struct drm_radeon_cs {
 774         uint32_t        num_chunks;
 775         uint32_t        cs_id;
 776         uint64_t        chunks; /* this points to uint64_t * which point to
 777                                    cs chunks */
 778 };
 779
 780 #endif