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Recognize the cpu ident for additional VIA processors.
[dragonfly.git] / sys / i386 / i386 / identcpu.c
blobdd9ef4117e02cb7aa267a1408c629b205c984365
1 /*
2 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
3 * Copyright (c) 1992 Terrence R. Lambert.
4 * Copyright (c) 1997 KATO Takenori.
5 * Copyright (c) 2001 Tamotsu Hattori.
6 * Copyright (c) 2001 Mitsuru IWASAKI.
7 * All rights reserved.
8 *
9 * This code is derived from software contributed to Berkeley by
10 * William Jolitz.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 * 3. All advertising materials mentioning features or use of this software
21 * must display the following acknowledgement:
22 * This product includes software developed by the University of
23 * California, Berkeley and its contributors.
24 * 4. Neither the name of the University nor the names of its contributors
25 * may be used to endorse or promote products derived from this software
26 * without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38 * SUCH DAMAGE.
39 *
40 * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
41 * $FreeBSD: src/sys/i386/i386/identcpu.c,v 1.80.2.15 2003/04/11 17:06:41 jhb Exp $
42 * $DragonFly: src/sys/i386/i386/Attic/identcpu.c,v 1.10 2006/05/11 16:44:43 dillon Exp $
43 */
44
45 #include "opt_cpu.h"
46
47 #include <sys/param.h>
48 #include <sys/systm.h>
49 #include <sys/kernel.h>
50 #include <sys/sysctl.h>
51 #include <sys/lock.h>
52
53 #include <machine/asmacros.h>
54 #include <machine/clock.h>
55 #include <machine/cputypes.h>
56 #include <machine/segments.h>
57 #include <machine/specialreg.h>
58 #include <machine/md_var.h>
59
60 #include <i386/isa/intr_machdep.h>
61
62 #define IDENTBLUE_CYRIX486 0
63 #define IDENTBLUE_IBMCPU 1
64 #define IDENTBLUE_CYRIXM2 2
65
66 /* XXX - should be in header file: */
67 void printcpuinfo(void);
68 void finishidentcpu(void);
69 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
70 void enable_K5_wt_alloc(void);
71 void enable_K6_wt_alloc(void);
72 void enable_K6_2_wt_alloc(void);
73 #endif
74 void panicifcpuunsupported(void);
75
76 static void identifycyrix(void);
77 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
78 static void print_AMD_features(void);
79 #endif
80 static void print_AMD_info(void);
81 static void print_AMD_assoc(int i);
82 static void print_transmeta_info(void);
83 static void setup_tmx86_longrun(void);
84
85 int cpu_class = CPUCLASS_386;
86 u_int cpu_exthigh; /* Highest arg to extended CPUID */
87 u_int cyrix_did; /* Device ID of Cyrix CPU */
88 char machine[] = "i386";
89 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
90 machine, 0, "Machine class");
91
92 static char cpu_model[128];
93 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD,
94 cpu_model, 0, "Machine model");
95
96 static char cpu_brand[48];
97
98 #define MAX_ADDITIONAL_INFO 16
99
100 static const char *additional_cpu_info_ary[MAX_ADDITIONAL_INFO];
101 static u_int additional_cpu_info_count;
102
103 #define MAX_BRAND_INDEX 8
104
105 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
106 NULL, /* No brand */
107 "Intel Celeron",
108 "Intel Pentium III",
109 "Intel Pentium III Xeon",
110 NULL,
111 NULL,
112 NULL,
113 NULL,
114 "Intel Pentium 4"
115 };
116
117 static struct cpu_nameclass i386_cpus[] = {
118 { "Intel 80286", CPUCLASS_286 }, /* CPU_286 */
119 { "i386SX", CPUCLASS_386 }, /* CPU_386SX */
120 { "i386DX", CPUCLASS_386 }, /* CPU_386 */
121 { "i486SX", CPUCLASS_486 }, /* CPU_486SX */
122 { "i486DX", CPUCLASS_486 }, /* CPU_486 */
123 { "Pentium", CPUCLASS_586 }, /* CPU_586 */
124 { "Cyrix 486", CPUCLASS_486 }, /* CPU_486DLC */
125 { "Pentium Pro", CPUCLASS_686 }, /* CPU_686 */
126 { "Cyrix 5x86", CPUCLASS_486 }, /* CPU_M1SC */
127 { "Cyrix 6x86", CPUCLASS_486 }, /* CPU_M1 */
128 { "Blue Lightning", CPUCLASS_486 }, /* CPU_BLUE */
129 { "Cyrix 6x86MX", CPUCLASS_686 }, /* CPU_M2 */
130 { "NexGen 586", CPUCLASS_386 }, /* CPU_NX586 (XXX) */
131 { "Cyrix 486S/DX", CPUCLASS_486 }, /* CPU_CY486DX */
132 { "Pentium II", CPUCLASS_686 }, /* CPU_PII */
133 { "Pentium III", CPUCLASS_686 }, /* CPU_PIII */
134 { "Pentium 4", CPUCLASS_686 }, /* CPU_P4 */
135 };
136
137 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
138 int has_f00f_bug = 0; /* Initialized so that it can be patched. */
139 #endif
140
141 void
142 printcpuinfo(void)
143 {
144 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
145 u_int regs[4], i;
146 #endif
147 char *brand;
148
149 cpu_class = i386_cpus[cpu].cpu_class;
150 printf("CPU: ");
151 strncpy(cpu_model, i386_cpus[cpu].cpu_name, sizeof (cpu_model));
152
153 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
154 /* Check for extended CPUID information and a processor name. */
155 if (cpu_high > 0 &&
156 (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
157 strcmp(cpu_vendor, "AuthenticAMD") == 0 ||
158 strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
159 strcmp(cpu_vendor, "TransmetaCPU") == 0)) {
160 do_cpuid(0x80000000, regs);
161 if (regs[0] >= 0x80000000) {
162 cpu_exthigh = regs[0];
163 if (cpu_exthigh >= 0x80000004) {
164 brand = cpu_brand;
165 for (i = 0x80000002; i < 0x80000005; i++) {
166 do_cpuid(i, regs);
167 memcpy(brand, regs, sizeof(regs));
168 brand += sizeof(regs);
169 }
170 }
171 }
172 }
173
174 if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
175 if ((cpu_id & 0xf00) > 0x300) {
176 u_int brand_index;
177
178 cpu_model[0] = '\0';
179
180 switch (cpu_id & 0x3000) {
181 case 0x1000:
182 strcpy(cpu_model, "Overdrive ");
183 break;
184 case 0x2000:
185 strcpy(cpu_model, "Dual ");
186 break;
187 }
188
189 switch (cpu_id & 0xf00) {
190 case 0x400:
191 strcat(cpu_model, "i486 ");
192 /* Check the particular flavor of 486 */
193 switch (cpu_id & 0xf0) {
194 case 0x00:
195 case 0x10:
196 strcat(cpu_model, "DX");
197 break;
198 case 0x20:
199 strcat(cpu_model, "SX");
200 break;
201 case 0x30:
202 strcat(cpu_model, "DX2");
203 break;
204 case 0x40:
205 strcat(cpu_model, "SL");
206 break;
207 case 0x50:
208 strcat(cpu_model, "SX2");
209 break;
210 case 0x70:
211 strcat(cpu_model,
212 "DX2 Write-Back Enhanced");
213 break;
214 case 0x80:
215 strcat(cpu_model, "DX4");
216 break;
217 }
218 break;
219 case 0x500:
220 /* Check the particular flavor of 586 */
221 strcat(cpu_model, "Pentium");
222 switch (cpu_id & 0xf0) {
223 case 0x00:
224 strcat(cpu_model, " A-step");
225 break;
226 case 0x10:
227 strcat(cpu_model, "/P5");
228 break;
229 case 0x20:
230 strcat(cpu_model, "/P54C");
231 break;
232 case 0x30:
233 strcat(cpu_model, "/P54T Overdrive");
234 break;
235 case 0x40:
236 strcat(cpu_model, "/P55C");
237 break;
238 case 0x70:
239 strcat(cpu_model, "/P54C");
240 break;
241 case 0x80:
242 strcat(cpu_model, "/P55C (quarter-micron)");
243 break;
244 default:
245 /* nothing */
246 break;
247 }
248 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
249 /*
250 * XXX - If/when Intel fixes the bug, this
251 * should also check the version of the
252 * CPU, not just that it's a Pentium.
253 */
254 has_f00f_bug = 1;
255 #endif
256 break;
257 case 0x600:
258 /* Check the particular flavor of 686 */
259 switch (cpu_id & 0xf0) {
260 case 0x00:
261 strcat(cpu_model, "Pentium Pro A-step");
262 break;
263 case 0x10:
264 strcat(cpu_model, "Pentium Pro");
265 break;
266 case 0x30:
267 case 0x50:
268 case 0x60:
269 strcat(cpu_model,
270 "Pentium II/Pentium II Xeon/Celeron");
271 cpu = CPU_PII;
272 break;
273 case 0x70:
274 case 0x80:
275 case 0xa0:
276 case 0xb0:
277 strcat(cpu_model,
278 "Pentium III/Pentium III Xeon/Celeron");
279 cpu = CPU_PIII;
280 break;
281 default:
282 strcat(cpu_model, "Unknown 80686");
283 break;
284 }
285 break;
286 case 0xf00:
287 strcat(cpu_model, "Pentium 4");
288 cpu = CPU_P4;
289 break;
290 default:
291 strcat(cpu_model, "unknown");
292 break;
293 }
294
295 /*
296 * If we didn't get a brand name from the extended
297 * CPUID, try to look it up in the brand table.
298 */
299 if (cpu_high > 0 && *cpu_brand == '\0') {
300 brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
301 if (brand_index <= MAX_BRAND_INDEX &&
302 cpu_brandtable[brand_index] != NULL)
303 strcpy(cpu_brand,
304 cpu_brandtable[brand_index]);
305 }
306 }
307 } else if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
308 /*
309 * Values taken from AMD Processor Recognition
310 * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
311 * (also describes ``Features'' encodings.
312 */
313 strcpy(cpu_model, "AMD ");
314 switch (cpu_id & 0xFF0) {
315 case 0x410:
316 strcat(cpu_model, "Standard Am486DX");
317 break;
318 case 0x430:
319 strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
320 break;
321 case 0x470:
322 strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
323 break;
324 case 0x480:
325 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
326 break;
327 case 0x490:
328 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
329 break;
330 case 0x4E0:
331 strcat(cpu_model, "Am5x86 Write-Through");
332 break;
333 case 0x4F0:
334 strcat(cpu_model, "Am5x86 Write-Back");
335 break;
336 case 0x500:
337 strcat(cpu_model, "K5 model 0");
338 tsc_is_broken = 1;
339 break;
340 case 0x510:
341 strcat(cpu_model, "K5 model 1");
342 break;
343 case 0x520:
344 strcat(cpu_model, "K5 PR166 (model 2)");
345 break;
346 case 0x530:
347 strcat(cpu_model, "K5 PR200 (model 3)");
348 break;
349 case 0x560:
350 strcat(cpu_model, "K6");
351 break;
352 case 0x570:
353 strcat(cpu_model, "K6 266 (model 1)");
354 break;
355 case 0x580:
356 strcat(cpu_model, "K6-2");
357 break;
358 case 0x590:
359 strcat(cpu_model, "K6-III");
360 break;
361 default:
362 strcat(cpu_model, "Unknown");
363 break;
364 }
365 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
366 if ((cpu_id & 0xf00) == 0x500) {
367 if (((cpu_id & 0x0f0) > 0)
368 && ((cpu_id & 0x0f0) < 0x60)
369 && ((cpu_id & 0x00f) > 3))
370 enable_K5_wt_alloc();
371 else if (((cpu_id & 0x0f0) > 0x80)
372 || (((cpu_id & 0x0f0) == 0x80)
373 && (cpu_id & 0x00f) > 0x07))
374 enable_K6_2_wt_alloc();
375 else if ((cpu_id & 0x0f0) > 0x50)
376 enable_K6_wt_alloc();
377 }
378 #endif
379 } else if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
380 strcpy(cpu_model, "Cyrix ");
381 switch (cpu_id & 0xff0) {
382 case 0x440:
383 strcat(cpu_model, "MediaGX");
384 break;
385 case 0x520:
386 strcat(cpu_model, "6x86");
387 break;
388 case 0x540:
389 cpu_class = CPUCLASS_586;
390 strcat(cpu_model, "GXm");
391 break;
392 case 0x600:
393 strcat(cpu_model, "6x86MX");
394 break;
395 default:
396 /*
397 * Even though CPU supports the cpuid
398 * instruction, it can be disabled.
399 * Therefore, this routine supports all Cyrix
400 * CPUs.
401 */
402 switch (cyrix_did & 0xf0) {
403 case 0x00:
404 switch (cyrix_did & 0x0f) {
405 case 0x00:
406 strcat(cpu_model, "486SLC");
407 break;
408 case 0x01:
409 strcat(cpu_model, "486DLC");
410 break;
411 case 0x02:
412 strcat(cpu_model, "486SLC2");
413 break;
414 case 0x03:
415 strcat(cpu_model, "486DLC2");
416 break;
417 case 0x04:
418 strcat(cpu_model, "486SRx");
419 break;
420 case 0x05:
421 strcat(cpu_model, "486DRx");
422 break;
423 case 0x06:
424 strcat(cpu_model, "486SRx2");
425 break;
426 case 0x07:
427 strcat(cpu_model, "486DRx2");
428 break;
429 case 0x08:
430 strcat(cpu_model, "486SRu");
431 break;
432 case 0x09:
433 strcat(cpu_model, "486DRu");
434 break;
435 case 0x0a:
436 strcat(cpu_model, "486SRu2");
437 break;
438 case 0x0b:
439 strcat(cpu_model, "486DRu2");
440 break;
441 default:
442 strcat(cpu_model, "Unknown");
443 break;
444 }
445 break;
446 case 0x10:
447 switch (cyrix_did & 0x0f) {
448 case 0x00:
449 strcat(cpu_model, "486S");
450 break;
451 case 0x01:
452 strcat(cpu_model, "486S2");
453 break;
454 case 0x02:
455 strcat(cpu_model, "486Se");
456 break;
457 case 0x03:
458 strcat(cpu_model, "486S2e");
459 break;
460 case 0x0a:
461 strcat(cpu_model, "486DX");
462 break;
463 case 0x0b:
464 strcat(cpu_model, "486DX2");
465 break;
466 case 0x0f:
467 strcat(cpu_model, "486DX4");
468 break;
469 default:
470 strcat(cpu_model, "Unknown");
471 break;
472 }
473 break;
474 case 0x20:
475 if ((cyrix_did & 0x0f) < 8)
476 strcat(cpu_model, "6x86"); /* Where did you get it? */
477 else
478 strcat(cpu_model, "5x86");
479 break;
480 case 0x30:
481 strcat(cpu_model, "6x86");
482 break;
483 case 0x40:
484 if ((cyrix_did & 0xf000) == 0x3000) {
485 cpu_class = CPUCLASS_586;
486 strcat(cpu_model, "GXm");
487 } else
488 strcat(cpu_model, "MediaGX");
489 break;
490 case 0x50:
491 strcat(cpu_model, "6x86MX");
492 break;
493 case 0xf0:
494 switch (cyrix_did & 0x0f) {
495 case 0x0d:
496 strcat(cpu_model, "Overdrive CPU");
497 case 0x0e:
498 strcpy(cpu_model, "Texas Instruments 486SXL");
499 break;
500 case 0x0f:
501 strcat(cpu_model, "486SLC/DLC");
502 break;
503 default:
504 strcat(cpu_model, "Unknown");
505 break;
506 }
507 break;
508 default:
509 strcat(cpu_model, "Unknown");
510 break;
511 }
512 break;
513 }
514 } else if (strcmp(cpu_vendor, "RiseRiseRise") == 0) {
515 strcpy(cpu_model, "Rise ");
516 switch (cpu_id & 0xff0) {
517 case 0x500:
518 strcat(cpu_model, "mP6");
519 break;
520 default:
521 strcat(cpu_model, "Unknown");
522 }
523 } else if (strcmp(cpu_vendor, "CentaurHauls") == 0) {
524 switch (cpu_id & 0xff0) {
525 case 0x540:
526 strcpy(cpu_model, "IDT WinChip C6");
527 tsc_is_broken = 1;
528 break;
529 case 0x580:
530 strcpy(cpu_model, "IDT WinChip 2");
531 break;
532 case 0x660:
533 strcpy(cpu_model, "VIA C3 Samuel");
534 break;
535 case 0x670:
536 if (cpu_id & 0x8)
537 strcpy(cpu_model, "VIA C3 Ezra");
538 else
539 strcpy(cpu_model, "VIA C3 Samuel 2");
540 break;
541 case 0x680:
542 strcpy(cpu_model, "VIA C3 Ezra-T");
543 break;
544 case 0x690:
545 strcpy(cpu_model, "VIA C3 Nehemiah");
546 do_cpuid(0xc0000000, regs);
547 if (regs[0] == 0xc0000001) {
548 do_cpuid(0xc0000001, regs);
549 if ((cpu_id & 0xf) >= 3)
550 if ((regs[3] & 0x0c) == 0x0c)
551 strcat(cpu_model, "+RNG");
552 if ((cpu_id & 0xf) >= 8)
553 if ((regs[3] & 0xc0) == 0xc0)
554 strcat(cpu_model, "+ACE");
555 }
556 break;
557 default:
558 strcpy(cpu_model, "VIA/IDT Unknown");
559 }
560 } else if (strcmp(cpu_vendor, "IBM") == 0) {
561 strcpy(cpu_model, "Blue Lightning CPU");
562 }
563
564 /*
565 * Replace cpu_model with cpu_brand minus leading spaces if
566 * we have one.
567 */
568 brand = cpu_brand;
569 while (*brand == ' ')
570 ++brand;
571 if (*brand != '\0')
572 strcpy(cpu_model, brand);
573
574 #endif
575
576 printf("%s (", cpu_model);
577 switch(cpu_class) {
578 case CPUCLASS_286:
579 printf("286");
580 break;
581 #if defined(I386_CPU)
582 case CPUCLASS_386:
583 printf("386");
584 break;
585 #endif
586 #if defined(I486_CPU)
587 case CPUCLASS_486:
588 printf("486");
589 /* bzero = i486_bzero; */
590 break;
591 #endif
592 #if defined(I586_CPU)
593 case CPUCLASS_586:
594 printf("%d.%02d-MHz ",
595 (tsc_freq + 4999) / 1000000,
596 ((tsc_freq + 4999) / 10000) % 100);
597 printf("586");
598 break;
599 #endif
600 #if defined(I686_CPU)
601 case CPUCLASS_686:
602 printf("%d.%02d-MHz ",
603 (tsc_freq + 4999) / 1000000,
604 ((tsc_freq + 4999) / 10000) % 100);
605 printf("686");
606 break;
607 #endif
608 default:
609 printf("Unknown"); /* will panic below... */
610 }
611 printf("-class CPU)\n");
612 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
613 if(*cpu_vendor)
614 printf(" Origin = \"%s\"",cpu_vendor);
615 if(cpu_id)
616 printf(" Id = 0x%x", cpu_id);
617
618 if (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
619 strcmp(cpu_vendor, "AuthenticAMD") == 0 ||
620 strcmp(cpu_vendor, "RiseRiseRise") == 0 ||
621 strcmp(cpu_vendor, "CentaurHauls") == 0 ||
622 ((strcmp(cpu_vendor, "CyrixInstead") == 0) &&
623 ((cpu_id & 0xf00) > 0x500))) {
624 printf(" Stepping = %u", cpu_id & 0xf);
625 if (strcmp(cpu_vendor, "CyrixInstead") == 0)
626 printf(" DIR=0x%04x", cyrix_did);
627 if (cpu_high > 0) {
628 /*
629 * Here we should probably set up flags indicating
630 * whether or not various features are available.
631 * The interesting ones are probably VME, PSE, PAE,
632 * and PGE. The code already assumes without bothering
633 * to check that all CPUs >= Pentium have a TSC and
634 * MSRs.
635 */
636 printf("\n Features=0x%b", cpu_feature,
637 "\020"
638 "\001FPU" /* Integral FPU */
639 "\002VME" /* Extended VM86 mode support */
640 "\003DE" /* Debugging Extensions (CR4.DE) */
641 "\004PSE" /* 4MByte page tables */
642 "\005TSC" /* Timestamp counter */
643 "\006MSR" /* Machine specific registers */
644 "\007PAE" /* Physical address extension */
645 "\010MCE" /* Machine Check support */
646 "\011CX8" /* CMPEXCH8 instruction */
647 "\012APIC" /* SMP local APIC */
648 "\013oldMTRR" /* Previous implementation of MTRR */
649 "\014SEP" /* Fast System Call */
650 "\015MTRR" /* Memory Type Range Registers */
651 "\016PGE" /* PG_G (global bit) support */
652 "\017MCA" /* Machine Check Architecture */
653 "\020CMOV" /* CMOV instruction */
654 "\021PAT" /* Page attributes table */
655 "\022PSE36" /* 36 bit address space support */
656 "\023PN" /* Processor Serial number */
657 "\024CLFLUSH" /* Has the CLFLUSH instruction */
658 "\025<b20>"
659 "\026DTS" /* Debug Trace Store */
660 "\027ACPI" /* ACPI support */
661 "\030MMX" /* MMX instructions */
662 "\031FXSR" /* FXSAVE/FXRSTOR */
663 "\032SSE" /* Streaming SIMD Extensions */
664 "\033SSE2" /* Streaming SIMD Extensions #2 */
665 "\034SS" /* Self snoop */
666 "\035HTT" /* Hyperthreading (see EBX bit 16-23) */
667 "\036TM" /* Thermal Monitor clock slowdown */
668 "\037IA64" /* CPU can execute IA64 instructions */
669 "\040PBE" /* Pending Break Enable */
670 );
671
672 /*
673 * If this CPU supports hyperthreading then mention
674 * the number of logical CPU's it contains.
675 */
676 if (cpu_feature & CPUID_HTT &&
677 (cpu_procinfo & CPUID_HTT_CORES) >> 16 > 1)
678 printf("\n Hyperthreading: %d logical CPUs",
679 (cpu_procinfo & CPUID_HTT_CORES) >> 16);
680 }
681 if (strcmp(cpu_vendor, "AuthenticAMD") == 0 &&
682 cpu_exthigh >= 0x80000001)
683 print_AMD_features();
684 } else if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
685 printf(" DIR=0x%04x", cyrix_did);
686 printf(" Stepping=%u", (cyrix_did & 0xf000) >> 12);
687 printf(" Revision=%u", (cyrix_did & 0x0f00) >> 8);
688 #ifndef CYRIX_CACHE_REALLY_WORKS
689 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
690 printf("\n CPU cache: write-through mode");
691 #endif
692 }
693 /* Avoid ugly blank lines: only print newline when we have to. */
694 if (*cpu_vendor || cpu_id)
695 printf("\n");
696
697 #endif
698 if (strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
699 strcmp(cpu_vendor, "TransmetaCPU") == 0) {
700 setup_tmx86_longrun();
701 }
702
703 for (i = 0; i < additional_cpu_info_count; ++i) {
704 printf(" %s\n", additional_cpu_info_ary[i]);
705 }
706
707 if (!bootverbose)
708 return;
709
710 if (strcmp(cpu_vendor, "AuthenticAMD") == 0)
711 print_AMD_info();
712 else if (strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
713 strcmp(cpu_vendor, "TransmetaCPU") == 0)
714 print_transmeta_info();
715
716 #ifdef I686_CPU
717 /*
718 * XXX - Do PPro CPUID level=2 stuff here?
719 *
720 * No, but maybe in a print_Intel_info() function called from here.
721 */
722 #endif
723 }
724
725 void
726 panicifcpuunsupported(void)
727 {
728
729 #if !defined(I386_CPU) && !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
730 #error This kernel is not configured for one of the supported CPUs
731 #endif
732 /*
733 * Now that we have told the user what they have,
734 * let them know if that machine type isn't configured.
735 */
736 switch (cpu_class) {
737 case CPUCLASS_286: /* a 286 should not make it this far, anyway */
738 #if !defined(I386_CPU)
739 case CPUCLASS_386:
740 #endif
741 #if !defined(I486_CPU)
742 case CPUCLASS_486:
743 #endif
744 #if !defined(I586_CPU)
745 case CPUCLASS_586:
746 #endif
747 #if !defined(I686_CPU)
748 case CPUCLASS_686:
749 #endif
750 panic("CPU class not configured");
751 default:
752 break;
753 }
754 }
755
756
757 static volatile u_int trap_by_rdmsr;
758
759 /*
760 * Special exception 6 handler.
761 * The rdmsr instruction generates invalid opcodes fault on 486-class
762 * Cyrix CPU. Stacked eip register points the rdmsr instruction in the
763 * function identblue() when this handler is called. Stacked eip should
764 * be advanced.
765 */
766 inthand_t bluetrap6;
767
768 __asm(
769 " .text \n"
770 " .p2align 2,0x90 \n"
771 " .type " __XSTRING(CNAME(bluetrap6)) ",@function \n"
772 __XSTRING(CNAME(bluetrap6)) ": \n"
773 " ss \n"
774 " movl $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) " \n"
775 " addl $2, (%esp) # I know rdmsr is a 2-bytes instruction. \n"
776 " iret \n"
777 );
778
779 /*
780 * Special exception 13 handler.
781 * Accessing non-existent MSR generates general protection fault.
782 */
783 inthand_t bluetrap13;
784
785 __asm(
786 " .text \n"
787 " .p2align 2,0x90 \n"
788 " .type " __XSTRING(CNAME(bluetrap13)) ",@function \n"
789 __XSTRING(CNAME(bluetrap13)) ": \n"
790 " ss \n"
791 " movl $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) " \n"
792 " popl %eax # discard errorcode. \n"
793 " addl $2, (%esp) # I know rdmsr is a 2-bytes instruction. \n"
794 " iret \n"
795 );
796
797 /*
798 * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
799 * support cpuid instruction. This function should be called after
800 * loading interrupt descriptor table register.
801 *
802 * I don't like this method that handles fault, but I couldn't get
803 * information for any other methods. Does blue giant know?
804 */
805 static int
806 identblue(void)
807 {
808
809 trap_by_rdmsr = 0;
810
811 /*
812 * Cyrix 486-class CPU does not support rdmsr instruction.
813 * The rdmsr instruction generates invalid opcode fault, and exception
814 * will be trapped by bluetrap6() on Cyrix 486-class CPU. The
815 * bluetrap6() set the magic number to trap_by_rdmsr.
816 */
817 setidt(6, bluetrap6, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
818
819 /*
820 * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
821 * In this case, rdmsr generates general protection fault, and
822 * exception will be trapped by bluetrap13().
823 */
824 setidt(13, bluetrap13, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
825
826 rdmsr(0x1002); /* Cyrix CPU generates fault. */
827
828 if (trap_by_rdmsr == 0xa8c1d)
829 return IDENTBLUE_CYRIX486;
830 else if (trap_by_rdmsr == 0xa89c4)
831 return IDENTBLUE_CYRIXM2;
832 return IDENTBLUE_IBMCPU;
833 }
834
835
836 /*
837 * identifycyrix() set lower 16 bits of cyrix_did as follows:
838 *
839 * F E D C B A 9 8 7 6 5 4 3 2 1 0
840 * +-------+-------+---------------+
841 * | SID | RID | Device ID |
842 * | (DIR 1) | (DIR 0) |
843 * +-------+-------+---------------+
844 */
845 static void
846 identifycyrix(void)
847 {
848 int ccr2_test = 0, dir_test = 0;
849 u_char ccr2, ccr3;
850
851 mpintr_lock();
852
853 ccr2 = read_cyrix_reg(CCR2);
854 write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
855 read_cyrix_reg(CCR2);
856 if (read_cyrix_reg(CCR2) != ccr2)
857 ccr2_test = 1;
858 write_cyrix_reg(CCR2, ccr2);
859
860 ccr3 = read_cyrix_reg(CCR3);
861 write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
862 read_cyrix_reg(CCR3);
863 if (read_cyrix_reg(CCR3) != ccr3)
864 dir_test = 1; /* CPU supports DIRs. */
865 write_cyrix_reg(CCR3, ccr3);
866
867 if (dir_test) {
868 /* Device ID registers are available. */
869 cyrix_did = read_cyrix_reg(DIR1) << 8;
870 cyrix_did += read_cyrix_reg(DIR0);
871 } else if (ccr2_test)
872 cyrix_did = 0x0010; /* 486S A-step */
873 else
874 cyrix_did = 0x00ff; /* Old 486SLC/DLC and TI486SXLC/SXL */
875
876 mpintr_unlock();
877 }
878
879 /*
880 * Final stage of CPU identification. -- Should I check TI?
881 */
882 void
883 finishidentcpu(void)
884 {
885 int isblue = 0;
886 u_char ccr3;
887 u_int regs[4];
888
889 if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
890 if (cpu == CPU_486) {
891 /*
892 * These conditions are equivalent to:
893 * - CPU does not support cpuid instruction.
894 * - Cyrix/IBM CPU is detected.
895 */
896 isblue = identblue();
897 if (isblue == IDENTBLUE_IBMCPU) {
898 strcpy(cpu_vendor, "IBM");
899 cpu = CPU_BLUE;
900 return;
901 }
902 }
903 switch (cpu_id & 0xf00) {
904 case 0x600:
905 /*
906 * Cyrix's datasheet does not describe DIRs.
907 * Therefor, I assume it does not have them
908 * and use the result of the cpuid instruction.
909 * XXX they seem to have it for now at least. -Peter
910 */
911 identifycyrix();
912 cpu = CPU_M2;
913 break;
914 default:
915 identifycyrix();
916 /*
917 * This routine contains a trick.
918 * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
919 */
920 switch (cyrix_did & 0x00f0) {
921 case 0x00:
922 case 0xf0:
923 cpu = CPU_486DLC;
924 break;
925 case 0x10:
926 cpu = CPU_CY486DX;
927 break;
928 case 0x20:
929 if ((cyrix_did & 0x000f) < 8)
930 cpu = CPU_M1;
931 else
932 cpu = CPU_M1SC;
933 break;
934 case 0x30:
935 cpu = CPU_M1;
936 break;
937 case 0x40:
938 /* MediaGX CPU */
939 cpu = CPU_M1SC;
940 break;
941 default:
942 /* M2 and later CPUs are treated as M2. */
943 cpu = CPU_M2;
944
945 /*
946 * enable cpuid instruction.
947 */
948 ccr3 = read_cyrix_reg(CCR3);
949 write_cyrix_reg(CCR3, CCR3_MAPEN0);
950 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID);
951 write_cyrix_reg(CCR3, ccr3);
952
953 do_cpuid(0, regs);
954 cpu_high = regs[0]; /* eax */
955 do_cpuid(1, regs);
956 cpu_id = regs[0]; /* eax */
957 cpu_feature = regs[3]; /* edx */
958 break;
959 }
960 }
961 } else if (cpu == CPU_486 && *cpu_vendor == '\0') {
962 /*
963 * There are BlueLightning CPUs that do not change
964 * undefined flags by dividing 5 by 2. In this case,
965 * the CPU identification routine in locore.s leaves
966 * cpu_vendor null string and puts CPU_486 into the
967 * cpu.
968 */
969 isblue = identblue();
970 if (isblue == IDENTBLUE_IBMCPU) {
971 strcpy(cpu_vendor, "IBM");
972 cpu = CPU_BLUE;
973 return;
974 }
975 }
976 }
977
978 static void
979 print_AMD_assoc(int i)
980 {
981 if (i == 255)
982 printf(", fully associative\n");
983 else
984 printf(", %d-way associative\n", i);
985 }
986
987 static void
988 print_AMD_info(void)
989 {
990 quad_t amd_whcr;
991
992 if (cpu_exthigh >= 0x80000005) {
993 u_int regs[4];
994
995 do_cpuid(0x80000005, regs);
996 printf("Data TLB: %d entries", (regs[1] >> 16) & 0xff);
997 print_AMD_assoc(regs[1] >> 24);
998 printf("Instruction TLB: %d entries", regs[1] & 0xff);
999 print_AMD_assoc((regs[1] >> 8) & 0xff);
1000 printf("L1 data cache: %d kbytes", regs[2] >> 24);
1001 printf(", %d bytes/line", regs[2] & 0xff);
1002 printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
1003 print_AMD_assoc((regs[2] >> 16) & 0xff);
1004 printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
1005 printf(", %d bytes/line", regs[3] & 0xff);
1006 printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
1007 print_AMD_assoc((regs[3] >> 16) & 0xff);
1008 if (cpu_exthigh >= 0x80000006) { /* K6-III, or later */
1009 do_cpuid(0x80000006, regs);
1010 /*
1011 * Report right L2 cache size on Duron rev. A0.
1012 */
1013 if ((cpu_id & 0xFF0) == 0x630)
1014 printf("L2 internal cache: 64 kbytes");
1015 else
1016 printf("L2 internal cache: %d kbytes",
1017 regs[2] >> 16);
1018
1019 printf(", %d bytes/line", regs[2] & 0xff);
1020 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
1021 print_AMD_assoc((regs[2] >> 12) & 0x0f);
1022 }
1023 }
1024 if (((cpu_id & 0xf00) == 0x500)
1025 && (((cpu_id & 0x0f0) > 0x80)
1026 || (((cpu_id & 0x0f0) == 0x80)
1027 && (cpu_id & 0x00f) > 0x07))) {
1028 /* K6-2(new core [Stepping 8-F]), K6-III or later */
1029 amd_whcr = rdmsr(0xc0000082);
1030 if (!(amd_whcr & (0x3ff << 22))) {
1031 printf("Write Allocate Disable\n");
1032 } else {
1033 printf("Write Allocate Enable Limit: %dM bytes\n",
1034 (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
1035 printf("Write Allocate 15-16M bytes: %s\n",
1036 (amd_whcr & (1 << 16)) ? "Enable" : "Disable");
1037 }
1038 } else if (((cpu_id & 0xf00) == 0x500)
1039 && ((cpu_id & 0x0f0) > 0x50)) {
1040 /* K6, K6-2(old core) */
1041 amd_whcr = rdmsr(0xc0000082);
1042 if (!(amd_whcr & (0x7f << 1))) {
1043 printf("Write Allocate Disable\n");
1044 } else {
1045 printf("Write Allocate Enable Limit: %dM bytes\n",
1046 (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
1047 printf("Write Allocate 15-16M bytes: %s\n",
1048 (amd_whcr & 0x0001) ? "Enable" : "Disable");
1049 printf("Hardware Write Allocate Control: %s\n",
1050 (amd_whcr & 0x0100) ? "Enable" : "Disable");
1051 }
1052 }
1053 }
1054
1055 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
1056 static void
1057 print_AMD_features(void)
1058 {
1059 u_int regs[4];
1060
1061 /*
1062 * Values taken from AMD Processor Recognition
1063 * http://www.amd.com/products/cpg/athlon/techdocs/pdf/20734.pdf
1064 */
1065 do_cpuid(0x80000001, regs);
1066 printf("\n AMD Features=0x%b", regs[3] &~ cpu_feature,
1067 "\020" /* in hex */
1068 "\001FPU" /* Integral FPU */
1069 "\002VME" /* Extended VM86 mode support */
1070 "\003DE" /* Debug extensions */
1071 "\004PSE" /* 4MByte page tables */
1072 "\005TSC" /* Timestamp counter */
1073 "\006MSR" /* Machine specific registers */
1074 "\007PAE" /* Physical address extension */
1075 "\010MCE" /* Machine Check support */
1076 "\011CX8" /* CMPEXCH8 instruction */
1077 "\012APIC" /* SMP local APIC */
1078 "\013<b10>"
1079 "\014SYSCALL" /* SYSENTER/SYSEXIT instructions */
1080 "\015MTRR" /* Memory Type Range Registers */
1081 "\016PGE" /* PG_G (global bit) support */
1082 "\017MCA" /* Machine Check Architecture */
1083 "\020ICMOV" /* CMOV instruction */
1084 "\021PAT" /* Page attributes table */
1085 "\022PGE36" /* 36 bit address space support */
1086 "\023RSVD" /* Reserved, unknown */
1087 "\024MP" /* Multiprocessor Capable */
1088 "\025<b20>"
1089 "\026<b21>"
1090 "\027AMIE" /* AMD MMX Instruction Extensions */
1091 "\030MMX"
1092 "\031FXSAVE" /* FXSAVE/FXRSTOR */
1093 "\032<b25>"
1094 "\033<b26>"
1095 "\034<b27>"
1096 "\035<b28>"
1097 "\036<b29>"
1098 "\037DSP" /* AMD 3DNow! Instruction Extensions */
1099 "\0403DNow!"
1100 );
1101 }
1102 #endif
1103
1104 /*
1105 * Transmeta Crusoe LongRun Support by Tamotsu Hattori.
1106 */
1107
1108 #define MSR_TMx86_LONGRUN 0x80868010
1109 #define MSR_TMx86_LONGRUN_FLAGS 0x80868011
1110
1111 #define LONGRUN_MODE_MASK(x) ((x) & 0x000000007f)
1112 #define LONGRUN_MODE_RESERVED(x) ((x) & 0xffffff80)
1113 #define LONGRUN_MODE_WRITE(x, y) (LONGRUN_MODE_RESERVED(x) | LONGRUN_MODE_MASK(y))
1114
1115 #define LONGRUN_MODE_MINFREQUENCY 0x00
1116 #define LONGRUN_MODE_ECONOMY 0x01
1117 #define LONGRUN_MODE_PERFORMANCE 0x02
1118 #define LONGRUN_MODE_MAXFREQUENCY 0x03
1119 #define LONGRUN_MODE_UNKNOWN 0x04
1120 #define LONGRUN_MODE_MAX 0x04
1121
1122 union msrinfo {
1123 u_int64_t msr;
1124 u_int32_t regs[2];
1125 };
1126
1127 u_int32_t longrun_modes[LONGRUN_MODE_MAX][3] = {
1128 /* MSR low, MSR high, flags bit0 */
1129 { 0, 0, 0}, /* LONGRUN_MODE_MINFREQUENCY */
1130 { 0, 100, 0}, /* LONGRUN_MODE_ECONOMY */
1131 { 0, 100, 1}, /* LONGRUN_MODE_PERFORMANCE */
1132 { 100, 100, 1}, /* LONGRUN_MODE_MAXFREQUENCY */
1133 };
1134
1135 static u_int
1136 tmx86_get_longrun_mode(void)
1137 {
1138 union msrinfo msrinfo;
1139 u_int low, high, flags, mode;
1140
1141 mpintr_lock();
1142
1143 msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN);
1144 low = LONGRUN_MODE_MASK(msrinfo.regs[0]);
1145 high = LONGRUN_MODE_MASK(msrinfo.regs[1]);
1146 flags = rdmsr(MSR_TMx86_LONGRUN_FLAGS) & 0x01;
1147
1148 for (mode = 0; mode < LONGRUN_MODE_MAX; mode++) {
1149 if (low == longrun_modes[mode][0] &&
1150 high == longrun_modes[mode][1] &&
1151 flags == longrun_modes[mode][2]) {
1152 goto out;
1153 }
1154 }
1155 mode = LONGRUN_MODE_UNKNOWN;
1156 out:
1157 mpintr_unlock();
1158 return (mode);
1159 }
1160
1161 static u_int
1162 tmx86_get_longrun_status(u_int * frequency, u_int * voltage, u_int * percentage)
1163 {
1164 u_int regs[4];
1165
1166 mpintr_lock();
1167
1168 do_cpuid(0x80860007, regs);
1169 *frequency = regs[0];
1170 *voltage = regs[1];
1171 *percentage = regs[2];
1172
1173 mpintr_unlock();
1174 return (1);
1175 }
1176
1177 static u_int
1178 tmx86_set_longrun_mode(u_int mode)
1179 {
1180 union msrinfo msrinfo;
1181
1182 if (mode >= LONGRUN_MODE_UNKNOWN) {
1183 return (0);
1184 }
1185
1186 mpintr_lock();
1187
1188 /* Write LongRun mode values to Model Specific Register. */
1189 msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN);
1190 msrinfo.regs[0] = LONGRUN_MODE_WRITE(msrinfo.regs[0],
1191 longrun_modes[mode][0]);
1192 msrinfo.regs[1] = LONGRUN_MODE_WRITE(msrinfo.regs[1],
1193 longrun_modes[mode][1]);
1194 wrmsr(MSR_TMx86_LONGRUN, msrinfo.msr);
1195
1196 /* Write LongRun mode flags to Model Specific Register. */
1197 msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN_FLAGS);
1198 msrinfo.regs[0] = (msrinfo.regs[0] & ~0x01) | longrun_modes[mode][2];
1199 wrmsr(MSR_TMx86_LONGRUN_FLAGS, msrinfo.msr);
1200
1201 mpintr_unlock();
1202 return (1);
1203 }
1204
1205 static u_int crusoe_longrun;
1206 static u_int crusoe_frequency;
1207 static u_int crusoe_voltage;
1208 static u_int crusoe_percentage;
1209 static struct sysctl_ctx_list crusoe_sysctl_ctx;
1210 static struct sysctl_oid *crusoe_sysctl_tree;
1211
1212 static int
1213 tmx86_longrun_sysctl(SYSCTL_HANDLER_ARGS)
1214 {
1215 u_int mode;
1216 int error;
1217
1218 crusoe_longrun = tmx86_get_longrun_mode();
1219 mode = crusoe_longrun;
1220 error = sysctl_handle_int(oidp, &mode, 0, req);
1221 if (error || !req->newptr) {
1222 return (error);
1223 }
1224 if (mode >= LONGRUN_MODE_UNKNOWN) {
1225 error = EINVAL;
1226 return (error);
1227 }
1228 if (crusoe_longrun != mode) {
1229 crusoe_longrun = mode;
1230 tmx86_set_longrun_mode(crusoe_longrun);
1231 }
1232
1233 return (error);
1234 }
1235
1236 static int
1237 tmx86_status_sysctl(SYSCTL_HANDLER_ARGS)
1238 {
1239 u_int val;
1240 int error;
1241
1242 tmx86_get_longrun_status(&crusoe_frequency,
1243 &crusoe_voltage, &crusoe_percentage);
1244 val = *(u_int *)oidp->oid_arg1;
1245 error = sysctl_handle_int(oidp, &val, 0, req);
1246 return (error);
1247 }
1248
1249 static void
1250 setup_tmx86_longrun(void)
1251 {
1252 static int done = 0;
1253
1254 if (done)
1255 return;
1256 done++;
1257
1258 sysctl_ctx_init(&crusoe_sysctl_ctx);
1259 crusoe_sysctl_tree = SYSCTL_ADD_NODE(&crusoe_sysctl_ctx,
1260 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
1261 "crusoe", CTLFLAG_RD, 0,
1262 "Transmeta Crusoe LongRun support");
1263 SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
1264 OID_AUTO, "longrun", CTLTYPE_INT | CTLFLAG_RW,
1265 &crusoe_longrun, 0, tmx86_longrun_sysctl, "I",
1266 "LongRun mode [0-3]");
1267 SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
1268 OID_AUTO, "frequency", CTLTYPE_INT | CTLFLAG_RD,
1269 &crusoe_frequency, 0, tmx86_status_sysctl, "I",
1270 "Current frequency (MHz)");
1271 SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
1272 OID_AUTO, "voltage", CTLTYPE_INT | CTLFLAG_RD,
1273 &crusoe_voltage, 0, tmx86_status_sysctl, "I",
1274 "Current voltage (mV)");
1275 SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
1276 OID_AUTO, "percentage", CTLTYPE_INT | CTLFLAG_RD,
1277 &crusoe_percentage, 0, tmx86_status_sysctl, "I",
1278 "Processing performance (%)");
1279 }
1280
1281 static void
1282 print_transmeta_info()
1283 {
1284 u_int regs[4], nreg = 0;
1285
1286 do_cpuid(0x80860000, regs);
1287 nreg = regs[0];
1288 if (nreg >= 0x80860001) {
1289 do_cpuid(0x80860001, regs);
1290 printf(" Processor revision %u.%u.%u.%u\n",
1291 (regs[1] >> 24) & 0xff,
1292 (regs[1] >> 16) & 0xff,
1293 (regs[1] >> 8) & 0xff,
1294 regs[1] & 0xff);
1295 }
1296 if (nreg >= 0x80860002) {
1297 do_cpuid(0x80860002, regs);
1298 printf(" Code Morphing Software revision %u.%u.%u-%u-%u\n",
1299 (regs[1] >> 24) & 0xff,
1300 (regs[1] >> 16) & 0xff,
1301 (regs[1] >> 8) & 0xff,
1302 regs[1] & 0xff,
1303 regs[2]);
1304 }
1305 if (nreg >= 0x80860006) {
1306 char info[65];
1307 do_cpuid(0x80860003, (u_int*) &info[0]);
1308 do_cpuid(0x80860004, (u_int*) &info[16]);
1309 do_cpuid(0x80860005, (u_int*) &info[32]);
1310 do_cpuid(0x80860006, (u_int*) &info[48]);
1311 info[64] = 0;
1312 printf(" %s\n", info);
1313 }
1314
1315 crusoe_longrun = tmx86_get_longrun_mode();
1316 tmx86_get_longrun_status(&crusoe_frequency,
1317 &crusoe_voltage, &crusoe_percentage);
1318 printf(" LongRun mode: %d <%dMHz %dmV %d%%>\n", crusoe_longrun,
1319 crusoe_frequency, crusoe_voltage, crusoe_percentage);
1320 }
1321
1322 void
1323 additional_cpu_info(const char *line)
1324 {
1325 int i;
1326
1327 if ((i = additional_cpu_info_count) < MAX_ADDITIONAL_INFO) {
1328 additional_cpu_info_ary[i] = line;
1329 ++additional_cpu_info_count;
1330 }
1331 }
1332
DragonFly BSD