sys/dev/virtual/amazon/ena/ena-com/ena_admin_defs.h

   1 /*-
   2  * BSD LICENSE
   3  *
   4  * Copyright (c) 2015-2017 Amazon.com, Inc. or its affiliates.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  *
  11  * * Redistributions of source code must retain the above copyright
  12  * notice, this list of conditions and the following disclaimer.
  13  * * Redistributions in binary form must reproduce the above copyright
  14  * notice, this list of conditions and the following disclaimer in
  15  * the documentation and/or other materials provided with the
  16  * distribution.
  17  * * Neither the name of copyright holder nor the names of its
  18  * contributors may be used to endorse or promote products derived
  19  * from this software without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #ifndef _ENA_ADMIN_H_
  35 #define _ENA_ADMIN_H_
  36
  37 enum ena_admin_aq_opcode {
  38         ENA_ADMIN_CREATE_SQ     = 1,
  39
  40         ENA_ADMIN_DESTROY_SQ    = 2,
  41
  42         ENA_ADMIN_CREATE_CQ     = 3,
  43
  44         ENA_ADMIN_DESTROY_CQ    = 4,
  45
  46         ENA_ADMIN_GET_FEATURE   = 8,
  47
  48         ENA_ADMIN_SET_FEATURE   = 9,
  49
  50         ENA_ADMIN_GET_STATS     = 11,
  51 };
  52
  53 enum ena_admin_aq_completion_status {
  54         ENA_ADMIN_SUCCESS                       = 0,
  55
  56         ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE   = 1,
  57
  58         ENA_ADMIN_BAD_OPCODE                    = 2,
  59
  60         ENA_ADMIN_UNSUPPORTED_OPCODE            = 3,
  61
  62         ENA_ADMIN_MALFORMED_REQUEST             = 4,
  63
  64         /* Additional status is provided in ACQ entry extended_status */
  65         ENA_ADMIN_ILLEGAL_PARAMETER             = 5,
  66
  67         ENA_ADMIN_UNKNOWN_ERROR                 = 6,
  68 };
  69
  70 enum ena_admin_aq_feature_id {
  71         ENA_ADMIN_DEVICE_ATTRIBUTES             = 1,
  72
  73         ENA_ADMIN_MAX_QUEUES_NUM                = 2,
  74
  75         ENA_ADMIN_HW_HINTS                      = 3,
  76
  77         ENA_ADMIN_RSS_HASH_FUNCTION             = 10,
  78
  79         ENA_ADMIN_STATELESS_OFFLOAD_CONFIG      = 11,
  80
  81         ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG  = 12,
  82
  83         ENA_ADMIN_MTU                           = 14,
  84
  85         ENA_ADMIN_RSS_HASH_INPUT                = 18,
  86
  87         ENA_ADMIN_INTERRUPT_MODERATION          = 20,
  88
  89         ENA_ADMIN_AENQ_CONFIG                   = 26,
  90
  91         ENA_ADMIN_LINK_CONFIG                   = 27,
  92
  93         ENA_ADMIN_HOST_ATTR_CONFIG              = 28,
  94
  95         ENA_ADMIN_FEATURES_OPCODE_NUM           = 32,
  96 };
  97
  98 enum ena_admin_placement_policy_type {
  99         /* descriptors and headers are in host memory */
 100         ENA_ADMIN_PLACEMENT_POLICY_HOST = 1,
 101
 102         /* descriptors and headers are in device memory (a.k.a Low Latency
 103          * Queue)
 104          */
 105         ENA_ADMIN_PLACEMENT_POLICY_DEV  = 3,
 106 };
 107
 108 enum ena_admin_link_types {
 109         ENA_ADMIN_LINK_SPEED_1G         = 0x1,
 110
 111         ENA_ADMIN_LINK_SPEED_2_HALF_G   = 0x2,
 112
 113         ENA_ADMIN_LINK_SPEED_5G         = 0x4,
 114
 115         ENA_ADMIN_LINK_SPEED_10G        = 0x8,
 116
 117         ENA_ADMIN_LINK_SPEED_25G        = 0x10,
 118
 119         ENA_ADMIN_LINK_SPEED_40G        = 0x20,
 120
 121         ENA_ADMIN_LINK_SPEED_50G        = 0x40,
 122
 123         ENA_ADMIN_LINK_SPEED_100G       = 0x80,
 124
 125         ENA_ADMIN_LINK_SPEED_200G       = 0x100,
 126
 127         ENA_ADMIN_LINK_SPEED_400G       = 0x200,
 128 };
 129
 130 enum ena_admin_completion_policy_type {
 131         /* completion queue entry for each sq descriptor */
 132         ENA_ADMIN_COMPLETION_POLICY_DESC                = 0,
 133
 134         /* completion queue entry upon request in sq descriptor */
 135         ENA_ADMIN_COMPLETION_POLICY_DESC_ON_DEMAND      = 1,
 136
 137         /* current queue head pointer is updated in OS memory upon sq
 138          * descriptor request
 139          */
 140         ENA_ADMIN_COMPLETION_POLICY_HEAD_ON_DEMAND      = 2,
 141
 142         /* current queue head pointer is updated in OS memory for each sq
 143          * descriptor
 144          */
 145         ENA_ADMIN_COMPLETION_POLICY_HEAD                = 3,
 146 };
 147
 148 /* basic stats return ena_admin_basic_stats while extanded stats return a
 149  * buffer (string format) with additional statistics per queue and per
 150  * device id
 151  */
 152 enum ena_admin_get_stats_type {
 153         ENA_ADMIN_GET_STATS_TYPE_BASIC          = 0,
 154
 155         ENA_ADMIN_GET_STATS_TYPE_EXTENDED       = 1,
 156 };
 157
 158 enum ena_admin_get_stats_scope {
 159         ENA_ADMIN_SPECIFIC_QUEUE        = 0,
 160
 161         ENA_ADMIN_ETH_TRAFFIC           = 1,
 162 };
 163
 164 struct ena_admin_aq_common_desc {
 165         /* 11:0 : command_id
 166          * 15:12 : reserved12
 167          */
 168         uint16_t command_id;
 169
 170         /* as appears in ena_admin_aq_opcode */
 171         uint8_t opcode;
 172
 173         /* 0 : phase
 174          * 1 : ctrl_data - control buffer address valid
 175          * 2 : ctrl_data_indirect - control buffer address
 176          *    points to list of pages with addresses of control
 177          *    buffers
 178          * 7:3 : reserved3
 179          */
 180         uint8_t flags;
 181 };
 182
 183 /* used in ena_admin_aq_entry. Can point directly to control data, or to a
 184  * page list chunk. Used also at the end of indirect mode page list chunks,
 185  * for chaining.
 186  */
 187 struct ena_admin_ctrl_buff_info {
 188         uint32_t length;
 189
 190         struct ena_common_mem_addr address;
 191 };
 192
 193 struct ena_admin_sq {
 194         uint16_t sq_idx;
 195
 196         /* 4:0 : reserved
 197          * 7:5 : sq_direction - 0x1 - Tx; 0x2 - Rx
 198          */
 199         uint8_t sq_identity;
 200
 201         uint8_t reserved1;
 202 };
 203
 204 struct ena_admin_aq_entry {
 205         struct ena_admin_aq_common_desc aq_common_descriptor;
 206
 207         union {
 208                 uint32_t inline_data_w1[3];
 209
 210                 struct ena_admin_ctrl_buff_info control_buffer;
 211         } u;
 212
 213         uint32_t inline_data_w4[12];
 214 };
 215
 216 struct ena_admin_acq_common_desc {
 217         /* command identifier to associate it with the aq descriptor
 218          * 11:0 : command_id
 219          * 15:12 : reserved12
 220          */
 221         uint16_t command;
 222
 223         uint8_t status;
 224
 225         /* 0 : phase
 226          * 7:1 : reserved1
 227          */
 228         uint8_t flags;
 229
 230         uint16_t extended_status;
 231
 232         /* serves as a hint what AQ entries can be revoked */
 233         uint16_t sq_head_indx;
 234 };
 235
 236 struct ena_admin_acq_entry {
 237         struct ena_admin_acq_common_desc acq_common_descriptor;
 238
 239         uint32_t response_specific_data[14];
 240 };
 241
 242 struct ena_admin_aq_create_sq_cmd {
 243         struct ena_admin_aq_common_desc aq_common_descriptor;
 244
 245         /* 4:0 : reserved0_w1
 246          * 7:5 : sq_direction - 0x1 - Tx, 0x2 - Rx
 247          */
 248         uint8_t sq_identity;
 249
 250         uint8_t reserved8_w1;
 251
 252         /* 3:0 : placement_policy - Describing where the SQ
 253          *    descriptor ring and the SQ packet headers reside:
 254          *    0x1 - descriptors and headers are in OS memory,
 255          *    0x3 - descriptors and headers in device memory
 256          *    (a.k.a Low Latency Queue)
 257          * 6:4 : completion_policy - Describing what policy
 258          *    to use for generation completion entry (cqe) in
 259          *    the CQ associated with this SQ: 0x0 - cqe for each
 260          *    sq descriptor, 0x1 - cqe upon request in sq
 261          *    descriptor, 0x2 - current queue head pointer is
 262          *    updated in OS memory upon sq descriptor request
 263          *    0x3 - current queue head pointer is updated in OS
 264          *    memory for each sq descriptor
 265          * 7 : reserved15_w1
 266          */
 267         uint8_t sq_caps_2;
 268
 269         /* 0 : is_physically_contiguous - Described if the
 270          *    queue ring memory is allocated in physical
 271          *    contiguous pages or split.
 272          * 7:1 : reserved17_w1
 273          */
 274         uint8_t sq_caps_3;
 275
 276         /* associated completion queue id. This CQ must be created prior to
 277          *    SQ creation
 278          */
 279         uint16_t cq_idx;
 280
 281         /* submission queue depth in entries */
 282         uint16_t sq_depth;
 283
 284         /* SQ physical base address in OS memory. This field should not be
 285          * used for Low Latency queues. Has to be page aligned.
 286          */
 287         struct ena_common_mem_addr sq_ba;
 288
 289         /* specifies queue head writeback location in OS memory. Valid if
 290          * completion_policy is set to completion_policy_head_on_demand or
 291          * completion_policy_head. Has to be cache aligned
 292          */
 293         struct ena_common_mem_addr sq_head_writeback;
 294
 295         uint32_t reserved0_w7;
 296
 297         uint32_t reserved0_w8;
 298 };
 299
 300 enum ena_admin_sq_direction {
 301         ENA_ADMIN_SQ_DIRECTION_TX       = 1,
 302
 303         ENA_ADMIN_SQ_DIRECTION_RX       = 2,
 304 };
 305
 306 struct ena_admin_acq_create_sq_resp_desc {
 307         struct ena_admin_acq_common_desc acq_common_desc;
 308
 309         uint16_t sq_idx;
 310
 311         uint16_t reserved;
 312
 313         /* queue doorbell address as an offset to PCIe MMIO REG BAR */
 314         uint32_t sq_doorbell_offset;
 315
 316         /* low latency queue ring base address as an offset to PCIe MMIO
 317          * LLQ_MEM BAR
 318          */
 319         uint32_t llq_descriptors_offset;
 320
 321         /* low latency queue headers' memory as an offset to PCIe MMIO
 322          * LLQ_MEM BAR
 323          */
 324         uint32_t llq_headers_offset;
 325 };
 326
 327 struct ena_admin_aq_destroy_sq_cmd {
 328         struct ena_admin_aq_common_desc aq_common_descriptor;
 329
 330         struct ena_admin_sq sq;
 331 };
 332
 333 struct ena_admin_acq_destroy_sq_resp_desc {
 334         struct ena_admin_acq_common_desc acq_common_desc;
 335 };
 336
 337 struct ena_admin_aq_create_cq_cmd {
 338         struct ena_admin_aq_common_desc aq_common_descriptor;
 339
 340         /* 4:0 : reserved5
 341          * 5 : interrupt_mode_enabled - if set, cq operates
 342          *    in interrupt mode, otherwise - polling
 343          * 7:6 : reserved6
 344          */
 345         uint8_t cq_caps_1;
 346
 347         /* 4:0 : cq_entry_size_words - size of CQ entry in
 348          *    32-bit words, valid values: 4, 8.
 349          * 7:5 : reserved7
 350          */
 351         uint8_t cq_caps_2;
 352
 353         /* completion queue depth in # of entries. must be power of 2 */
 354         uint16_t cq_depth;
 355
 356         /* msix vector assigned to this cq */
 357         uint32_t msix_vector;
 358
 359         /* cq physical base address in OS memory. CQ must be physically
 360          * contiguous
 361          */
 362         struct ena_common_mem_addr cq_ba;
 363 };
 364
 365 struct ena_admin_acq_create_cq_resp_desc {
 366         struct ena_admin_acq_common_desc acq_common_desc;
 367
 368         uint16_t cq_idx;
 369
 370         /* actual cq depth in number of entries */
 371         uint16_t cq_actual_depth;
 372
 373         uint32_t numa_node_register_offset;
 374
 375         uint32_t cq_head_db_register_offset;
 376
 377         uint32_t cq_interrupt_unmask_register_offset;
 378 };
 379
 380 struct ena_admin_aq_destroy_cq_cmd {
 381         struct ena_admin_aq_common_desc aq_common_descriptor;
 382
 383         uint16_t cq_idx;
 384
 385         uint16_t reserved1;
 386 };
 387
 388 struct ena_admin_acq_destroy_cq_resp_desc {
 389         struct ena_admin_acq_common_desc acq_common_desc;
 390 };
 391
 392 /* ENA AQ Get Statistics command. Extended statistics are placed in control
 393  * buffer pointed by AQ entry
 394  */
 395 struct ena_admin_aq_get_stats_cmd {
 396         struct ena_admin_aq_common_desc aq_common_descriptor;
 397
 398         union {
 399                 /* command specific inline data */
 400                 uint32_t inline_data_w1[3];
 401
 402                 struct ena_admin_ctrl_buff_info control_buffer;
 403         } u;
 404
 405         /* stats type as defined in enum ena_admin_get_stats_type */
 406         uint8_t type;
 407
 408         /* stats scope defined in enum ena_admin_get_stats_scope */
 409         uint8_t scope;
 410
 411         uint16_t reserved3;
 412
 413         /* queue id. used when scope is specific_queue */
 414         uint16_t queue_idx;
 415
 416         /* device id, value 0xFFFF means mine. only privileged device can get
 417          *    stats of other device
 418          */
 419         uint16_t device_id;
 420 };
 421
 422 /* Basic Statistics Command. */
 423 struct ena_admin_basic_stats {
 424         uint32_t tx_bytes_low;
 425
 426         uint32_t tx_bytes_high;
 427
 428         uint32_t tx_pkts_low;
 429
 430         uint32_t tx_pkts_high;
 431
 432         uint32_t rx_bytes_low;
 433
 434         uint32_t rx_bytes_high;
 435
 436         uint32_t rx_pkts_low;
 437
 438         uint32_t rx_pkts_high;
 439
 440         uint32_t rx_drops_low;
 441
 442         uint32_t rx_drops_high;
 443 };
 444
 445 struct ena_admin_acq_get_stats_resp {
 446         struct ena_admin_acq_common_desc acq_common_desc;
 447
 448         struct ena_admin_basic_stats basic_stats;
 449 };
 450
 451 struct ena_admin_get_set_feature_common_desc {
 452         /* 1:0 : select - 0x1 - current value; 0x3 - default
 453          *    value
 454          * 7:3 : reserved3
 455          */
 456         uint8_t flags;
 457
 458         /* as appears in ena_admin_aq_feature_id */
 459         uint8_t feature_id;
 460
 461         uint16_t reserved16;
 462 };
 463
 464 struct ena_admin_device_attr_feature_desc {
 465         uint32_t impl_id;
 466
 467         uint32_t device_version;
 468
 469         /* bitmap of ena_admin_aq_feature_id */
 470         uint32_t supported_features;
 471
 472         uint32_t reserved3;
 473
 474         /* Indicates how many bits are used physical address access. */
 475         uint32_t phys_addr_width;
 476
 477         /* Indicates how many bits are used virtual address access. */
 478         uint32_t virt_addr_width;
 479
 480         /* unicast MAC address (in Network byte order) */
 481         uint8_t mac_addr[6];
 482
 483         uint8_t reserved7[2];
 484
 485         uint32_t max_mtu;
 486 };
 487
 488 struct ena_admin_queue_feature_desc {
 489         /* including LLQs */
 490         uint32_t max_sq_num;
 491
 492         uint32_t max_sq_depth;
 493
 494         uint32_t max_cq_num;
 495
 496         uint32_t max_cq_depth;
 497
 498         uint32_t max_llq_num;
 499
 500         uint32_t max_llq_depth;
 501
 502         uint32_t max_header_size;
 503
 504         /* Maximum Descriptors number, including meta descriptor, allowed for
 505          *    a single Tx packet
 506          */
 507         uint16_t max_packet_tx_descs;
 508
 509         /* Maximum Descriptors number allowed for a single Rx packet */
 510         uint16_t max_packet_rx_descs;
 511 };
 512
 513 struct ena_admin_set_feature_mtu_desc {
 514         /* exclude L2 */
 515         uint32_t mtu;
 516 };
 517
 518 struct ena_admin_set_feature_host_attr_desc {
 519         /* host OS info base address in OS memory. host info is 4KB of
 520          * physically contiguous
 521          */
 522         struct ena_common_mem_addr os_info_ba;
 523
 524         /* host debug area base address in OS memory. debug area must be
 525          * physically contiguous
 526          */
 527         struct ena_common_mem_addr debug_ba;
 528
 529         /* debug area size */
 530         uint32_t debug_area_size;
 531 };
 532
 533 struct ena_admin_feature_intr_moder_desc {
 534         /* interrupt delay granularity in usec */
 535         uint16_t intr_delay_resolution;
 536
 537         uint16_t reserved;
 538 };
 539
 540 struct ena_admin_get_feature_link_desc {
 541         /* Link speed in Mb */
 542         uint32_t speed;
 543
 544         /* bit field of enum ena_admin_link types */
 545         uint32_t supported;
 546
 547         /* 0 : autoneg
 548          * 1 : duplex - Full Duplex
 549          * 31:2 : reserved2
 550          */
 551         uint32_t flags;
 552 };
 553
 554 struct ena_admin_feature_aenq_desc {
 555         /* bitmask for AENQ groups the device can report */
 556         uint32_t supported_groups;
 557
 558         /* bitmask for AENQ groups to report */
 559         uint32_t enabled_groups;
 560 };
 561
 562 struct ena_admin_feature_offload_desc {
 563         /* 0 : TX_L3_csum_ipv4
 564          * 1 : TX_L4_ipv4_csum_part - The checksum field
 565          *    should be initialized with pseudo header checksum
 566          * 2 : TX_L4_ipv4_csum_full
 567          * 3 : TX_L4_ipv6_csum_part - The checksum field
 568          *    should be initialized with pseudo header checksum
 569          * 4 : TX_L4_ipv6_csum_full
 570          * 5 : tso_ipv4
 571          * 6 : tso_ipv6
 572          * 7 : tso_ecn
 573          */
 574         uint32_t tx;
 575
 576         /* Receive side supported stateless offload
 577          * 0 : RX_L3_csum_ipv4 - IPv4 checksum
 578          * 1 : RX_L4_ipv4_csum - TCP/UDP/IPv4 checksum
 579          * 2 : RX_L4_ipv6_csum - TCP/UDP/IPv6 checksum
 580          * 3 : RX_hash - Hash calculation
 581          */
 582         uint32_t rx_supported;
 583
 584         uint32_t rx_enabled;
 585 };
 586
 587 enum ena_admin_hash_functions {
 588         ENA_ADMIN_TOEPLITZ      = 1,
 589
 590         ENA_ADMIN_CRC32         = 2,
 591 };
 592
 593 struct ena_admin_feature_rss_flow_hash_control {
 594         uint32_t keys_num;
 595
 596         uint32_t reserved;
 597
 598         uint32_t key[10];
 599 };
 600
 601 struct ena_admin_feature_rss_flow_hash_function {
 602         /* 7:0 : funcs - bitmask of ena_admin_hash_functions */
 603         uint32_t supported_func;
 604
 605         /* 7:0 : selected_func - bitmask of
 606          *    ena_admin_hash_functions
 607          */
 608         uint32_t selected_func;
 609
 610         /* initial value */
 611         uint32_t init_val;
 612 };
 613
 614 /* RSS flow hash protocols */
 615 enum ena_admin_flow_hash_proto {
 616         ENA_ADMIN_RSS_TCP4      = 0,
 617
 618         ENA_ADMIN_RSS_UDP4      = 1,
 619
 620         ENA_ADMIN_RSS_TCP6      = 2,
 621
 622         ENA_ADMIN_RSS_UDP6      = 3,
 623
 624         ENA_ADMIN_RSS_IP4       = 4,
 625
 626         ENA_ADMIN_RSS_IP6       = 5,
 627
 628         ENA_ADMIN_RSS_IP4_FRAG  = 6,
 629
 630         ENA_ADMIN_RSS_NOT_IP    = 7,
 631
 632         /* TCPv6 with extension header */
 633         ENA_ADMIN_RSS_TCP6_EX   = 8,
 634
 635         /* IPv6 with extension header */
 636         ENA_ADMIN_RSS_IP6_EX    = 9,
 637
 638         ENA_ADMIN_RSS_PROTO_NUM = 16,
 639 };
 640
 641 /* RSS flow hash fields */
 642 enum ena_admin_flow_hash_fields {
 643         /* Ethernet Dest Addr */
 644         ENA_ADMIN_RSS_L2_DA     = BIT(0),
 645
 646         /* Ethernet Src Addr */
 647         ENA_ADMIN_RSS_L2_SA     = BIT(1),
 648
 649         /* ipv4/6 Dest Addr */
 650         ENA_ADMIN_RSS_L3_DA     = BIT(2),
 651
 652         /* ipv4/6 Src Addr */
 653         ENA_ADMIN_RSS_L3_SA     = BIT(3),
 654
 655         /* tcp/udp Dest Port */
 656         ENA_ADMIN_RSS_L4_DP     = BIT(4),
 657
 658         /* tcp/udp Src Port */
 659         ENA_ADMIN_RSS_L4_SP     = BIT(5),
 660 };
 661
 662 struct ena_admin_proto_input {
 663         /* flow hash fields (bitwise according to ena_admin_flow_hash_fields) */
 664         uint16_t fields;
 665
 666         uint16_t reserved2;
 667 };
 668
 669 struct ena_admin_feature_rss_hash_control {
 670         struct ena_admin_proto_input supported_fields[ENA_ADMIN_RSS_PROTO_NUM];
 671
 672         struct ena_admin_proto_input selected_fields[ENA_ADMIN_RSS_PROTO_NUM];
 673
 674         struct ena_admin_proto_input reserved2[ENA_ADMIN_RSS_PROTO_NUM];
 675
 676         struct ena_admin_proto_input reserved3[ENA_ADMIN_RSS_PROTO_NUM];
 677 };
 678
 679 struct ena_admin_feature_rss_flow_hash_input {
 680         /* supported hash input sorting
 681          * 1 : L3_sort - support swap L3 addresses if DA is
 682          *    smaller than SA
 683          * 2 : L4_sort - support swap L4 ports if DP smaller
 684          *    SP
 685          */
 686         uint16_t supported_input_sort;
 687
 688         /* enabled hash input sorting
 689          * 1 : enable_L3_sort - enable swap L3 addresses if
 690          *    DA smaller than SA
 691          * 2 : enable_L4_sort - enable swap L4 ports if DP
 692          *    smaller than SP
 693          */
 694         uint16_t enabled_input_sort;
 695 };
 696
 697 enum ena_admin_os_type {
 698         ENA_ADMIN_OS_LINUX      = 1,
 699
 700         ENA_ADMIN_OS_WIN        = 2,
 701
 702         ENA_ADMIN_OS_DPDK       = 3,
 703
 704         ENA_ADMIN_OS_FREEBSD    = 4,
 705
 706         ENA_ADMIN_OS_IPXE       = 5,
 707 };
 708
 709 struct ena_admin_host_info {
 710         /* defined in enum ena_admin_os_type */
 711         uint32_t os_type;
 712
 713         /* os distribution string format */
 714         uint8_t os_dist_str[128];
 715
 716         /* OS distribution numeric format */
 717         uint32_t os_dist;
 718
 719         /* kernel version string format */
 720         uint8_t kernel_ver_str[32];
 721
 722         /* Kernel version numeric format */
 723         uint32_t kernel_ver;
 724
 725         /* 7:0 : major
 726          * 15:8 : minor
 727          * 23:16 : sub_minor
 728          */
 729         uint32_t driver_version;
 730
 731         /* features bitmap */
 732         uint32_t supported_network_features[4];
 733 };
 734
 735 struct ena_admin_rss_ind_table_entry {
 736         uint16_t cq_idx;
 737
 738         uint16_t reserved;
 739 };
 740
 741 struct ena_admin_feature_rss_ind_table {
 742         /* min supported table size (2^min_size) */
 743         uint16_t min_size;
 744
 745         /* max supported table size (2^max_size) */
 746         uint16_t max_size;
 747
 748         /* table size (2^size) */
 749         uint16_t size;
 750
 751         uint16_t reserved;
 752
 753         /* index of the inline entry. 0xFFFFFFFF means invalid */
 754         uint32_t inline_index;
 755
 756         /* used for updating single entry, ignored when setting the entire
 757          * table through the control buffer.
 758          */
 759         struct ena_admin_rss_ind_table_entry inline_entry;
 760 };
 761
 762 /* When hint value is 0, driver should use it's own predefined value */
 763 struct ena_admin_ena_hw_hints {
 764         /* value in ms */
 765         uint16_t mmio_read_timeout;
 766
 767         /* value in ms */
 768         uint16_t driver_watchdog_timeout;
 769
 770         /* Per packet tx completion timeout. value in ms */
 771         uint16_t missing_tx_completion_timeout;
 772
 773         uint16_t missed_tx_completion_count_threshold_to_reset;
 774
 775         /* value in ms */
 776         uint16_t admin_completion_tx_timeout;
 777
 778         uint16_t netdev_wd_timeout;
 779
 780         uint16_t max_tx_sgl_size;
 781
 782         uint16_t max_rx_sgl_size;
 783
 784         uint16_t reserved[8];
 785 };
 786
 787 struct ena_admin_get_feat_cmd {
 788         struct ena_admin_aq_common_desc aq_common_descriptor;
 789
 790         struct ena_admin_ctrl_buff_info control_buffer;
 791
 792         struct ena_admin_get_set_feature_common_desc feat_common;
 793
 794         uint32_t raw[11];
 795 };
 796
 797 struct ena_admin_get_feat_resp {
 798         struct ena_admin_acq_common_desc acq_common_desc;
 799
 800         union {
 801                 uint32_t raw[14];
 802
 803                 struct ena_admin_device_attr_feature_desc dev_attr;
 804
 805                 struct ena_admin_queue_feature_desc max_queue;
 806
 807                 struct ena_admin_feature_aenq_desc aenq;
 808
 809                 struct ena_admin_get_feature_link_desc link;
 810
 811                 struct ena_admin_feature_offload_desc offload;
 812
 813                 struct ena_admin_feature_rss_flow_hash_function flow_hash_func;
 814
 815                 struct ena_admin_feature_rss_flow_hash_input flow_hash_input;
 816
 817                 struct ena_admin_feature_rss_ind_table ind_table;
 818
 819                 struct ena_admin_feature_intr_moder_desc intr_moderation;
 820
 821                 struct ena_admin_ena_hw_hints hw_hints;
 822         } u;
 823 };
 824
 825 struct ena_admin_set_feat_cmd {
 826         struct ena_admin_aq_common_desc aq_common_descriptor;
 827
 828         struct ena_admin_ctrl_buff_info control_buffer;
 829
 830         struct ena_admin_get_set_feature_common_desc feat_common;
 831
 832         union {
 833                 uint32_t raw[11];
 834
 835                 /* mtu size */
 836                 struct ena_admin_set_feature_mtu_desc mtu;
 837
 838                 /* host attributes */
 839                 struct ena_admin_set_feature_host_attr_desc host_attr;
 840
 841                 /* AENQ configuration */
 842                 struct ena_admin_feature_aenq_desc aenq;
 843
 844                 /* rss flow hash function */
 845                 struct ena_admin_feature_rss_flow_hash_function flow_hash_func;
 846
 847                 /* rss flow hash input */
 848                 struct ena_admin_feature_rss_flow_hash_input flow_hash_input;
 849
 850                 /* rss indirection table */
 851                 struct ena_admin_feature_rss_ind_table ind_table;
 852         } u;
 853 };
 854
 855 struct ena_admin_set_feat_resp {
 856         struct ena_admin_acq_common_desc acq_common_desc;
 857
 858         union {
 859                 uint32_t raw[14];
 860         } u;
 861 };
 862
 863 struct ena_admin_aenq_common_desc {
 864         uint16_t group;
 865
 866         uint16_t syndrom;
 867
 868         /* 0 : phase */
 869         uint8_t flags;
 870
 871         uint8_t reserved1[3];
 872
 873         uint32_t timestamp_low;
 874
 875         uint32_t timestamp_high;
 876 };
 877
 878 /* asynchronous event notification groups */
 879 enum ena_admin_aenq_group {
 880         ENA_ADMIN_LINK_CHANGE           = 0,
 881
 882         ENA_ADMIN_FATAL_ERROR           = 1,
 883
 884         ENA_ADMIN_WARNING               = 2,
 885
 886         ENA_ADMIN_NOTIFICATION          = 3,
 887
 888         ENA_ADMIN_KEEP_ALIVE            = 4,
 889
 890         ENA_ADMIN_AENQ_GROUPS_NUM       = 5,
 891 };
 892
 893 enum ena_admin_aenq_notification_syndrom {
 894         ENA_ADMIN_SUSPEND       = 0,
 895
 896         ENA_ADMIN_RESUME        = 1,
 897
 898         ENA_ADMIN_UPDATE_HINTS  = 2,
 899 };
 900
 901 struct ena_admin_aenq_entry {
 902         struct ena_admin_aenq_common_desc aenq_common_desc;
 903
 904         /* command specific inline data */
 905         uint32_t inline_data_w4[12];
 906 };
 907
 908 struct ena_admin_aenq_link_change_desc {
 909         struct ena_admin_aenq_common_desc aenq_common_desc;
 910
 911         /* 0 : link_status */
 912         uint32_t flags;
 913 };
 914
 915 struct ena_admin_aenq_keep_alive_desc {
 916         struct ena_admin_aenq_common_desc aenq_common_desc;
 917
 918         uint32_t rx_drops_low;
 919
 920         uint32_t rx_drops_high;
 921 };
 922
 923 struct ena_admin_ena_mmio_req_read_less_resp {
 924         uint16_t req_id;
 925
 926         uint16_t reg_off;
 927
 928         /* value is valid when poll is cleared */
 929         uint32_t reg_val;
 930 };
 931
 932 /* aq_common_desc */
 933 #define ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0)
 934 #define ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK BIT(0)
 935 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT 1
 936 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK BIT(1)
 937 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT 2
 938 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK BIT(2)
 939
 940 /* sq */
 941 #define ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT 5
 942 #define ENA_ADMIN_SQ_SQ_DIRECTION_MASK GENMASK(7, 5)
 943
 944 /* acq_common_desc */
 945 #define ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0)
 946 #define ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK BIT(0)
 947
 948 /* aq_create_sq_cmd */
 949 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT 5
 950 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK GENMASK(7, 5)
 951 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK GENMASK(3, 0)
 952 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT 4
 953 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK GENMASK(6, 4)
 954 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK BIT(0)
 955
 956 /* aq_create_cq_cmd */
 957 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT 5
 958 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK BIT(5)
 959 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK GENMASK(4, 0)
 960
 961 /* get_set_feature_common_desc */
 962 #define ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK GENMASK(1, 0)
 963
 964 /* get_feature_link_desc */
 965 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK BIT(0)
 966 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT 1
 967 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK BIT(1)
 968
 969 /* feature_offload_desc */
 970 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK BIT(0)
 971 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT 1
 972 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK BIT(1)
 973 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT 2
 974 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK BIT(2)
 975 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT 3
 976 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK BIT(3)
 977 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT 4
 978 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK BIT(4)
 979 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT 5
 980 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK BIT(5)
 981 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT 6
 982 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK BIT(6)
 983 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT 7
 984 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK BIT(7)
 985 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK BIT(0)
 986 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT 1
 987 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK BIT(1)
 988 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT 2
 989 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK BIT(2)
 990 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT 3
 991 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK BIT(3)
 992
 993 /* feature_rss_flow_hash_function */
 994 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK GENMASK(7, 0)
 995 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK GENMASK(7, 0)
 996
 997 /* feature_rss_flow_hash_input */
 998 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT 1
 999 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK BIT(1)
1000 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT 2
1001 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK BIT(2)
1002 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT 1
1003 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK BIT(1)
1004 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT 2
1005 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK BIT(2)
1006
1007 /* host_info */
1008 #define ENA_ADMIN_HOST_INFO_MAJOR_MASK GENMASK(7, 0)
1009 #define ENA_ADMIN_HOST_INFO_MINOR_SHIFT 8
1010 #define ENA_ADMIN_HOST_INFO_MINOR_MASK GENMASK(15, 8)
1011 #define ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT 16
1012 #define ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK GENMASK(23, 16)
1013
1014 /* aenq_common_desc */
1015 #define ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK BIT(0)
1016
1017 /* aenq_link_change_desc */
1018 #define ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK BIT(0)
1019
1020 #if !defined(ENA_DEFS_LINUX_MAINLINE)
1021 static inline uint16_t get_ena_admin_aq_common_desc_command_id(const struct ena_admin_aq_common_desc *p)
1022 {
1023         return p->command_id & ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK;
1024 }
1025
1026 static inline void set_ena_admin_aq_common_desc_command_id(struct ena_admin_aq_common_desc *p, uint16_t val)
1027 {
1028         p->command_id |= val & ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK;
1029 }
1030
1031 static inline uint8_t get_ena_admin_aq_common_desc_phase(const struct ena_admin_aq_common_desc *p)
1032 {
1033         return p->flags & ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK;
1034 }
1035
1036 static inline void set_ena_admin_aq_common_desc_phase(struct ena_admin_aq_common_desc *p, uint8_t val)
1037 {
1038         p->flags |= val & ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK;
1039 }
1040
1041 static inline uint8_t get_ena_admin_aq_common_desc_ctrl_data(const struct ena_admin_aq_common_desc *p)
1042 {
1043         return (p->flags & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK) >> ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT;
1044 }
1045
1046 static inline void set_ena_admin_aq_common_desc_ctrl_data(struct ena_admin_aq_common_desc *p, uint8_t val)
1047 {
1048         p->flags |= (val << ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT) & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK;
1049 }
1050
1051 static inline uint8_t get_ena_admin_aq_common_desc_ctrl_data_indirect(const struct ena_admin_aq_common_desc *p)
1052 {
1053         return (p->flags & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK) >> ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT;
1054 }
1055
1056 static inline void set_ena_admin_aq_common_desc_ctrl_data_indirect(struct ena_admin_aq_common_desc *p, uint8_t val)
1057 {
1058         p->flags |= (val << ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT) & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
1059 }
1060
1061 static inline uint8_t get_ena_admin_sq_sq_direction(const struct ena_admin_sq *p)
1062 {
1063         return (p->sq_identity & ENA_ADMIN_SQ_SQ_DIRECTION_MASK) >> ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT;
1064 }
1065
1066 static inline void set_ena_admin_sq_sq_direction(struct ena_admin_sq *p, uint8_t val)
1067 {
1068         p->sq_identity |= (val << ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT) & ENA_ADMIN_SQ_SQ_DIRECTION_MASK;
1069 }
1070
1071 static inline uint16_t get_ena_admin_acq_common_desc_command_id(const struct ena_admin_acq_common_desc *p)
1072 {
1073         return p->command & ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK;
1074 }
1075
1076 static inline void set_ena_admin_acq_common_desc_command_id(struct ena_admin_acq_common_desc *p, uint16_t val)
1077 {
1078         p->command |= val & ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK;
1079 }
1080
1081 static inline uint8_t get_ena_admin_acq_common_desc_phase(const struct ena_admin_acq_common_desc *p)
1082 {
1083         return p->flags & ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK;
1084 }
1085
1086 static inline void set_ena_admin_acq_common_desc_phase(struct ena_admin_acq_common_desc *p, uint8_t val)
1087 {
1088         p->flags |= val & ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK;
1089 }
1090
1091 static inline uint8_t get_ena_admin_aq_create_sq_cmd_sq_direction(const struct ena_admin_aq_create_sq_cmd *p)
1092 {
1093         return (p->sq_identity & ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK) >> ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT;
1094 }
1095
1096 static inline void set_ena_admin_aq_create_sq_cmd_sq_direction(struct ena_admin_aq_create_sq_cmd *p, uint8_t val)
1097 {
1098         p->sq_identity |= (val << ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT) & ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK;
1099 }
1100
1101 static inline uint8_t get_ena_admin_aq_create_sq_cmd_placement_policy(const struct ena_admin_aq_create_sq_cmd *p)
1102 {
1103         return p->sq_caps_2 & ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK;
1104 }
1105
1106 static inline void set_ena_admin_aq_create_sq_cmd_placement_policy(struct ena_admin_aq_create_sq_cmd *p, uint8_t val)
1107 {
1108         p->sq_caps_2 |= val & ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK;
1109 }
1110
1111 static inline uint8_t get_ena_admin_aq_create_sq_cmd_completion_policy(const struct ena_admin_aq_create_sq_cmd *p)
1112 {
1113         return (p->sq_caps_2 & ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK) >> ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT;
1114 }
1115
1116 static inline void set_ena_admin_aq_create_sq_cmd_completion_policy(struct ena_admin_aq_create_sq_cmd *p, uint8_t val)
1117 {
1118         p->sq_caps_2 |= (val << ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT) & ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK;
1119 }
1120
1121 static inline uint8_t get_ena_admin_aq_create_sq_cmd_is_physically_contiguous(const struct ena_admin_aq_create_sq_cmd *p)
1122 {
1123         return p->sq_caps_3 & ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK;
1124 }
1125
1126 static inline void set_ena_admin_aq_create_sq_cmd_is_physically_contiguous(struct ena_admin_aq_create_sq_cmd *p, uint8_t val)
1127 {
1128         p->sq_caps_3 |= val & ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK;
1129 }
1130
1131 static inline uint8_t get_ena_admin_aq_create_cq_cmd_interrupt_mode_enabled(const struct ena_admin_aq_create_cq_cmd *p)
1132 {
1133         return (p->cq_caps_1 & ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK) >> ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT;
1134 }
1135
1136 static inline void set_ena_admin_aq_create_cq_cmd_interrupt_mode_enabled(struct ena_admin_aq_create_cq_cmd *p, uint8_t val)
1137 {
1138         p->cq_caps_1 |= (val << ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT) & ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK;
1139 }
1140
1141 static inline uint8_t get_ena_admin_aq_create_cq_cmd_cq_entry_size_words(const struct ena_admin_aq_create_cq_cmd *p)
1142 {
1143         return p->cq_caps_2 & ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK;
1144 }
1145
1146 static inline void set_ena_admin_aq_create_cq_cmd_cq_entry_size_words(struct ena_admin_aq_create_cq_cmd *p, uint8_t val)
1147 {
1148         p->cq_caps_2 |= val & ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK;
1149 }
1150
1151 static inline uint8_t get_ena_admin_get_set_feature_common_desc_select(const struct ena_admin_get_set_feature_common_desc *p)
1152 {
1153         return p->flags & ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK;
1154 }
1155
1156 static inline void set_ena_admin_get_set_feature_common_desc_select(struct ena_admin_get_set_feature_common_desc *p, uint8_t val)
1157 {
1158         p->flags |= val & ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK;
1159 }
1160
1161 static inline uint32_t get_ena_admin_get_feature_link_desc_autoneg(const struct ena_admin_get_feature_link_desc *p)
1162 {
1163         return p->flags & ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK;
1164 }
1165
1166 static inline void set_ena_admin_get_feature_link_desc_autoneg(struct ena_admin_get_feature_link_desc *p, uint32_t val)
1167 {
1168         p->flags |= val & ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK;
1169 }
1170
1171 static inline uint32_t get_ena_admin_get_feature_link_desc_duplex(const struct ena_admin_get_feature_link_desc *p)
1172 {
1173         return (p->flags & ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK) >> ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT;
1174 }
1175
1176 static inline void set_ena_admin_get_feature_link_desc_duplex(struct ena_admin_get_feature_link_desc *p, uint32_t val)
1177 {
1178         p->flags |= (val << ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT) & ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK;
1179 }
1180
1181 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L3_csum_ipv4(const struct ena_admin_feature_offload_desc *p)
1182 {
1183         return p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK;
1184 }
1185
1186 static inline void set_ena_admin_feature_offload_desc_TX_L3_csum_ipv4(struct ena_admin_feature_offload_desc *p, uint32_t val)
1187 {
1188         p->tx |= val & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK;
1189 }
1190
1191 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_part(const struct ena_admin_feature_offload_desc *p)
1192 {
1193         return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT;
1194 }
1195
1196 static inline void set_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_part(struct ena_admin_feature_offload_desc *p, uint32_t val)
1197 {
1198         p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK;
1199 }
1200
1201 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_full(const struct ena_admin_feature_offload_desc *p)
1202 {
1203         return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT;
1204 }
1205
1206 static inline void set_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_full(struct ena_admin_feature_offload_desc *p, uint32_t val)
1207 {
1208         p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK;
1209 }
1210
1211 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_part(const struct ena_admin_feature_offload_desc *p)
1212 {
1213         return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT;
1214 }
1215
1216 static inline void set_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_part(struct ena_admin_feature_offload_desc *p, uint32_t val)
1217 {
1218         p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK;
1219 }
1220
1221 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_full(const struct ena_admin_feature_offload_desc *p)
1222 {
1223         return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT;
1224 }
1225
1226 static inline void set_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_full(struct ena_admin_feature_offload_desc *p, uint32_t val)
1227 {
1228         p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK;
1229 }
1230
1231 static inline uint32_t get_ena_admin_feature_offload_desc_tso_ipv4(const struct ena_admin_feature_offload_desc *p)
1232 {
1233         return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT;
1234 }
1235
1236 static inline void set_ena_admin_feature_offload_desc_tso_ipv4(struct ena_admin_feature_offload_desc *p, uint32_t val)
1237 {
1238         p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK;
1239 }
1240
1241 static inline uint32_t get_ena_admin_feature_offload_desc_tso_ipv6(const struct ena_admin_feature_offload_desc *p)
1242 {
1243         return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT;
1244 }
1245
1246 static inline void set_ena_admin_feature_offload_desc_tso_ipv6(struct ena_admin_feature_offload_desc *p, uint32_t val)
1247 {
1248         p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK;
1249 }
1250
1251 static inline uint32_t get_ena_admin_feature_offload_desc_tso_ecn(const struct ena_admin_feature_offload_desc *p)
1252 {
1253         return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT;
1254 }
1255
1256 static inline void set_ena_admin_feature_offload_desc_tso_ecn(struct ena_admin_feature_offload_desc *p, uint32_t val)
1257 {
1258         p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK;
1259 }
1260
1261 static inline uint32_t get_ena_admin_feature_offload_desc_RX_L3_csum_ipv4(const struct ena_admin_feature_offload_desc *p)
1262 {
1263         return p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK;
1264 }
1265
1266 static inline void set_ena_admin_feature_offload_desc_RX_L3_csum_ipv4(struct ena_admin_feature_offload_desc *p, uint32_t val)
1267 {
1268         p->rx_supported |= val & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK;
1269 }
1270
1271 static inline uint32_t get_ena_admin_feature_offload_desc_RX_L4_ipv4_csum(const struct ena_admin_feature_offload_desc *p)
1272 {
1273         return (p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT;
1274 }
1275
1276 static inline void set_ena_admin_feature_offload_desc_RX_L4_ipv4_csum(struct ena_admin_feature_offload_desc *p, uint32_t val)
1277 {
1278         p->rx_supported |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK;
1279 }
1280
1281 static inline uint32_t get_ena_admin_feature_offload_desc_RX_L4_ipv6_csum(const struct ena_admin_feature_offload_desc *p)
1282 {
1283         return (p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT;
1284 }
1285
1286 static inline void set_ena_admin_feature_offload_desc_RX_L4_ipv6_csum(struct ena_admin_feature_offload_desc *p, uint32_t val)
1287 {
1288         p->rx_supported |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK;
1289 }
1290
1291 static inline uint32_t get_ena_admin_feature_offload_desc_RX_hash(const struct ena_admin_feature_offload_desc *p)
1292 {
1293         return (p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT;
1294 }
1295
1296 static inline void set_ena_admin_feature_offload_desc_RX_hash(struct ena_admin_feature_offload_desc *p, uint32_t val)
1297 {
1298         p->rx_supported |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK;
1299 }
1300
1301 static inline uint32_t get_ena_admin_feature_rss_flow_hash_function_funcs(const struct ena_admin_feature_rss_flow_hash_function *p)
1302 {
1303         return p->supported_func & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK;
1304 }
1305
1306 static inline void set_ena_admin_feature_rss_flow_hash_function_funcs(struct ena_admin_feature_rss_flow_hash_function *p, uint32_t val)
1307 {
1308         p->supported_func |= val & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK;
1309 }
1310
1311 static inline uint32_t get_ena_admin_feature_rss_flow_hash_function_selected_func(const struct ena_admin_feature_rss_flow_hash_function *p)
1312 {
1313         return p->selected_func & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK;
1314 }
1315
1316 static inline void set_ena_admin_feature_rss_flow_hash_function_selected_func(struct ena_admin_feature_rss_flow_hash_function *p, uint32_t val)
1317 {
1318         p->selected_func |= val & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK;
1319 }
1320
1321 static inline uint16_t get_ena_admin_feature_rss_flow_hash_input_L3_sort(const struct ena_admin_feature_rss_flow_hash_input *p)
1322 {
1323         return (p->supported_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT;
1324 }
1325
1326 static inline void set_ena_admin_feature_rss_flow_hash_input_L3_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val)
1327 {
1328         p->supported_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK;
1329 }
1330
1331 static inline uint16_t get_ena_admin_feature_rss_flow_hash_input_L4_sort(const struct ena_admin_feature_rss_flow_hash_input *p)
1332 {
1333         return (p->supported_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT;
1334 }
1335
1336 static inline void set_ena_admin_feature_rss_flow_hash_input_L4_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val)
1337 {
1338         p->supported_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK;
1339 }
1340
1341 static inline uint16_t get_ena_admin_feature_rss_flow_hash_input_enable_L3_sort(const struct ena_admin_feature_rss_flow_hash_input *p)
1342 {
1343         return (p->enabled_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT;
1344 }
1345
1346 static inline void set_ena_admin_feature_rss_flow_hash_input_enable_L3_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val)
1347 {
1348         p->enabled_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK;
1349 }
1350
1351 static inline uint16_t get_ena_admin_feature_rss_flow_hash_input_enable_L4_sort(const struct ena_admin_feature_rss_flow_hash_input *p)
1352 {
1353         return (p->enabled_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT;
1354 }
1355
1356 static inline void set_ena_admin_feature_rss_flow_hash_input_enable_L4_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val)
1357 {
1358         p->enabled_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK;
1359 }
1360
1361 static inline uint32_t get_ena_admin_host_info_major(const struct ena_admin_host_info *p)
1362 {
1363         return p->driver_version & ENA_ADMIN_HOST_INFO_MAJOR_MASK;
1364 }
1365
1366 static inline void set_ena_admin_host_info_major(struct ena_admin_host_info *p, uint32_t val)
1367 {
1368         p->driver_version |= val & ENA_ADMIN_HOST_INFO_MAJOR_MASK;
1369 }
1370
1371 static inline uint32_t get_ena_admin_host_info_minor(const struct ena_admin_host_info *p)
1372 {
1373         return (p->driver_version & ENA_ADMIN_HOST_INFO_MINOR_MASK) >> ENA_ADMIN_HOST_INFO_MINOR_SHIFT;
1374 }
1375
1376 static inline void set_ena_admin_host_info_minor(struct ena_admin_host_info *p, uint32_t val)
1377 {
1378         p->driver_version |= (val << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) & ENA_ADMIN_HOST_INFO_MINOR_MASK;
1379 }
1380
1381 static inline uint32_t get_ena_admin_host_info_sub_minor(const struct ena_admin_host_info *p)
1382 {
1383         return (p->driver_version & ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK) >> ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT;
1384 }
1385
1386 static inline void set_ena_admin_host_info_sub_minor(struct ena_admin_host_info *p, uint32_t val)
1387 {
1388         p->driver_version |= (val << ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT) & ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK;
1389 }
1390
1391 static inline uint8_t get_ena_admin_aenq_common_desc_phase(const struct ena_admin_aenq_common_desc *p)
1392 {
1393         return p->flags & ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK;
1394 }
1395
1396 static inline void set_ena_admin_aenq_common_desc_phase(struct ena_admin_aenq_common_desc *p, uint8_t val)
1397 {
1398         p->flags |= val & ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK;
1399 }
1400
1401 static inline uint32_t get_ena_admin_aenq_link_change_desc_link_status(const struct ena_admin_aenq_link_change_desc *p)
1402 {
1403         return p->flags & ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK;
1404 }
1405
1406 static inline void set_ena_admin_aenq_link_change_desc_link_status(struct ena_admin_aenq_link_change_desc *p, uint32_t val)
1407 {
1408         p->flags |= val & ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK;
1409 }
1410
1411 #endif /* !defined(ENA_DEFS_LINUX_MAINLINE) */
1412 #endif /*_ENA_ADMIN_H_ */