sys/platform/pc32/i386/initcpu.c

   1 /*
   2  * Copyright (c) KATO Takenori, 1997, 1998.
   3  *
   4  * All rights reserved.  Unpublished rights reserved under the copyright
   5  * laws of Japan.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  *
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer as
  13  *    the first lines of this file unmodified.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  19  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  20  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  21  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  22  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  23  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  27  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  *
  29  * $FreeBSD: src/sys/i386/i386/initcpu.c,v 1.19.2.9 2003/04/05 13:47:19 dwmalone Exp $
  30  * $DragonFly: src/sys/platform/pc32/i386/initcpu.c,v 1.10 2006/12/23 00:27:03 swildner Exp $
  31  */
  32
  33 #include "opt_cpu.h"
  34
  35 #include <sys/param.h>
  36 #include <sys/kernel.h>
  37 #include <sys/systm.h>
  38 #include <sys/sysctl.h>
  39
  40 #include <machine/cputypes.h>
  41 #include <machine/md_var.h>
  42 #include <machine/specialreg.h>
  43
  44 void initializecpu(void);
  45 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
  46 void    enable_K5_wt_alloc(void);
  47 void    enable_K6_wt_alloc(void);
  48 void    enable_K6_2_wt_alloc(void);
  49 #endif
  50
  51 #ifdef I486_CPU
  52 static void init_5x86(void);
  53 static void init_bluelightning(void);
  54 static void init_486dlc(void);
  55 static void init_cy486dx(void);
  56 #ifdef CPU_I486_ON_386
  57 static void init_i486_on_386(void);
  58 #endif
  59 static void init_6x86(void);
  60 #endif /* I486_CPU */
  61
  62 #ifdef I686_CPU
  63 static void     init_6x86MX(void);
  64 static void     init_ppro(void);
  65 static void     init_mendocino(void);
  66 #endif
  67
  68 static int      hw_instruction_sse;
  69 SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD,
  70     &hw_instruction_sse, 0, "SIMD/MMX2 instructions available in CPU");
  71
  72 /* Must *NOT* be BSS or locore will bzero these after setting them */
  73 int     cpu = 0;                /* Are we 386, 386sx, 486, etc? */
  74 u_int   cpu_feature = 0;        /* Feature flags */
  75 u_int   cpu_feature2 = 0;       /* Feature flags */
  76 u_int   amd_feature = 0;        /* AMD feature flags */
  77 u_int   amd_feature2 = 0;       /* AMD feature flags */
  78 u_int   amd_pminfo = 0;         /* AMD advanced power management info */
  79 u_int   via_feature_rng = 0;    /* VIA RNG features */
  80 u_int   via_feature_xcrypt = 0; /* VIA ACE features */
  81 u_int   cpu_high = 0;           /* Highest arg to CPUID */
  82 u_int   cpu_id = 0;             /* Stepping ID */
  83 u_int   cpu_procinfo = 0;       /* HyperThreading Info / Brand Index / CLFUSH */
  84 u_int   cpu_procinfo2 = 0;      /* Multicore info */
  85 char    cpu_vendor[20] = "";    /* CPU Origin code */
  86 u_int   cpu_vendor_id = 0;      /* CPU vendor ID */
  87
  88 SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD,
  89         &via_feature_rng, 0, "VIA C3/C7 RNG feature available in CPU");
  90 SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD,
  91         &via_feature_xcrypt, 0, "VIA C3/C7 xcrypt feature available in CPU");
  92
  93 #ifndef CPU_DISABLE_SSE
  94 u_int   cpu_fxsr;               /* SSE enabled */
  95 #endif
  96
  97 #ifdef I486_CPU
  98 /*
  99  * IBM Blue Lightning
 100  */
 101 static void
 102 init_bluelightning(void)
 103 {
 104         u_long  eflags;
 105
 106         eflags = read_eflags();
 107         cpu_disable_intr();
 108
 109         load_cr0(rcr0() | CR0_CD | CR0_NW);
 110         invd();
 111
 112 #ifdef CPU_BLUELIGHTNING_FPU_OP_CACHE
 113         wrmsr(0x1000, 0x9c92LL);        /* FP operand can be cacheable on Cyrix FPU */
 114 #else
 115         wrmsr(0x1000, 0x1c92LL);        /* Intel FPU */
 116 #endif
 117         /* Enables 13MB and 0-640KB cache. */
 118         wrmsr(0x1001, (0xd0LL << 32) | 0x3ff);
 119 #ifdef CPU_BLUELIGHTNING_3X
 120         wrmsr(0x1002, 0x04000000LL);    /* Enables triple-clock mode. */
 121 #else
 122         wrmsr(0x1002, 0x03000000LL);    /* Enables double-clock mode. */
 123 #endif
 124
 125         /* Enable caching in CR0. */
 126         load_cr0(rcr0() & ~(CR0_CD | CR0_NW));  /* CD = 0 and NW = 0 */
 127         invd();
 128         write_eflags(eflags);
 129 }
 130
 131 /*
 132  * Cyrix 486SLC/DLC/SR/DR series
 133  */
 134 static void
 135 init_486dlc(void)
 136 {
 137         u_long  eflags;
 138         u_char  ccr0;
 139
 140         eflags = read_eflags();
 141         cpu_disable_intr();
 142         invd();
 143
 144         ccr0 = read_cyrix_reg(CCR0);
 145 #ifndef CYRIX_CACHE_WORKS
 146         ccr0 |= CCR0_NC1 | CCR0_BARB;
 147         write_cyrix_reg(CCR0, ccr0);
 148         invd();
 149 #else
 150         ccr0 &= ~CCR0_NC0;
 151 #ifndef CYRIX_CACHE_REALLY_WORKS
 152         ccr0 |= CCR0_NC1 | CCR0_BARB;
 153 #else
 154         ccr0 |= CCR0_NC1;
 155 #endif
 156 #ifdef CPU_DIRECT_MAPPED_CACHE
 157         ccr0 |= CCR0_CO;                        /* Direct mapped mode. */
 158 #endif
 159         write_cyrix_reg(CCR0, ccr0);
 160
 161         /* Clear non-cacheable region. */
 162         write_cyrix_reg(NCR1+2, NCR_SIZE_0K);
 163         write_cyrix_reg(NCR2+2, NCR_SIZE_0K);
 164         write_cyrix_reg(NCR3+2, NCR_SIZE_0K);
 165         write_cyrix_reg(NCR4+2, NCR_SIZE_0K);
 166
 167         write_cyrix_reg(0, 0);  /* dummy write */
 168
 169         /* Enable caching in CR0. */
 170         load_cr0(rcr0() & ~(CR0_CD | CR0_NW));  /* CD = 0 and NW = 0 */
 171         invd();
 172 #endif /* !CYRIX_CACHE_WORKS */
 173         write_eflags(eflags);
 174 }
 175
 176
 177 /*
 178  * Cyrix 486S/DX series
 179  */
 180 static void
 181 init_cy486dx(void)
 182 {
 183         u_long  eflags;
 184         u_char  ccr2;
 185
 186         eflags = read_eflags();
 187         cpu_disable_intr();
 188         invd();
 189
 190         ccr2 = read_cyrix_reg(CCR2);
 191 #ifdef CPU_SUSP_HLT
 192         ccr2 |= CCR2_SUSP_HLT;
 193 #endif
 194
 195         write_cyrix_reg(CCR2, ccr2);
 196         write_eflags(eflags);
 197 }
 198
 199
 200 /*
 201  * Cyrix 5x86
 202  */
 203 static void
 204 init_5x86(void)
 205 {
 206         u_long  eflags;
 207         u_char  ccr2, ccr3, ccr4, pcr0;
 208
 209         eflags = read_eflags();
 210         cpu_disable_intr();
 211
 212         load_cr0(rcr0() | CR0_CD | CR0_NW);
 213         wbinvd();
 214
 215         read_cyrix_reg(CCR3);           /* dummy */
 216
 217         /* Initialize CCR2. */
 218         ccr2 = read_cyrix_reg(CCR2);
 219         ccr2 |= CCR2_WB;
 220 #ifdef CPU_SUSP_HLT
 221         ccr2 |= CCR2_SUSP_HLT;
 222 #else
 223         ccr2 &= ~CCR2_SUSP_HLT;
 224 #endif
 225         ccr2 |= CCR2_WT1;
 226         write_cyrix_reg(CCR2, ccr2);
 227
 228         /* Initialize CCR4. */
 229         ccr3 = read_cyrix_reg(CCR3);
 230         write_cyrix_reg(CCR3, CCR3_MAPEN0);
 231
 232         ccr4 = read_cyrix_reg(CCR4);
 233         ccr4 |= CCR4_DTE;
 234         ccr4 |= CCR4_MEM;
 235 #ifdef CPU_FASTER_5X86_FPU
 236         ccr4 |= CCR4_FASTFPE;
 237 #else
 238         ccr4 &= ~CCR4_FASTFPE;
 239 #endif
 240         ccr4 &= ~CCR4_IOMASK;
 241         /********************************************************************
 242          * WARNING: The "BIOS Writers Guide" mentions that I/O recovery time
 243          * should be 0 for errata fix.
 244          ********************************************************************/
 245 #ifdef CPU_IORT
 246         ccr4 |= CPU_IORT & CCR4_IOMASK;
 247 #endif
 248         write_cyrix_reg(CCR4, ccr4);
 249
 250         /* Initialize PCR0. */
 251         /****************************************************************
 252          * WARNING: RSTK_EN and LOOP_EN could make your system unstable.
 253          * BTB_EN might make your system unstable.
 254          ****************************************************************/
 255         pcr0 = read_cyrix_reg(PCR0);
 256 #ifdef CPU_RSTK_EN
 257         pcr0 |= PCR0_RSTK;
 258 #else
 259         pcr0 &= ~PCR0_RSTK;
 260 #endif
 261 #ifdef CPU_BTB_EN
 262         pcr0 |= PCR0_BTB;
 263 #else
 264         pcr0 &= ~PCR0_BTB;
 265 #endif
 266 #ifdef CPU_LOOP_EN
 267         pcr0 |= PCR0_LOOP;
 268 #else
 269         pcr0 &= ~PCR0_LOOP;
 270 #endif
 271
 272         /****************************************************************
 273          * WARNING: if you use a memory mapped I/O device, don't use
 274          * DISABLE_5X86_LSSER option, which may reorder memory mapped
 275          * I/O access.
 276          * IF YOUR MOTHERBOARD HAS PCI BUS, DON'T DISABLE LSSER.
 277          ****************************************************************/
 278 #ifdef CPU_DISABLE_5X86_LSSER
 279         pcr0 &= ~PCR0_LSSER;
 280 #else
 281         pcr0 |= PCR0_LSSER;
 282 #endif
 283         write_cyrix_reg(PCR0, pcr0);
 284
 285         /* Restore CCR3. */
 286         write_cyrix_reg(CCR3, ccr3);
 287
 288         read_cyrix_reg(0x80);           /* dummy */
 289
 290         /* Unlock NW bit in CR0. */
 291         write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
 292         load_cr0((rcr0() & ~CR0_CD) | CR0_NW);  /* CD = 0, NW = 1 */
 293         /* Lock NW bit in CR0. */
 294         write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
 295
 296         write_eflags(eflags);
 297 }
 298
 299 #ifdef CPU_I486_ON_386
 300 /*
 301  * There are i486 based upgrade products for i386 machines.
 302  * In this case, BIOS doesn't enables CPU cache.
 303  */
 304 void
 305 init_i486_on_386(void)
 306 {
 307         u_long  eflags;
 308
 309         eflags = read_eflags();
 310         cpu_disable_intr();
 311
 312         load_cr0(rcr0() & ~(CR0_CD | CR0_NW));  /* CD = 0, NW = 0 */
 313
 314         write_eflags(eflags);
 315 }
 316 #endif
 317
 318 /*
 319  * Cyrix 6x86
 320  *
 321  * XXX - What should I do here?  Please let me know.
 322  */
 323 static void
 324 init_6x86(void)
 325 {
 326         u_long  eflags;
 327         u_char  ccr3, ccr4;
 328
 329         eflags = read_eflags();
 330         cpu_disable_intr();
 331
 332         load_cr0(rcr0() | CR0_CD | CR0_NW);
 333         wbinvd();
 334
 335         /* Initialize CCR0. */
 336         write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1);
 337
 338         /* Initialize CCR1. */
 339 #ifdef CPU_CYRIX_NO_LOCK
 340         write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) | CCR1_NO_LOCK);
 341 #else
 342         write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) & ~CCR1_NO_LOCK);
 343 #endif
 344
 345         /* Initialize CCR2. */
 346 #ifdef CPU_SUSP_HLT
 347         write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT);
 348 #else
 349         write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT);
 350 #endif
 351
 352         ccr3 = read_cyrix_reg(CCR3);
 353         write_cyrix_reg(CCR3, CCR3_MAPEN0);
 354
 355         /* Initialize CCR4. */
 356         ccr4 = read_cyrix_reg(CCR4);
 357         ccr4 |= CCR4_DTE;
 358         ccr4 &= ~CCR4_IOMASK;
 359 #ifdef CPU_IORT
 360         write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK));
 361 #else
 362         write_cyrix_reg(CCR4, ccr4 | 7);
 363 #endif
 364
 365         /* Initialize CCR5. */
 366 #ifdef CPU_WT_ALLOC
 367         write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC);
 368 #endif
 369
 370         /* Restore CCR3. */
 371         write_cyrix_reg(CCR3, ccr3);
 372
 373         /* Unlock NW bit in CR0. */
 374         write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
 375
 376         /*
 377          * Earlier revision of the 6x86 CPU could crash the system if
 378          * L1 cache is in write-back mode.
 379          */
 380         if ((cyrix_did & 0xff00) > 0x1600)
 381                 load_cr0(rcr0() & ~(CR0_CD | CR0_NW));  /* CD = 0 and NW = 0 */
 382         else {
 383                 /* Revision 2.6 and lower. */
 384 #ifdef CYRIX_CACHE_REALLY_WORKS
 385                 load_cr0(rcr0() & ~(CR0_CD | CR0_NW));  /* CD = 0 and NW = 0 */
 386 #else
 387                 load_cr0((rcr0() & ~CR0_CD) | CR0_NW);  /* CD = 0 and NW = 1 */
 388 #endif
 389         }
 390
 391         /* Lock NW bit in CR0. */
 392         write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
 393
 394         write_eflags(eflags);
 395 }
 396 #endif /* I486_CPU */
 397
 398 #ifdef I686_CPU
 399 /*
 400  * Cyrix 6x86MX (code-named M2)
 401  *
 402  * XXX - What should I do here?  Please let me know.
 403  */
 404 static void
 405 init_6x86MX(void)
 406 {
 407         u_long  eflags;
 408         u_char  ccr3, ccr4;
 409
 410         eflags = read_eflags();
 411         cpu_disable_intr();
 412
 413         load_cr0(rcr0() | CR0_CD | CR0_NW);
 414         wbinvd();
 415
 416         /* Initialize CCR0. */
 417         write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1);
 418
 419         /* Initialize CCR1. */
 420 #ifdef CPU_CYRIX_NO_LOCK
 421         write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) | CCR1_NO_LOCK);
 422 #else
 423         write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) & ~CCR1_NO_LOCK);
 424 #endif
 425
 426         /* Initialize CCR2. */
 427 #ifdef CPU_SUSP_HLT
 428         write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT);
 429 #else
 430         write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT);
 431 #endif
 432
 433         ccr3 = read_cyrix_reg(CCR3);
 434         write_cyrix_reg(CCR3, CCR3_MAPEN0);
 435
 436         /* Initialize CCR4. */
 437         ccr4 = read_cyrix_reg(CCR4);
 438         ccr4 &= ~CCR4_IOMASK;
 439 #ifdef CPU_IORT
 440         write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK));
 441 #else
 442         write_cyrix_reg(CCR4, ccr4 | 7);
 443 #endif
 444
 445         /* Initialize CCR5. */
 446 #ifdef CPU_WT_ALLOC
 447         write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC);
 448 #endif
 449
 450         /* Restore CCR3. */
 451         write_cyrix_reg(CCR3, ccr3);
 452
 453         /* Unlock NW bit in CR0. */
 454         write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
 455
 456         load_cr0(rcr0() & ~(CR0_CD | CR0_NW));  /* CD = 0 and NW = 0 */
 457
 458         /* Lock NW bit in CR0. */
 459         write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
 460
 461         write_eflags(eflags);
 462 }
 463
 464 static void
 465 init_ppro(void)
 466 {
 467 #ifndef SMP
 468         u_int64_t       apicbase;
 469
 470         /*
 471          * Local APIC should be diabled in UP kernel.
 472          */
 473         apicbase = rdmsr(0x1b);
 474         apicbase &= ~0x800LL;
 475         wrmsr(0x1b, apicbase);
 476 #endif
 477 }
 478
 479 /*
 480  * Initialize BBL_CR_CTL3 (Control register 3: used to configure the
 481  * L2 cache).
 482  */
 483 void
 484 init_mendocino(void)
 485 {
 486 #ifdef CPU_PPRO2CELERON
 487         u_long  eflags;
 488         u_int64_t       bbl_cr_ctl3;
 489
 490         eflags = read_eflags();
 491         cpu_disable_intr();
 492
 493         load_cr0(rcr0() | CR0_CD | CR0_NW);
 494         wbinvd();
 495
 496         bbl_cr_ctl3 = rdmsr(0x11e);
 497
 498         /* If the L2 cache is configured, do nothing. */
 499         if (!(bbl_cr_ctl3 & 1)) {
 500                 bbl_cr_ctl3 = 0x134052bLL;
 501
 502                 /* Set L2 Cache Latency (Default: 5). */
 503 #ifdef  CPU_CELERON_L2_LATENCY
 504 #if CPU_L2_LATENCY > 15
 505 #error invalid CPU_L2_LATENCY.
 506 #endif
 507                 bbl_cr_ctl3 |= CPU_L2_LATENCY << 1;
 508 #else
 509                 bbl_cr_ctl3 |= 5 << 1;
 510 #endif
 511                 wrmsr(0x11e, bbl_cr_ctl3);
 512         }
 513
 514         load_cr0(rcr0() & ~(CR0_CD | CR0_NW));
 515         write_eflags(eflags);
 516 #endif /* CPU_PPRO2CELERON */
 517 }
 518
 519 /*
 520  * Initialize special VIA C3/C7 features
 521  */
 522 static void
 523 init_via(void)
 524 {
 525         u_int regs[4], val;
 526         u_int64_t msreg;
 527
 528         do_cpuid(0xc0000000, regs);
 529         val = regs[0];
 530         if (val >= 0xc0000001) {
 531                 do_cpuid(0xc0000001, regs);
 532                 val = regs[3];
 533         } else
 534                 val = 0;
 535
 536         /* Enable RNG if present and disabled */
 537         if (val & VIA_CPUID_HAS_RNG) {
 538                 if (!(val & VIA_CPUID_DO_RNG)) {
 539                         msreg = rdmsr(0x110B);
 540                         msreg |= 0x40;
 541                         wrmsr(0x110B, msreg);
 542                 }
 543                 via_feature_rng = VIA_HAS_RNG;
 544         }
 545         /* Enable AES engine if present and disabled */
 546         if (val & VIA_CPUID_HAS_ACE) {
 547                 if (!(val & VIA_CPUID_DO_ACE)) {
 548                         msreg = rdmsr(0x1107);
 549                         msreg |= (0x01 << 28);
 550                         wrmsr(0x1107, msreg);
 551                 }
 552                 via_feature_xcrypt |= VIA_HAS_AES;
 553         }
 554         /* Enable ACE2 engine if present and disabled */
 555         if (val & VIA_CPUID_HAS_ACE2) {
 556                 if (!(val & VIA_CPUID_DO_ACE2)) {
 557                         msreg = rdmsr(0x1107);
 558                         msreg |= (0x01 << 28);
 559                         wrmsr(0x1107, msreg);
 560                 }
 561                 via_feature_xcrypt |= VIA_HAS_AESCTR;
 562         }
 563         /* Enable SHA engine if present and disabled */
 564         if (val & VIA_CPUID_HAS_PHE) {
 565                 if (!(val & VIA_CPUID_DO_PHE)) {
 566                         msreg = rdmsr(0x1107);
 567                         msreg |= (0x01 << 28/**/);
 568                         wrmsr(0x1107, msreg);
 569                 }
 570                 via_feature_xcrypt |= VIA_HAS_SHA;
 571         }
 572         /* Enable MM engine if present and disabled */
 573         if (val & VIA_CPUID_HAS_PMM) {
 574                 if (!(val & VIA_CPUID_DO_PMM)) {
 575                         msreg = rdmsr(0x1107);
 576                         msreg |= (0x01 << 28/**/);
 577                         wrmsr(0x1107, msreg);
 578                 }
 579                 via_feature_xcrypt |= VIA_HAS_MM;
 580         }
 581 }
 582
 583 #endif /* I686_CPU */
 584
 585 /*
 586  * Initialize CR4 (Control register 4) to enable SSE instructions.
 587  */
 588 void
 589 enable_sse(void)
 590 {
 591 #ifndef CPU_DISABLE_SSE
 592         if ((cpu_feature & CPUID_SSE) && (cpu_feature & CPUID_FXSR)) {
 593                 load_cr4(rcr4() | CR4_FXSR | CR4_XMM);
 594                 cpu_fxsr = hw_instruction_sse = 1;
 595         }
 596 #endif
 597 }
 598
 599 #ifdef I686_CPU
 600 static
 601 void
 602 init_686_amd(void)
 603 {
 604 #ifdef CPU_ATHLON_SSE_HACK
 605         /*
 606          * Sometimes the BIOS doesn't enable SSE instructions.
 607          * According to AMD document 20734, the mobile
 608          * Duron, the (mobile) Athlon 4 and the Athlon MP
 609          * support SSE. These correspond to cpu_id 0x66X
 610          * or 0x67X.
 611          */
 612         if ((cpu_feature & CPUID_XMM) == 0 &&
 613             ((cpu_id & ~0xf) == 0x660 ||
 614              (cpu_id & ~0xf) == 0x670 ||
 615              (cpu_id & ~0xf) == 0x680)) {
 616                 u_int regs[4];
 617                 wrmsr(0xC0010015, rdmsr(0xC0010015) & ~0x08000);
 618                 do_cpuid(1, regs);
 619                 cpu_feature = regs[3];
 620         }
 621 #endif
 622 #ifdef CPU_AMD64X2_INTR_SPAM
 623         /*
 624          * Set the LINTEN bit in the HyperTransport Transaction
 625          * Control Register.
 626          *
 627          * This will cause EXTINT and NMI interrupts routed over the
 628          * hypertransport bus to be fed into the LAPIC LINT0/LINT1.  If
 629          * the bit isn't set, the interrupts will go to the general cpu
 630          * INTR/NMI pins.  On a dual-core cpu the interrupt winds up
 631          * going to BOTH cpus.  The first cpu that does the interrupt ack
 632          * cycle will get the correct interrupt.  The second cpu that does
 633          * it will get a spurious interrupt vector (typically IRQ 7).
 634          */
 635         if ((cpu_id & 0xff0) == 0xf30) {
 636             int32_t tcr;
 637             outl(0x0cf8,
 638                     (1 << 31) | /* enable */
 639                     (0 << 16) | /* bus */
 640                     (24 << 11) |        /* dev (cpu + 24) */
 641                     (0 << 8) |  /* func */
 642                     0x68                /* reg */
 643             );
 644             tcr = inl(0xcfc);
 645             if ((tcr & 0x00010000) == 0) {
 646                     outl(0xcfc, tcr|0x00010000);
 647                     additional_cpu_info("AMD: Rerouting HyperTransport "
 648                                         "EXTINT/NMI to APIC");
 649             }
 650             outl(0x0cf8, 0);
 651         }
 652 #endif
 653 }
 654 #endif /* I686_CPU */
 655
 656 void
 657 initializecpu(void)
 658 {
 659         switch (cpu) {
 660 #ifdef I486_CPU
 661         case CPU_BLUE:
 662                 init_bluelightning();
 663                 break;
 664         case CPU_486DLC:
 665                 init_486dlc();
 666                 break;
 667         case CPU_CY486DX:
 668                 init_cy486dx();
 669                 break;
 670         case CPU_M1SC:
 671                 init_5x86();
 672                 break;
 673 #ifdef CPU_I486_ON_386
 674         case CPU_486:
 675                 init_i486_on_386();
 676                 break;
 677 #endif
 678         case CPU_M1:
 679                 init_6x86();
 680                 break;
 681 #endif /* I486_CPU */
 682 #ifdef I686_CPU
 683         case CPU_M2:
 684                 init_6x86MX();
 685                 break;
 686         case CPU_686:
 687                 if (cpu_vendor_id == CPU_VENDOR_INTEL) {
 688                         switch (cpu_id & 0xff0) {
 689                         case 0x610:
 690                                 init_ppro();
 691                                 break;
 692                         case 0x660:
 693                                 init_mendocino();
 694                                 break;
 695                         }
 696                 } else if (cpu_vendor_id == CPU_VENDOR_AMD) {
 697                         init_686_amd();
 698                 } else if (cpu_vendor_id == CPU_VENDOR_CENTAUR) {
 699                         switch (cpu_id & 0xff0) {
 700                         case 0x690:
 701                                 if ((cpu_id & 0xf) < 3)
 702                                         break;
 703                                 /* fall through. */
 704                         case 0x6a0:
 705                         case 0x6d0:
 706                         case 0x6f0:
 707                                 init_via();
 708                                 break;
 709                         default:
 710                                 break;
 711                         }
 712                 }
 713                 break;
 714 #endif
 715         default:
 716                 break;
 717         }
 718         enable_sse();
 719 }
 720
 721 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
 722 /*
 723  * Enable write allocate feature of AMD processors.
 724  * Following two functions require the Maxmem variable being set.
 725  */
 726 void
 727 enable_K5_wt_alloc(void)
 728 {
 729         u_int64_t       msr;
 730
 731         /*
 732          * Write allocate is supported only on models 1, 2, and 3, with
 733          * a stepping of 4 or greater.
 734          */
 735         if (((cpu_id & 0xf0) > 0) && ((cpu_id & 0x0f) > 3)) {
 736                 cpu_disable_intr();
 737                 msr = rdmsr(0x83);              /* HWCR */
 738                 wrmsr(0x83, msr & !(0x10));
 739
 740                 /*
 741                  * We have to tell the chip where the top of memory is,
 742                  * since video cards could have frame bufferes there,
 743                  * memory-mapped I/O could be there, etc.
 744                  */
 745                 if(Maxmem > 0)
 746                   msr = Maxmem / 16;
 747                 else
 748                   msr = 0;
 749                 msr |= AMD_WT_ALLOC_TME | AMD_WT_ALLOC_FRE;
 750
 751                 /*
 752                  * There is no way to know wheter 15-16M hole exists or not.
 753                  * Therefore, we disable write allocate for this range.
 754                  */
 755                 wrmsr(0x86, 0x0ff00f0);
 756                 msr |= AMD_WT_ALLOC_PRE;
 757                 wrmsr(0x85, msr);
 758
 759                 msr=rdmsr(0x83);
 760                 wrmsr(0x83, msr|0x10); /* enable write allocate */
 761
 762                 cpu_enable_intr();
 763         }
 764 }
 765
 766 void
 767 enable_K6_wt_alloc(void)
 768 {
 769         quad_t  size;
 770         u_int64_t       whcr;
 771         u_long  eflags;
 772
 773         eflags = read_eflags();
 774         cpu_disable_intr();
 775         wbinvd();
 776
 777 #ifdef CPU_DISABLE_CACHE
 778         /*
 779          * Certain K6-2 box becomes unstable when write allocation is
 780          * enabled.
 781          */
 782         /*
 783          * The AMD-K6 processer provides the 64-bit Test Register 12(TR12),
 784          * but only the Cache Inhibit(CI) (bit 3 of TR12) is suppported.
 785          * All other bits in TR12 have no effect on the processer's operation.
 786          * The I/O Trap Restart function (bit 9 of TR12) is always enabled
 787          * on the AMD-K6.
 788          */
 789         wrmsr(0x0000000e, (u_int64_t)0x0008);
 790 #endif
 791         /* Don't assume that memory size is aligned with 4M. */
 792         if (Maxmem > 0)
 793           size = ((Maxmem >> 8) + 3) >> 2;
 794         else
 795           size = 0;
 796
 797         /* Limit is 508M bytes. */
 798         if (size > 0x7f)
 799                 size = 0x7f;
 800         whcr = (rdmsr(0xc0000082) & ~(0x7fLL << 1)) | (size << 1);
 801
 802 #if defined(NO_MEMORY_HOLE)
 803         if (whcr & (0x7fLL << 1))
 804                 whcr |=  0x0001LL;
 805 #else
 806         /*
 807          * There is no way to know wheter 15-16M hole exists or not.
 808          * Therefore, we disable write allocate for this range.
 809          */
 810         whcr &= ~0x0001LL;
 811 #endif
 812         wrmsr(0x0c0000082, whcr);
 813
 814         write_eflags(eflags);
 815 }
 816
 817 void
 818 enable_K6_2_wt_alloc(void)
 819 {
 820         quad_t  size;
 821         u_int64_t       whcr;
 822         u_long  eflags;
 823
 824         eflags = read_eflags();
 825         cpu_disable_intr();
 826         wbinvd();
 827
 828 #ifdef CPU_DISABLE_CACHE
 829         /*
 830          * Certain K6-2 box becomes unstable when write allocation is
 831          * enabled.
 832          */
 833         /*
 834          * The AMD-K6 processer provides the 64-bit Test Register 12(TR12),
 835          * but only the Cache Inhibit(CI) (bit 3 of TR12) is suppported.
 836          * All other bits in TR12 have no effect on the processer's operation.
 837          * The I/O Trap Restart function (bit 9 of TR12) is always enabled
 838          * on the AMD-K6.
 839          */
 840         wrmsr(0x0000000e, (u_int64_t)0x0008);
 841 #endif
 842         /* Don't assume that memory size is aligned with 4M. */
 843         if (Maxmem > 0)
 844           size = ((Maxmem >> 8) + 3) >> 2;
 845         else
 846           size = 0;
 847
 848         /* Limit is 4092M bytes. */
 849         if (size > 0x3fff)
 850                 size = 0x3ff;
 851         whcr = (rdmsr(0xc0000082) & ~(0x3ffLL << 22)) | (size << 22);
 852
 853 #if defined(NO_MEMORY_HOLE)
 854         if (whcr & (0x3ffLL << 22))
 855                 whcr |=  1LL << 16;
 856 #else
 857         /*
 858          * There is no way to know wheter 15-16M hole exists or not.
 859          * Therefore, we disable write allocate for this range.
 860          */
 861         whcr &= ~(1LL << 16);
 862 #endif
 863         wrmsr(0x0c0000082, whcr);
 864
 865         write_eflags(eflags);
 866 }
 867 #endif /* I585_CPU && CPU_WT_ALLOC */
 868
 869 #include "opt_ddb.h"
 870 #ifdef DDB
 871 #include <ddb/ddb.h>
 872
 873 DB_SHOW_COMMAND(cyrixreg, cyrixreg)
 874 {
 875         u_long  eflags;
 876         u_int   cr0;
 877         u_char  ccr1, ccr2, ccr3;
 878         u_char  ccr0 = 0, ccr4 = 0, ccr5 = 0, pcr0 = 0;
 879
 880         cr0 = rcr0();
 881         if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
 882                 eflags = read_eflags();
 883                 cpu_disable_intr();
 884
 885
 886                 if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX)) {
 887                         ccr0 = read_cyrix_reg(CCR0);
 888                 }
 889                 ccr1 = read_cyrix_reg(CCR1);
 890                 ccr2 = read_cyrix_reg(CCR2);
 891                 ccr3 = read_cyrix_reg(CCR3);
 892                 if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) {
 893                         write_cyrix_reg(CCR3, CCR3_MAPEN0);
 894                         ccr4 = read_cyrix_reg(CCR4);
 895                         if ((cpu == CPU_M1) || (cpu == CPU_M2))
 896                                 ccr5 = read_cyrix_reg(CCR5);
 897                         else
 898                                 pcr0 = read_cyrix_reg(PCR0);
 899                         write_cyrix_reg(CCR3, ccr3);            /* Restore CCR3. */
 900                 }
 901                 write_eflags(eflags);
 902
 903                 if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX))
 904                         kprintf("CCR0=%x, ", (u_int)ccr0);
 905
 906                 kprintf("CCR1=%x, CCR2=%x, CCR3=%x",
 907                         (u_int)ccr1, (u_int)ccr2, (u_int)ccr3);
 908                 if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) {
 909                         kprintf(", CCR4=%x, ", (u_int)ccr4);
 910                         if (cpu == CPU_M1SC)
 911                                 kprintf("PCR0=%x\n", pcr0);
 912                         else
 913                                 kprintf("CCR5=%x\n", ccr5);
 914                 }
 915         }
 916         kprintf("CR0=%x\n", cr0);
 917 }
 918 #endif /* DDB */