sys/dev/misc/ecc/ecc_e31200.c

   1 /*
   2  * Copyright (c) 2011 The DragonFly Project.  All rights reserved.
   3  *
   4  * This code is derived from software contributed to The DragonFly Project
   5  * by Sepherosa Ziehau <sepherosa@gmail.com>
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  *
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in
  15  *    the documentation and/or other materials provided with the
  16  *    distribution.
  17  * 3. Neither the name of The DragonFly Project nor the names of its
  18  *    contributors may be used to endorse or promote products derived
  19  *    from this software without specific, prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  24  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
  25  * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  26  * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
  27  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  28  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  29  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  30  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  31  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  32  * SUCH DAMAGE.
  33  */
  34
  35 #include <sys/param.h>
  36 #include <sys/systm.h>
  37 #include <sys/bus.h>
  38 #include <sys/kernel.h>
  39 #include <sys/malloc.h>
  40 #include <sys/bitops.h>
  41
  42 #include <bus/pci/pcivar.h>
  43 #include <bus/pci/pcireg.h>
  44 #include <bus/pci/pcibus.h>
  45 #include <bus/pci/pci_cfgreg.h>
  46 #include <bus/pci/pcib_private.h>
  47
  48 #include <vm/pmap.h>
  49
  50 #include "pcib_if.h"
  51
  52 #include <dev/misc/ecc/ecc_e31200_reg.h>
  53
  54 #define ECC_E31200_VER_1        1       /* Sandy Bridge */
  55 #define ECC_E31200_VER_2        2       /* Ivy Bridge */
  56 #define ECC_E31200_VER_3        3       /* Haswell */
  57
  58 struct ecc_e31200_memctrl {
  59         uint16_t        vid;
  60         uint16_t        did;
  61         const char      *desc;
  62         int             ver;            /* ECC_E31200_VER_ */
  63 };
  64
  65 struct ecc_e31200_softc {
  66         device_t        ecc_device;
  67         device_t        ecc_mydev;
  68         struct callout  ecc_callout;
  69         int             ecc_ver;        /* ECC_E31200_VER_ */
  70         volatile uint8_t *ecc_addr;
  71 };
  72
  73 #define CSR_READ_4(sc, ofs)     (*(volatile uint32_t *)((sc)->ecc_addr + (ofs)))
  74
  75 #define ecc_printf(sc, fmt, arg...) \
  76         device_printf((sc)->ecc_mydev, fmt , ##arg)
  77
  78 static int      ecc_e31200_probe(device_t);
  79 static int      ecc_e31200_attach(device_t);
  80 static int      ecc_e31200_detach(device_t);
  81 static void     ecc_e31200_shutdown(device_t);
  82
  83 static void     ecc_e31200_chaninfo(struct ecc_e31200_softc *, uint32_t,
  84                     const char *);
  85 static void     ecc_e31200_status(struct ecc_e31200_softc *);
  86 static void     ecc_e31200_callout(void *);
  87 static void     ecc_e31200_errlog(struct ecc_e31200_softc *);
  88 static void     ecc_e31200_errlog_ch(struct ecc_e31200_softc *, int, int,
  89                     const char *);
  90
  91 static const struct ecc_e31200_memctrl ecc_memctrls[] = {
  92         { 0x8086, 0x0108, "Intel E3-1200 memory controller",
  93           ECC_E31200_VER_1 },
  94         { 0x8086, 0x0158, "Intel E3-1200 v2 memory controller",
  95           ECC_E31200_VER_2 },
  96         { 0x8086, 0x0c08, "Intel E3-1200 v3 memory controller",
  97           ECC_E31200_VER_3 },
  98         { 0, 0, NULL } /* required last entry */
  99 };
 100
 101 static device_method_t ecc_e31200_methods[] = {
 102         /* Device interface */
 103         DEVMETHOD(device_probe,         ecc_e31200_probe),
 104         DEVMETHOD(device_attach,        ecc_e31200_attach),
 105         DEVMETHOD(device_detach,        ecc_e31200_detach),
 106         DEVMETHOD(device_shutdown,      ecc_e31200_shutdown),
 107         DEVMETHOD(device_suspend,       bus_generic_suspend),
 108         DEVMETHOD(device_resume,        bus_generic_resume),
 109         DEVMETHOD_END
 110 };
 111
 112 static driver_t ecc_e31200_driver = {
 113         "ecc",
 114         ecc_e31200_methods,
 115         sizeof(struct ecc_e31200_softc)
 116 };
 117 static devclass_t ecc_devclass;
 118 DRIVER_MODULE(ecc_e31200, hostb, ecc_e31200_driver, ecc_devclass, NULL, NULL);
 119 MODULE_DEPEND(ecc_e31200, pci, 1, 1, 1);
 120
 121 static int
 122 ecc_e31200_probe(device_t dev)
 123 {
 124         const struct ecc_e31200_memctrl *mc;
 125         uint16_t vid, did;
 126
 127         vid = pci_get_vendor(dev);
 128         did = pci_get_device(dev);
 129
 130         for (mc = ecc_memctrls; mc->desc != NULL; ++mc) {
 131                 if (mc->vid == vid && mc->did == did) {
 132                         struct ecc_e31200_softc *sc = device_get_softc(dev);
 133
 134                         device_set_desc(dev, mc->desc);
 135                         sc->ecc_mydev = dev;
 136                         sc->ecc_device = device_get_parent(dev);
 137                         sc->ecc_ver = mc->ver;
 138                         return (0);
 139                 }
 140         }
 141         return (ENXIO);
 142 }
 143
 144 static int
 145 ecc_e31200_attach(device_t dev)
 146 {
 147         struct ecc_e31200_softc *sc = device_get_softc(dev);
 148         uint32_t capa, dmfc, mch_barlo, mch_barhi;
 149         uint64_t mch_bar;
 150         int bus, slot, dmfc_parsed = 1;
 151
 152         callout_init_mp(&sc->ecc_callout);
 153
 154         dev = sc->ecc_device; /* XXX */
 155
 156         bus = pci_get_bus(dev);
 157         slot = pci_get_slot(dev);
 158
 159         capa = pcib_read_config(dev, bus, slot, 0, PCI_E31200_CAPID0_A, 4);
 160
 161         if (sc->ecc_ver == ECC_E31200_VER_1) {
 162                 dmfc = __SHIFTOUT(capa, PCI_E31200_CAPID0_A_DMFC);
 163         } else { /* V2/V3 */
 164                 uint32_t capb;
 165
 166                 capb = pcib_read_config(dev, bus, slot, 0,
 167                     PCI_E31200_CAPID0_B, 4);
 168                 dmfc = __SHIFTOUT(capb, PCI_E31200_CAPID0_B_DMFC);
 169         }
 170
 171         if (dmfc == PCI_E31200_CAPID0_DMFC_1067) {
 172                 ecc_printf(sc, "CAP DDR3 1067 ");
 173         } else if (dmfc == PCI_E31200_CAPID0_DMFC_1333) {
 174                 ecc_printf(sc, "CAP DDR3 1333 ");
 175         } else {
 176                 if (sc->ecc_ver == ECC_E31200_VER_1) {
 177                         if (dmfc == PCI_E31200_CAPID0_DMFC_V1_ALL)
 178                                 ecc_printf(sc, "no CAP ");
 179                         else
 180                                 dmfc_parsed = 0;
 181                 } else { /* V2/V3 */
 182                         if (dmfc == PCI_E31200_CAPID0_DMFC_1600)
 183                                 ecc_printf(sc, "CAP DDR3 1600 ");
 184                         else if (dmfc == PCI_E31200_CAPID0_DMFC_1867)
 185                                 ecc_printf(sc, "CAP DDR3 1867 ");
 186                         else if (dmfc == PCI_E31200_CAPID0_DMFC_2133)
 187                                 ecc_printf(sc, "CAP DDR3 2133 ");
 188                         else if (dmfc == PCI_E31200_CAPID0_DMFC_2400)
 189                                 ecc_printf(sc, "CAP DDR3 2400 ");
 190                         else if (dmfc == PCI_E31200_CAPID0_DMFC_2667)
 191                                 ecc_printf(sc, "CAP DDR3 2667 ");
 192                         else if (dmfc == PCI_E31200_CAPID0_DMFC_2933)
 193                                 ecc_printf(sc, "CAP DDR3 2933 ");
 194                         else
 195                                 dmfc_parsed = 0;
 196                 }
 197         }
 198         if (!dmfc_parsed) {
 199                 ecc_printf(sc, "unknown DMFC %#x\n", dmfc);
 200                 return 0;
 201         }
 202
 203         if (capa & PCI_E31200_CAPID0_A_ECCDIS) {
 204                 kprintf("NON-ECC\n");
 205                 return 0;
 206         } else {
 207                 kprintf("ECC\n");
 208         }
 209
 210         mch_barlo = pcib_read_config(dev, bus, slot, 0,
 211             PCI_E31200_MCHBAR_LO, 4);
 212         mch_barhi = pcib_read_config(dev, bus, slot, 0,
 213             PCI_E31200_MCHBAR_HI, 4);
 214
 215         mch_bar = (uint64_t)mch_barlo | (((uint64_t)mch_barhi) << 32);
 216         if (bootverbose)
 217                 ecc_printf(sc, "MCHBAR %jx\n", (uintmax_t)mch_bar);
 218
 219         if (mch_bar & PCI_E31200_MCHBAR_LO_EN) {
 220                 uint64_t map_addr = mch_bar & PCI_E31200_MCHBAR_ADDRMASK;
 221                 uint32_t dimm_ch0, dimm_ch1;
 222                 int ecc_active;
 223
 224                 sc->ecc_addr = pmap_mapdev_uncacheable(map_addr,
 225                     MCH_E31200_SIZE);
 226
 227                 if (bootverbose) {
 228                         ecc_printf(sc, "LOG0_C0 %#x\n",
 229                             CSR_READ_4(sc, MCH_E31200_ERRLOG0_C0));
 230                         ecc_printf(sc, "LOG0_C1 %#x\n",
 231                             CSR_READ_4(sc, MCH_E31200_ERRLOG0_C1));
 232                 }
 233
 234                 dimm_ch0 = CSR_READ_4(sc, MCH_E31200_DIMM_CH0);
 235                 dimm_ch1 = CSR_READ_4(sc, MCH_E31200_DIMM_CH1);
 236
 237                 if (bootverbose) {
 238                         ecc_e31200_chaninfo(sc, dimm_ch0, "channel0");
 239                         ecc_e31200_chaninfo(sc, dimm_ch1, "channel1");
 240                 }
 241
 242                 ecc_active = 1;
 243                 if (sc->ecc_ver == ECC_E31200_VER_1 ||
 244                     sc->ecc_ver == ECC_E31200_VER_2) {
 245                         if (((dimm_ch0 | dimm_ch1) & MCH_E31200_DIMM_ECC) ==
 246                             MCH_E31200_DIMM_ECC_NONE) {
 247                                 ecc_active = 0;
 248                                 ecc_printf(sc, "No ECC active\n");
 249                         }
 250                 } else { /* V3 */
 251                         uint32_t ecc_mode0, ecc_mode1;
 252
 253                         ecc_mode0 = __SHIFTOUT(dimm_ch0, MCH_E31200_DIMM_ECC);
 254                         ecc_mode1 = __SHIFTOUT(dimm_ch1, MCH_E31200_DIMM_ECC);
 255
 256                         /*
 257                          * Only active ALL/NONE is supported
 258                          */
 259
 260                         if (ecc_mode0 != MCH_E31200_DIMM_ECC_NONE &&
 261                             ecc_mode0 != MCH_E31200_DIMM_ECC_ALL) {
 262                                 ecc_active = 0;
 263                                 ecc_printf(sc, "channel0, invalid ECC "
 264                                     "active 0x%x\n", ecc_mode0);
 265                         }
 266                         if (ecc_mode1 != MCH_E31200_DIMM_ECC_NONE &&
 267                             ecc_mode1 != MCH_E31200_DIMM_ECC_ALL) {
 268                                 ecc_active = 0;
 269                                 ecc_printf(sc, "channel1, invalid ECC "
 270                                     "active 0x%x\n", ecc_mode1);
 271                         }
 272
 273                         if (ecc_mode0 == MCH_E31200_DIMM_ECC_NONE &&
 274                             ecc_mode1 == MCH_E31200_DIMM_ECC_NONE) {
 275                                 ecc_active = 0;
 276                                 ecc_printf(sc, "No ECC active\n");
 277                         }
 278                 }
 279
 280                 if (!ecc_active) {
 281                         pmap_unmapdev((vm_offset_t)sc->ecc_addr,
 282                             MCH_E31200_SIZE);
 283                         sc->ecc_addr = NULL;
 284                         return 0;
 285                 }
 286         } else {
 287                 ecc_printf(sc, "MCHBAR is not enabled\n");
 288         }
 289
 290         ecc_e31200_status(sc);
 291         callout_reset(&sc->ecc_callout, hz, ecc_e31200_callout, sc);
 292
 293         return 0;
 294 }
 295
 296 static void
 297 ecc_e31200_callout(void *xsc)
 298 {
 299         struct ecc_e31200_softc *sc = xsc;
 300
 301         ecc_e31200_status(sc);
 302         callout_reset(&sc->ecc_callout, hz, ecc_e31200_callout, sc);
 303 }
 304
 305 static void
 306 ecc_e31200_status(struct ecc_e31200_softc *sc)
 307 {
 308         device_t dev = sc->ecc_device;
 309         uint16_t errsts;
 310         int bus, slot;
 311
 312         bus = pci_get_bus(dev);
 313         slot = pci_get_slot(dev);
 314
 315         errsts = pcib_read_config(dev, bus, slot, 0, PCI_E31200_ERRSTS, 2);
 316         if (errsts & PCI_E31200_ERRSTS_DMERR)
 317                 ecc_printf(sc, "Uncorrectable multilple-bit ECC error\n");
 318         else if (errsts & PCI_E31200_ERRSTS_DSERR)
 319                 ecc_printf(sc, "Correctable single-bit ECC error\n");
 320
 321         if (errsts & (PCI_E31200_ERRSTS_DSERR | PCI_E31200_ERRSTS_DMERR)) {
 322                 if (sc->ecc_addr != NULL)
 323                         ecc_e31200_errlog(sc);
 324
 325                 /* Clear pending errors */
 326                 pcib_write_config(dev, bus, slot, 0, PCI_E31200_ERRSTS,
 327                     errsts, 2);
 328         }
 329 }
 330
 331 static void
 332 ecc_e31200_chaninfo(struct ecc_e31200_softc *sc, uint32_t dimm_ch,
 333     const char *desc)
 334 {
 335         int size_a, size_b, ecc;
 336
 337         size_a = __SHIFTOUT(dimm_ch, MCH_E31200_DIMM_A_SIZE);
 338         if (size_a != 0) {
 339                 ecc_printf(sc, "%s, DIMM A %dMB %s %s\n", desc,
 340                     size_a * MCH_E31200_DIMM_SIZE_UNIT,
 341                     (dimm_ch & MCH_E31200_DIMM_A_X16) ? "X16" : "X8",
 342                     (dimm_ch & MCH_E31200_DIMM_A_DUAL_RANK) ?
 343                         "DUAL" : "SINGLE");
 344         }
 345
 346         size_b = __SHIFTOUT(dimm_ch, MCH_E31200_DIMM_B_SIZE);
 347         if (size_b != 0) {
 348                 ecc_printf(sc, "%s, DIMM B %dMB %s %s\n", desc,
 349                     size_b * MCH_E31200_DIMM_SIZE_UNIT,
 350                     (dimm_ch & MCH_E31200_DIMM_B_X16) ? "X16" : "X8",
 351                     (dimm_ch & MCH_E31200_DIMM_B_DUAL_RANK) ?
 352                         "DUAL" : "SINGLE");
 353         }
 354
 355         if (size_a == 0 && size_b == 0)
 356                 return;
 357
 358         ecc = __SHIFTOUT(dimm_ch, MCH_E31200_DIMM_ECC);
 359         if (ecc == MCH_E31200_DIMM_ECC_NONE) {
 360                 ecc_printf(sc, "%s, no ECC active\n", desc);
 361         } else if (ecc == MCH_E31200_DIMM_ECC_ALL) {
 362                 ecc_printf(sc, "%s, ECC active IO/logic\n", desc);
 363         } else {
 364                 if (sc->ecc_ver == ECC_E31200_VER_1 ||
 365                     sc->ecc_ver == ECC_E31200_VER_2) {
 366                         if (ecc == MCH_E31200_DIMM_ECC_IO)
 367                                 ecc_printf(sc, "%s, ECC active IO\n", desc);
 368                         else
 369                                 ecc_printf(sc, "%s, ECC active logic\n", desc);
 370                 } else { /* V3 */
 371                         ecc_printf(sc, "%s, invalid ECC active 0x%x\n",
 372                             desc, ecc);
 373                 }
 374         }
 375
 376         if (sc->ecc_ver == ECC_E31200_VER_1 ||
 377             sc->ecc_ver == ECC_E31200_VER_2) {
 378                 /* This bit is V3 only */
 379                 dimm_ch &= ~MCH_E31200_DIMM_HORI;
 380         }
 381         if (dimm_ch & (MCH_E31200_DIMM_ENHI | MCH_E31200_DIMM_RI |
 382             MCH_E31200_DIMM_HORI)) {
 383                 ecc_printf(sc, "%s", desc);
 384                 if (dimm_ch & MCH_E31200_DIMM_RI)
 385                         kprintf(", rank interleave");
 386                 if (dimm_ch & MCH_E31200_DIMM_ENHI)
 387                         kprintf(", enhanced interleave");
 388                 if (dimm_ch & MCH_E31200_DIMM_HORI)
 389                         kprintf(", high order rank interleave");
 390                 kprintf("\n");
 391         }
 392 }
 393
 394 static void
 395 ecc_e31200_errlog(struct ecc_e31200_softc *sc)
 396 {
 397         ecc_e31200_errlog_ch(sc, MCH_E31200_ERRLOG0_C0, MCH_E31200_ERRLOG1_C0,
 398             "channel0");
 399         ecc_e31200_errlog_ch(sc, MCH_E31200_ERRLOG0_C1, MCH_E31200_ERRLOG1_C1,
 400             "channel1");
 401 }
 402
 403 static void
 404 ecc_e31200_errlog_ch(struct ecc_e31200_softc *sc,
 405     int err0_ofs, int err1_ofs, const char *desc)
 406 {
 407         uint32_t err0, err1;
 408
 409         err0 = CSR_READ_4(sc, err0_ofs);
 410         if ((err0 & (MCH_E31200_ERRLOG0_CERRSTS | MCH_E31200_ERRLOG0_MERRSTS))
 411             == 0)
 412                 return;
 413
 414         err1 = CSR_READ_4(sc, err1_ofs);
 415
 416         ecc_printf(sc, "%s error @bank %d, rank %d, chunk %d, syndrome %d, "
 417             "row %d, col %d\n", desc,
 418             __SHIFTOUT(err0, MCH_E31200_ERRLOG0_ERRBANK),
 419             __SHIFTOUT(err0, MCH_E31200_ERRLOG0_ERRRANK),
 420             __SHIFTOUT(err0, MCH_E31200_ERRLOG0_ERRCHUNK),
 421             __SHIFTOUT(err0, MCH_E31200_ERRLOG0_ERRSYND),
 422             __SHIFTOUT(err1, MCH_E31200_ERRLOG1_ERRROW),
 423             __SHIFTOUT(err1, MCH_E31200_ERRLOG1_ERRCOL));
 424 }
 425
 426 static int
 427 ecc_e31200_detach(device_t dev)
 428 {
 429         struct ecc_e31200_softc *sc = device_get_softc(dev);
 430
 431         callout_stop_sync(&sc->ecc_callout);
 432         if (sc->ecc_addr != NULL)
 433                 pmap_unmapdev((vm_offset_t)sc->ecc_addr, MCH_E31200_SIZE);
 434         return 0;
 435 }
 436
 437 static void
 438 ecc_e31200_shutdown(device_t dev)
 439 {
 440         struct ecc_e31200_softc *sc = device_get_softc(dev);
 441
 442         callout_stop_sync(&sc->ecc_callout);
 443 }