?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Implement suspend method and wait for channels to be idle
[dragonfly.git] / sys / dev / disk / ata / ata-pci.c
blob2a066ba93e60303845086cd76668b6348ae8a21f
1 /*-
2 * Copyright (c) 1998,1999,2000,2001,2002 Søren Schmidt <sos@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * $FreeBSD: src/sys/dev/ata/ata-pci.c,v 1.32.2.15 2003/06/06 13:27:05 fjoe Exp $
29 * $DragonFly: src/sys/dev/disk/ata/ata-pci.c,v 1.24 2006/10/12 04:02:37 y0netan1 Exp $
30 */
31
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/kernel.h>
35 #include <sys/disk.h>
36 #include <sys/module.h>
37 #include <sys/bus.h>
38 #include <sys/buf.h>
39 #include <sys/malloc.h>
40 #include <sys/devicestat.h>
41 #include <sys/sysctl.h>
42 #include <machine/stdarg.h>
43 #include <machine/resource.h>
44 #include <machine/bus.h>
45 #include <machine/clock.h>
46 #include <sys/rman.h>
47 #include <bus/pci/pcivar.h>
48 #include <bus/pci/pcireg.h>
49 #include "ata-all.h"
50
51 /* device structures */
52 struct ata_pci_controller {
53 struct resource *bmio;
54 int bmaddr;
55 struct resource *irq;
56 int irqcnt;
57 };
58
59 /* misc defines */
60 #define IOMASK 0xfffffffc
61 #define GRANDPARENT(dev) device_get_parent(device_get_parent(dev))
62 #define ATA_MASTERDEV(dev) ((pci_get_progif(dev) & 0x80) && \
63 (pci_get_progif(dev) & 0x05) != 0x05)
64
65 int
66 ata_find_dev(device_t dev, u_int32_t devid, u_int32_t revid)
67 {
68 device_t *children;
69 int nchildren, i;
70
71 if (device_get_children(device_get_parent(dev), &children, &nchildren))
72 return 0;
73
74 for (i = 0; i < nchildren; i++) {
75 if (pci_get_devid(children[i]) == devid &&
76 pci_get_revid(children[i]) >= revid) {
77 kfree(children, M_TEMP);
78 return 1;
79 }
80 }
81 kfree(children, M_TEMP);
82 return 0;
83 }
84
85 static void
86 ata_via_southbridge_fixup(device_t dev)
87 {
88 device_t *children;
89 int nchildren, i;
90
91 if (device_get_children(device_get_parent(dev), &children, &nchildren))
92 return;
93
94 for (i = 0; i < nchildren; i++) {
95 if (pci_get_devid(children[i]) == 0x03051106 || /* VIA VT8363 */
96 pci_get_devid(children[i]) == 0x03911106 || /* VIA VT8371 */
97 pci_get_devid(children[i]) == 0x31021106 || /* VIA VT8662 */
98 pci_get_devid(children[i]) == 0x31121106) { /* VIA VT8361 */
99 u_int8_t reg76 = pci_read_config(children[i], 0x76, 1);
100
101 if ((reg76 & 0xf0) != 0xd0) {
102 device_printf(dev,
103 "Correcting VIA config for southbridge data corruption bug\n");
104 pci_write_config(children[i], 0x75, 0x80, 1);
105 pci_write_config(children[i], 0x76, (reg76 & 0x0f) | 0xd0, 1);
106 }
107 break;
108 }
109 }
110 kfree(children, M_TEMP);
111 }
112
113 static const char *
114 ata_pci_match(device_t dev)
115 {
116 if (pci_get_class(dev) != PCIC_STORAGE)
117 return NULL;
118
119 switch (pci_get_devid(dev)) {
120 /* supported chipsets */
121 case 0x12308086:
122 return "Intel PIIX ATA controller";
123
124 case 0x70108086:
125 return "Intel PIIX3 ATA controller";
126
127 case 0x71118086:
128 case 0x71998086:
129 case 0x84ca8086:
130 return "Intel PIIX4 ATA33 controller";
131
132 case 0x24218086:
133 return "Intel ICH0 ATA33 controller";
134
135 case 0x24118086:
136 case 0x76018086:
137 return "Intel ICH ATA66 controller";
138
139 case 0x244a8086:
140 case 0x244b8086:
141 return "Intel ICH2 ATA100 controller";
142
143 case 0x248a8086:
144 case 0x248b8086:
145 return "Intel ICH3 ATA100 controller";
146
147 case 0x24ca8086:
148 case 0x24cb8086:
149 return "Intel ICH4 ATA100 controller";
150
151 case 0x24d18086:
152 return "Intel ICH5 SATA150 controller";
153
154 case 0x24db8086:
155 return "Intel ICH5 ATA100 controller";
156
157 case 0x26518086:
158 return "Intel ICH6/W SATA150 controller";
159
160 case 0x26528086:
161 return "Intel ICH6R/RW SATA150 controller";
162
163 case 0x266f8086:
164 return "Intel ICH6R/RW ATA100 controller";
165
166 case 0x27df8086:
167 return "Intel ICH7 ATA controller";
168
169 case 0x27c48086:
170 return "Intel ICH7M SATA controller";
171
172 case 0x522910b9:
173 if (pci_get_revid(dev) >= 0xc4)
174 return "AcerLabs Aladdin ATA100 controller";
175 else if (pci_get_revid(dev) >= 0xc2)
176 return "AcerLabs Aladdin ATA66 controller";
177 else if (pci_get_revid(dev) >= 0x20)
178 return "AcerLabs Aladdin ATA33 controller";
179 else
180 return "AcerLabs Aladdin ATA controller";
181
182 case 0x05711106:
183 if (ata_find_dev(dev, 0x05861106, 0x02))
184 return "VIA 82C586 ATA33 controller";
185 if (ata_find_dev(dev, 0x05861106, 0))
186 return "VIA 82C586 ATA controller";
187 if (ata_find_dev(dev, 0x05961106, 0x12))
188 return "VIA 82C596 ATA66 controller";
189 if (ata_find_dev(dev, 0x05961106, 0))
190 return "VIA 82C596 ATA33 controller";
191 if (ata_find_dev(dev, 0x06861106, 0x40))
192 return "VIA 82C686 ATA100 controller";
193 if (ata_find_dev(dev, 0x06861106, 0x10))
194 return "VIA 82C686 ATA66 controller";
195 if (ata_find_dev(dev, 0x06861106, 0))
196 return "VIA 82C686 ATA33 controller";
197 if (ata_find_dev(dev, 0x82311106, 0))
198 return "VIA 8231 ATA100 controller";
199 if (ata_find_dev(dev, 0x30741106, 0) ||
200 ata_find_dev(dev, 0x31091106, 0))
201 return "VIA 8233 ATA100 controller";
202 if (ata_find_dev(dev, 0x31471106, 0))
203 return "VIA 8233 ATA133 controller";
204 if (ata_find_dev(dev, 0x31771106, 0))
205 return "VIA 8235 ATA133 controller";
206 if (ata_find_dev(dev, 0x31491106, 0))
207 return "VIA 8237 ATA133 controller";
208 return "VIA Apollo ATA controller";
209
210 case 0x31491106:
211 return "VIA 8237 SATA 150 controller";
212
213 case 0x55131039:
214 if (ata_find_dev(dev, 0x07461039, 0))
215 return "SiS 5591 ATA133 controller";
216 if (ata_find_dev(dev, 0x06301039, 0x30) ||
217 ata_find_dev(dev, 0x06331039, 0) ||
218 ata_find_dev(dev, 0x06351039, 0) ||
219 ata_find_dev(dev, 0x06401039, 0) ||
220 ata_find_dev(dev, 0x06451039, 0) ||
221 ata_find_dev(dev, 0x06461039, 0) ||
222 ata_find_dev(dev, 0x06481039, 0) ||
223 ata_find_dev(dev, 0x06501039, 0) ||
224 ata_find_dev(dev, 0x07301039, 0) ||
225 ata_find_dev(dev, 0x07331039, 0) ||
226 ata_find_dev(dev, 0x07351039, 0) ||
227 ata_find_dev(dev, 0x07401039, 0) ||
228 ata_find_dev(dev, 0x07451039, 0) ||
229 ata_find_dev(dev, 0x07501039, 0))
230 return "SiS 5591 ATA100 controller";
231 else if (ata_find_dev(dev, 0x05301039, 0) ||
232 ata_find_dev(dev, 0x05401039, 0) ||
233 ata_find_dev(dev, 0x06201039, 0) ||
234 ata_find_dev(dev, 0x06301039, 0))
235 return "SiS 5591 ATA66 controller";
236 else
237 return "SiS 5591 ATA33 controller";
238
239 case 0x35121095:
240 return "SiI 3512 SATA controller";
241
242 case 0x31121095:
243 return "SiI 3112 SATA controller";
244
245 case 0x31141095:
246 return "SiI 3114 SATA controller";
247
248 case 0x31241095:
249 return "SiI 3124 SATA controller";
250
251 case 0x06801095:
252 return "SiI 0680 ATA133 controller";
253
254 case 0x06491095:
255 return "CMD 649 ATA100 controller";
256
257 case 0x06481095:
258 return "CMD 648 ATA66 controller";
259
260 case 0x06461095:
261 return "CMD 646 ATA controller";
262
263 case 0xc6931080:
264 if (pci_get_subclass(dev) == PCIS_STORAGE_IDE)
265 return "Cypress 82C693 ATA controller";
266 return NULL;
267
268 case 0x01021078:
269 return "Cyrix 5530 ATA33 controller";
270
271 case 0x74091022:
272 return "AMD 756 ATA66 controller";
273
274 case 0x74111022:
275 return "AMD 766 ATA100 controller";
276
277 case 0x74411022:
278 return "AMD 768 ATA100 controller";
279
280 case 0x74691022:
281 return "AMD 8111 UltraATA/133 controller";
282
283 case 0x01bc10de:
284 return "nVIDIA nForce1 ATA100 controller";
285
286 case 0x006510de:
287 return "nVIDIA nForce2 ATA133 controller";
288
289 case 0x00d510de:
290 return "nVIDIA nForce3 ATA133 controller";
291
292 case 0x00e310de:
293 return "nVIDIA nForce3 PRO S1 controller";
294
295 case 0x00e510de:
296 return "nVIDIA nForce3 PRO controller";
297
298 case 0x02111166:
299 return "ServerWorks ROSB4 ATA33 controller";
300
301 case 0x02121166:
302 if (pci_get_revid(dev) >= 0x92)
303 return "ServerWorks CSB5 ATA100 controller";
304 else
305 return "ServerWorks CSB5 ATA66 controller";
306
307 case 0x02131166:
308 return "ServerWorks CSB6 ATA100 controller (channel 0+1)";
309
310 case 0x02171166:
311 return "ServerWorks CSB6 ATA66 controller (channel 2)";
312
313 case 0x4d33105a:
314 return "Promise ATA33 controller";
315
316 case 0x0d38105a:
317 case 0x4d38105a:
318 return "Promise ATA66 controller";
319
320 case 0x0d30105a:
321 case 0x4d30105a:
322 return "Promise ATA100 controller";
323
324 case 0x4d68105a:
325 case 0x6268105a:
326 if (pci_get_devid(GRANDPARENT(dev)) == 0x00221011 &&
327 pci_get_class(GRANDPARENT(dev)) == PCIC_BRIDGE) {
328 static long start = 0, end = 0;
329
330 /* we belive we are on a TX4, now do our (simple) magic */
331 if (pci_get_slot(dev) == 1) {
332 bus_get_resource(dev, SYS_RES_IRQ, 0, &start, &end);
333 return "Promise TX4 ATA100 controller (channel 0+1)";
334 }
335 else if (pci_get_slot(dev) == 2 && start && end) {
336 bus_set_resource(dev, SYS_RES_IRQ, 0, start, end);
337 start = end = 0;
338 return "Promise TX4 ATA100 controller (channel 2+3)";
339 }
340 else
341 start = end = 0;
342 }
343 return "Promise TX2 ATA100 controller";
344
345 case 0x4d69105a:
346 case 0x5275105a:
347 case 0x6269105a:
348 case 0x7275105a:
349 return "Promise TX2 ATA133 controller";
350
351 case 0x00041103:
352 switch (pci_get_revid(dev)) {
353 case 0x00:
354 case 0x01:
355 return "HighPoint HPT366 ATA66 controller";
356 case 0x02:
357 return "HighPoint HPT368 ATA66 controller";
358 case 0x03:
359 case 0x04:
360 return "HighPoint HPT370 ATA100 controller";
361 case 0x05:
362 return "HighPoint HPT372 ATA133 controller";
363 }
364 return NULL;
365
366 case 0x00051103:
367 switch (pci_get_revid(dev)) {
368 case 0x01:
369 case 0x02:
370 return "HighPoint HPT372 ATA133 controller";
371 }
372 return NULL;
373
374 case 0x00081103:
375 switch (pci_get_revid(dev)) {
376 case 0x07:
377 return "HighPoint HPT374 ATA133 controller";
378 }
379 return NULL;
380
381 case 0x000116ca:
382 return "Cenatek Rocket Drive controller";
383
384 /* unsupported but known chipsets, generic DMA only */
385 case 0x10001042:
386 case 0x10011042:
387 return "RZ 100? ATA controller !WARNING! buggy chip data loss possible";
388
389 case 0x06401095:
390 return "CMD 640 ATA controller !WARNING! buggy chip data loss possible";
391
392 /* unknown chipsets, try generic DMA if it seems possible */
393 default:
394 if (pci_get_class(dev) == PCIC_STORAGE &&
395 (pci_get_subclass(dev) == PCIS_STORAGE_IDE))
396 return "Generic PCI ATA controller";
397 }
398 return NULL;
399 }
400
401 static int
402 ata_pci_probe(device_t dev)
403 {
404 const char *desc = ata_pci_match(dev);
405
406 if (desc) {
407 device_set_desc(dev, desc);
408 return 0;
409 }
410 else
411 return ENXIO;
412 }
413
414 static int
415 ata_pci_add_child(device_t dev, int unit)
416 {
417 device_t child;
418
419 /* check if this is located at one of the std addresses */
420 if (ATA_MASTERDEV(dev)) {
421 if (!(child = device_add_child(dev, "ata", unit)))
422 return ENOMEM;
423 }
424 else {
425 if (!(child = device_add_child(dev, "ata", 2)))
426 return ENOMEM;
427 }
428 return 0;
429 }
430
431 static int
432 ata_pci_attach(device_t dev)
433 {
434 struct ata_pci_controller *controller = device_get_softc(dev);
435 u_int8_t class, subclass;
436 u_int32_t type, cmd;
437 int rid;
438 int flags;
439
440 /* set up vendor-specific stuff */
441 type = pci_get_devid(dev);
442 class = pci_get_class(dev);
443 subclass = pci_get_subclass(dev);
444 cmd = pci_read_config(dev, PCIR_COMMAND, 4);
445
446 if (!(cmd & PCIM_CMD_PORTEN)) {
447 device_printf(dev, "ATA channel disabled by BIOS\n");
448 return 0;
449 }
450
451 /* is busmastering supported ? */
452 if ((cmd & (PCIM_CMD_PORTEN | PCIM_CMD_BUSMASTEREN)) ==
453 (PCIM_CMD_PORTEN | PCIM_CMD_BUSMASTEREN)) {
454
455 /* is there a valid port range to connect to ? */
456 rid = 0x20;
457 controller->bmio = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
458 0, ~0, 1, RF_ACTIVE);
459 if (!controller->bmio)
460 device_printf(dev, "Busmastering DMA not configured\n");
461 }
462 else
463 device_printf(dev, "Busmastering DMA not supported\n");
464
465 /* do extra chipset specific setups */
466 flags = 0;
467
468 switch (type) {
469 case 0x522910b9: /* Aladdin need to activate the ATAPI FIFO */
470 pci_write_config(dev, 0x53,
471 (pci_read_config(dev, 0x53, 1) & ~0x01) | 0x02, 1);
472 break;
473
474 case 0x4d38105a: /* Promise 66 & 100 (before TX2) need the clock changed */
475 case 0x4d30105a:
476 case 0x0d30105a:
477 ATA_OUTB(controller->bmio, 0x11, ATA_INB(controller->bmio, 0x11)|0x0a);
478 /* FALLTHROUGH */
479
480 case 0x4d33105a: /* Promise (before TX2) need burst mode turned on */
481 ATA_OUTB(controller->bmio, 0x1f, ATA_INB(controller->bmio, 0x1f)|0x01);
482 break;
483
484 case 0x00041103: /* HighPoint HPT366/368/370/372 */
485 if (pci_get_revid(dev) < 2) { /* HPT 366 */
486 /* turn off interrupt prediction */
487 pci_write_config(dev, 0x51,
488 (pci_read_config(dev, 0x51, 1) & ~0x80), 1);
489 break;
490 }
491 if (pci_get_revid(dev) < 5) { /* HPT368/370 */
492 /* turn off interrupt prediction */
493 pci_write_config(dev, 0x51,
494 (pci_read_config(dev, 0x51, 1) & ~0x03), 1);
495 pci_write_config(dev, 0x55,
496 (pci_read_config(dev, 0x55, 1) & ~0x03), 1);
497
498 /* turn on interrupts */
499 pci_write_config(dev, 0x5a,
500 (pci_read_config(dev, 0x5a, 1) & ~0x10), 1);
501
502 /* set clocks etc */
503 pci_write_config(dev, 0x5b, 0x22, 1);
504 break;
505 }
506 /* FALLTHROUGH */
507
508 case 0x00051103: /* HighPoint HPT372 */
509 case 0x00081103: /* HighPoint HPT374 */
510 /* turn off interrupt prediction */
511 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x03), 1);
512 pci_write_config(dev, 0x55, (pci_read_config(dev, 0x55, 1) & ~0x03), 1);
513
514 /* turn on interrupts */
515 pci_write_config(dev, 0x5a, (pci_read_config(dev, 0x5a, 1) & ~0x10), 1);
516
517 /* set clocks etc */
518 pci_write_config(dev, 0x5b,
519 (pci_read_config(dev, 0x5b, 1) & 0x01) | 0x20, 1);
520 break;
521
522 case 0x05711106: /* VIA 82C586, '596, '686 default setup */
523 /* prepare for ATA-66 on the 82C686a and 82C596b */
524 if ((ata_find_dev(dev, 0x06861106, 0x10) &&
525 !ata_find_dev(dev, 0x06861106, 0x40)) ||
526 ata_find_dev(dev, 0x05961106, 0x12))
527 pci_write_config(dev, 0x50, 0x030b030b, 4);
528
529 /* the southbridge might need the data corruption fix */
530 if (ata_find_dev(dev, 0x06861106, 0x40) ||
531 ata_find_dev(dev, 0x82311106, 0x10))
532 ata_via_southbridge_fixup(dev);
533
534 /* set fifo configuration half'n'half */
535 pci_write_config(dev, 0x43,
536 (pci_read_config(dev, 0x43, 1) & 0x90) | 0x2a, 1);
537
538 /* set status register read retry */
539 pci_write_config(dev, 0x44, pci_read_config(dev, 0x44, 1) | 0x08, 1);
540
541 /* set DMA read & end-of-sector fifo flush */
542 pci_write_config(dev, 0x46,
543 (pci_read_config(dev, 0x46, 1) & 0x0c) | 0xf0, 1);
544
545 /* set sector size */
546 pci_write_config(dev, 0x60, DEV_BSIZE, 2);
547 pci_write_config(dev, 0x68, DEV_BSIZE, 2);
548 break;
549 case 0x74111022: /* AMD 766 default setup */
550 flags = 1; /* bugged */
551 /* fall through */
552 case 0x74091022: /* AMD 756 default setup */
553 case 0x74411022: /* AMD 768 default setup */
554 case 0x746d1022: /* AMD 8111 default setup */
555 if (flags) {
556 pci_write_config(dev, 0x41,
557 pci_read_config(dev, 0x41, 1) & 0x0f, 1);
558 } else {
559 pci_write_config(dev, 0x41,
560 pci_read_config(dev, 0x41, 1) | 0xf0, 1);
561 }
562 break;
563 case 0x01bc10de: /* NVIDIA nForce1 default setup */
564 case 0x006510de: /* NVIDIA nForce2 default setup */
565 flags = 1;
566 /* fall through */
567 case 0x00d510de: /* NVIDIA nForce3 default setup */
568 if (flags) {
569 pci_write_config(dev, 0x51,
570 pci_read_config(dev, 0x51, 1) & 0x0f, 1);
571 } else {
572 pci_write_config(dev, 0x51,
573 pci_read_config(dev, 0x51, 1) | 0xf0, 1);
574 }
575 break;
576
577 case 0x02111166: /* ServerWorks ROSB4 enable UDMA33 */
578 pci_write_config(dev, 0x64,
579 (pci_read_config(dev, 0x64, 4) & ~0x00002000) |
580 0x00004000, 4);
581 break;
582
583 case 0x02121166: /* ServerWorks CSB5 enable UDMA66/100 depending on rev */
584 pci_write_config(dev, 0x5a,
585 (pci_read_config(dev, 0x5a, 1) & ~0x40) |
586 (pci_get_revid(dev) >= 0x92) ? 0x03 : 0x02, 1);
587 break;
588
589 case 0x06801095: /* SiI 0680 set ATA reference clock speed */
590 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
591 pci_write_config(dev, 0x8a,
592 (pci_read_config(dev, 0x8a, 1) & 0x0F) | 0x10, 1);
593 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
594 device_printf(dev, "SiI 0680 could not set clock\n");
595 break;
596
597 case 0x06491095:
598 case 0x06481095:
599 case 0x06461095: /* CMD 646 enable interrupts, set DMA read mode */
600 pci_write_config(dev, 0x71, 0x01, 1);
601 break;
602
603 case 0x10001042: /* RZ 100? known bad, no DMA */
604 case 0x10011042:
605 case 0x06401095: /* CMD 640 known bad, no DMA */
606 controller->bmio = NULL;
607 device_printf(dev, "Busmastering DMA disabled\n");
608 }
609
610 if (controller->bmio) {
611 controller->bmaddr = rman_get_start(controller->bmio);
612 BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
613 SYS_RES_IOPORT, rid, controller->bmio);
614 controller->bmio = NULL;
615 }
616
617 /*
618 * the Cypress chip is a mess, it contains two ATA functions, but
619 * both channels are visible on the first one.
620 * simply ignore the second function for now, as the right
621 * solution (ignoring the second channel on the first function)
622 * doesn't work with the crappy ATA interrupt setup on the alpha.
623 */
624 if (pci_get_devid(dev) == 0xc6931080 && pci_get_function(dev) > 1)
625 return 0;
626
627 ata_pci_add_child(dev, 0);
628
629 if (ATA_MASTERDEV(dev) || pci_read_config(dev, 0x18, 4) & IOMASK)
630 ata_pci_add_child(dev, 1);
631
632 return bus_generic_attach(dev);
633 }
634
635 static int
636 ata_pci_intr(struct ata_channel *ch)
637 {
638 u_int8_t dmastat;
639
640 /*
641 * since we might share the IRQ with another device, and in some
642 * cases with our twin channel, we only want to process interrupts
643 * that we know this channel generated.
644 */
645 switch (ch->chiptype) {
646 case 0x00041103: /* HighPoint HPT366/368/370/372 */
647 case 0x00051103: /* HighPoint HPT372 */
648 case 0x00081103: /* HighPoint HPT374 */
649 if (((dmastat = ata_dmastatus(ch)) &
650 (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) != ATA_BMSTAT_INTERRUPT)
651 return 1;
652 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, dmastat | ATA_BMSTAT_INTERRUPT);
653 DELAY(1);
654 return 0;
655
656 case 0x06481095: /* CMD 648 */
657 case 0x06491095: /* CMD 649 */
658 if (!(pci_read_config(device_get_parent(ch->dev), 0x71, 1) &
659 (ch->unit ? 0x08 : 0x04)))
660 return 1;
661 #if !defined(NO_ATANG)
662 pci_write_config(device_get_parent(ch->dev), 0x71,
663 pci_read_config(device_get_parent(ch->dev), 0x71, 1) &
664 ~(ch->unit ? 0x04 : 0x08), 1);
665 break;
666 #endif
667
668 case 0x06801095: /* SiI 680 */
669 if (!(pci_read_config(device_get_parent(ch->dev),
670 (ch->unit ? 0xb1 : 0xa1), 1) & 0x08))
671 return 1;
672 break;
673
674 case 0x4d33105a: /* Promise Ultra/Fasttrak 33 */
675 case 0x0d38105a: /* Promise Fasttrak 66 */
676 case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */
677 case 0x0d30105a: /* Promise OEM ATA100 */
678 case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */
679 if (!(ATA_INL(ch->r_bmio, (ch->unit ? 0x14 : 0x1c)) &
680 (ch->unit ? 0x00004000 : 0x00000400)))
681 return 1;
682 break;
683
684 case 0x4d68105a: /* Promise TX2 ATA100 */
685 case 0x6268105a: /* Promise TX2 ATA100 */
686 case 0x4d69105a: /* Promise TX2 ATA133 */
687 case 0x5275105a: /* Promise TX2 ATA133 */
688 case 0x6269105a: /* Promise TX2 ATA133 */
689 case 0x7275105a: /* Promise TX2 ATA133 */
690 ATA_OUTB(ch->r_bmio, ATA_BMDEVSPEC_0, 0x0b);
691 if (!(ATA_INB(ch->r_bmio, ATA_BMDEVSPEC_1) & 0x20))
692 return 1;
693 break;
694
695 case 0x24d18086: /* Intel ICH5 SATA150 */
696 case 0x24db8086: /* Intel ICH5 ATA100 */
697 case 0x26518086: /* Intel ICH6 SATA150 */
698 case 0x26528086: /* Intel ICH6R SATA150 */
699 dmastat = ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT);
700 if ((dmastat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
701 ATA_BMSTAT_INTERRUPT)
702 return 1;
703 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, dmastat &
704 ~(ATA_BMSTAT_DMA_SIMPLEX | ATA_BMSTAT_ERROR));
705 DELAY(1);
706 return 0;
707
708 }
709
710 if (ch->flags & ATA_DMA_ACTIVE) {
711 if (!((dmastat = ata_dmastatus(ch)) & ATA_BMSTAT_INTERRUPT))
712 return 1;
713 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, dmastat | ATA_BMSTAT_INTERRUPT);
714 DELAY(1);
715 }
716 return 0;
717 }
718
719 static int
720 ata_pci_print_child(device_t dev, device_t child)
721 {
722 struct ata_channel *ch = device_get_softc(child);
723 int retval = 0;
724
725 retval += bus_print_child_header(dev, child);
726 retval += printf(": at 0x%lx", rman_get_start(ch->r_io));
727
728 if (ATA_MASTERDEV(dev))
729 retval += printf(" irq %d", 14 + ch->unit);
730
731 retval += bus_print_child_footer(dev, child);
732
733 return retval;
734 }
735
736 static struct resource *
737 ata_pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
738 u_long start, u_long end, u_long count, u_int flags)
739 {
740 struct ata_pci_controller *controller = device_get_softc(dev);
741 struct resource *res = NULL;
742 int unit = ((struct ata_channel *)device_get_softc(child))->unit;
743 int myrid;
744
745 if (type == SYS_RES_IOPORT) {
746 switch (*rid) {
747 case ATA_IOADDR_RID:
748 if (ATA_MASTERDEV(dev)) {
749 myrid = 0;
750 start = (unit ? ATA_SECONDARY : ATA_PRIMARY);
751 end = start + ATA_IOSIZE - 1;
752 count = ATA_IOSIZE;
753 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
754 SYS_RES_IOPORT, &myrid,
755 start, end, count, flags);
756 }
757 else {
758 myrid = 0x10 + 8 * unit;
759 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
760 SYS_RES_IOPORT, &myrid,
761 start, end, count, flags);
762 }
763 break;
764
765 case ATA_ALTADDR_RID:
766 if (ATA_MASTERDEV(dev)) {
767 myrid = 0;
768 start = (unit ? ATA_SECONDARY : ATA_PRIMARY) + ATA_ALTOFFSET;
769 end = start + ATA_ALTIOSIZE - 1;
770 count = ATA_ALTIOSIZE;
771 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
772 SYS_RES_IOPORT, &myrid,
773 start, end, count, flags);
774 }
775 else {
776 myrid = 0x14 + 8 * unit;
777 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
778 SYS_RES_IOPORT, &myrid,
779 start, end, count, flags);
780 if (res) {
781 start = rman_get_start(res) + 2;
782 end = start + ATA_ALTIOSIZE - 1;
783 count = ATA_ALTIOSIZE;
784 BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
785 SYS_RES_IOPORT, myrid, res);
786 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
787 SYS_RES_IOPORT, &myrid,
788 start, end, count, flags);
789 }
790 }
791 break;
792
793 case ATA_BMADDR_RID:
794 if (controller->bmaddr) {
795 myrid = 0x20;
796 start = (unit == 0 ?
797 controller->bmaddr : controller->bmaddr+ATA_BMIOSIZE);
798 end = start + ATA_BMIOSIZE - 1;
799 count = ATA_BMIOSIZE;
800 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
801 SYS_RES_IOPORT, &myrid,
802 start, end, count, flags);
803 }
804 }
805 return res;
806 }
807
808 if (type == SYS_RES_IRQ && *rid == ATA_IRQ_RID) {
809 if (ATA_MASTERDEV(dev)) {
810 int irq = (unit == 0 ? 14 : 15);
811
812 return BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
813 SYS_RES_IRQ, rid, irq, irq, 1, flags);
814 }
815 else {
816 /* primary and secondary channels share interrupt, keep track */
817 if (!controller->irq)
818 controller->irq = BUS_ALLOC_RESOURCE(device_get_parent(dev),
819 dev, SYS_RES_IRQ,
820 rid, 0, ~0, 1, flags);
821 controller->irqcnt++;
822 return controller->irq;
823 }
824 }
825 return 0;
826 }
827
828 static int
829 ata_pci_release_resource(device_t dev, device_t child, int type, int rid,
830 struct resource *r)
831 {
832 struct ata_pci_controller *controller = device_get_softc(dev);
833 int unit = ((struct ata_channel *)device_get_softc(child))->unit;
834
835 if (type == SYS_RES_IOPORT) {
836 switch (rid) {
837 case ATA_IOADDR_RID:
838 if (ATA_MASTERDEV(dev))
839 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
840 SYS_RES_IOPORT, 0x0, r);
841 else
842 return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
843 SYS_RES_IOPORT, 0x10 + 8 * unit, r);
844 break;
845
846 case ATA_ALTADDR_RID:
847 if (ATA_MASTERDEV(dev))
848 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
849 SYS_RES_IOPORT, 0x0, r);
850 else
851 return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
852 SYS_RES_IOPORT, 0x14 + 8 * unit, r);
853 break;
854
855 case ATA_BMADDR_RID:
856 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
857 SYS_RES_IOPORT, 0x20, r);
858 default:
859 return ENOENT;
860 }
861 }
862 if (type == SYS_RES_IRQ) {
863 if (rid != ATA_IRQ_RID)
864 return ENOENT;
865
866 if (ATA_MASTERDEV(dev)) {
867 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
868 SYS_RES_IRQ, rid, r);
869 }
870 else {
871 /* primary and secondary channels share interrupt, keep track */
872 if (--controller->irqcnt)
873 return 0;
874 controller->irq = NULL;
875 return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
876 SYS_RES_IRQ, rid, r);
877 }
878 }
879 return EINVAL;
880 }
881
882 static int
883 ata_pci_setup_intr(device_t dev, device_t child, struct resource *irq,
884 int flags, driver_intr_t *intr, void *arg,
885 void **cookiep, lwkt_serialize_t serializer)
886 {
887 if (ATA_MASTERDEV(dev)) {
888 return BUS_SETUP_INTR(device_get_parent(dev), child, irq,
889 flags, intr, arg, cookiep, serializer);
890 }
891 else
892 return BUS_SETUP_INTR(device_get_parent(dev), dev, irq,
893 flags, intr, arg, cookiep, serializer);
894 }
895
896 static int
897 ata_pci_teardown_intr(device_t dev, device_t child, struct resource *irq,
898 void *cookie)
899 {
900 if (ATA_MASTERDEV(dev)) {
901 return BUS_TEARDOWN_INTR(device_get_parent(dev), child, irq, cookie);
902 }
903 else
904 return BUS_TEARDOWN_INTR(device_get_parent(dev), dev, irq, cookie);
905 }
906
907 static device_method_t ata_pci_methods[] = {
908 /* device interface */
909 DEVMETHOD(device_probe, ata_pci_probe),
910 DEVMETHOD(device_attach, ata_pci_attach),
911 DEVMETHOD(device_shutdown, bus_generic_shutdown),
912 DEVMETHOD(device_suspend, bus_generic_suspend),
913 DEVMETHOD(device_resume, bus_generic_resume),
914
915 /* bus methods */
916 DEVMETHOD(bus_print_child, ata_pci_print_child),
917 DEVMETHOD(bus_alloc_resource, ata_pci_alloc_resource),
918 DEVMETHOD(bus_release_resource, ata_pci_release_resource),
919 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
920 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
921 DEVMETHOD(bus_setup_intr, ata_pci_setup_intr),
922 DEVMETHOD(bus_teardown_intr, ata_pci_teardown_intr),
923 { 0, 0 }
924 };
925
926 static driver_t ata_pci_driver = {
927 "atapci",
928 ata_pci_methods,
929 sizeof(struct ata_pci_controller),
930 };
931
932 static devclass_t ata_pci_devclass;
933
934 DRIVER_MODULE(atapci, pci, ata_pci_driver, ata_pci_devclass, 0, 0);
935
936 static int
937 ata_pcisub_probe(device_t dev)
938 {
939 struct ata_channel *ch = device_get_softc(dev);
940 device_t *children;
941 int count, i;
942
943 /* find channel number on this controller */
944 device_get_children(device_get_parent(dev), &children, &count);
945 for (i = 0; i < count; i++) {
946 if (children[i] == dev)
947 ch->unit = i;
948 }
949 kfree(children, M_TEMP);
950 ch->chiptype = pci_get_devid(device_get_parent(dev));
951 ch->intr_func = ata_pci_intr;
952 return ata_probe(dev);
953 }
954
955 static device_method_t ata_pcisub_methods[] = {
956 /* device interface */
957 DEVMETHOD(device_probe, ata_pcisub_probe),
958 DEVMETHOD(device_attach, ata_attach),
959 DEVMETHOD(device_detach, ata_detach),
960 DEVMETHOD(device_resume, ata_resume),
961 DEVMETHOD(device_suspend, ata_suspend),
962 { 0, 0 }
963 };
964
965 static driver_t ata_pcisub_driver = {
966 "ata",
967 ata_pcisub_methods,
968 sizeof(struct ata_channel),
969 };
970
971 DRIVER_MODULE(ata, atapci, ata_pcisub_driver, ata_devclass, 0, 0);
DragonFly BSD