sys/dev/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/i2c.h>
  29 #include <linux/hdmi.h>
  30 #include <drm/i915_drm.h>
  31 #include "i915_drv.h"
  32 #include <drm/drm_crtc.h>
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/drm_fb_helper.h>
  35 #include <drm/drm_dp_mst_helper.h>
  36
  37 /**
  38  * _wait_for - magic (register) wait macro
  39  *
  40  * Does the right thing for modeset paths when run under kdgb or similar atomic
  41  * contexts. Note that it's important that we check the condition again after
  42  * having timed out, since the timeout could be due to preemption or similar and
  43  * we've never had a chance to check the condition before the timeout.
  44  */
  45 #define _wait_for(COND, MS, W) ({ \
  46         unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1;   \
  47         int ret__ = 0;                                                  \
  48         while (!(COND)) {                                               \
  49                 if (time_after(jiffies, timeout__)) {                   \
  50                         if (!(COND))                                    \
  51                                 ret__ = -ETIMEDOUT;                     \
  52                         break;                                          \
  53                 }                                                       \
  54                 if (W && drm_can_sleep())  {                            \
  55                         msleep(W);                                      \
  56                 } else {                                                \
  57                         cpu_pause();                                    \
  58                 }                                                       \
  59         }                                                               \
  60         ret__;                                                          \
  61 })
  62
  63 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
  64 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
  65 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
  66                                                DIV_ROUND_UP((US), 1000), 0)
  67
  68 #define KHz(x) (1000 * (x))
  69 #define MHz(x) KHz(1000 * (x))
  70
  71 /*
  72  * Display related stuff
  73  */
  74
  75 /* store information about an Ixxx DVO */
  76 /* The i830->i865 use multiple DVOs with multiple i2cs */
  77 /* the i915, i945 have a single sDVO i2c bus - which is different */
  78 #define MAX_OUTPUTS 6
  79 /* maximum connectors per crtcs in the mode set */
  80
  81 /* Maximum cursor sizes */
  82 #define GEN2_CURSOR_WIDTH 64
  83 #define GEN2_CURSOR_HEIGHT 64
  84 #define MAX_CURSOR_WIDTH 256
  85 #define MAX_CURSOR_HEIGHT 256
  86
  87 #define INTEL_I2C_BUS_DVO 1
  88 #define INTEL_I2C_BUS_SDVO 2
  89
  90 /* these are outputs from the chip - integrated only
  91    external chips are via DVO or SDVO output */
  92 #define INTEL_OUTPUT_UNUSED 0
  93 #define INTEL_OUTPUT_ANALOG 1
  94 #define INTEL_OUTPUT_DVO 2
  95 #define INTEL_OUTPUT_SDVO 3
  96 #define INTEL_OUTPUT_LVDS 4
  97 #define INTEL_OUTPUT_TVOUT 5
  98 #define INTEL_OUTPUT_HDMI 6
  99 #define INTEL_OUTPUT_DISPLAYPORT 7
 100 #define INTEL_OUTPUT_EDP 8
 101 #define INTEL_OUTPUT_DSI 9
 102 #define INTEL_OUTPUT_UNKNOWN 10
 103 #define INTEL_OUTPUT_DP_MST 11
 104
 105 #define INTEL_DVO_CHIP_NONE 0
 106 #define INTEL_DVO_CHIP_LVDS 1
 107 #define INTEL_DVO_CHIP_TMDS 2
 108 #define INTEL_DVO_CHIP_TVOUT 4
 109
 110 #define INTEL_DSI_VIDEO_MODE    0
 111 #define INTEL_DSI_COMMAND_MODE  1
 112
 113 struct intel_framebuffer {
 114         struct drm_framebuffer base;
 115         struct drm_i915_gem_object *obj;
 116 };
 117
 118 struct intel_fbdev {
 119         struct drm_fb_helper helper;
 120         struct intel_framebuffer *fb;
 121         struct list_head fbdev_list;
 122         struct drm_display_mode *our_mode;
 123         int preferred_bpp;
 124 };
 125
 126 struct intel_encoder {
 127         struct drm_encoder base;
 128         /*
 129          * The new crtc this encoder will be driven from. Only differs from
 130          * base->crtc while a modeset is in progress.
 131          */
 132         struct intel_crtc *new_crtc;
 133
 134         int type;
 135         unsigned int cloneable;
 136         bool connectors_active;
 137         void (*hot_plug)(struct intel_encoder *);
 138         bool (*compute_config)(struct intel_encoder *,
 139                                struct intel_crtc_config *);
 140         void (*pre_pll_enable)(struct intel_encoder *);
 141         void (*pre_enable)(struct intel_encoder *);
 142         void (*enable)(struct intel_encoder *);
 143         void (*mode_set)(struct intel_encoder *intel_encoder);
 144         void (*disable)(struct intel_encoder *);
 145         void (*post_disable)(struct intel_encoder *);
 146         /* Read out the current hw state of this connector, returning true if
 147          * the encoder is active. If the encoder is enabled it also set the pipe
 148          * it is connected to in the pipe parameter. */
 149         bool (*get_hw_state)(struct intel_encoder *, enum i915_pipe *pipe);
 150         /* Reconstructs the equivalent mode flags for the current hardware
 151          * state. This must be called _after_ display->get_pipe_config has
 152          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 153          * be set correctly before calling this function. */
 154         void (*get_config)(struct intel_encoder *,
 155                            struct intel_crtc_config *pipe_config);
 156         /*
 157          * Called during system suspend after all pending requests for the
 158          * encoder are flushed (for example for DP AUX transactions) and
 159          * device interrupts are disabled.
 160          */
 161         void (*suspend)(struct intel_encoder *);
 162         int crtc_mask;
 163         enum hpd_pin hpd_pin;
 164 };
 165
 166 struct intel_panel {
 167         struct drm_display_mode *fixed_mode;
 168         struct drm_display_mode *downclock_mode;
 169         int fitting_mode;
 170
 171         /* backlight */
 172         struct {
 173                 bool present;
 174                 u32 level;
 175                 u32 min;
 176                 u32 max;
 177                 bool enabled;
 178                 bool combination_mode;  /* gen 2/4 only */
 179                 bool active_low_pwm;
 180                 struct backlight_device *device;
 181         } backlight;
 182 };
 183
 184 struct intel_connector {
 185         struct drm_connector base;
 186         /*
 187          * The fixed encoder this connector is connected to.
 188          */
 189         struct intel_encoder *encoder;
 190
 191         /*
 192          * The new encoder this connector will be driven. Only differs from
 193          * encoder while a modeset is in progress.
 194          */
 195         struct intel_encoder *new_encoder;
 196
 197         /* Reads out the current hw, returning true if the connector is enabled
 198          * and active (i.e. dpms ON state). */
 199         bool (*get_hw_state)(struct intel_connector *);
 200
 201         /*
 202          * Removes all interfaces through which the connector is accessible
 203          * - like sysfs, debugfs entries -, so that no new operations can be
 204          * started on the connector. Also makes sure all currently pending
 205          * operations finish before returing.
 206          */
 207         void (*unregister)(struct intel_connector *);
 208
 209         /* Panel info for eDP and LVDS */
 210         struct intel_panel panel;
 211
 212         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 213         struct edid *edid;
 214
 215         /* since POLL and HPD connectors may use the same HPD line keep the native
 216            state of connector->polled in case hotplug storm detection changes it */
 217         u8 polled;
 218
 219         void *port; /* store this opaque as its illegal to dereference it */
 220
 221         struct intel_dp *mst_port;
 222 };
 223
 224 typedef struct dpll {
 225         /* given values */
 226         int n;
 227         int m1, m2;
 228         int p1, p2;
 229         /* derived values */
 230         int     dot;
 231         int     vco;
 232         int     m;
 233         int     p;
 234 } intel_clock_t;
 235
 236 struct intel_plane_config {
 237         bool tiled;
 238         int size;
 239         u32 base;
 240 };
 241
 242 struct intel_crtc_config {
 243         /**
 244          * quirks - bitfield with hw state readout quirks
 245          *
 246          * For various reasons the hw state readout code might not be able to
 247          * completely faithfully read out the current state. These cases are
 248          * tracked with quirk flags so that fastboot and state checker can act
 249          * accordingly.
 250          */
 251 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
 252 #define PIPE_CONFIG_QUIRK_INHERITED_MODE        (1<<1) /* mode inherited from firmware */
 253         unsigned long quirks;
 254
 255         /* User requested mode, only valid as a starting point to
 256          * compute adjusted_mode, except in the case of (S)DVO where
 257          * it's also for the output timings of the (S)DVO chip.
 258          * adjusted_mode will then correspond to the S(DVO) chip's
 259          * preferred input timings. */
 260         struct drm_display_mode requested_mode;
 261         /* Actual pipe timings ie. what we program into the pipe timing
 262          * registers. adjusted_mode.crtc_clock is the pipe pixel clock. */
 263         struct drm_display_mode adjusted_mode;
 264
 265         /* Pipe source size (ie. panel fitter input size)
 266          * All planes will be positioned inside this space,
 267          * and get clipped at the edges. */
 268         int pipe_src_w, pipe_src_h;
 269
 270         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 271          * between pch encoders and cpu encoders. */
 272         bool has_pch_encoder;
 273
 274         /* CPU Transcoder for the pipe. Currently this can only differ from the
 275          * pipe on Haswell (where we have a special eDP transcoder). */
 276         enum transcoder cpu_transcoder;
 277
 278         /*
 279          * Use reduced/limited/broadcast rbg range, compressing from the full
 280          * range fed into the crtcs.
 281          */
 282         bool limited_color_range;
 283
 284         /* DP has a bunch of special case unfortunately, so mark the pipe
 285          * accordingly. */
 286         bool has_dp_encoder;
 287
 288         /* Whether we should send NULL infoframes. Required for audio. */
 289         bool has_hdmi_sink;
 290
 291         /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
 292          * has_dp_encoder is set. */
 293         bool has_audio;
 294
 295         /*
 296          * Enable dithering, used when the selected pipe bpp doesn't match the
 297          * plane bpp.
 298          */
 299         bool dither;
 300
 301         /* Controls for the clock computation, to override various stages. */
 302         bool clock_set;
 303
 304         /* SDVO TV has a bunch of special case. To make multifunction encoders
 305          * work correctly, we need to track this at runtime.*/
 306         bool sdvo_tv_clock;
 307
 308         /*
 309          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 310          * required. This is set in the 2nd loop of calling encoder's
 311          * ->compute_config if the first pick doesn't work out.
 312          */
 313         bool bw_constrained;
 314
 315         /* Settings for the intel dpll used on pretty much everything but
 316          * haswell. */
 317         struct dpll dpll;
 318
 319         /* Selected dpll when shared or DPLL_ID_PRIVATE. */
 320         enum intel_dpll_id shared_dpll;
 321
 322         /* PORT_CLK_SEL for DDI ports. */
 323         uint32_t ddi_pll_sel;
 324
 325         /* Actual register state of the dpll, for shared dpll cross-checking. */
 326         struct intel_dpll_hw_state dpll_hw_state;
 327
 328         int pipe_bpp;
 329         struct intel_link_m_n dp_m_n;
 330
 331         /* m2_n2 for eDP downclock */
 332         struct intel_link_m_n dp_m2_n2;
 333
 334         /*
 335          * Frequence the dpll for the port should run at. Differs from the
 336          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 337          * already multiplied by pixel_multiplier.
 338          */
 339         int port_clock;
 340
 341         /* Used by SDVO (and if we ever fix it, HDMI). */
 342         unsigned pixel_multiplier;
 343
 344         /* Panel fitter controls for gen2-gen4 + VLV */
 345         struct {
 346                 u32 control;
 347                 u32 pgm_ratios;
 348                 u32 lvds_border_bits;
 349         } gmch_pfit;
 350
 351         /* Panel fitter placement and size for Ironlake+ */
 352         struct {
 353                 u32 pos;
 354                 u32 size;
 355                 bool enabled;
 356                 bool force_thru;
 357         } pch_pfit;
 358
 359         /* FDI configuration, only valid if has_pch_encoder is set. */
 360         int fdi_lanes;
 361         struct intel_link_m_n fdi_m_n;
 362
 363         bool ips_enabled;
 364
 365         bool double_wide;
 366
 367         bool dp_encoder_is_mst;
 368         int pbn;
 369 };
 370
 371 struct intel_pipe_wm {
 372         struct intel_wm_level wm[5];
 373         uint32_t linetime;
 374         bool fbc_wm_enabled;
 375         bool pipe_enabled;
 376         bool sprites_enabled;
 377         bool sprites_scaled;
 378 };
 379
 380 struct intel_mmio_flip {
 381         u32 seqno;
 382         u32 ring_id;
 383 };
 384
 385 struct intel_crtc {
 386         struct drm_crtc base;
 387         enum i915_pipe pipe;
 388         enum plane plane;
 389         u8 lut_r[256], lut_g[256], lut_b[256];
 390         /*
 391          * Whether the crtc and the connected output pipeline is active. Implies
 392          * that crtc->enabled is set, i.e. the current mode configuration has
 393          * some outputs connected to this crtc.
 394          */
 395         bool active;
 396         unsigned long enabled_power_domains;
 397         bool primary_enabled; /* is the primary plane (partially) visible? */
 398         bool lowfreq_avail;
 399         struct intel_overlay *overlay;
 400         struct intel_unpin_work *unpin_work;
 401
 402         atomic_t unpin_work_count;
 403
 404         /* Display surface base address adjustement for pageflips. Note that on
 405          * gen4+ this only adjusts up to a tile, offsets within a tile are
 406          * handled in the hw itself (with the TILEOFF register). */
 407         unsigned long dspaddr_offset;
 408
 409         struct drm_i915_gem_object *cursor_bo;
 410         uint32_t cursor_addr;
 411         int16_t cursor_width, cursor_height;
 412         uint32_t cursor_cntl;
 413         uint32_t cursor_base;
 414
 415         struct intel_plane_config plane_config;
 416         struct intel_crtc_config config;
 417         struct intel_crtc_config *new_config;
 418         bool new_enabled;
 419
 420         /* reset counter value when the last flip was submitted */
 421         unsigned int reset_counter;
 422
 423         /* Access to these should be protected by dev_priv->irq_lock. */
 424         bool cpu_fifo_underrun_disabled;
 425         bool pch_fifo_underrun_disabled;
 426
 427         /* per-pipe watermark state */
 428         struct {
 429                 /* watermarks currently being used  */
 430                 struct intel_pipe_wm active;
 431         } wm;
 432
 433         wait_queue_head_t vbl_wait;
 434
 435         int scanline_offset;
 436         struct intel_mmio_flip mmio_flip;
 437 };
 438
 439 struct intel_plane_wm_parameters {
 440         uint32_t horiz_pixels;
 441         uint32_t vert_pixels;
 442         uint8_t bytes_per_pixel;
 443         bool enabled;
 444         bool scaled;
 445 };
 446
 447 struct intel_plane {
 448         struct drm_plane base;
 449         int plane;
 450         enum i915_pipe pipe;
 451         struct drm_i915_gem_object *obj;
 452         bool can_scale;
 453         int max_downscale;
 454         int crtc_x, crtc_y;
 455         unsigned int crtc_w, crtc_h;
 456         uint32_t src_x, src_y;
 457         uint32_t src_w, src_h;
 458
 459         /* Since we need to change the watermarks before/after
 460          * enabling/disabling the planes, we need to store the parameters here
 461          * as the other pieces of the struct may not reflect the values we want
 462          * for the watermark calculations. Currently only Haswell uses this.
 463          */
 464         struct intel_plane_wm_parameters wm;
 465
 466         void (*update_plane)(struct drm_plane *plane,
 467                              struct drm_crtc *crtc,
 468                              struct drm_framebuffer *fb,
 469                              struct drm_i915_gem_object *obj,
 470                              int crtc_x, int crtc_y,
 471                              unsigned int crtc_w, unsigned int crtc_h,
 472                              uint32_t x, uint32_t y,
 473                              uint32_t src_w, uint32_t src_h);
 474         void (*disable_plane)(struct drm_plane *plane,
 475                               struct drm_crtc *crtc);
 476         int (*update_colorkey)(struct drm_plane *plane,
 477                                struct drm_intel_sprite_colorkey *key);
 478         void (*get_colorkey)(struct drm_plane *plane,
 479                              struct drm_intel_sprite_colorkey *key);
 480 };
 481
 482 struct intel_watermark_params {
 483         unsigned long fifo_size;
 484         unsigned long max_wm;
 485         unsigned long default_wm;
 486         unsigned long guard_size;
 487         unsigned long cacheline_size;
 488 };
 489
 490 struct cxsr_latency {
 491         int is_desktop;
 492         int is_ddr3;
 493         unsigned long fsb_freq;
 494         unsigned long mem_freq;
 495         unsigned long display_sr;
 496         unsigned long display_hpll_disable;
 497         unsigned long cursor_sr;
 498         unsigned long cursor_hpll_disable;
 499 };
 500
 501 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
 502 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
 503 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
 504 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
 505 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
 506 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
 507
 508 struct intel_hdmi {
 509         u32 hdmi_reg;
 510         int ddc_bus;
 511         uint32_t color_range;
 512         bool color_range_auto;
 513         bool has_hdmi_sink;
 514         bool has_audio;
 515         enum hdmi_force_audio force_audio;
 516         bool rgb_quant_range_selectable;
 517         enum hdmi_picture_aspect aspect_ratio;
 518         void (*write_infoframe)(struct drm_encoder *encoder,
 519                                 enum hdmi_infoframe_type type,
 520                                 const void *frame, ssize_t len);
 521         void (*set_infoframes)(struct drm_encoder *encoder,
 522                                bool enable,
 523                                struct drm_display_mode *adjusted_mode);
 524 };
 525
 526 struct intel_dp_mst_encoder;
 527 #define DP_MAX_DOWNSTREAM_PORTS         0x10
 528
 529 /**
 530  * HIGH_RR is the highest eDP panel refresh rate read from EDID
 531  * LOW_RR is the lowest eDP panel refresh rate found from EDID
 532  * parsing for same resolution.
 533  */
 534 enum edp_drrs_refresh_rate_type {
 535         DRRS_HIGH_RR,
 536         DRRS_LOW_RR,
 537         DRRS_MAX_RR, /* RR count */
 538 };
 539
 540 struct intel_dp {
 541         uint32_t output_reg;
 542         uint32_t aux_ch_ctl_reg;
 543         uint32_t DP;
 544         bool has_audio;
 545         enum hdmi_force_audio force_audio;
 546         uint32_t color_range;
 547         bool color_range_auto;
 548         uint8_t link_bw;
 549         uint8_t lane_count;
 550         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 551         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 552         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 553         struct drm_dp_aux aux;
 554         device_t dp_iic_bus;
 555         device_t adapter;
 556         uint8_t train_set[4];
 557         int panel_power_up_delay;
 558         int panel_power_down_delay;
 559         int panel_power_cycle_delay;
 560         int backlight_on_delay;
 561         int backlight_off_delay;
 562         struct delayed_work panel_vdd_work;
 563         bool want_panel_vdd;
 564         unsigned long last_power_cycle;
 565         unsigned long last_power_on;
 566         unsigned long last_backlight_off;
 567
 568         struct notifier_block edp_notifier;
 569
 570         bool use_tps3;
 571         bool can_mst; /* this port supports mst */
 572         bool is_mst;
 573         int active_mst_links;
 574         /* connector directly attached - won't be use for modeset in mst world */
 575         struct intel_connector *attached_connector;
 576
 577         /* mst connector list */
 578         struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
 579         struct drm_dp_mst_topology_mgr mst_mgr;
 580
 581         uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
 582         /*
 583          * This function returns the value we have to program the AUX_CTL
 584          * register with to kick off an AUX transaction.
 585          */
 586         uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
 587                                      bool has_aux_irq,
 588                                      int send_bytes,
 589                                      uint32_t aux_clock_divider);
 590         struct {
 591                 enum drrs_support_type type;
 592                 enum edp_drrs_refresh_rate_type refresh_rate_type;
 593                 struct lock mutex;
 594         } drrs_state;
 595
 596 };
 597
 598 struct intel_digital_port {
 599         struct intel_encoder base;
 600         enum port port;
 601         u32 saved_port_bits;
 602         struct intel_dp dp;
 603         struct intel_hdmi hdmi;
 604         bool (*hpd_pulse)(struct intel_digital_port *, bool);
 605 };
 606
 607 struct intel_dp_mst_encoder {
 608         struct intel_encoder base;
 609         enum i915_pipe pipe;
 610         struct intel_digital_port *primary;
 611         void *port; /* store this opaque as its illegal to dereference it */
 612 };
 613
 614 static inline int
 615 vlv_dport_to_channel(struct intel_digital_port *dport)
 616 {
 617         switch (dport->port) {
 618         case PORT_B:
 619         case PORT_D:
 620                 return DPIO_CH0;
 621         case PORT_C:
 622                 return DPIO_CH1;
 623         default:
 624                 BUG();
 625         }
 626 }
 627
 628 static inline int
 629 vlv_pipe_to_channel(enum i915_pipe pipe)
 630 {
 631         switch (pipe) {
 632         case PIPE_A:
 633         case PIPE_C:
 634                 return DPIO_CH0;
 635         case PIPE_B:
 636                 return DPIO_CH1;
 637         default:
 638                 BUG();
 639         }
 640 }
 641
 642 static inline struct drm_crtc *
 643 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
 644 {
 645         struct drm_i915_private *dev_priv = dev->dev_private;
 646         return dev_priv->pipe_to_crtc_mapping[pipe];
 647 }
 648
 649 static inline struct drm_crtc *
 650 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
 651 {
 652         struct drm_i915_private *dev_priv = dev->dev_private;
 653         return dev_priv->plane_to_crtc_mapping[plane];
 654 }
 655
 656 struct intel_unpin_work {
 657         struct work_struct work;
 658         struct drm_crtc *crtc;
 659         struct drm_i915_gem_object *old_fb_obj;
 660         struct drm_i915_gem_object *pending_flip_obj;
 661         struct drm_pending_vblank_event *event;
 662         atomic_t pending;
 663 #define INTEL_FLIP_INACTIVE     0
 664 #define INTEL_FLIP_PENDING      1
 665 #define INTEL_FLIP_COMPLETE     2
 666         u32 flip_count;
 667         u32 gtt_offset;
 668         bool enable_stall_check;
 669 };
 670
 671 struct intel_set_config {
 672         struct drm_encoder **save_connector_encoders;
 673         struct drm_crtc **save_encoder_crtcs;
 674         bool *save_crtc_enabled;
 675
 676         bool fb_changed;
 677         bool mode_changed;
 678 };
 679
 680 struct intel_load_detect_pipe {
 681         struct drm_framebuffer *release_fb;
 682         bool load_detect_temp;
 683         int dpms_mode;
 684 };
 685
 686 static inline struct intel_encoder *
 687 intel_attached_encoder(struct drm_connector *connector)
 688 {
 689         return to_intel_connector(connector)->encoder;
 690 }
 691
 692 static inline struct intel_digital_port *
 693 enc_to_dig_port(struct drm_encoder *encoder)
 694 {
 695         return container_of(encoder, struct intel_digital_port, base.base);
 696 }
 697
 698 static inline struct intel_dp_mst_encoder *
 699 enc_to_mst(struct drm_encoder *encoder)
 700 {
 701         return container_of(encoder, struct intel_dp_mst_encoder, base.base);
 702 }
 703
 704 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
 705 {
 706         return &enc_to_dig_port(encoder)->dp;
 707 }
 708
 709 static inline struct intel_digital_port *
 710 dp_to_dig_port(struct intel_dp *intel_dp)
 711 {
 712         return container_of(intel_dp, struct intel_digital_port, dp);
 713 }
 714
 715 static inline struct intel_digital_port *
 716 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
 717 {
 718         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
 719 }
 720
 721
 722 /* i915_irq.c */
 723 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
 724                                            enum i915_pipe pipe, bool enable);
 725 bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
 726                                            enum transcoder pch_transcoder,
 727                                            bool enable);
 728 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 729 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 730 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 731 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 732 void gen8_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 733 void gen8_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 734 void intel_runtime_pm_disable_interrupts(struct drm_device *dev);
 735 void intel_runtime_pm_restore_interrupts(struct drm_device *dev);
 736 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
 737 {
 738         /*
 739          * We only use drm_irq_uninstall() at unload and VT switch, so
 740          * this is the only thing we need to check.
 741          */
 742         return !dev_priv->pm._irqs_disabled;
 743 }
 744
 745 int intel_get_crtc_scanline(struct intel_crtc *crtc);
 746 void i9xx_check_fifo_underruns(struct drm_device *dev);
 747 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv);
 748
 749 /* intel_crt.c */
 750 void intel_crt_init(struct drm_device *dev);
 751
 752
 753 /* intel_ddi.c */
 754 void intel_prepare_ddi(struct drm_device *dev);
 755 void hsw_fdi_link_train(struct drm_crtc *crtc);
 756 void intel_ddi_init(struct drm_device *dev, enum port port);
 757 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
 758 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum i915_pipe *pipe);
 759 int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
 760 void intel_ddi_pll_init(struct drm_device *dev);
 761 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
 762 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
 763                                        enum transcoder cpu_transcoder);
 764 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
 765 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
 766 bool intel_ddi_pll_select(struct intel_crtc *crtc);
 767 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
 768 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
 769 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
 770 void intel_ddi_fdi_disable(struct drm_crtc *crtc);
 771 void intel_ddi_get_config(struct intel_encoder *encoder,
 772                           struct intel_crtc_config *pipe_config);
 773
 774 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
 775 void intel_ddi_clock_get(struct intel_encoder *encoder,
 776                          struct intel_crtc_config *pipe_config);
 777 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
 778
 779 /* intel_display.c */
 780 const char *intel_output_name(int output);
 781 bool intel_has_pending_fb_unpin(struct drm_device *dev);
 782 int intel_pch_rawclk(struct drm_device *dev);
 783 void intel_mark_busy(struct drm_device *dev);
 784 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
 785                              struct intel_engine_cs *ring);
 786 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
 787                                     unsigned frontbuffer_bits);
 788 void intel_frontbuffer_flip_complete(struct drm_device *dev,
 789                                      unsigned frontbuffer_bits);
 790 void intel_frontbuffer_flush(struct drm_device *dev,
 791                              unsigned frontbuffer_bits);
 792 /**
 793  * intel_frontbuffer_flip - prepare frontbuffer flip
 794  * @dev: DRM device
 795  * @frontbuffer_bits: frontbuffer plane tracking bits
 796  *
 797  * This function gets called after scheduling a flip on @obj. This is for
 798  * synchronous plane updates which will happen on the next vblank and which will
 799  * not get delayed by pending gpu rendering.
 800  *
 801  * Can be called without any locks held.
 802  */
 803 static inline
 804 void intel_frontbuffer_flip(struct drm_device *dev,
 805                             unsigned frontbuffer_bits)
 806 {
 807         intel_frontbuffer_flush(dev, frontbuffer_bits);
 808 }
 809
 810 void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire);
 811 void intel_mark_idle(struct drm_device *dev);
 812 void intel_crtc_restore_mode(struct drm_crtc *crtc);
 813 void intel_crtc_control(struct drm_crtc *crtc, bool enable);
 814 void intel_crtc_update_dpms(struct drm_crtc *crtc);
 815 void intel_encoder_destroy(struct drm_encoder *encoder);
 816 void intel_connector_dpms(struct drm_connector *, int mode);
 817 bool intel_connector_get_hw_state(struct intel_connector *connector);
 818 void intel_modeset_check_state(struct drm_device *dev);
 819 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 820                                 struct intel_digital_port *port);
 821 void intel_connector_attach_encoder(struct intel_connector *connector,
 822                                     struct intel_encoder *encoder);
 823 struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
 824 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
 825                                              struct drm_crtc *crtc);
 826 enum i915_pipe intel_get_pipe_from_connector(struct intel_connector *connector);
 827 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
 828                                 struct drm_file *file_priv);
 829 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 830                                              enum i915_pipe pipe);
 831 void intel_wait_for_vblank(struct drm_device *dev, int pipe);
 832 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
 833 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
 834 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
 835                          struct intel_digital_port *dport);
 836 bool intel_get_load_detect_pipe(struct drm_connector *connector,
 837                                 struct drm_display_mode *mode,
 838                                 struct intel_load_detect_pipe *old,
 839                                 struct drm_modeset_acquire_ctx *ctx);
 840 void intel_release_load_detect_pipe(struct drm_connector *connector,
 841                                     struct intel_load_detect_pipe *old);
 842 int intel_pin_and_fence_fb_obj(struct drm_device *dev,
 843                                struct drm_i915_gem_object *obj,
 844                                struct intel_engine_cs *pipelined);
 845 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
 846 struct drm_framebuffer *
 847 __intel_framebuffer_create(struct drm_device *dev,
 848                            struct drm_mode_fb_cmd2 *mode_cmd,
 849                            struct drm_i915_gem_object *obj);
 850 void intel_prepare_page_flip(struct drm_device *dev, int plane);
 851 void intel_finish_page_flip(struct drm_device *dev, int pipe);
 852 void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
 853
 854 /* shared dpll functions */
 855 struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
 856 void assert_shared_dpll(struct drm_i915_private *dev_priv,
 857                         struct intel_shared_dpll *pll,
 858                         bool state);
 859 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
 860 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
 861 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc);
 862 void intel_put_shared_dpll(struct intel_crtc *crtc);
 863
 864 /* modesetting asserts */
 865 void assert_pll(struct drm_i915_private *dev_priv,
 866                 enum i915_pipe pipe, bool state);
 867 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 868 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 869 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
 870                        enum i915_pipe pipe, bool state);
 871 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
 872 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
 873 void assert_pipe(struct drm_i915_private *dev_priv, enum i915_pipe pipe, bool state);
 874 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
 875 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
 876 void intel_write_eld(struct drm_encoder *encoder,
 877                      struct drm_display_mode *mode);
 878 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
 879                                              unsigned int tiling_mode,
 880                                              unsigned int bpp,
 881                                              unsigned int pitch);
 882 void intel_display_handle_reset(struct drm_device *dev);
 883 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
 884 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
 885 void intel_dp_get_m_n(struct intel_crtc *crtc,
 886                       struct intel_crtc_config *pipe_config);
 887 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
 888 void
 889 ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
 890                                 int dotclock);
 891 bool intel_crtc_active(struct drm_crtc *crtc);
 892 void hsw_enable_ips(struct intel_crtc *crtc);
 893 void hsw_disable_ips(struct intel_crtc *crtc);
 894 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
 895 enum intel_display_power_domain
 896 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
 897 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
 898                                  struct intel_crtc_config *pipe_config);
 899 int intel_format_to_fourcc(int format);
 900 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc);
 901
 902
 903 /* intel_dp.c */
 904 void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
 905 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
 906                              struct intel_connector *intel_connector);
 907 void intel_dp_start_link_train(struct intel_dp *intel_dp);
 908 void intel_dp_complete_link_train(struct intel_dp *intel_dp);
 909 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
 910 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
 911 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
 912 void intel_dp_check_link_status(struct intel_dp *intel_dp);
 913 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
 914 bool intel_dp_compute_config(struct intel_encoder *encoder,
 915                              struct intel_crtc_config *pipe_config);
 916 bool intel_dp_is_edp(struct drm_device *dev, enum port port);
 917 bool intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
 918                         bool long_hpd);
 919 void intel_edp_backlight_on(struct intel_dp *intel_dp);
 920 void intel_edp_backlight_off(struct intel_dp *intel_dp);
 921 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
 922 void intel_edp_panel_vdd_sanitize(struct intel_encoder *intel_encoder);
 923 void intel_edp_panel_on(struct intel_dp *intel_dp);
 924 void intel_edp_panel_off(struct intel_dp *intel_dp);
 925 void intel_edp_psr_enable(struct intel_dp *intel_dp);
 926 void intel_edp_psr_disable(struct intel_dp *intel_dp);
 927 void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate);
 928 void intel_edp_psr_invalidate(struct drm_device *dev,
 929                               unsigned frontbuffer_bits);
 930 void intel_edp_psr_flush(struct drm_device *dev,
 931                          unsigned frontbuffer_bits);
 932 void intel_edp_psr_init(struct drm_device *dev);
 933
 934 int intel_dp_handle_hpd_irq(struct intel_digital_port *digport, bool long_hpd);
 935 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
 936 void intel_dp_mst_suspend(struct drm_device *dev);
 937 void intel_dp_mst_resume(struct drm_device *dev);
 938 int intel_dp_max_link_bw(struct intel_dp *intel_dp);
 939 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
 940 /* intel_dp_mst.c */
 941 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
 942 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
 943 /* intel_dsi.c */
 944 void intel_dsi_init(struct drm_device *dev);
 945
 946
 947 /* intel_dvo.c */
 948 void intel_dvo_init(struct drm_device *dev);
 949
 950
 951 /* legacy fbdev emulation in intel_fbdev.c */
 952 #ifdef CONFIG_DRM_I915_FBDEV
 953 extern int intel_fbdev_init(struct drm_device *dev);
 954 extern void intel_fbdev_initial_config(struct drm_device *dev);
 955 extern void intel_fbdev_fini(struct drm_device *dev);
 956 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state);
 957 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
 958 extern void intel_fbdev_restore_mode(struct drm_device *dev);
 959 #else
 960 static inline int intel_fbdev_init(struct drm_device *dev)
 961 {
 962         return 0;
 963 }
 964
 965 static inline void intel_fbdev_initial_config(struct drm_device *dev)
 966 {
 967 }
 968
 969 static inline void intel_fbdev_fini(struct drm_device *dev)
 970 {
 971 }
 972
 973 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state)
 974 {
 975 }
 976
 977 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
 978 {
 979 }
 980 #endif
 981
 982 /* intel_hdmi.c */
 983 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port);
 984 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
 985                                struct intel_connector *intel_connector);
 986 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
 987 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
 988                                struct intel_crtc_config *pipe_config);
 989
 990
 991 /* intel_lvds.c */
 992 void intel_lvds_init(struct drm_device *dev);
 993 bool intel_is_dual_link_lvds(struct drm_device *dev);
 994
 995
 996 /* intel_modes.c */
 997 int intel_connector_update_modes(struct drm_connector *connector,
 998                                  struct edid *edid);
 999 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1000 void intel_attach_force_audio_property(struct drm_connector *connector);
1001 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1002
1003
1004 /* intel_overlay.c */
1005 void intel_setup_overlay(struct drm_device *dev);
1006 void intel_cleanup_overlay(struct drm_device *dev);
1007 int intel_overlay_switch_off(struct intel_overlay *overlay);
1008 int intel_overlay_put_image(struct drm_device *dev, void *data,
1009                             struct drm_file *file_priv);
1010 int intel_overlay_attrs(struct drm_device *dev, void *data,
1011                         struct drm_file *file_priv);
1012
1013
1014 /* intel_panel.c */
1015 int intel_panel_init(struct intel_panel *panel,
1016                      struct drm_display_mode *fixed_mode,
1017                      struct drm_display_mode *downclock_mode);
1018 void intel_panel_fini(struct intel_panel *panel);
1019 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1020                             struct drm_display_mode *adjusted_mode);
1021 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1022                              struct intel_crtc_config *pipe_config,
1023                              int fitting_mode);
1024 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1025                               struct intel_crtc_config *pipe_config,
1026                               int fitting_mode);
1027 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1028                                     u32 level, u32 max);
1029 int intel_panel_setup_backlight(struct drm_connector *connector);
1030 void intel_panel_enable_backlight(struct intel_connector *connector);
1031 void intel_panel_disable_backlight(struct intel_connector *connector);
1032 void intel_panel_destroy_backlight(struct drm_connector *connector);
1033 void intel_panel_init_backlight_funcs(struct drm_device *dev);
1034 enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1035 extern struct drm_display_mode *intel_find_panel_downclock(
1036                                 struct drm_device *dev,
1037                                 struct drm_display_mode *fixed_mode,
1038                                 struct drm_connector *connector);
1039
1040 /* intel_pm.c */
1041 void intel_init_clock_gating(struct drm_device *dev);
1042 void intel_suspend_hw(struct drm_device *dev);
1043 int ilk_wm_max_level(const struct drm_device *dev);
1044 void intel_update_watermarks(struct drm_crtc *crtc);
1045 void intel_update_sprite_watermarks(struct drm_plane *plane,
1046                                     struct drm_crtc *crtc,
1047                                     uint32_t sprite_width,
1048                                     uint32_t sprite_height,
1049                                     int pixel_size,
1050                                     bool enabled, bool scaled);
1051 void intel_init_pm(struct drm_device *dev);
1052 void intel_pm_setup(struct drm_device *dev);
1053 bool intel_fbc_enabled(struct drm_device *dev);
1054 void intel_update_fbc(struct drm_device *dev);
1055 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1056 void intel_gpu_ips_teardown(void);
1057 int intel_power_domains_init(struct drm_i915_private *);
1058 void intel_power_domains_remove(struct drm_i915_private *);
1059 bool intel_display_power_enabled(struct drm_i915_private *dev_priv,
1060                                  enum intel_display_power_domain domain);
1061 bool intel_display_power_enabled_unlocked(struct drm_i915_private *dev_priv,
1062                                           enum intel_display_power_domain domain);
1063 void intel_display_power_get(struct drm_i915_private *dev_priv,
1064                              enum intel_display_power_domain domain);
1065 void intel_display_power_put(struct drm_i915_private *dev_priv,
1066                              enum intel_display_power_domain domain);
1067 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv);
1068 void intel_init_gt_powersave(struct drm_device *dev);
1069 void intel_cleanup_gt_powersave(struct drm_device *dev);
1070 void intel_enable_gt_powersave(struct drm_device *dev);
1071 void intel_disable_gt_powersave(struct drm_device *dev);
1072 void intel_suspend_gt_powersave(struct drm_device *dev);
1073 void intel_reset_gt_powersave(struct drm_device *dev);
1074 void ironlake_teardown_rc6(struct drm_device *dev);
1075 void gen6_update_ring_freq(struct drm_device *dev);
1076 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1077 void gen6_rps_boost(struct drm_i915_private *dev_priv);
1078 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv);
1079 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv);
1080 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1081 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1082 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1083 void intel_init_runtime_pm(struct drm_i915_private *dev_priv);
1084 void intel_fini_runtime_pm(struct drm_i915_private *dev_priv);
1085 void ilk_wm_get_hw_state(struct drm_device *dev);
1086
1087
1088 /* intel_sdvo.c */
1089 bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
1090
1091
1092 /* intel_sprite.c */
1093 int intel_plane_init(struct drm_device *dev, enum i915_pipe pipe, int plane);
1094 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
1095                                enum plane plane);
1096 void intel_plane_restore(struct drm_plane *plane);
1097 void intel_plane_disable(struct drm_plane *plane);
1098 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1099                               struct drm_file *file_priv);
1100 int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
1101                               struct drm_file *file_priv);
1102
1103
1104 /* intel_tv.c */
1105 void intel_tv_init(struct drm_device *dev);
1106
1107 #endif /* __INTEL_DRV_H__ */